2 * Copyright (c) 1998, 1999 Takanori Watanabe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <machine/bus.h>
39 #include <dev/smbus/smbconf.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #include <pci/intpmreg.h>
47 #include "opt_intpm.h"
51 struct resource *io_res;
52 struct resource *irq_res;
59 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock)
60 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock)
61 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED)
63 static int intsmb_probe(device_t);
64 static int intsmb_attach(device_t);
65 static int intsmb_detach(device_t);
66 static int intsmb_intr(struct intsmb_softc *sc);
67 static int intsmb_slvintr(struct intsmb_softc *sc);
68 static void intsmb_alrintr(struct intsmb_softc *sc);
69 static int intsmb_callback(device_t dev, int index, void *data);
70 static int intsmb_quick(device_t dev, u_char slave, int how);
71 static int intsmb_sendb(device_t dev, u_char slave, char byte);
72 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
73 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
74 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
75 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
76 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
77 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
78 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
79 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
80 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr);
81 static int intsmb_stop(struct intsmb_softc *sc);
82 static int intsmb_stop_poll(struct intsmb_softc *sc);
83 static int intsmb_free(struct intsmb_softc *sc);
84 static void intsmb_rawintr(void *arg);
87 intsmb_probe(device_t dev)
90 switch (pci_get_devid(dev)) {
91 case 0x71138086: /* Intel 82371AB */
92 case 0x719b8086: /* Intel 82443MX */
94 /* Not a good idea yet, this stops isab0 functioning */
95 case 0x02001166: /* ServerWorks OSB4 */
97 device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
103 return (BUS_PROBE_DEFAULT);
107 intsmb_attach(device_t dev)
109 struct intsmb_softc *sc = device_get_softc(dev);
110 int error, rid, value;
113 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
115 rid = PCI_BASE_ADDR_SMB;
116 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
118 if (sc->io_res == NULL) {
119 device_printf(dev, "Could not allocate I/O space\n");
124 #ifndef NO_CHANGE_PCICONF
125 pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
126 pci_write_config(dev, PCI_HST_CFG_SMB,
127 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
129 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
130 switch (value & 0xe) {
131 case PCI_INTR_SMB_SMI:
134 case PCI_INTR_SMB_IRQ9:
140 device_printf(dev, "intr %s %s ", str,
141 (value & 1) ? "enabled" : "disabled");
142 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
144 if ((value & 0xe) != PCI_INTR_SMB_IRQ9) {
145 device_printf(dev, "Unsupported interrupt mode\n");
152 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
153 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
154 RF_SHAREABLE | RF_ACTIVE);
155 if (sc->irq_res == NULL) {
156 device_printf(dev, "Could not allocate irq\n");
161 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC, NULL,
162 intsmb_rawintr, sc, &sc->irq_hand);
164 device_printf(dev, "Failed to map intr\n");
168 value = pci_read_config(dev, PCI_BASE_ADDR_PM, 4);
169 device_printf(dev, "PM %s %x\n", (value & 1) ? "I/O mapped" : "Memory",
173 sc->smbus = device_add_child(dev, "smbus", -1);
174 if (sc->smbus == NULL) {
178 error = device_probe_and_attach(sc->smbus);
184 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
194 intsmb_detach(device_t dev)
196 struct intsmb_softc *sc = device_get_softc(dev);
199 error = bus_generic_detach(dev);
204 device_delete_child(dev, sc->smbus);
206 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
208 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
210 bus_release_resource(dev, SYS_RES_IOPORT, PCI_BASE_ADDR_SMB,
212 mtx_destroy(&sc->lock);
217 intsmb_rawintr(void *arg)
219 struct intsmb_softc *sc = arg;
228 intsmb_callback(device_t dev, int index, void *data)
233 case SMB_REQUEST_BUS:
235 case SMB_RELEASE_BUS:
244 /* Counterpart of smbtx_smb_free(). */
246 intsmb_free(struct intsmb_softc *sc)
249 INTSMB_LOCK_ASSERT(sc);
250 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
252 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
258 /* Disable Interrupt in slave part. */
260 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
262 /* Reset INTR Flag to prepare INTR. */
263 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
264 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
265 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
270 intsmb_intr(struct intsmb_softc *sc)
274 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
275 if (status & PIIX4_SMBHSTSTAT_BUSY)
278 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
279 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
281 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
282 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
283 tmp & ~PIIX4_SMBHSTCNT_INTREN);
290 return (1); /* Not Completed */
294 intsmb_slvintr(struct intsmb_softc *sc)
298 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
299 if (status & PIIX4_SMBSLVSTS_BUSY)
301 if (status & PIIX4_SMBSLVSTS_ALART)
303 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
304 | PIIX4_SMBSLVSTS_SDW1)) {
307 /* Reset Status Register */
308 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
309 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
310 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
315 intsmb_alrintr(struct intsmb_softc *sc)
323 /* Stop generating INTR from ALART. */
324 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
326 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
327 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
331 /* Ask bus who asserted it and then ask it what's the matter. */
333 error = intsmb_free(sc);
337 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
338 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
339 error = intsmb_stop_poll(sc);
341 device_printf(sc->dev, "ALART: ERROR\n");
343 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
344 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
347 /* Re-enable INTR from ALART. */
348 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
349 slvcnt | PIIX4_SMBSLVCNT_ALTEN);
355 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
359 INTSMB_LOCK_ASSERT(sc);
360 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
363 tmp |= PIIX4_SMBHSTCNT_START;
365 /* While not in autoconfiguration enable interrupts. */
366 if (!cold || !nointr)
367 tmp |= PIIX4_SMBHSTCNT_INTREN;
368 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
372 intsmb_error(int status)
376 if (status & PIIX4_SMBHSTSTAT_ERR)
377 error |= SMB_EBUSERR;
378 if (status & PIIX4_SMBHSTSTAT_BUSC)
380 if (status & PIIX4_SMBHSTSTAT_FAIL)
388 * Polling is not encouraged because it requires waiting for the
389 * device if it is busy.
390 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
394 intsmb_stop_poll(struct intsmb_softc *sc)
396 int error, i, status, tmp;
398 INTSMB_LOCK_ASSERT(sc);
400 /* First, wait for busy to be set. */
401 for (i = 0; i < 0x7fff; i++)
402 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
403 PIIX4_SMBHSTSTAT_BUSY)
406 /* Wait for busy to clear. */
407 for (i = 0; i < 0x7fff; i++) {
408 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
409 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
411 error = intsmb_error(status);
412 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
413 device_printf(sc->dev, "unknown cause why?");
418 /* Timed out waiting for busy to clear. */
420 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
421 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
422 return (SMB_ETIMEOUT);
426 * Wait for completion and return result.
429 intsmb_stop(struct intsmb_softc *sc)
433 INTSMB_LOCK_ASSERT(sc);
436 /* So that it can use device during device probe on SMBus. */
437 return (intsmb_stop_poll(sc));
439 error = tsleep(sc, PWAIT | PCATCH, "SMBWAI", hz / 8);
441 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
442 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
443 error = intsmb_error(status);
444 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
445 device_printf(sc->dev, "unknown cause why?\n");
447 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
448 PIIX4_SMBSLVCNT_ALTEN);
454 /* Timeout Procedure. */
457 /* Re-enable supressed interrupt from slave part. */
458 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
459 if (error == EWOULDBLOCK)
460 return (SMB_ETIMEOUT);
466 intsmb_quick(device_t dev, u_char slave, int how)
468 struct intsmb_softc *sc = device_get_softc(dev);
474 /* Quick command is part of Address, I think. */
487 error = intsmb_free(sc);
492 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
493 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0);
494 error = intsmb_stop(sc);
500 intsmb_sendb(device_t dev, u_char slave, char byte)
502 struct intsmb_softc *sc = device_get_softc(dev);
506 error = intsmb_free(sc);
511 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
512 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
513 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
514 error = intsmb_stop(sc);
520 intsmb_recvb(device_t dev, u_char slave, char *byte)
522 struct intsmb_softc *sc = device_get_softc(dev);
526 error = intsmb_free(sc);
531 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
532 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
533 error = intsmb_stop(sc);
535 #ifdef RECV_IS_IN_CMD
537 * Linux SMBus stuff also troubles
538 * Because Intel's datasheet does not make clear.
540 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
542 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
550 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
552 struct intsmb_softc *sc = device_get_softc(dev);
556 error = intsmb_free(sc);
561 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
562 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
563 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
564 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
565 error = intsmb_stop(sc);
571 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
573 struct intsmb_softc *sc = device_get_softc(dev);
577 error = intsmb_free(sc);
582 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
583 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
584 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
585 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
586 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
587 error = intsmb_stop(sc);
593 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
595 struct intsmb_softc *sc = device_get_softc(dev);
599 error = intsmb_free(sc);
604 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
605 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
606 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
607 error = intsmb_stop(sc);
609 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
615 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
617 struct intsmb_softc *sc = device_get_softc(dev);
621 error = intsmb_free(sc);
626 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
627 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
628 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
629 error = intsmb_stop(sc);
631 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
632 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
639 * Data sheet claims that it implements all function, but also claims
640 * that it implements 7 function and not mention PCALL. So I don't know
641 * whether it will work.
644 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
647 struct intsmb_softc *sc = device_get_softc(dev);
651 error = intsmb_free(sc);
656 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
657 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
658 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, sdata & 0xff);
659 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (sdata & 0xff) >> 8);
660 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
661 error = intsmb_stop(sc);
663 *rdata = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
664 *rdata |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
669 return (SMB_ENOTSUPP);
674 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
676 struct intsmb_softc *sc = device_get_softc(dev);
679 if (count > SMBBLOCKTRANS_MAX || count == 0)
683 error = intsmb_free(sc);
689 /* Reset internal array index. */
690 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
692 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
693 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
694 for (i = 0; i < count; i++)
695 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
696 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
697 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
698 error = intsmb_stop(sc);
704 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
706 struct intsmb_softc *sc = device_get_softc(dev);
710 if (*count > SMBBLOCKTRANS_MAX || *count == 0)
714 error = intsmb_free(sc);
720 /* Reset internal array index. */
721 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
723 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
724 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
725 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, *count);
726 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
727 error = intsmb_stop(sc);
729 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
730 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
731 for (i = 0; i < nread; i++) {
732 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
744 static devclass_t intsmb_devclass;
746 static device_method_t intsmb_methods[] = {
747 /* Device interface */
748 DEVMETHOD(device_probe, intsmb_probe),
749 DEVMETHOD(device_attach, intsmb_attach),
750 DEVMETHOD(device_detach, intsmb_detach),
753 DEVMETHOD(bus_print_child, bus_generic_print_child),
755 /* SMBus interface */
756 DEVMETHOD(smbus_callback, intsmb_callback),
757 DEVMETHOD(smbus_quick, intsmb_quick),
758 DEVMETHOD(smbus_sendb, intsmb_sendb),
759 DEVMETHOD(smbus_recvb, intsmb_recvb),
760 DEVMETHOD(smbus_writeb, intsmb_writeb),
761 DEVMETHOD(smbus_writew, intsmb_writew),
762 DEVMETHOD(smbus_readb, intsmb_readb),
763 DEVMETHOD(smbus_readw, intsmb_readw),
764 DEVMETHOD(smbus_pcall, intsmb_pcall),
765 DEVMETHOD(smbus_bwrite, intsmb_bwrite),
766 DEVMETHOD(smbus_bread, intsmb_bread),
771 static driver_t intsmb_driver = {
774 sizeof(struct intsmb_softc),
777 DRIVER_MODULE(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0);
778 DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0);
779 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
780 MODULE_VERSION(intsmb, 1);