2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_simos.h"
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
47 #include <vm/vm_extern.h>
50 #include <machine/bus.h>
52 #include <machine/resource.h>
53 #include <machine/md_var.h> /* For the Alpha */
55 #include <sys/pciio.h>
56 #include <pci/pcireg.h>
57 #include <pci/pcivar.h>
62 #include <machine/rpb.h>
66 #include <machine/smp.h>
69 static devclass_t pci_devclass;
72 u_int32_t devid; /* Vendor/device of the card */
74 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in wierd place */
79 struct pci_quirk pci_quirks[] = {
81 * The Intel 82371AB has a map register at offset 0x90.
83 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
88 /* map register information */
89 #define PCI_MAPMEM 0x01 /* memory map */
90 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
91 #define PCI_MAPPORT 0x04 /* port map */
93 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
94 u_int32_t pci_numdevs = 0;
95 static u_int32_t pci_generation = 0;
97 /* return base address of memory or port map */
100 pci_mapbase(unsigned mapreg)
103 if ((mapreg & 0x01) == 0)
105 return (mapreg & ~mask);
108 /* return map type of memory or port map */
111 pci_maptype(unsigned mapreg)
113 static u_int8_t maptype[0x10] = {
114 PCI_MAPMEM, PCI_MAPPORT,
116 PCI_MAPMEM, PCI_MAPPORT,
118 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
119 PCI_MAPMEM|PCI_MAPMEMP, 0,
120 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
124 return maptype[mapreg & 0x0f];
127 /* return log2 of map size decoded for memory or port map */
130 pci_mapsize(unsigned testval)
134 testval = pci_mapbase(testval);
137 while ((testval & 1) == 0)
146 /* return log2 of address range supported by map register */
149 pci_maprange(unsigned mapreg)
152 switch (mapreg & 0x07) {
168 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
171 pci_fixancient(pcicfgregs *cfg)
173 if (cfg->hdrtype != 0)
176 /* PCI to PCI bridges use header type 1 */
177 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
181 /* read config data specific to header type 1 device (PCI to PCI bridge) */
184 pci_readppb(device_t pcib, int b, int s, int f)
188 p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
192 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
193 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
195 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
197 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
199 PCIB_READ_CONFIG(pcib, b, s, f,
201 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
203 PCIB_READ_CONFIG(pcib, b, s, f,
204 PCIR_IOLIMITL_1, 1));
206 p->membase = PCI_PPBMEMBASE (0,
207 PCIB_READ_CONFIG(pcib, b, s, f,
209 p->memlimit = PCI_PPBMEMLIMIT (0,
210 PCIB_READ_CONFIG(pcib, b, s, f,
211 PCIR_MEMLIMIT_1, 2));
213 p->pmembase = PCI_PPBMEMBASE (
214 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
215 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
217 p->pmemlimit = PCI_PPBMEMLIMIT (
218 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
220 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
225 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
228 pci_readpcb(device_t pcib, int b, int s, int f)
232 p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
236 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
237 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
239 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
241 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
242 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
243 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
244 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
246 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
247 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
248 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
249 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
251 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
255 /* extract header type specific config data */
258 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
260 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
261 switch (cfg->hdrtype) {
263 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
264 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
265 cfg->nummaps = PCI_MAXMAPS_0;
268 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
269 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
270 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
271 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
272 cfg->nummaps = PCI_MAXMAPS_1;
273 cfg->hdrspec = pci_readppb(pcib, b, s, f);
276 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
277 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
278 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
279 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
280 cfg->nummaps = PCI_MAXMAPS_2;
281 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
287 /* read configuration header into pcicfgrect structure */
289 static struct pci_devinfo *
290 pci_read_device(device_t pcib, int b, int s, int f)
292 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
293 pcicfgregs *cfg = NULL;
294 struct pci_devinfo *devlist_entry;
295 struct devlist *devlist_head;
297 devlist_head = &pci_devq;
299 devlist_entry = NULL;
301 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
302 devlist_entry = malloc(sizeof(struct pci_devinfo),
303 M_DEVBUF, M_WAITOK | M_ZERO);
304 if (devlist_entry == NULL)
307 cfg = &devlist_entry->cfg;
312 cfg->vendor = REG(PCIR_VENDOR, 2);
313 cfg->device = REG(PCIR_DEVICE, 2);
314 cfg->cmdreg = REG(PCIR_COMMAND, 2);
315 cfg->statreg = REG(PCIR_STATUS, 2);
316 cfg->baseclass = REG(PCIR_CLASS, 1);
317 cfg->subclass = REG(PCIR_SUBCLASS, 1);
318 cfg->progif = REG(PCIR_PROGIF, 1);
319 cfg->revid = REG(PCIR_REVID, 1);
320 cfg->hdrtype = REG(PCIR_HEADERTYPE, 1);
321 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
322 cfg->lattimer = REG(PCIR_LATTIMER, 1);
323 cfg->intpin = REG(PCIR_INTPIN, 1);
324 cfg->intline = REG(PCIR_INTLINE, 1);
326 alpha_platform_assign_pciintr(cfg);
330 if (cfg->intpin != 0) {
333 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
335 /* PCI specific entry found in MP table */
336 if (airq != cfg->intline) {
337 undirect_pci_irq(cfg->intline);
342 * PCI interrupts might be redirected to the
343 * ISA bus according to some MP tables. Use the
344 * same methods as used by the ISA devices
345 * devices to find the proper IOAPIC int pin.
347 airq = isa_apic_irq(cfg->intline);
348 if ((airq >= 0) && (airq != cfg->intline)) {
349 /* XXX: undirect_pci_irq() ? */
350 undirect_isa_irq(cfg->intline);
357 cfg->mingnt = REG(PCIR_MINGNT, 1);
358 cfg->maxlat = REG(PCIR_MAXLAT, 1);
360 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
361 cfg->hdrtype &= ~PCIM_MFDEV;
364 pci_hdrtypedata(pcib, b, s, f, cfg);
366 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
368 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
369 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
370 devlist_entry->conf.pc_sel.pc_func = cfg->func;
371 devlist_entry->conf.pc_hdr = cfg->hdrtype;
373 devlist_entry->conf.pc_subvendor = cfg->subvendor;
374 devlist_entry->conf.pc_subdevice = cfg->subdevice;
375 devlist_entry->conf.pc_vendor = cfg->vendor;
376 devlist_entry->conf.pc_device = cfg->device;
378 devlist_entry->conf.pc_class = cfg->baseclass;
379 devlist_entry->conf.pc_subclass = cfg->subclass;
380 devlist_entry->conf.pc_progif = cfg->progif;
381 devlist_entry->conf.pc_revid = cfg->revid;
386 return (devlist_entry);
391 /* free pcicfgregs structure and all depending data structures */
394 pci_freecfg(struct pci_devinfo *dinfo)
396 struct devlist *devlist_head;
398 devlist_head = &pci_devq;
400 if (dinfo->cfg.hdrspec != NULL)
401 free(dinfo->cfg.hdrspec, M_DEVBUF);
402 if (dinfo->cfg.map != NULL)
403 free(dinfo->cfg.map, M_DEVBUF);
404 /* XXX this hasn't been tested */
405 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
406 free(dinfo, M_DEVBUF);
408 /* increment the generation count */
411 /* we're losing one device */
419 * This is the user interface to PCI configuration space.
423 pci_open(dev_t dev, int oflags, int devtype, struct proc *p)
425 if ((oflags & FWRITE) && securelevel > 0) {
432 pci_close(dev_t dev, int flag, int devtype, struct proc *p)
438 * Match a single pci_conf structure against an array of pci_match_conf
439 * structures. The first argument, 'matches', is an array of num_matches
440 * pci_match_conf structures. match_buf is a pointer to the pci_conf
441 * structure that will be compared to every entry in the matches array.
442 * This function returns 1 on failure, 0 on success.
445 pci_conf_match(struct pci_match_conf *matches, int num_matches,
446 struct pci_conf *match_buf)
450 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
453 for (i = 0; i < num_matches; i++) {
455 * I'm not sure why someone would do this...but...
457 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
461 * Look at each of the match flags. If it's set, do the
462 * comparison. If the comparison fails, we don't have a
463 * match, go on to the next item if there is one.
465 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
466 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
469 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
470 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
473 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
474 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
477 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
478 && (match_buf->pc_vendor != matches[i].pc_vendor))
481 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
482 && (match_buf->pc_device != matches[i].pc_device))
485 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
486 && (match_buf->pc_class != matches[i].pc_class))
489 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
490 && (match_buf->pd_unit != matches[i].pd_unit))
493 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
494 && (strncmp(matches[i].pd_name, match_buf->pd_name,
495 sizeof(match_buf->pd_name)) != 0))
505 * Locate the parent of a PCI device by scanning the PCI devlist
506 * and return the entry for the parent.
507 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
508 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
512 pci_devlist_get_parent(pcicfgregs *cfg)
514 struct devlist *devlist_head;
515 struct pci_devinfo *dinfo;
516 pcicfgregs *bridge_cfg;
519 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
521 /* If the device is on PCI bus 0, look for the host */
523 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
524 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
525 bridge_cfg = &dinfo->cfg;
526 if (bridge_cfg->baseclass == PCIC_BRIDGE
527 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
528 && bridge_cfg->bus == cfg->bus) {
534 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
536 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
537 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
538 bridge_cfg = &dinfo->cfg;
539 if (bridge_cfg->baseclass == PCIC_BRIDGE
540 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
541 && bridge_cfg->secondarybus == cfg->bus) {
551 pci_ioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
558 if (!(flag & FWRITE))
565 struct pci_devinfo *dinfo;
566 struct pci_conf_io *cio;
567 struct devlist *devlist_head;
568 struct pci_match_conf *pattern_buf;
573 cio = (struct pci_conf_io *)data;
579 * Hopefully the user won't pass in a null pointer, but it
580 * can't hurt to check.
588 * If the user specified an offset into the device list,
589 * but the list has changed since they last called this
590 * ioctl, tell them that the list has changed. They will
591 * have to get the list from the beginning.
593 if ((cio->offset != 0)
594 && (cio->generation != pci_generation)){
595 cio->num_matches = 0;
596 cio->status = PCI_GETCONF_LIST_CHANGED;
602 * Check to see whether the user has asked for an offset
603 * past the end of our list.
605 if (cio->offset >= pci_numdevs) {
606 cio->num_matches = 0;
607 cio->status = PCI_GETCONF_LAST_DEVICE;
612 /* get the head of the device queue */
613 devlist_head = &pci_devq;
616 * Determine how much room we have for pci_conf structures.
617 * Round the user's buffer size down to the nearest
618 * multiple of sizeof(struct pci_conf) in case the user
619 * didn't specify a multiple of that size.
621 iolen = min(cio->match_buf_len -
622 (cio->match_buf_len % sizeof(struct pci_conf)),
623 pci_numdevs * sizeof(struct pci_conf));
626 * Since we know that iolen is a multiple of the size of
627 * the pciconf union, it's okay to do this.
629 ionum = iolen / sizeof(struct pci_conf);
632 * If this test is true, the user wants the pci_conf
633 * structures returned to match the supplied entries.
635 if ((cio->num_patterns > 0)
636 && (cio->pat_buf_len > 0)) {
638 * pat_buf_len needs to be:
639 * num_patterns * sizeof(struct pci_match_conf)
640 * While it is certainly possible the user just
641 * allocated a large buffer, but set the number of
642 * matches correctly, it is far more likely that
643 * their kernel doesn't match the userland utility
644 * they're using. It's also possible that the user
645 * forgot to initialize some variables. Yes, this
646 * may be overly picky, but I hazard to guess that
647 * it's far more likely to just catch folks that
648 * updated their kernel but not their userland.
650 if ((cio->num_patterns *
651 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
652 /* The user made a mistake, return an error*/
653 cio->status = PCI_GETCONF_ERROR;
654 printf("pci_ioctl: pat_buf_len %d != "
655 "num_patterns (%d) * sizeof(struct "
656 "pci_match_conf) (%d)\npci_ioctl: "
657 "pat_buf_len should be = %d\n",
658 cio->pat_buf_len, cio->num_patterns,
659 (int)sizeof(struct pci_match_conf),
660 (int)sizeof(struct pci_match_conf) *
662 printf("pci_ioctl: do your headers match your "
664 cio->num_matches = 0;
670 * Check the user's buffer to make sure it's readable.
672 if (!useracc((caddr_t)cio->patterns,
673 cio->pat_buf_len, VM_PROT_READ)) {
674 printf("pci_ioctl: pattern buffer %p, "
675 "length %u isn't user accessible for"
676 " READ\n", cio->patterns,
682 * Allocate a buffer to hold the patterns.
684 pattern_buf = malloc(cio->pat_buf_len, M_TEMP,
686 error = copyin(cio->patterns, pattern_buf,
690 num_patterns = cio->num_patterns;
692 } else if ((cio->num_patterns > 0)
693 || (cio->pat_buf_len > 0)) {
695 * The user made a mistake, spit out an error.
697 cio->status = PCI_GETCONF_ERROR;
698 cio->num_matches = 0;
699 printf("pci_ioctl: invalid GETCONF arguments\n");
706 * Make sure we can write to the match buffer.
708 if (!useracc((caddr_t)cio->matches,
709 cio->match_buf_len, VM_PROT_WRITE)) {
710 printf("pci_ioctl: match buffer %p, length %u "
711 "isn't user accessible for WRITE\n",
712 cio->matches, cio->match_buf_len);
718 * Go through the list of devices and copy out the devices
719 * that match the user's criteria.
721 for (cio->num_matches = 0, error = 0, i = 0,
722 dinfo = STAILQ_FIRST(devlist_head);
723 (dinfo != NULL) && (cio->num_matches < ionum)
724 && (error == 0) && (i < pci_numdevs);
725 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
730 /* Populate pd_name and pd_unit */
732 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
733 name = device_get_name(dinfo->cfg.dev);
735 strncpy(dinfo->conf.pd_name, name,
736 sizeof(dinfo->conf.pd_name));
737 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
738 dinfo->conf.pd_unit =
739 device_get_unit(dinfo->cfg.dev);
742 if ((pattern_buf == NULL) ||
743 (pci_conf_match(pattern_buf, num_patterns,
744 &dinfo->conf) == 0)) {
747 * If we've filled up the user's buffer,
748 * break out at this point. Since we've
749 * got a match here, we'll pick right back
750 * up at the matching entry. We can also
751 * tell the user that there are more matches
754 if (cio->num_matches >= ionum)
757 error = copyout(&dinfo->conf,
758 &cio->matches[cio->num_matches],
759 sizeof(struct pci_conf));
765 * Set the pointer into the list, so if the user is getting
766 * n records at a time, where n < pci_numdevs,
771 * Set the generation, the user will need this if they make
772 * another ioctl call with offset != 0.
774 cio->generation = pci_generation;
777 * If this is the last device, inform the user so he won't
778 * bother asking for more devices. If dinfo isn't NULL, we
779 * know that there are more matches in the list because of
780 * the way the traversal is done.
783 cio->status = PCI_GETCONF_LAST_DEVICE;
785 cio->status = PCI_GETCONF_MORE_DEVS;
787 if (pattern_buf != NULL)
788 free(pattern_buf, M_TEMP);
793 io = (struct pci_io *)data;
794 switch(io->pi_width) {
799 * Assume that the user-level bus number is
800 * actually the pciN instance number. We map
801 * from that to the real pcib+bus combination.
803 pci = devclass_get_device(pci_devclass,
806 int b = pcib_get_bus(pci);
807 pcib = device_get_parent(pci);
809 PCIB_READ_CONFIG(pcib,
827 io = (struct pci_io *)data;
828 switch(io->pi_width) {
833 * Assume that the user-level bus number is
834 * actually the pciN instance number. We map
835 * from that to the real pcib+bus combination.
837 pci = devclass_get_device(pci_devclass,
840 int b = pcib_get_bus(pci);
841 pcib = device_get_parent(pci);
842 PCIB_WRITE_CONFIG(pcib,
870 static struct cdevsw pcicdev = {
872 /* close */ pci_close,
875 /* ioctl */ pci_ioctl,
878 /* strategy */ nostrategy,
890 * New style pci driver. Parent device is either a pci-host-bridge or a
891 * pci-pci-bridge. Both kinds are represented by instances of pcib.
895 pci_print_verbose(struct pci_devinfo *dinfo)
898 pcicfgregs *cfg = &dinfo->cfg;
900 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
901 cfg->vendor, cfg->device, cfg->revid);
902 printf("\tbus=%d, slot=%d, func=%d\n",
903 cfg->bus, cfg->slot, cfg->func);
904 printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
905 cfg->baseclass, cfg->subclass, cfg->progif,
906 cfg->hdrtype, cfg->mfdev);
907 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
908 cfg->subordinatebus, cfg->secondarybus);
910 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
911 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
912 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
913 cfg->lattimer, cfg->lattimer * 30,
914 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
915 #endif /* PCI_DEBUG */
917 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
922 pci_porten(device_t pcib, int b, int s, int f)
924 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
925 & PCIM_CMD_PORTEN) != 0;
929 pci_memen(device_t pcib, int b, int s, int f)
931 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
932 & PCIM_CMD_MEMEN) != 0;
936 * Add a resource based on a pci map register. Return 1 if the map
937 * register is a 32bit map register or 2 if it is a 64bit register.
940 pci_add_map(device_t pcib, int b, int s, int f, int reg,
941 struct resource_list *rl)
948 #ifdef PCI_ENABLE_IO_MODES
953 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
955 if (map == 0 || map == 0xffffffff)
956 return 1; /* skip invalid entry */
958 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
959 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
960 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
962 base = pci_mapbase(map);
963 if (pci_maptype(map) & PCI_MAPMEM)
964 type = SYS_RES_MEMORY;
966 type = SYS_RES_IOPORT;
967 ln2size = pci_mapsize(testval);
968 ln2range = pci_maprange(testval);
969 if (ln2range == 64) {
970 /* Read the other half of a 64bit map register */
971 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
975 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d",
976 reg, pci_maptype(map), ln2range,
977 (unsigned int) base, ln2size);
978 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
979 printf(", port disabled\n");
980 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
981 printf(", memory disabled\n");
983 printf(", enabled\n");
987 * This code theoretically does the right thing, but has
988 * undesirable side effects in some cases where
989 * peripherals respond oddly to having these bits
990 * enabled. Leave them alone by default.
992 #ifdef PCI_ENABLE_IO_MODES
993 /* Turn on resources that have been left off by a lazy BIOS */
994 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
995 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
996 cmd |= PCIM_CMD_PORTEN;
997 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
999 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1000 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1001 cmd |= PCIM_CMD_MEMEN;
1002 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1005 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1007 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1011 resource_list_add(rl, type, reg,
1012 base, base + (1 << ln2size) - 1,
1015 return (ln2range == 64) ? 2 : 1;
1019 pci_add_resources(device_t pcib, int b, int s, int f, device_t dev)
1021 struct pci_devinfo *dinfo = device_get_ivars(dev);
1022 pcicfgregs *cfg = &dinfo->cfg;
1023 struct resource_list *rl = &dinfo->resources;
1024 struct pci_quirk *q;
1027 for (i = 0; i < cfg->nummaps;) {
1028 i += pci_add_map(pcib, b, s, f, PCIR_MAPS + i*4, rl);
1031 for (q = &pci_quirks[0]; q->devid; q++) {
1032 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1033 && q->type == PCI_QUIRK_MAP_REG)
1034 pci_add_map(pcib, b, s, f, q->arg1, rl);
1037 if (cfg->intpin > 0 && cfg->intline != 255)
1038 resource_list_add(rl, SYS_RES_IRQ, 0,
1039 cfg->intline, cfg->intline, 1);
1043 pci_add_children(device_t dev, int busno)
1045 device_t pcib = device_get_parent(dev);
1049 maxslots = PCIB_MAXSLOTS(pcib);
1051 for (s = 0; s <= maxslots; s++) {
1052 int pcifunchigh = 0;
1053 for (f = 0; f <= pcifunchigh; f++) {
1054 struct pci_devinfo *dinfo =
1055 pci_read_device(pcib, busno, s, f);
1056 if (dinfo != NULL) {
1057 if (dinfo->cfg.mfdev)
1060 pci_print_verbose(dinfo);
1061 dinfo->cfg.dev = device_add_child(dev, NULL, -1);
1062 device_set_ivars(dinfo->cfg.dev, dinfo);
1063 pci_add_resources(pcib, busno, s, f,
1071 pci_probe(device_t dev)
1073 static int once, busno;
1075 device_set_desc(dev, "PCI bus");
1078 device_printf(dev, "physical bus=%d\n", pcib_get_bus(dev));
1081 * Since there can be multiple independantly numbered PCI
1082 * busses on some large alpha systems, we can't use the unit
1083 * number to decide what bus we are probing. We ask the parent
1084 * pcib what our bus number is.
1086 busno = pcib_get_bus(dev);
1089 pci_add_children(dev, busno);
1092 make_dev(&pcicdev, 0, UID_ROOT, GID_WHEEL, 0644, "pci");
1100 pci_print_resources(struct resource_list *rl, const char *name, int type,
1103 struct resource_list_entry *rle;
1104 int printed, retval;
1108 /* Yes, this is kinda cheating */
1109 SLIST_FOREACH(rle, rl, link) {
1110 if (rle->type == type) {
1112 retval += printf(" %s ", name);
1113 else if (printed > 0)
1114 retval += printf(",");
1116 retval += printf(format, rle->start);
1117 if (rle->count > 1) {
1118 retval += printf("-");
1119 retval += printf(format, rle->start +
1128 pci_print_child(device_t dev, device_t child)
1130 struct pci_devinfo *dinfo;
1131 struct resource_list *rl;
1135 dinfo = device_get_ivars(child);
1137 rl = &dinfo->resources;
1139 retval += bus_print_child_header(dev, child);
1141 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1142 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1143 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1144 if (device_get_flags(dev))
1145 retval += printf(" flags %#x", device_get_flags(dev));
1147 retval += printf(" at device %d.%d", pci_get_slot(child),
1148 pci_get_function(child));
1150 retval += bus_print_child_footer(dev, child);
1156 pci_probe_nomatch(device_t dev, device_t child)
1158 struct pci_devinfo *dinfo;
1164 dinfo = device_get_ivars(child);
1166 desc = pci_ata_match(child);
1167 if (!desc) desc = pci_usb_match(child);
1168 if (!desc) desc = pci_vga_match(child);
1169 if (!desc) desc = pci_chip_match(child);
1171 desc = "unknown card";
1174 device_printf(dev, "<%s>", desc);
1175 if (bootverbose || unknown) {
1176 printf(" (vendor=0x%04x, dev=0x%04x)",
1181 pci_get_slot(child),
1182 pci_get_function(child));
1183 if (cfg->intpin > 0 && cfg->intline != 255) {
1184 printf(" irq %d", cfg->intline);
1192 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1194 struct pci_devinfo *dinfo;
1197 dinfo = device_get_ivars(child);
1201 case PCI_IVAR_SUBVENDOR:
1202 *result = cfg->subvendor;
1204 case PCI_IVAR_SUBDEVICE:
1205 *result = cfg->subdevice;
1207 case PCI_IVAR_VENDOR:
1208 *result = cfg->vendor;
1210 case PCI_IVAR_DEVICE:
1211 *result = cfg->device;
1213 case PCI_IVAR_DEVID:
1214 *result = (cfg->device << 16) | cfg->vendor;
1216 case PCI_IVAR_CLASS:
1217 *result = cfg->baseclass;
1219 case PCI_IVAR_SUBCLASS:
1220 *result = cfg->subclass;
1222 case PCI_IVAR_PROGIF:
1223 *result = cfg->progif;
1225 case PCI_IVAR_REVID:
1226 *result = cfg->revid;
1228 case PCI_IVAR_INTPIN:
1229 *result = cfg->intpin;
1232 *result = cfg->intline;
1238 *result = cfg->slot;
1240 case PCI_IVAR_FUNCTION:
1241 *result = cfg->func;
1243 case PCI_IVAR_SECONDARYBUS:
1244 *result = cfg->secondarybus;
1246 case PCI_IVAR_SUBORDINATEBUS:
1247 *result = cfg->subordinatebus;
1256 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1258 struct pci_devinfo *dinfo;
1261 dinfo = device_get_ivars(child);
1265 case PCI_IVAR_SUBVENDOR:
1266 case PCI_IVAR_SUBDEVICE:
1267 case PCI_IVAR_VENDOR:
1268 case PCI_IVAR_DEVICE:
1269 case PCI_IVAR_DEVID:
1270 case PCI_IVAR_CLASS:
1271 case PCI_IVAR_SUBCLASS:
1272 case PCI_IVAR_PROGIF:
1273 case PCI_IVAR_REVID:
1274 case PCI_IVAR_INTPIN:
1278 case PCI_IVAR_FUNCTION:
1279 return EINVAL; /* disallow for now */
1281 case PCI_IVAR_SECONDARYBUS:
1282 cfg->secondarybus = value;
1284 case PCI_IVAR_SUBORDINATEBUS:
1285 cfg->subordinatebus = value;
1293 static struct resource *
1294 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1295 u_long start, u_long end, u_long count, u_int flags)
1297 struct pci_devinfo *dinfo = device_get_ivars(child);
1298 struct resource_list *rl = &dinfo->resources;
1299 pcicfgregs *cfg = &dinfo->cfg;
1302 * Perform lazy resource allocation
1304 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1306 if (device_get_parent(child) == dev) {
1307 if ((type == SYS_RES_IRQ) && (cfg->intline == 255)) {
1309 cfg->intline = PCIB_ROUTE_INTERRUPT(
1310 device_get_parent(dev), pci_get_slot(child),
1312 #endif /* __i386__ */
1313 if (cfg->intline != 255) {
1314 pci_write_config(child, PCIR_INTLINE, cfg->intline, 1);
1315 resource_list_add(rl, SYS_RES_IRQ, 0,
1316 cfg->intline, cfg->intline, 1);
1321 return resource_list_alloc(rl, dev, child, type, rid,
1322 start, end, count, flags);
1326 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1328 printf("pci_delete_resource: PCI resources can not be deleted\n");
1331 static struct resource_list *
1332 pci_get_resource_list (device_t dev, device_t child)
1334 struct pci_devinfo * dinfo = device_get_ivars(child);
1335 struct resource_list * rl = &dinfo->resources;
1344 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1346 struct pci_devinfo *dinfo = device_get_ivars(child);
1347 pcicfgregs *cfg = &dinfo->cfg;
1349 return PCIB_READ_CONFIG(device_get_parent(dev),
1350 cfg->bus, cfg->slot, cfg->func,
1355 pci_write_config_method(device_t dev, device_t child, int reg,
1356 u_int32_t val, int width)
1358 struct pci_devinfo *dinfo = device_get_ivars(child);
1359 pcicfgregs *cfg = &dinfo->cfg;
1361 PCIB_WRITE_CONFIG(device_get_parent(dev),
1362 cfg->bus, cfg->slot, cfg->func,
1367 pci_modevent(module_t mod, int what, void *arg)
1371 STAILQ_INIT(&pci_devq);
1381 static device_method_t pci_methods[] = {
1382 /* Device interface */
1383 DEVMETHOD(device_probe, pci_probe),
1384 DEVMETHOD(device_attach, bus_generic_attach),
1385 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1386 DEVMETHOD(device_suspend, bus_generic_suspend),
1387 DEVMETHOD(device_resume, bus_generic_resume),
1390 DEVMETHOD(bus_print_child, pci_print_child),
1391 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1392 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1393 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1394 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1395 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1396 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1398 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
1399 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
1400 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
1401 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1402 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1403 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
1404 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1405 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1408 DEVMETHOD(pci_read_config, pci_read_config_method),
1409 DEVMETHOD(pci_write_config, pci_write_config_method),
1414 static driver_t pci_driver = {
1419 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
1420 DRIVER_MODULE(pci, acpi_pcib, pci_driver, pci_devclass, pci_modevent, 0);