2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND 4-Clause-BSD
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
33 * Copyright (C) 1995, 1996 TooLs GmbH.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. All advertising materials mentioning features or use of this software
45 * must display the following acknowledgement:
46 * This product includes software developed by TooLs GmbH.
47 * 4. The name of TooLs GmbH may not be used to endorse or promote products
48 * derived from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
64 * Copyright (C) 2001 Benno Rice.
65 * All rights reserved.
67 * Redistribution and use in source and binary forms, with or without
68 * modification, are permitted provided that the following conditions
70 * 1. Redistributions of source code must retain the above copyright
71 * notice, this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright
73 * notice, this list of conditions and the following disclaimer in the
74 * documentation and/or other materials provided with the distribution.
76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Native 64-bit page table operations for running without a hypervisor.
95 #include <sys/param.h>
96 #include <sys/kernel.h>
99 #include <sys/mutex.h>
100 #include <sys/proc.h>
101 #include <sys/sched.h>
102 #include <sys/sysctl.h>
103 #include <sys/systm.h>
104 #include <sys/rwlock.h>
105 #include <sys/endian.h>
110 #include <vm/vm_param.h>
111 #include <vm/vm_kern.h>
112 #include <vm/vm_page.h>
113 #include <vm/vm_map.h>
114 #include <vm/vm_object.h>
115 #include <vm/vm_extern.h>
116 #include <vm/vm_pageout.h>
118 #include <machine/cpu.h>
119 #include <machine/hid.h>
120 #include <machine/md_var.h>
121 #include <machine/mmuvar.h>
123 #include "mmu_oea64.h"
125 #include "moea64_if.h"
127 #define PTESYNC() __asm __volatile("ptesync");
128 #define TLBSYNC() __asm __volatile("tlbsync; ptesync");
129 #define SYNC() __asm __volatile("sync");
130 #define EIEIO() __asm __volatile("eieio");
132 #define VSID_HASH_MASK 0x0000007fffffffffULL
134 /* POWER9 only permits a 64k partition table size. */
135 #define PART_SIZE 0x10000
140 vpn <<= ADDR_PIDX_SHFT;
142 __asm __volatile("tlbie %0" :: "r"(vpn) : "memory");
143 __asm __volatile("eieio; tlbsync; ptesync" ::: "memory");
146 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
147 #define ENABLE_TRANS(msr) mtmsr(msr)
152 static volatile struct pate *isa3_part_table;
153 static volatile struct lpte *isa3_hashtb_pteg_table;
154 static struct rwlock isa3_hashtb_eviction_lock;
159 static int isa3_hashtb_pte_insert(mmu_t, struct pvo_entry *);
160 static int64_t isa3_hashtb_pte_synch(mmu_t, struct pvo_entry *);
161 static int64_t isa3_hashtb_pte_clear(mmu_t, struct pvo_entry *, uint64_t);
162 static int64_t isa3_hashtb_pte_replace(mmu_t, struct pvo_entry *, int);
163 static int64_t isa3_hashtb_pte_unset(mmu_t mmu, struct pvo_entry *);
168 static void isa3_hashtb_bootstrap(mmu_t mmup,
169 vm_offset_t kernelstart, vm_offset_t kernelend);
170 static void isa3_hashtb_cpu_bootstrap(mmu_t, int ap);
171 static void tlbia(void);
173 static mmu_method_t isa3_hashtb_methods[] = {
174 /* Internal interfaces */
175 MMUMETHOD(mmu_bootstrap, isa3_hashtb_bootstrap),
176 MMUMETHOD(mmu_cpu_bootstrap, isa3_hashtb_cpu_bootstrap),
178 MMUMETHOD(moea64_pte_synch, isa3_hashtb_pte_synch),
179 MMUMETHOD(moea64_pte_clear, isa3_hashtb_pte_clear),
180 MMUMETHOD(moea64_pte_unset, isa3_hashtb_pte_unset),
181 MMUMETHOD(moea64_pte_replace, isa3_hashtb_pte_replace),
182 MMUMETHOD(moea64_pte_insert, isa3_hashtb_pte_insert),
187 MMU_DEF_INHERIT(isa3_mmu_native, MMU_TYPE_P9H, isa3_hashtb_methods,
191 isa3_hashtb_pte_synch(mmu_t mmu, struct pvo_entry *pvo)
193 volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
194 struct lpte properpt;
197 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
199 moea64_pte_from_pvo(pvo, &properpt);
201 rw_rlock(&isa3_hashtb_eviction_lock);
202 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) !=
203 (properpt.pte_hi & LPTE_AVPN_MASK)) {
205 rw_runlock(&isa3_hashtb_eviction_lock);
210 ptelo = be64toh(pt->pte_lo);
212 rw_runlock(&isa3_hashtb_eviction_lock);
214 return (ptelo & (LPTE_REF | LPTE_CHG));
218 isa3_hashtb_pte_clear(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit)
220 volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
221 struct lpte properpt;
224 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
226 moea64_pte_from_pvo(pvo, &properpt);
228 rw_rlock(&isa3_hashtb_eviction_lock);
229 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) !=
230 (properpt.pte_hi & LPTE_AVPN_MASK)) {
232 rw_runlock(&isa3_hashtb_eviction_lock);
236 if (ptebit == LPTE_REF) {
237 /* See "Resetting the Reference Bit" in arch manual */
239 /* 2-step here safe: precision is not guaranteed */
240 ptelo = be64toh(pt->pte_lo);
242 /* One-byte store to avoid touching the C bit */
243 ((volatile uint8_t *)(&pt->pte_lo))[6] =
244 #if BYTE_ORDER == BIG_ENDIAN
245 ((uint8_t *)(&properpt.pte_lo))[6];
247 ((uint8_t *)(&properpt.pte_lo))[1];
249 rw_runlock(&isa3_hashtb_eviction_lock);
255 rw_runlock(&isa3_hashtb_eviction_lock);
256 ptelo = isa3_hashtb_pte_unset(mmu, pvo);
257 isa3_hashtb_pte_insert(mmu, pvo);
260 return (ptelo & (LPTE_REF | LPTE_CHG));
264 isa3_hashtb_pte_unset(mmu_t mmu, struct pvo_entry *pvo)
266 volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
267 struct lpte properpt;
270 moea64_pte_from_pvo(pvo, &properpt);
272 rw_rlock(&isa3_hashtb_eviction_lock);
273 if ((be64toh(pt->pte_hi & LPTE_AVPN_MASK)) !=
274 (properpt.pte_hi & LPTE_AVPN_MASK)) {
276 moea64_pte_overflow--;
277 rw_runlock(&isa3_hashtb_eviction_lock);
282 * Invalidate the pte, briefly locking it to collect RC bits. No
283 * atomics needed since this is protected against eviction by the lock.
287 pt->pte_hi = be64toh((pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED);
290 ptelo = be64toh(pt->pte_lo);
291 *((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */
293 rw_runlock(&isa3_hashtb_eviction_lock);
295 /* Keep statistics */
298 return (ptelo & (LPTE_CHG | LPTE_REF));
302 isa3_hashtb_pte_replace(mmu_t mmu, struct pvo_entry *pvo, int flags)
304 volatile struct lpte *pt = isa3_hashtb_pteg_table + pvo->pvo_pte.slot;
305 struct lpte properpt;
309 /* Just some software bits changing. */
310 moea64_pte_from_pvo(pvo, &properpt);
312 rw_rlock(&isa3_hashtb_eviction_lock);
313 if ((be64toh(pt->pte_hi) & LPTE_AVPN_MASK) !=
314 (properpt.pte_hi & LPTE_AVPN_MASK)) {
315 rw_runlock(&isa3_hashtb_eviction_lock);
318 pt->pte_hi = htobe64(properpt.pte_hi);
319 ptelo = be64toh(pt->pte_lo);
320 rw_runlock(&isa3_hashtb_eviction_lock);
322 /* Otherwise, need reinsertion and deletion */
323 ptelo = isa3_hashtb_pte_unset(mmu, pvo);
324 isa3_hashtb_pte_insert(mmu, pvo);
331 isa3_hashtb_cpu_bootstrap(mmu_t mmup, int ap)
334 struct slb *slb = PCPU_GET(aim.slb);
338 * Initialize segment registers and MMU
341 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR);
343 switch (mfpvr() >> 16) {
345 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_RADIX);
350 * Install kernel SLB entries
353 __asm __volatile ("slbia");
354 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
357 for (i = 0; i < n_slbs; i++) {
358 if (!(slb[i].slbe & SLBE_VALID))
361 __asm __volatile ("slbmte %0, %1" ::
362 "r"(slb[i].slbv), "r"(slb[i].slbe));
370 ((uintptr_t)isa3_part_table & ~DMAP_BASE_ADDRESS) |
371 flsl((PART_SIZE >> 12) - 1));
376 isa3_hashtb_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
377 vm_offset_t kernelend)
384 moea64_early_bootstrap(mmup, kernelstart, kernelend);
387 * Allocate PTEG table.
390 size = moea64_pteg_count * sizeof(struct lpteg);
391 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %lu bytes",
392 moea64_pteg_count, size);
393 rw_init(&isa3_hashtb_eviction_lock, "pte eviction");
396 * We now need to allocate memory. This memory, to be allocated,
397 * has to reside in a page table. The page table we are about to
398 * allocate. We don't have BAT. So drop to data real mode for a minute
399 * as a measure of last resort. We do this a couple times.
403 (struct pate *)moea64_bootstrap_alloc(PART_SIZE, PART_SIZE);
405 isa3_part_table = (struct pate *)PHYS_TO_DMAP(
406 (vm_offset_t)isa3_part_table);
408 * PTEG table must be aligned on a 256k boundary, but can be placed
409 * anywhere with that alignment on POWER ISA 3+ systems.
411 isa3_hashtb_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size,
412 MAX(256*1024, size));
414 isa3_hashtb_pteg_table =
415 (struct lpte *)PHYS_TO_DMAP((vm_offset_t)isa3_hashtb_pteg_table);
417 bzero(__DEVOLATILE(void *, isa3_part_table), PART_SIZE);
418 isa3_part_table[0].pagetab =
419 ((uintptr_t)isa3_hashtb_pteg_table & ~DMAP_BASE_ADDRESS) |
420 (uintptr_t)(flsl((moea64_pteg_count - 1) >> 11));
421 bzero(__DEVOLATILE(void *, isa3_hashtb_pteg_table), moea64_pteg_count *
422 sizeof(struct lpteg));
425 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", isa3_hashtb_pteg_table);
427 moea64_mid_bootstrap(mmup, kernelstart, kernelend);
430 * Add a mapping for the page table itself if there is no direct map.
432 if (!hw_direct_map) {
433 size = moea64_pteg_count * sizeof(struct lpteg);
434 off = (vm_offset_t)(isa3_hashtb_pteg_table);
436 for (pa = off; pa < off + size; pa += PAGE_SIZE)
441 /* Bring up virtual memory */
442 moea64_late_bootstrap(mmup, kernelstart, kernelend);
450 i = 0xc00; /* IS = 11 */
454 for (; i < 0x200000; i += 0x00001000) {
455 __asm __volatile("tlbiel %0" :: "r"(i));
463 atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi)
469 * Note: in principle, if just the locked bit were set here, we
470 * could avoid needing the eviction lock. However, eviction occurs
471 * so rarely that it isn't worth bothering about in practice.
475 "1:\tlwarx %1, 0, %3\n\t" /* load old value */
476 "and. %0,%1,%4\n\t" /* check if any bits set */
477 "bne 2f\n\t" /* exit if any set */
478 "stwcx. %5, 0, %3\n\t" /* attempt to store */
479 "bne- 1b\n\t" /* spin if failed */
480 "li %0, 1\n\t" /* success - retval = 1 */
481 "b 3f\n\t" /* we've succeeded */
483 "stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */
484 "li %0, 0\n\t" /* failure - retval = 0 */
486 : "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi)
487 : "r" ((volatile char *)&pte->pte_hi + 4),
488 "r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED),
490 : "cr0", "cr1", "cr2", "memory");
492 *oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf;
498 isa3_hashtb_insert_to_pteg(struct lpte *pvo_pt, uintptr_t slotbase,
501 volatile struct lpte *pt;
502 uint64_t oldptehi, va;
506 /* Start at a random slot */
508 for (j = 0; j < 8; j++) {
509 k = slotbase + (i + j) % 8;
510 pt = &isa3_hashtb_pteg_table[k];
511 /* Invalidate and seize lock only if no bits in mask set */
512 if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */
519 if (oldptehi & LPTE_VALID) {
520 KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry"));
522 * Need to invalidate old entry completely: see
523 * "Modifying a Page Table Entry". Need to reconstruct
524 * the virtual address for the outgoing entry to do that.
526 if (oldptehi & LPTE_BIG)
527 va = oldptehi >> moea64_large_page_shift;
529 va = oldptehi >> ADDR_PIDX_SHFT;
530 if (oldptehi & LPTE_HID)
531 va = (((k >> 3) ^ moea64_pteg_mask) ^ va) &
534 va = ((k >> 3) ^ va) & VSID_HASH_MASK;
535 va |= (oldptehi & LPTE_AVPN_MASK) <<
536 (ADDR_API_SHFT64 - ADDR_PIDX_SHFT);
540 moea64_pte_overflow++;
544 * Update the PTE as per "Adding a Page Table Entry". Lock is released
545 * by setting the high doubleworld.
547 pt->pte_lo = htobe64(pvo_pt->pte_lo);
549 pt->pte_hi = htobe64(pvo_pt->pte_hi);
552 /* Keep statistics */
559 isa3_hashtb_pte_insert(mmu_t mmu, struct pvo_entry *pvo)
561 struct lpte insertpt;
565 moea64_pte_from_pvo(pvo, &insertpt);
567 /* Make sure further insertion is locked out during evictions */
568 rw_rlock(&isa3_hashtb_eviction_lock);
571 * First try primary hash.
573 pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */
574 slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
575 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED);
577 rw_runlock(&isa3_hashtb_eviction_lock);
578 pvo->pvo_pte.slot = slot;
583 * Now try secondary hash.
585 pvo->pvo_vaddr ^= PVO_HID;
586 insertpt.pte_hi ^= LPTE_HID;
587 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
588 slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
589 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED);
591 rw_runlock(&isa3_hashtb_eviction_lock);
592 pvo->pvo_pte.slot = slot;
597 * Out of luck. Find a PTE to sacrifice.
600 /* Lock out all insertions for a bit */
601 if (!rw_try_upgrade(&isa3_hashtb_eviction_lock)) {
602 rw_runlock(&isa3_hashtb_eviction_lock);
603 rw_wlock(&isa3_hashtb_eviction_lock);
606 slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
607 LPTE_WIRED | LPTE_LOCKED);
609 rw_wunlock(&isa3_hashtb_eviction_lock);
610 pvo->pvo_pte.slot = slot;
614 /* Try other hash table. Now we're getting desperate... */
615 pvo->pvo_vaddr ^= PVO_HID;
616 insertpt.pte_hi ^= LPTE_HID;
617 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
618 slot = isa3_hashtb_insert_to_pteg(&insertpt, pvo->pvo_pte.slot,
619 LPTE_WIRED | LPTE_LOCKED);
621 rw_wunlock(&isa3_hashtb_eviction_lock);
622 pvo->pvo_pte.slot = slot;
626 /* No freeable slots in either PTEG? We're hosed. */
627 rw_wunlock(&isa3_hashtb_eviction_lock);
628 panic("moea64_pte_insert: overflow");