2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Copyright (C) 2001 Benno Rice
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include "opt_compat.h"
62 #include "opt_kstack_pages.h"
63 #include "opt_platform.h"
65 #include <sys/param.h>
67 #include <sys/systm.h>
73 #include <sys/eventhandler.h>
75 #include <sys/imgact.h>
77 #include <sys/kernel.h>
79 #include <sys/linker.h>
81 #include <sys/malloc.h>
83 #include <sys/msgbuf.h>
84 #include <sys/mutex.h>
85 #include <sys/ptrace.h>
86 #include <sys/reboot.h>
87 #include <sys/rwlock.h>
88 #include <sys/signalvar.h>
89 #include <sys/syscallsubr.h>
90 #include <sys/sysctl.h>
91 #include <sys/sysent.h>
92 #include <sys/sysproto.h>
93 #include <sys/ucontext.h>
95 #include <sys/vmmeter.h>
96 #include <sys/vnode.h>
98 #include <net/netisr.h>
101 #include <vm/vm_extern.h>
102 #include <vm/vm_kern.h>
103 #include <vm/vm_page.h>
104 #include <vm/vm_map.h>
105 #include <vm/vm_object.h>
106 #include <vm/vm_pager.h>
108 #include <machine/altivec.h>
109 #ifndef __powerpc64__
110 #include <machine/bat.h>
112 #include <machine/cpu.h>
113 #include <machine/elf.h>
114 #include <machine/fpu.h>
115 #include <machine/hid.h>
116 #include <machine/kdb.h>
117 #include <machine/md_var.h>
118 #include <machine/metadata.h>
119 #include <machine/mmuvar.h>
120 #include <machine/pcb.h>
121 #include <machine/reg.h>
122 #include <machine/sigframe.h>
123 #include <machine/spr.h>
124 #include <machine/trap.h>
125 #include <machine/vmparam.h>
126 #include <machine/ofw_machdep.h>
130 #include <dev/ofw/openfirm.h>
135 int cacheline_size = 128;
137 int cacheline_size = 32;
139 int hw_direct_map = 1;
141 extern void *ap_pcpu;
143 struct pcpu __pcpu[MAXCPU];
145 static struct trapframe frame0;
147 char machine[] = "powerpc";
148 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
150 static void cpu_startup(void *);
151 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
153 SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
154 CTLFLAG_RD, &cacheline_size, 0, "");
156 uintptr_t powerpc_init(vm_offset_t, vm_offset_t, vm_offset_t, void *);
161 #ifndef __powerpc64__
162 struct bat battable[16];
165 struct kva_md_info kmi;
168 cpu_startup(void *dummy)
172 * Initialise the decrementer-based clock.
177 * Good {morning,afternoon,evening,night}.
179 cpu_setup(PCPU_GET(cpuid));
184 printf("real memory = %ld (%ld MB)\n", ptoa(physmem),
185 ptoa(physmem) / 1048576);
189 printf("available KVA = %zd (%zd MB)\n",
190 virtual_end - virtual_avail,
191 (virtual_end - virtual_avail) / 1048576);
194 * Display any holes after the first chunk of extended memory.
199 printf("Physical memory chunk(s):\n");
200 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
202 phys_avail[indx + 1] - phys_avail[indx];
205 printf("0x%016lx - 0x%016lx, %ld bytes (%ld pages)\n",
207 printf("0x%08x - 0x%08x, %d bytes (%ld pages)\n",
209 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
214 vm_ksubmap_init(&kmi);
216 printf("avail memory = %ld (%ld MB)\n", ptoa(vm_cnt.v_free_count),
217 ptoa(vm_cnt.v_free_count) / 1048576);
220 * Set up buffers, so they can be used to read disk labels.
223 vm_pager_bufferinit();
226 extern vm_offset_t __startkernel, __endkernel;
227 extern unsigned char __bss_start[];
228 extern unsigned char __sbss_start[];
229 extern unsigned char __sbss_end[];
230 extern unsigned char _end[];
232 #ifndef __powerpc64__
233 /* Bits for running on 64-bit systems in 32-bit mode. */
234 extern void *testppc64, *testppc64size;
235 extern void *restorebridge, *restorebridgesize;
236 extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
237 extern void *trapcode64;
240 extern void *rstcode, *rstsize;
241 extern void *trapcode, *trapsize, *trapcode2;
242 extern void *slbtrap, *slbtrapsize;
243 extern void *alitrap, *alisize;
244 extern void *dsitrap, *dsisize;
245 extern void *decrint, *decrsize;
246 extern void *extint, *extsize;
247 extern void *dblow, *dbsize;
248 extern void *imisstrap, *imisssize;
249 extern void *dlmisstrap, *dlmisssize;
250 extern void *dsmisstrap, *dsmisssize;
253 powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
256 vm_offset_t startkernel, endkernel;
261 register_t msr, scratch;
265 uint8_t *cache_check;
267 #ifndef __powerpc64__
271 vm_offset_t ksym_start;
272 vm_offset_t ksym_end;
279 /* First guess at start/end kernel positions */
280 startkernel = __startkernel;
281 endkernel = __endkernel;
285 * The Wii loader doesn't pass us any environment so, mdp
286 * points to garbage at this point. The Wii CPU is a 750CL.
289 if ((vers & 0xfffff0e0) == (MPC750 << 16 | MPC750CL))
293 /* Check for ePAPR loader, which puts a magic value into r6 */
294 if (mdp == (void *)0x65504150)
298 * Parse metadata if present and fetch parameters. Must be done
299 * before console is inited so cninit gets the right value of
303 preload_metadata = mdp;
304 kmdp = preload_search_by_type("elf kernel");
306 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
307 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
308 endkernel = ulmax(endkernel, MD_FETCH(kmdp,
309 MODINFOMD_KERNEND, vm_offset_t));
311 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
312 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
313 db_fetch_ksymtab(ksym_start, ksym_end);
317 bzero(__sbss_start, __sbss_end - __sbss_start);
318 bzero(__bss_start, _end - __bss_start);
321 /* Store boot environment state */
322 OF_initial_setup((void *)fdt, NULL, (int (*)(void *))ofentry);
325 * Init params/tunables that can be overridden by the loader
330 * Start initializing proc0 and thread0.
332 proc_linkup0(&proc0, &thread0);
333 thread0.td_frame = &frame0;
336 * Set up per-cpu data.
339 pcpu_init(pc, 0, sizeof(struct pcpu));
340 pc->pc_curthread = &thread0;
342 __asm __volatile("mr 13,%0" :: "r"(pc->pc_curthread));
344 __asm __volatile("mr 2,%0" :: "r"(pc->pc_curthread));
348 __asm __volatile("mtsprg 0, %0" :: "r"(pc));
351 * Init mutexes, which we use heavily in PMAP
357 * Install the OF client interface
363 * Initialize the console before printing anything.
368 * Complain if there is no metadata.
370 if (mdp == NULL || kmdp == NULL) {
371 printf("powerpc_init: no loader metadata.\n");
380 /* Various very early CPU fix ups */
381 switch (mfpvr() >> 16) {
383 * PowerPC 970 CPUs have a misfeature requested by Apple that
384 * makes them pretend they have a 32-byte cacheline. Turn this
385 * off before we measure the cacheline size.
391 scratch = mfspr(SPR_HID5);
392 scratch &= ~HID5_970_DCBZ_SIZE_HI;
393 mtspr(SPR_HID5, scratch);
397 /* XXX: get from ibm,slb-size in device tree */
404 * Initialize the interrupt tables and figure out our cache line
405 * size and whether or not we need the 64-bit bridge code.
409 * Disable translation in case the vector area hasn't been
410 * mapped (G5). Note that no OFW calls can be made until
411 * translation is re-enabled.
415 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI);
418 * Measure the cacheline size using dcbz
420 * Use EXC_PGM as a playground. We are about to overwrite it
421 * anyway, we know it exists, and we know it is cache-aligned.
424 cache_check = (void *)EXC_PGM;
426 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++)
427 cache_check[cacheline_size] = 0xff;
429 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory");
431 /* Find the first byte dcbz did not zero to get the cache line size */
432 for (cacheline_size = 0; cacheline_size < 0x100 &&
433 cache_check[cacheline_size] == 0; cacheline_size++);
435 /* Work around psim bug */
436 if (cacheline_size == 0) {
441 /* Make sure the kernel icache is valid before we go too much further */
442 __syncicache((caddr_t)startkernel, endkernel - startkernel);
444 #ifndef __powerpc64__
446 * Figure out whether we need to use the 64 bit PMAP. This works by
447 * executing an instruction that is only legal on 64-bit PPC (mtmsrd),
448 * and setting ppc64 = 0 if that causes a trap.
453 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size);
454 __syncicache((void *)EXC_PGM, (size_t)&testppc64size);
462 : "=r"(scratch), "=r"(ppc64));
465 cpu_features |= PPC_FEATURE_64;
468 * Now copy restorebridge into all the handlers, if necessary,
469 * and set up the trap tables.
472 if (cpu_features & PPC_FEATURE_64) {
473 /* Patch the two instances of rfi -> rfid */
474 bcopy(&rfid_patch,&rfi_patch1,4);
476 /* rfi_patch2 is at the end of dbleave */
477 bcopy(&rfid_patch,&rfi_patch2,4);
481 * Copy a code snippet to restore 32-bit bridge mode
482 * to the top of every non-generic trap handler
485 trap_offset += (size_t)&restorebridgesize;
486 bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
487 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
488 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
489 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
490 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
491 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
492 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
495 * Set the common trap entry point to the one that
496 * knows to restore 32-bit operation on execution.
499 generictrap = &trapcode64;
501 generictrap = &trapcode;
504 #else /* powerpc64 */
505 cpu_features |= PPC_FEATURE_64;
506 generictrap = &trapcode;
508 /* Set TOC base so that the interrupt code can get at it */
509 *((void **)TRAP_GENTRAP) = &trapcode2;
510 *((register_t *)TRAP_TOCBASE) = toc;
513 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstsize);
516 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbsize);
517 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbsize);
518 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbsize);
519 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbsize);
521 bcopy(generictrap, (void *)EXC_MCHK, (size_t)&trapsize);
522 bcopy(generictrap, (void *)EXC_PGM, (size_t)&trapsize);
523 bcopy(generictrap, (void *)EXC_TRC, (size_t)&trapsize);
524 bcopy(generictrap, (void *)EXC_BPT, (size_t)&trapsize);
526 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&alisize);
527 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsisize);
528 bcopy(generictrap, (void *)EXC_ISI, (size_t)&trapsize);
530 bcopy(&slbtrap, (void *)EXC_DSE, (size_t)&slbtrapsize);
531 bcopy(&slbtrap, (void *)EXC_ISE, (size_t)&slbtrapsize);
533 bcopy(generictrap, (void *)EXC_EXI, (size_t)&trapsize);
534 bcopy(generictrap, (void *)EXC_FPU, (size_t)&trapsize);
535 bcopy(generictrap, (void *)EXC_DECR, (size_t)&trapsize);
536 bcopy(generictrap, (void *)EXC_SC, (size_t)&trapsize);
537 bcopy(generictrap, (void *)EXC_FPA, (size_t)&trapsize);
538 bcopy(generictrap, (void *)EXC_VEC, (size_t)&trapsize);
539 bcopy(generictrap, (void *)EXC_PERF, (size_t)&trapsize);
540 bcopy(generictrap, (void *)EXC_VECAST_G4, (size_t)&trapsize);
541 bcopy(generictrap, (void *)EXC_VECAST_G5, (size_t)&trapsize);
542 #ifndef __powerpc64__
543 /* G2-specific TLB miss helper handlers */
544 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
545 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
546 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize);
548 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
555 /* Warn if cachline size was not determined */
556 if (cacheline_warn == 1) {
557 printf("WARNING: cacheline size undetermined, setting to 32\n");
561 * Choose a platform module so we can get the physical memory map.
564 platform_probe_and_attach();
567 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority
568 * in case the platform module had a better idea of what we
571 if (cpu_features & PPC_FEATURE_64)
572 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC);
574 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC);
576 pmap_bootstrap(startkernel, endkernel);
577 mtmsr(PSL_KERNSET & ~PSL_EE);
580 * Initialize params/tunables that are derived from memsize
582 init_param2(physmem);
585 * Grab booted kernel's name
587 env = kern_getenv("kernelname");
589 strlcpy(kernelname, env, sizeof(kernelname));
594 * Finish setting up thread0.
596 thread0.td_pcb = (struct pcb *)
597 ((thread0.td_kstack + thread0.td_kstack_pages * PAGE_SIZE -
598 sizeof(struct pcb)) & ~15UL);
599 bzero((void *)thread0.td_pcb, sizeof(struct pcb));
600 pc->pc_curpcb = thread0.td_pcb;
602 /* Initialise the message buffer. */
603 msgbufinit(msgbufp, msgbufsize);
606 if (boothowto & RB_KDB)
607 kdb_enter(KDB_WHY_BOOTFLAGS,
608 "Boot flags requested debugger");
611 return (((uintptr_t)thread0.td_pcb -
612 (sizeof(struct callframe) - 3*sizeof(register_t))) & ~15UL);
616 bzero(void *buf, size_t len)
622 while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) {
627 while (len >= sizeof(u_long) * 8) {
629 *((u_long*) p + 1) = 0;
630 *((u_long*) p + 2) = 0;
631 *((u_long*) p + 3) = 0;
632 len -= sizeof(u_long) * 8;
633 *((u_long*) p + 4) = 0;
634 *((u_long*) p + 5) = 0;
635 *((u_long*) p + 6) = 0;
636 *((u_long*) p + 7) = 0;
637 p += sizeof(u_long) * 8;
640 while (len >= sizeof(u_long)) {
642 len -= sizeof(u_long);
658 * Flush the D-cache for non-DMA I/O so that the I-cache can
659 * be made coherent later.
662 cpu_flush_dcache(void *ptr, size_t len)
668 * Shutdown the CPU as much as possible.
678 ptrace_set_pc(struct thread *td, unsigned long addr)
680 struct trapframe *tf;
683 tf->srr0 = (register_t)addr;
689 ptrace_single_step(struct thread *td)
691 struct trapframe *tf;
700 ptrace_clear_single_step(struct thread *td)
702 struct trapframe *tf;
711 kdb_cpu_clear_singlestep(void)
714 kdb_frame->srr1 &= ~PSL_SE;
718 kdb_cpu_set_singlestep(void)
721 kdb_frame->srr1 |= PSL_SE;
725 * Initialise a struct pcpu.
728 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
731 /* Copy the SLB contents from the current CPU */
732 memcpy(pcpu->pc_slb, PCPU_GET(slb), sizeof(pcpu->pc_slb));
743 if (td->td_md.md_spinlock_count == 0) {
744 msr = intr_disable();
745 td->td_md.md_spinlock_count = 1;
746 td->td_md.md_saved_msr = msr;
748 td->td_md.md_spinlock_count++;
760 msr = td->td_md.md_saved_msr;
761 td->td_md.md_spinlock_count--;
762 if (td->td_md.md_spinlock_count == 0)
766 int db_trap_glue(struct trapframe *); /* Called from trap_subr.S */
769 db_trap_glue(struct trapframe *frame)
771 if (!(frame->srr1 & PSL_PR)
772 && (frame->exc == EXC_TRC || frame->exc == EXC_RUNMODETRC
773 || (frame->exc == EXC_PGM
774 && (frame->srr1 & 0x20000))
775 || frame->exc == EXC_BPT
776 || frame->exc == EXC_DSI)) {
777 int type = frame->exc;
779 /* Ignore DTrace traps. */
780 if (*(uint32_t *)frame->srr0 == EXC_DTRACE)
782 if (type == EXC_PGM && (frame->srr1 & 0x20000)) {
785 return (kdb_trap(type, 0, frame));
791 #ifndef __powerpc64__
794 va_to_vsid(pmap_t pm, vm_offset_t va)
796 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
802 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
808 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
810 flush_disable_caches(void)
814 register_t cache_reg;
815 volatile uint32_t *memp;
822 mtmsr(msr & ~(PSL_EE | PSL_DR));
823 msscr0 = mfspr(SPR_MSSCR0);
824 msscr0 &= ~MSSCR0_L2PFE;
825 mtspr(SPR_MSSCR0, msscr0);
828 __asm__ __volatile__("dssall; sync");
831 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
832 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
833 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
835 /* Lock the L1 Data cache. */
836 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
840 mtspr(SPR_LDSTCR, 0);
843 * Perform this in two stages: Flush the cache starting in RAM, then do it
846 memp = (volatile uint32_t *)0x00000000;
847 for (i = 0; i < 128 * 1024; i++) {
849 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
850 memp += 32/sizeof(*memp);
853 memp = (volatile uint32_t *)0xfff00000;
857 mtspr(SPR_LDSTCR, x);
858 for (i = 0; i < 128; i++) {
860 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
861 memp += 32/sizeof(*memp);
863 x = ((x << 1) | 1) & 0xff;
865 mtspr(SPR_LDSTCR, 0);
867 cache_reg = mfspr(SPR_L2CR);
868 if (cache_reg & L2CR_L2E) {
869 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
870 mtspr(SPR_L2CR, cache_reg);
872 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
873 while (mfspr(SPR_L2CR) & L2CR_L2HWF)
874 ; /* Busy wait for cache to flush */
876 cache_reg &= ~L2CR_L2E;
877 mtspr(SPR_L2CR, cache_reg);
879 mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
881 while (mfspr(SPR_L2CR) & L2CR_L2I)
882 ; /* Busy wait for L2 cache invalidate */
886 cache_reg = mfspr(SPR_L3CR);
887 if (cache_reg & L3CR_L3E) {
888 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
889 mtspr(SPR_L3CR, cache_reg);
891 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
892 while (mfspr(SPR_L3CR) & L3CR_L3HWF)
893 ; /* Busy wait for cache to flush */
895 cache_reg &= ~L3CR_L3E;
896 mtspr(SPR_L3CR, cache_reg);
898 mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
900 while (mfspr(SPR_L3CR) & L3CR_L3I)
901 ; /* Busy wait for L3 cache invalidate */
905 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
915 static u_quad_t timebase = 0;
916 static register_t sprgs[4];
917 static register_t srrs[2];
920 struct thread *fputd;
921 struct thread *vectd;
924 register_t saved_msr;
928 PCPU_SET(restore, &resetjb);
931 fputd = PCPU_GET(fputhread);
932 vectd = PCPU_GET(vecthread);
937 if (setjmp(resetjb) == 0) {
938 sprgs[0] = mfspr(SPR_SPRG0);
939 sprgs[1] = mfspr(SPR_SPRG1);
940 sprgs[2] = mfspr(SPR_SPRG2);
941 sprgs[3] = mfspr(SPR_SPRG3);
942 srrs[0] = mfspr(SPR_SRR0);
943 srrs[1] = mfspr(SPR_SRR1);
946 flush_disable_caches();
947 hid0 = mfspr(SPR_HID0);
948 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
951 msr = mfmsr() | PSL_POW;
952 mtspr(SPR_HID0, hid0);
959 PCPU_SET(curthread, curthread);
960 PCPU_SET(curpcb, curthread->td_pcb);
961 pmap_activate(curthread);
963 mtspr(SPR_SPRG0, sprgs[0]);
964 mtspr(SPR_SPRG1, sprgs[1]);
965 mtspr(SPR_SPRG2, sprgs[2]);
966 mtspr(SPR_SPRG3, sprgs[3]);
967 mtspr(SPR_SRR0, srrs[0]);
968 mtspr(SPR_SRR1, srrs[1]);
970 if (fputd == curthread)
971 enable_fpu(curthread);
972 if (vectd == curthread)
973 enable_vec(curthread);