2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
31 * Copyright (C) 1995, 1996 TooLs GmbH.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by TooLs GmbH.
45 * 4. The name of TooLs GmbH may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62 * Copyright (C) 2001 Benno Rice.
63 * All rights reserved.
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is also stored by the
93 * logical address mapping module, this module may throw away valid virtual
94 * to physical mappings at almost any time. However, invalidations of
95 * mappings must be done as requested.
97 * In order to cope with hardware architectures which make virtual to
98 * physical map invalidates expensive, this module may delay invalidate
99 * reduced protection operations until such time as they are actually
100 * necessary. This module is given full information as to which processors
101 * are currently using which maps, and to when physical maps must be made
105 #include "opt_kstack_pages.h"
107 #include <sys/param.h>
108 #include <sys/kernel.h>
109 #include <sys/conf.h>
110 #include <sys/queue.h>
111 #include <sys/cpuset.h>
112 #include <sys/kerneldump.h>
114 #include <sys/lock.h>
115 #include <sys/msgbuf.h>
116 #include <sys/mutex.h>
117 #include <sys/proc.h>
118 #include <sys/rwlock.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/systm.h>
122 #include <sys/vmmeter.h>
124 #include <dev/ofw/openfirm.h>
127 #include <vm/vm_param.h>
128 #include <vm/vm_kern.h>
129 #include <vm/vm_page.h>
130 #include <vm/vm_map.h>
131 #include <vm/vm_object.h>
132 #include <vm/vm_extern.h>
133 #include <vm/vm_pageout.h>
136 #include <machine/cpu.h>
137 #include <machine/platform.h>
138 #include <machine/bat.h>
139 #include <machine/frame.h>
140 #include <machine/md_var.h>
141 #include <machine/psl.h>
142 #include <machine/pte.h>
143 #include <machine/smp.h>
144 #include <machine/sr.h>
145 #include <machine/mmuvar.h>
146 #include <machine/trap.h>
152 #define TODO panic("%s: not implemented", __func__);
154 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
155 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
156 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
165 extern unsigned char _etext[];
166 extern unsigned char _end[];
169 * Map of physical memory regions.
171 static struct mem_region *regions;
172 static struct mem_region *pregions;
173 static u_int phys_avail_count;
174 static int regions_sz, pregions_sz;
175 static struct ofw_map *translations;
178 * Lock for the pteg and pvo tables.
180 struct mtx moea_table_mutex;
181 struct mtx moea_vsid_mutex;
183 /* tlbie instruction synchronization */
184 static struct mtx tlbie_mtx;
189 static struct pteg *moea_pteg_table;
190 u_int moea_pteg_count;
191 u_int moea_pteg_mask;
196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
197 struct pvo_head moea_pvo_kunmanaged =
198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
200 static struct rwlock_padalign pvh_global_lock;
202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
205 #define BPVO_POOL_SIZE 32768
206 static struct pvo_entry *moea_bpvo_pool;
207 static int moea_bpvo_pool_index = 0;
209 #define VSID_NBPW (sizeof(u_int32_t) * 8)
210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
212 static boolean_t moea_initialized = FALSE;
217 u_int moea_pte_valid = 0;
218 u_int moea_pte_overflow = 0;
219 u_int moea_pte_replacements = 0;
220 u_int moea_pvo_entries = 0;
221 u_int moea_pvo_enter_calls = 0;
222 u_int moea_pvo_remove_calls = 0;
223 u_int moea_pte_spills = 0;
224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
227 &moea_pte_overflow, 0, "");
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
229 &moea_pte_replacements, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
233 &moea_pvo_enter_calls, 0, "");
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
235 &moea_pvo_remove_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
237 &moea_pte_spills, 0, "");
240 * Allocate physical memory for use in moea_bootstrap.
242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
247 static int moea_pte_insert(u_int, struct pte *);
252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
253 vm_offset_t, vm_paddr_t, u_int, int);
254 static void moea_pvo_remove(struct pvo_entry *, int);
255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
262 vm_prot_t, u_int, int8_t);
263 static void moea_syncicache(vm_paddr_t, vm_size_t);
264 static boolean_t moea_query_bit(vm_page_t, int);
265 static u_int moea_clear_bit(vm_page_t, int);
266 static void moea_kremove(mmu_t, vm_offset_t);
267 int moea_pte_spill(vm_offset_t);
270 * Kernel MMU interface
272 void moea_clear_modify(mmu_t, vm_page_t);
273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
275 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int,
278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
283 void moea_init(mmu_t);
284 boolean_t moea_is_modified(mmu_t, vm_page_t);
285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
286 boolean_t moea_is_referenced(mmu_t, vm_page_t);
287 int moea_ts_referenced(mmu_t, vm_page_t);
288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
290 int moea_page_wired_mappings(mmu_t, vm_page_t);
291 void moea_pinit(mmu_t, pmap_t);
292 void moea_pinit0(mmu_t, pmap_t);
293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
295 void moea_qremove(mmu_t, vm_offset_t, int);
296 void moea_release(mmu_t, pmap_t);
297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
298 void moea_remove_all(mmu_t, vm_page_t);
299 void moea_remove_write(mmu_t, vm_page_t);
300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_zero_page(mmu_t, vm_page_t);
302 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
303 void moea_activate(mmu_t, struct thread *);
304 void moea_deactivate(mmu_t, struct thread *);
305 void moea_cpu_bootstrap(mmu_t, int);
306 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
307 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
308 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
309 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
310 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
311 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
312 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
313 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
314 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
315 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
316 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va);
317 void moea_scan_init(mmu_t mmu);
318 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m);
319 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr);
321 static mmu_method_t moea_methods[] = {
322 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
323 MMUMETHOD(mmu_copy_page, moea_copy_page),
324 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
325 MMUMETHOD(mmu_enter, moea_enter),
326 MMUMETHOD(mmu_enter_object, moea_enter_object),
327 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
328 MMUMETHOD(mmu_extract, moea_extract),
329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
330 MMUMETHOD(mmu_init, moea_init),
331 MMUMETHOD(mmu_is_modified, moea_is_modified),
332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
333 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
335 MMUMETHOD(mmu_map, moea_map),
336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
338 MMUMETHOD(mmu_pinit, moea_pinit),
339 MMUMETHOD(mmu_pinit0, moea_pinit0),
340 MMUMETHOD(mmu_protect, moea_protect),
341 MMUMETHOD(mmu_qenter, moea_qenter),
342 MMUMETHOD(mmu_qremove, moea_qremove),
343 MMUMETHOD(mmu_release, moea_release),
344 MMUMETHOD(mmu_remove, moea_remove),
345 MMUMETHOD(mmu_remove_all, moea_remove_all),
346 MMUMETHOD(mmu_remove_write, moea_remove_write),
347 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
348 MMUMETHOD(mmu_unwire, moea_unwire),
349 MMUMETHOD(mmu_zero_page, moea_zero_page),
350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
351 MMUMETHOD(mmu_activate, moea_activate),
352 MMUMETHOD(mmu_deactivate, moea_deactivate),
353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
354 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page),
355 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page),
357 /* Internal interfaces */
358 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
359 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
360 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
361 MMUMETHOD(mmu_mapdev, moea_mapdev),
362 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
363 MMUMETHOD(mmu_kextract, moea_kextract),
364 MMUMETHOD(mmu_kenter, moea_kenter),
365 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
366 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
367 MMUMETHOD(mmu_scan_init, moea_scan_init),
368 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
373 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
375 static __inline uint32_t
376 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
381 if (ma != VM_MEMATTR_DEFAULT) {
383 case VM_MEMATTR_UNCACHEABLE:
384 return (PTE_I | PTE_G);
385 case VM_MEMATTR_CACHEABLE:
387 case VM_MEMATTR_WRITE_COMBINING:
388 case VM_MEMATTR_WRITE_BACK:
389 case VM_MEMATTR_PREFETCHABLE:
391 case VM_MEMATTR_WRITE_THROUGH:
392 return (PTE_W | PTE_M);
397 * Assume the page is cache inhibited and access is guarded unless
398 * it's in our available memory array.
400 pte_lo = PTE_I | PTE_G;
401 for (i = 0; i < pregions_sz; i++) {
402 if ((pa >= pregions[i].mr_start) &&
403 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
413 tlbie(vm_offset_t va)
416 mtx_lock_spin(&tlbie_mtx);
417 __asm __volatile("ptesync");
418 __asm __volatile("tlbie %0" :: "r"(va));
419 __asm __volatile("eieio; tlbsync; ptesync");
420 mtx_unlock_spin(&tlbie_mtx);
428 for (va = 0; va < 0x00040000; va += 0x00001000) {
429 __asm __volatile("tlbie %0" :: "r"(va));
432 __asm __volatile("tlbsync");
437 va_to_sr(u_int *sr, vm_offset_t va)
439 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
442 static __inline u_int
443 va_to_pteg(u_int sr, vm_offset_t addr)
447 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
449 return (hash & moea_pteg_mask);
452 static __inline struct pvo_head *
453 vm_page_to_pvoh(vm_page_t m)
456 return (&m->md.mdpg_pvoh);
460 moea_attr_clear(vm_page_t m, int ptebit)
463 rw_assert(&pvh_global_lock, RA_WLOCKED);
464 m->md.mdpg_attrs &= ~ptebit;
468 moea_attr_fetch(vm_page_t m)
471 return (m->md.mdpg_attrs);
475 moea_attr_save(vm_page_t m, int ptebit)
478 rw_assert(&pvh_global_lock, RA_WLOCKED);
479 m->md.mdpg_attrs |= ptebit;
483 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
485 if (pt->pte_hi == pvo_pt->pte_hi)
492 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
494 return (pt->pte_hi & ~PTE_VALID) ==
495 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
496 ((va >> ADDR_API_SHFT) & PTE_API) | which);
500 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
503 mtx_assert(&moea_table_mutex, MA_OWNED);
506 * Construct a PTE. Default to IMB initially. Valid bit only gets
507 * set when the real pte is set in memory.
509 * Note: Don't set the valid bit for correct operation of tlb update.
511 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
512 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
517 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
520 mtx_assert(&moea_table_mutex, MA_OWNED);
521 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
525 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
528 mtx_assert(&moea_table_mutex, MA_OWNED);
531 * As shown in Section 7.6.3.2.3
533 pt->pte_lo &= ~ptebit;
538 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
541 mtx_assert(&moea_table_mutex, MA_OWNED);
542 pvo_pt->pte_hi |= PTE_VALID;
545 * Update the PTE as defined in section 7.6.3.1.
546 * Note that the REF/CHG bits are from pvo_pt and thus should have
547 * been saved so this routine can restore them (if desired).
549 pt->pte_lo = pvo_pt->pte_lo;
551 pt->pte_hi = pvo_pt->pte_hi;
557 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
560 mtx_assert(&moea_table_mutex, MA_OWNED);
561 pvo_pt->pte_hi &= ~PTE_VALID;
564 * Force the reg & chg bits back into the PTEs.
569 * Invalidate the pte.
571 pt->pte_hi &= ~PTE_VALID;
576 * Save the reg & chg bits.
578 moea_pte_synch(pt, pvo_pt);
583 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
589 moea_pte_unset(pt, pvo_pt, va);
590 moea_pte_set(pt, pvo_pt);
594 * Quick sort callout for comparing memory regions.
596 static int om_cmp(const void *a, const void *b);
599 om_cmp(const void *a, const void *b)
601 const struct ofw_map *mapa;
602 const struct ofw_map *mapb;
606 if (mapa->om_pa < mapb->om_pa)
608 else if (mapa->om_pa > mapb->om_pa)
615 moea_cpu_bootstrap(mmu_t mmup, int ap)
622 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
623 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
625 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
626 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
630 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
631 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
634 __asm __volatile("mtibatu 1,%0" :: "r"(0));
635 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
636 __asm __volatile("mtibatu 2,%0" :: "r"(0));
637 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
638 __asm __volatile("mtibatu 3,%0" :: "r"(0));
641 for (i = 0; i < 16; i++)
642 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
645 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
646 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
653 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
656 phandle_t chosen, mmu;
659 vm_size_t size, physsz, hwphyssz;
660 vm_offset_t pa, va, off;
665 * Set up BAT0 to map the lowest 256 MB area
667 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
668 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
671 * Map PCI memory space.
673 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
674 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
676 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
677 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
679 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
680 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
682 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
683 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
688 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
689 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
692 * Use an IBAT and a DBAT to map the bottom segment of memory
693 * where we are. Turn off instruction relocation temporarily
694 * to prevent faults while reprogramming the IBAT.
697 mtmsr(msr & ~PSL_IR);
698 __asm (".balign 32; \n"
699 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
700 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
701 :: "r"(battable[0].batu), "r"(battable[0].batl));
705 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
706 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
709 /* set global direct map flag */
712 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
713 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
715 for (i = 0; i < pregions_sz; i++) {
719 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
720 pregions[i].mr_start,
721 pregions[i].mr_start + pregions[i].mr_size,
722 pregions[i].mr_size);
724 * Install entries into the BAT table to allow all
725 * of physmem to be convered by on-demand BAT entries.
726 * The loop will sometimes set the same battable element
727 * twice, but that's fine since they won't be used for
730 pa = pregions[i].mr_start & 0xf0000000;
731 end = pregions[i].mr_start + pregions[i].mr_size;
733 u_int n = pa >> ADDR_SR_SHFT;
735 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
736 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
737 pa += SEGMENT_LENGTH;
741 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
742 panic("moea_bootstrap: phys_avail too small");
744 phys_avail_count = 0;
747 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
748 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
749 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
750 regions[i].mr_start + regions[i].mr_size,
753 (physsz + regions[i].mr_size) >= hwphyssz) {
754 if (physsz < hwphyssz) {
755 phys_avail[j] = regions[i].mr_start;
756 phys_avail[j + 1] = regions[i].mr_start +
763 phys_avail[j] = regions[i].mr_start;
764 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
766 physsz += regions[i].mr_size;
769 /* Check for overlap with the kernel and exception vectors */
770 for (j = 0; j < 2*phys_avail_count; j+=2) {
771 if (phys_avail[j] < EXC_LAST)
772 phys_avail[j] += EXC_LAST;
774 if (kernelstart >= phys_avail[j] &&
775 kernelstart < phys_avail[j+1]) {
776 if (kernelend < phys_avail[j+1]) {
777 phys_avail[2*phys_avail_count] =
778 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
779 phys_avail[2*phys_avail_count + 1] =
784 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
787 if (kernelend >= phys_avail[j] &&
788 kernelend < phys_avail[j+1]) {
789 if (kernelstart > phys_avail[j]) {
790 phys_avail[2*phys_avail_count] = phys_avail[j];
791 phys_avail[2*phys_avail_count + 1] =
792 kernelstart & ~PAGE_MASK;
796 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
800 physmem = btoc(physsz);
803 * Allocate PTEG table.
806 moea_pteg_count = PTEGCOUNT;
808 moea_pteg_count = 0x1000;
810 while (moea_pteg_count < physmem)
811 moea_pteg_count <<= 1;
813 moea_pteg_count >>= 1;
814 #endif /* PTEGCOUNT */
816 size = moea_pteg_count * sizeof(struct pteg);
817 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
819 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
820 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
821 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
822 moea_pteg_mask = moea_pteg_count - 1;
825 * Allocate pv/overflow lists.
827 size = sizeof(struct pvo_head) * moea_pteg_count;
828 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
830 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
831 for (i = 0; i < moea_pteg_count; i++)
832 LIST_INIT(&moea_pvo_table[i]);
835 * Initialize the lock that synchronizes access to the pteg and pvo
838 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
840 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
842 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
845 * Initialise the unmanaged pvo pool.
847 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
848 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
849 moea_bpvo_pool_index = 0;
852 * Make sure kernel vsid is allocated as well as VSID 0.
854 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
855 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
856 moea_vsid_bitmap[0] |= 1;
859 * Initialize the kernel pmap (which is statically allocated).
861 PMAP_LOCK_INIT(kernel_pmap);
862 for (i = 0; i < 16; i++)
863 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
864 CPU_FILL(&kernel_pmap->pm_active);
865 RB_INIT(&kernel_pmap->pmap_pvo);
868 * Initialize the global pv list lock.
870 rw_init(&pvh_global_lock, "pmap pv global");
873 * Set up the Open Firmware mappings
875 chosen = OF_finddevice("/chosen");
876 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
877 (mmu = OF_instance_to_package(mmui)) != -1 &&
878 (sz = OF_getproplen(mmu, "translations")) != -1) {
880 for (i = 0; phys_avail[i] != 0; i += 2) {
881 if (phys_avail[i + 1] >= sz) {
882 translations = (struct ofw_map *)phys_avail[i];
886 if (translations == NULL)
887 panic("moea_bootstrap: no space to copy translations");
888 bzero(translations, sz);
889 if (OF_getprop(mmu, "translations", translations, sz) == -1)
890 panic("moea_bootstrap: can't get ofw translations");
891 CTR0(KTR_PMAP, "moea_bootstrap: translations");
892 sz /= sizeof(*translations);
893 qsort(translations, sz, sizeof (*translations), om_cmp);
894 for (i = 0; i < sz; i++) {
895 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
896 translations[i].om_pa, translations[i].om_va,
897 translations[i].om_len);
900 * If the mapping is 1:1, let the RAM and device
901 * on-demand BAT tables take care of the translation.
903 if (translations[i].om_va == translations[i].om_pa)
906 /* Enter the pages */
907 for (off = 0; off < translations[i].om_len;
909 moea_kenter(mmup, translations[i].om_va + off,
910 translations[i].om_pa + off);
915 * Calculate the last available physical address.
917 for (i = 0; phys_avail[i + 2] != 0; i += 2)
919 Maxmem = powerpc_btop(phys_avail[i + 1]);
921 moea_cpu_bootstrap(mmup,0);
922 mtmsr(mfmsr() | PSL_DR | PSL_IR);
926 * Set the start and end of kva.
928 virtual_avail = VM_MIN_KERNEL_ADDRESS;
929 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
932 * Allocate a kernel stack with a guard page for thread0 and map it
933 * into the kernel page map.
935 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
936 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
937 virtual_avail = va + kstack_pages * PAGE_SIZE;
938 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
939 thread0.td_kstack = va;
940 thread0.td_kstack_pages = kstack_pages;
941 for (i = 0; i < kstack_pages; i++) {
942 moea_kenter(mmup, va, pa);
948 * Allocate virtual address space for the message buffer.
950 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
951 msgbufp = (struct msgbuf *)virtual_avail;
953 virtual_avail += round_page(msgbufsize);
954 while (va < virtual_avail) {
955 moea_kenter(mmup, va, pa);
961 * Allocate virtual address space for the dynamic percpu area.
963 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
964 dpcpu = (void *)virtual_avail;
966 virtual_avail += DPCPU_SIZE;
967 while (va < virtual_avail) {
968 moea_kenter(mmup, va, pa);
972 dpcpu_init(dpcpu, 0);
976 * Activate a user pmap. The pmap must be activated before it's address
977 * space can be accessed in any way.
980 moea_activate(mmu_t mmu, struct thread *td)
985 * Load all the data we need up front to encourage the compiler to
986 * not issue any loads while we have interrupts disabled below.
988 pm = &td->td_proc->p_vmspace->vm_pmap;
991 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
992 PCPU_SET(curpmap, pmr);
994 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
998 moea_deactivate(mmu_t mmu, struct thread *td)
1002 pm = &td->td_proc->p_vmspace->vm_pmap;
1003 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1004 PCPU_SET(curpmap, NULL);
1008 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1010 struct pvo_entry key, *pvo;
1013 key.pvo_vaddr = sva;
1014 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1015 pvo != NULL && PVO_VADDR(pvo) < eva;
1016 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1017 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1018 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo);
1019 pvo->pvo_vaddr &= ~PVO_WIRED;
1020 pm->pm_stats.wired_count--;
1026 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1031 dst = VM_PAGE_TO_PHYS(mdst);
1032 src = VM_PAGE_TO_PHYS(msrc);
1034 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1038 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1039 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1042 vm_offset_t a_pg_offset, b_pg_offset;
1045 while (xfersize > 0) {
1046 a_pg_offset = a_offset & PAGE_MASK;
1047 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1048 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1050 b_pg_offset = b_offset & PAGE_MASK;
1051 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1052 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1054 bcopy(a_cp, b_cp, cnt);
1062 * Zero a page of physical memory by temporarily mapping it into the tlb.
1065 moea_zero_page(mmu_t mmu, vm_page_t m)
1067 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1069 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1070 __asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1074 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1076 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1077 void *va = (void *)(pa + off);
1083 moea_quick_enter_page(mmu_t mmu, vm_page_t m)
1086 return (VM_PAGE_TO_PHYS(m));
1090 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1095 * Map the given physical page at the specified virtual address in the
1096 * target pmap with the protection requested. If specified the page
1097 * will be wired down.
1100 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1101 u_int flags, int8_t psind)
1106 rw_wlock(&pvh_global_lock);
1108 error = moea_enter_locked(pmap, va, m, prot, flags, psind);
1109 rw_wunlock(&pvh_global_lock);
1111 if (error != ENOMEM)
1112 return (KERN_SUCCESS);
1113 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1114 return (KERN_RESOURCE_SHORTAGE);
1115 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1121 * Map the given physical page at the specified virtual address in the
1122 * target pmap with the protection requested. If specified the page
1123 * will be wired down.
1125 * The global pvh and pmap must be locked.
1128 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1129 u_int flags, int8_t psind __unused)
1131 struct pvo_head *pvo_head;
1133 u_int pte_lo, pvo_flags;
1136 if (pmap_bootstrapped)
1137 rw_assert(&pvh_global_lock, RA_WLOCKED);
1138 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1139 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1140 VM_OBJECT_ASSERT_LOCKED(m->object);
1142 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) {
1143 pvo_head = &moea_pvo_kunmanaged;
1144 zone = moea_upvo_zone;
1147 pvo_head = vm_page_to_pvoh(m);
1148 zone = moea_mpvo_zone;
1149 pvo_flags = PVO_MANAGED;
1152 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1154 if (prot & VM_PROT_WRITE) {
1156 if (pmap_bootstrapped &&
1157 (m->oflags & VPO_UNMANAGED) == 0)
1158 vm_page_aflag_set(m, PGA_WRITEABLE);
1162 if ((flags & PMAP_ENTER_WIRED) != 0)
1163 pvo_flags |= PVO_WIRED;
1165 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1169 * Flush the real page from the instruction cache. This has be done
1170 * for all user mappings to prevent information leakage via the
1171 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1172 * mapping for a page.
1174 if (pmap != kernel_pmap && error == ENOENT &&
1175 (pte_lo & (PTE_I | PTE_G)) == 0)
1176 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1182 * Maps a sequence of resident pages belonging to the same object.
1183 * The sequence begins with the given page m_start. This page is
1184 * mapped at the given virtual address start. Each subsequent page is
1185 * mapped at a virtual address that is offset from start by the same
1186 * amount as the page is offset from m_start within the object. The
1187 * last page in the sequence is the page with the largest offset from
1188 * m_start that can be mapped at a virtual address less than the given
1189 * virtual address end. Not every virtual page between start and end
1190 * is mapped; only those for which a resident page exists with the
1191 * corresponding offset from m_start are mapped.
1194 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1195 vm_page_t m_start, vm_prot_t prot)
1198 vm_pindex_t diff, psize;
1200 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1202 psize = atop(end - start);
1204 rw_wlock(&pvh_global_lock);
1206 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1207 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1208 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1209 m = TAILQ_NEXT(m, listq);
1211 rw_wunlock(&pvh_global_lock);
1216 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1220 rw_wlock(&pvh_global_lock);
1222 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1224 rw_wunlock(&pvh_global_lock);
1229 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1231 struct pvo_entry *pvo;
1235 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1239 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1245 * Atomically extract and hold the physical page with the given
1246 * pmap and virtual address pair if that mapping permits the given
1250 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1252 struct pvo_entry *pvo;
1260 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1261 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1262 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1263 (prot & VM_PROT_WRITE) == 0)) {
1264 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1266 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1275 moea_init(mmu_t mmu)
1278 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1279 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1280 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1281 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1282 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1283 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1284 moea_initialized = TRUE;
1288 moea_is_referenced(mmu_t mmu, vm_page_t m)
1292 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1293 ("moea_is_referenced: page %p is not managed", m));
1294 rw_wlock(&pvh_global_lock);
1295 rv = moea_query_bit(m, PTE_REF);
1296 rw_wunlock(&pvh_global_lock);
1301 moea_is_modified(mmu_t mmu, vm_page_t m)
1305 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1306 ("moea_is_modified: page %p is not managed", m));
1309 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1310 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1311 * is clear, no PTEs can have PTE_CHG set.
1313 VM_OBJECT_ASSERT_WLOCKED(m->object);
1314 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1316 rw_wlock(&pvh_global_lock);
1317 rv = moea_query_bit(m, PTE_CHG);
1318 rw_wunlock(&pvh_global_lock);
1323 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1325 struct pvo_entry *pvo;
1329 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1330 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1336 moea_clear_modify(mmu_t mmu, vm_page_t m)
1339 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1340 ("moea_clear_modify: page %p is not managed", m));
1341 VM_OBJECT_ASSERT_WLOCKED(m->object);
1342 KASSERT(!vm_page_xbusied(m),
1343 ("moea_clear_modify: page %p is exclusive busy", m));
1346 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1347 * set. If the object containing the page is locked and the page is
1348 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1350 if ((m->aflags & PGA_WRITEABLE) == 0)
1352 rw_wlock(&pvh_global_lock);
1353 moea_clear_bit(m, PTE_CHG);
1354 rw_wunlock(&pvh_global_lock);
1358 * Clear the write and modified bits in each of the given page's mappings.
1361 moea_remove_write(mmu_t mmu, vm_page_t m)
1363 struct pvo_entry *pvo;
1368 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1369 ("moea_remove_write: page %p is not managed", m));
1372 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1373 * set by another thread while the object is locked. Thus,
1374 * if PGA_WRITEABLE is clear, no page table entries need updating.
1376 VM_OBJECT_ASSERT_WLOCKED(m->object);
1377 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1379 rw_wlock(&pvh_global_lock);
1380 lo = moea_attr_fetch(m);
1382 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1383 pmap = pvo->pvo_pmap;
1385 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1386 pt = moea_pvo_to_pte(pvo, -1);
1387 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1388 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1390 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1391 lo |= pvo->pvo_pte.pte.pte_lo;
1392 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1393 moea_pte_change(pt, &pvo->pvo_pte.pte,
1395 mtx_unlock(&moea_table_mutex);
1400 if ((lo & PTE_CHG) != 0) {
1401 moea_attr_clear(m, PTE_CHG);
1404 vm_page_aflag_clear(m, PGA_WRITEABLE);
1405 rw_wunlock(&pvh_global_lock);
1409 * moea_ts_referenced:
1411 * Return a count of reference bits for a page, clearing those bits.
1412 * It is not necessary for every reference bit to be cleared, but it
1413 * is necessary that 0 only be returned when there are truly no
1414 * reference bits set.
1416 * XXX: The exact number of bits to check and clear is a matter that
1417 * should be tested and standardized at some point in the future for
1418 * optimal aging of shared pages.
1421 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1425 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1426 ("moea_ts_referenced: page %p is not managed", m));
1427 rw_wlock(&pvh_global_lock);
1428 count = moea_clear_bit(m, PTE_REF);
1429 rw_wunlock(&pvh_global_lock);
1434 * Modify the WIMG settings of all mappings for a page.
1437 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1439 struct pvo_entry *pvo;
1440 struct pvo_head *pvo_head;
1445 if ((m->oflags & VPO_UNMANAGED) != 0) {
1446 m->md.mdpg_cache_attrs = ma;
1450 rw_wlock(&pvh_global_lock);
1451 pvo_head = vm_page_to_pvoh(m);
1452 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1454 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1455 pmap = pvo->pvo_pmap;
1457 pt = moea_pvo_to_pte(pvo, -1);
1458 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1459 pvo->pvo_pte.pte.pte_lo |= lo;
1461 moea_pte_change(pt, &pvo->pvo_pte.pte,
1463 if (pvo->pvo_pmap == kernel_pmap)
1466 mtx_unlock(&moea_table_mutex);
1469 m->md.mdpg_cache_attrs = ma;
1470 rw_wunlock(&pvh_global_lock);
1474 * Map a wired page into kernel virtual address space.
1477 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1480 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1484 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1490 if (va < VM_MIN_KERNEL_ADDRESS)
1491 panic("moea_kenter: attempt to enter non-kernel address %#x",
1495 pte_lo = moea_calc_wimg(pa, ma);
1497 PMAP_LOCK(kernel_pmap);
1498 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1499 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1501 if (error != 0 && error != ENOENT)
1502 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1505 PMAP_UNLOCK(kernel_pmap);
1509 * Extract the physical page address associated with the given kernel virtual
1513 moea_kextract(mmu_t mmu, vm_offset_t va)
1515 struct pvo_entry *pvo;
1519 * Allow direct mappings on 32-bit OEA
1521 if (va < VM_MIN_KERNEL_ADDRESS) {
1525 PMAP_LOCK(kernel_pmap);
1526 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1527 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1528 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1529 PMAP_UNLOCK(kernel_pmap);
1534 * Remove a wired page from kernel virtual address space.
1537 moea_kremove(mmu_t mmu, vm_offset_t va)
1540 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1544 * Map a range of physical addresses into kernel virtual address space.
1546 * The value passed in *virt is a suggested virtual address for the mapping.
1547 * Architectures which can support a direct-mapped physical to virtual region
1548 * can return the appropriate address within that region, leaving '*virt'
1549 * unchanged. We cannot and therefore do not; *virt is updated with the
1550 * first usable address after the mapped region.
1553 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1554 vm_paddr_t pa_end, int prot)
1556 vm_offset_t sva, va;
1560 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1561 moea_kenter(mmu, va, pa_start);
1567 * Returns true if the pmap's pv is one of the first
1568 * 16 pvs linked to from this page. This count may
1569 * be changed upwards or downwards in the future; it
1570 * is only necessary that true be returned for a small
1571 * subset of pmaps for proper page aging.
1574 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1577 struct pvo_entry *pvo;
1580 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1581 ("moea_page_exists_quick: page %p is not managed", m));
1584 rw_wlock(&pvh_global_lock);
1585 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1586 if (pvo->pvo_pmap == pmap) {
1593 rw_wunlock(&pvh_global_lock);
1598 * Return the number of managed mappings to the given physical page
1602 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1604 struct pvo_entry *pvo;
1608 if ((m->oflags & VPO_UNMANAGED) != 0)
1610 rw_wlock(&pvh_global_lock);
1611 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1612 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1614 rw_wunlock(&pvh_global_lock);
1618 static u_int moea_vsidcontext;
1621 moea_pinit(mmu_t mmu, pmap_t pmap)
1626 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1627 RB_INIT(&pmap->pmap_pvo);
1630 __asm __volatile("mftb %0" : "=r"(entropy));
1632 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1634 pmap->pmap_phys = pmap;
1638 mtx_lock(&moea_vsid_mutex);
1640 * Allocate some segment registers for this pmap.
1642 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1646 * Create a new value by mutiplying by a prime and adding in
1647 * entropy from the timebase register. This is to make the
1648 * VSID more random so that the PT hash function collides
1649 * less often. (Note that the prime casues gcc to do shifts
1650 * instead of a multiply.)
1652 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1653 hash = moea_vsidcontext & (NPMAPS - 1);
1654 if (hash == 0) /* 0 is special, avoid it */
1657 mask = 1 << (hash & (VSID_NBPW - 1));
1658 hash = (moea_vsidcontext & 0xfffff);
1659 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1660 /* anything free in this bucket? */
1661 if (moea_vsid_bitmap[n] == 0xffffffff) {
1662 entropy = (moea_vsidcontext >> 20);
1665 i = ffs(~moea_vsid_bitmap[n]) - 1;
1667 hash &= rounddown2(0xfffff, VSID_NBPW);
1670 KASSERT(!(moea_vsid_bitmap[n] & mask),
1671 ("Allocating in-use VSID group %#x\n", hash));
1672 moea_vsid_bitmap[n] |= mask;
1673 for (i = 0; i < 16; i++)
1674 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1675 mtx_unlock(&moea_vsid_mutex);
1679 mtx_unlock(&moea_vsid_mutex);
1680 panic("moea_pinit: out of segments");
1684 * Initialize the pmap associated with process 0.
1687 moea_pinit0(mmu_t mmu, pmap_t pm)
1691 moea_pinit(mmu, pm);
1692 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1696 * Set the physical protection on the specified range of this map as requested.
1699 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1702 struct pvo_entry *pvo, *tpvo, key;
1705 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1706 ("moea_protect: non current pmap"));
1708 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1709 moea_remove(mmu, pm, sva, eva);
1713 rw_wlock(&pvh_global_lock);
1715 key.pvo_vaddr = sva;
1716 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1717 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1718 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1721 * Grab the PTE pointer before we diddle with the cached PTE
1724 pt = moea_pvo_to_pte(pvo, -1);
1726 * Change the protection of the page.
1728 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1729 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1732 * If the PVO is in the page table, update that pte as well.
1735 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1736 mtx_unlock(&moea_table_mutex);
1739 rw_wunlock(&pvh_global_lock);
1744 * Map a list of wired pages into kernel virtual address space. This is
1745 * intended for temporary mappings which do not need page modification or
1746 * references recorded. Existing mappings in the region are overwritten.
1749 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1754 while (count-- > 0) {
1755 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1762 * Remove page mappings from kernel virtual address space. Intended for
1763 * temporary mappings entered by moea_qenter.
1766 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1771 while (count-- > 0) {
1772 moea_kremove(mmu, va);
1778 moea_release(mmu_t mmu, pmap_t pmap)
1783 * Free segment register's VSID
1785 if (pmap->pm_sr[0] == 0)
1786 panic("moea_release");
1788 mtx_lock(&moea_vsid_mutex);
1789 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1790 mask = 1 << (idx % VSID_NBPW);
1792 moea_vsid_bitmap[idx] &= ~mask;
1793 mtx_unlock(&moea_vsid_mutex);
1797 * Remove the given range of addresses from the specified map.
1800 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1802 struct pvo_entry *pvo, *tpvo, key;
1804 rw_wlock(&pvh_global_lock);
1806 key.pvo_vaddr = sva;
1807 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1808 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1809 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1810 moea_pvo_remove(pvo, -1);
1813 rw_wunlock(&pvh_global_lock);
1817 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1818 * will reflect changes in pte's back to the vm_page.
1821 moea_remove_all(mmu_t mmu, vm_page_t m)
1823 struct pvo_head *pvo_head;
1824 struct pvo_entry *pvo, *next_pvo;
1827 rw_wlock(&pvh_global_lock);
1828 pvo_head = vm_page_to_pvoh(m);
1829 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1830 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1832 pmap = pvo->pvo_pmap;
1834 moea_pvo_remove(pvo, -1);
1837 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1838 moea_attr_clear(m, PTE_CHG);
1841 vm_page_aflag_clear(m, PGA_WRITEABLE);
1842 rw_wunlock(&pvh_global_lock);
1846 * Allocate a physical page of memory directly from the phys_avail map.
1847 * Can only be called from moea_bootstrap before avail start and end are
1851 moea_bootstrap_alloc(vm_size_t size, u_int align)
1856 size = round_page(size);
1857 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1859 s = roundup2(phys_avail[i], align);
1864 if (s < phys_avail[i] || e > phys_avail[i + 1])
1867 if (s == phys_avail[i]) {
1868 phys_avail[i] += size;
1869 } else if (e == phys_avail[i + 1]) {
1870 phys_avail[i + 1] -= size;
1872 for (j = phys_avail_count * 2; j > i; j -= 2) {
1873 phys_avail[j] = phys_avail[j - 2];
1874 phys_avail[j + 1] = phys_avail[j - 1];
1877 phys_avail[i + 3] = phys_avail[i + 1];
1878 phys_avail[i + 1] = s;
1879 phys_avail[i + 2] = e;
1885 panic("moea_bootstrap_alloc: could not allocate memory");
1889 moea_syncicache(vm_paddr_t pa, vm_size_t len)
1891 __syncicache((void *)pa, len);
1895 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1896 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags)
1898 struct pvo_entry *pvo;
1905 moea_pvo_enter_calls++;
1910 * Compute the PTE Group index.
1913 sr = va_to_sr(pm->pm_sr, va);
1914 ptegidx = va_to_pteg(sr, va);
1917 * Remove any existing mapping for this page. Reuse the pvo entry if
1918 * there is a mapping.
1920 mtx_lock(&moea_table_mutex);
1921 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1922 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1923 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1924 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1925 (pte_lo & PTE_PP)) {
1927 * The PTE is not changing. Instead, this may
1928 * be a request to change the mapping's wired
1931 mtx_unlock(&moea_table_mutex);
1932 if ((flags & PVO_WIRED) != 0 &&
1933 (pvo->pvo_vaddr & PVO_WIRED) == 0) {
1934 pvo->pvo_vaddr |= PVO_WIRED;
1935 pm->pm_stats.wired_count++;
1936 } else if ((flags & PVO_WIRED) == 0 &&
1937 (pvo->pvo_vaddr & PVO_WIRED) != 0) {
1938 pvo->pvo_vaddr &= ~PVO_WIRED;
1939 pm->pm_stats.wired_count--;
1943 moea_pvo_remove(pvo, -1);
1949 * If we aren't overwriting a mapping, try to allocate.
1951 if (moea_initialized) {
1952 pvo = uma_zalloc(zone, M_NOWAIT);
1954 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1955 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1956 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1957 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1959 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1960 moea_bpvo_pool_index++;
1965 mtx_unlock(&moea_table_mutex);
1970 pvo->pvo_vaddr = va;
1972 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1973 pvo->pvo_vaddr &= ~ADDR_POFF;
1974 if (flags & PVO_WIRED)
1975 pvo->pvo_vaddr |= PVO_WIRED;
1976 if (pvo_head != &moea_pvo_kunmanaged)
1977 pvo->pvo_vaddr |= PVO_MANAGED;
1979 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1981 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1986 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
1989 * Remember if the list was empty and therefore will be the first
1992 if (LIST_FIRST(pvo_head) == NULL)
1994 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1996 if (pvo->pvo_vaddr & PVO_WIRED)
1997 pm->pm_stats.wired_count++;
1998 pm->pm_stats.resident_count++;
2000 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2001 KASSERT(i < 8, ("Invalid PTE index"));
2003 PVO_PTEGIDX_SET(pvo, i);
2005 panic("moea_pvo_enter: overflow");
2006 moea_pte_overflow++;
2008 mtx_unlock(&moea_table_mutex);
2010 return (first ? ENOENT : 0);
2014 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2019 * If there is an active pte entry, we need to deactivate it (and
2020 * save the ref & cfg bits).
2022 pt = moea_pvo_to_pte(pvo, pteidx);
2024 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2025 mtx_unlock(&moea_table_mutex);
2026 PVO_PTEGIDX_CLR(pvo);
2028 moea_pte_overflow--;
2032 * Update our statistics.
2034 pvo->pvo_pmap->pm_stats.resident_count--;
2035 if (pvo->pvo_vaddr & PVO_WIRED)
2036 pvo->pvo_pmap->pm_stats.wired_count--;
2039 * Save the REF/CHG bits into their cache if the page is managed.
2041 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2044 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2046 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2047 (PTE_REF | PTE_CHG));
2052 * Remove this PVO from the PV and pmap lists.
2054 LIST_REMOVE(pvo, pvo_vlink);
2055 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2058 * Remove this from the overflow list and return it to the pool
2059 * if we aren't going to reuse it.
2061 LIST_REMOVE(pvo, pvo_olink);
2062 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2063 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2064 moea_upvo_zone, pvo);
2066 moea_pvo_remove_calls++;
2070 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2075 * We can find the actual pte entry without searching by grabbing
2076 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2077 * noticing the HID bit.
2079 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2080 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2081 pteidx ^= moea_pteg_mask * 8;
2086 static struct pvo_entry *
2087 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2089 struct pvo_entry *pvo;
2094 sr = va_to_sr(pm->pm_sr, va);
2095 ptegidx = va_to_pteg(sr, va);
2097 mtx_lock(&moea_table_mutex);
2098 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2099 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2101 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2105 mtx_unlock(&moea_table_mutex);
2111 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2116 * If we haven't been supplied the ptegidx, calculate it.
2122 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2123 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2124 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2127 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2128 mtx_lock(&moea_table_mutex);
2130 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2131 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2132 "valid pte index", pvo);
2135 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2136 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2137 "pvo but no valid pte", pvo);
2140 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2141 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2142 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2143 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2146 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2148 panic("moea_pvo_to_pte: pvo %p pte does not match "
2149 "pte %p in moea_pteg_table", pvo, pt);
2152 mtx_assert(&moea_table_mutex, MA_OWNED);
2156 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2157 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2158 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2161 mtx_unlock(&moea_table_mutex);
2166 * XXX: THIS STUFF SHOULD BE IN pte.c?
2169 moea_pte_spill(vm_offset_t addr)
2171 struct pvo_entry *source_pvo, *victim_pvo;
2172 struct pvo_entry *pvo;
2181 ptegidx = va_to_pteg(sr, addr);
2184 * Have to substitute some entry. Use the primary hash for this.
2185 * Use low bits of timebase as random generator.
2187 pteg = &moea_pteg_table[ptegidx];
2188 mtx_lock(&moea_table_mutex);
2189 __asm __volatile("mftb %0" : "=r"(i));
2195 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2197 * We need to find a pvo entry for this address.
2199 if (source_pvo == NULL &&
2200 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2201 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2203 * Now found an entry to be spilled into the pteg.
2204 * The PTE is now valid, so we know it's active.
2206 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2209 PVO_PTEGIDX_SET(pvo, j);
2210 moea_pte_overflow--;
2211 mtx_unlock(&moea_table_mutex);
2217 if (victim_pvo != NULL)
2222 * We also need the pvo entry of the victim we are replacing
2223 * so save the R & C bits of the PTE.
2225 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2226 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2228 if (source_pvo != NULL)
2233 if (source_pvo == NULL) {
2234 mtx_unlock(&moea_table_mutex);
2238 if (victim_pvo == NULL) {
2239 if ((pt->pte_hi & PTE_HID) == 0)
2240 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2244 * If this is a secondary PTE, we need to search it's primary
2245 * pvo bucket for the matching PVO.
2247 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2250 * We also need the pvo entry of the victim we are
2251 * replacing so save the R & C bits of the PTE.
2253 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2259 if (victim_pvo == NULL)
2260 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2265 * We are invalidating the TLB entry for the EA we are replacing even
2266 * though it's valid. If we don't, we lose any ref/chg bit changes
2267 * contained in the TLB entry.
2269 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2271 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2272 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2274 PVO_PTEGIDX_CLR(victim_pvo);
2275 PVO_PTEGIDX_SET(source_pvo, i);
2276 moea_pte_replacements++;
2278 mtx_unlock(&moea_table_mutex);
2282 static __inline struct pvo_entry *
2283 moea_pte_spillable_ident(u_int ptegidx)
2286 struct pvo_entry *pvo_walk, *pvo = NULL;
2288 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2289 if (pvo_walk->pvo_vaddr & PVO_WIRED)
2292 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2295 pt = moea_pvo_to_pte(pvo_walk, -1);
2302 mtx_unlock(&moea_table_mutex);
2303 if (!(pt->pte_lo & PTE_REF))
2311 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2314 struct pvo_entry *victim_pvo;
2317 u_int pteg_bkpidx = ptegidx;
2319 mtx_assert(&moea_table_mutex, MA_OWNED);
2322 * First try primary hash.
2324 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2325 if ((pt->pte_hi & PTE_VALID) == 0) {
2326 pvo_pt->pte_hi &= ~PTE_HID;
2327 moea_pte_set(pt, pvo_pt);
2333 * Now try secondary hash.
2335 ptegidx ^= moea_pteg_mask;
2337 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2338 if ((pt->pte_hi & PTE_VALID) == 0) {
2339 pvo_pt->pte_hi |= PTE_HID;
2340 moea_pte_set(pt, pvo_pt);
2345 /* Try again, but this time try to force a PTE out. */
2346 ptegidx = pteg_bkpidx;
2348 victim_pvo = moea_pte_spillable_ident(ptegidx);
2349 if (victim_pvo == NULL) {
2350 ptegidx ^= moea_pteg_mask;
2351 victim_pvo = moea_pte_spillable_ident(ptegidx);
2354 if (victim_pvo == NULL) {
2355 panic("moea_pte_insert: overflow");
2359 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2361 if (pteg_bkpidx == ptegidx)
2362 pvo_pt->pte_hi &= ~PTE_HID;
2364 pvo_pt->pte_hi |= PTE_HID;
2367 * Synchronize the sacrifice PTE with its PVO, then mark both
2368 * invalid. The PVO will be reused when/if the VM system comes
2369 * here after a fault.
2371 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2373 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2374 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2379 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2380 PVO_PTEGIDX_CLR(victim_pvo);
2381 moea_pte_overflow++;
2382 moea_pte_set(pt, pvo_pt);
2384 return (victim_idx & 7);
2388 moea_query_bit(vm_page_t m, int ptebit)
2390 struct pvo_entry *pvo;
2393 rw_assert(&pvh_global_lock, RA_WLOCKED);
2394 if (moea_attr_fetch(m) & ptebit)
2397 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2400 * See if we saved the bit off. If so, cache it and return
2403 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2404 moea_attr_save(m, ptebit);
2410 * No luck, now go through the hard part of looking at the PTEs
2411 * themselves. Sync so that any pending REF/CHG bits are flushed to
2415 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2418 * See if this pvo has a valid PTE. if so, fetch the
2419 * REF/CHG bits from the valid PTE. If the appropriate
2420 * ptebit is set, cache it and return success.
2422 pt = moea_pvo_to_pte(pvo, -1);
2424 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2425 mtx_unlock(&moea_table_mutex);
2426 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2427 moea_attr_save(m, ptebit);
2437 moea_clear_bit(vm_page_t m, int ptebit)
2440 struct pvo_entry *pvo;
2443 rw_assert(&pvh_global_lock, RA_WLOCKED);
2446 * Clear the cached value.
2448 moea_attr_clear(m, ptebit);
2451 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2452 * we can reset the right ones). note that since the pvo entries and
2453 * list heads are accessed via BAT0 and are never placed in the page
2454 * table, we don't have to worry about further accesses setting the
2460 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2461 * valid pte clear the ptebit from the valid pte.
2464 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2465 pt = moea_pvo_to_pte(pvo, -1);
2467 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2468 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2470 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2472 mtx_unlock(&moea_table_mutex);
2474 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2481 * Return true if the physical range is encompassed by the battable[idx]
2484 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size)
2492 * Return immediately if not a valid mapping
2494 if (!(battable[idx].batu & BAT_Vs))
2498 * The BAT entry must be cache-inhibited, guarded, and r/w
2499 * so it can function as an i/o page
2501 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2502 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2506 * The address should be within the BAT range. Assume that the
2507 * start address in the BAT has the correct alignment (thus
2508 * not requiring masking)
2510 start = battable[idx].batl & BAT_PBS;
2511 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2512 end = start | (bat_ble << 15) | 0x7fff;
2514 if ((pa < start) || ((pa + size) > end))
2521 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2526 * This currently does not work for entries that
2527 * overlap 256M BAT segments.
2530 for(i = 0; i < 16; i++)
2531 if (moea_bat_mapped(i, pa, size) == 0)
2538 * Map a set of physical memory pages into the kernel virtual
2539 * address space. Return a pointer to where it is mapped. This
2540 * routine is intended to be used for mapping device memory,
2544 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2547 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2551 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2553 vm_offset_t va, tmpva, ppa, offset;
2556 ppa = trunc_page(pa);
2557 offset = pa & PAGE_MASK;
2558 size = roundup(offset + size, PAGE_SIZE);
2561 * If the physical address lies within a valid BAT table entry,
2562 * return the 1:1 mapping. This currently doesn't work
2563 * for regions that overlap 256M BAT segments.
2565 for (i = 0; i < 16; i++) {
2566 if (moea_bat_mapped(i, pa, size) == 0)
2567 return ((void *) pa);
2570 va = kva_alloc(size);
2572 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2574 for (tmpva = va; size > 0;) {
2575 moea_kenter_attr(mmu, tmpva, ppa, ma);
2582 return ((void *)(va + offset));
2586 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2588 vm_offset_t base, offset;
2591 * If this is outside kernel virtual space, then it's a
2592 * battable entry and doesn't require unmapping
2594 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2595 base = trunc_page(va);
2596 offset = va & PAGE_MASK;
2597 size = roundup(offset + size, PAGE_SIZE);
2598 kva_free(base, size);
2603 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2605 struct pvo_entry *pvo;
2612 lim = round_page(va);
2613 len = MIN(lim - va, sz);
2614 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2616 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2618 moea_syncicache(pa, len);
2627 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2633 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2636 moea_scan_init(mmu_t mmu)
2638 struct pvo_entry *pvo;
2643 /* Initialize phys. segments for dumpsys(). */
2644 memset(&dump_map, 0, sizeof(dump_map));
2645 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2646 for (i = 0; i < pregions_sz; i++) {
2647 dump_map[i].pa_start = pregions[i].mr_start;
2648 dump_map[i].pa_size = pregions[i].mr_size;
2653 /* Virtual segments for minidumps: */
2654 memset(&dump_map, 0, sizeof(dump_map));
2656 /* 1st: kernel .data and .bss. */
2657 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2658 dump_map[0].pa_size =
2659 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2661 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2662 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
2663 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2665 /* 3rd: kernel VM. */
2666 va = dump_map[1].pa_start + dump_map[1].pa_size;
2667 /* Find start of next chunk (from va). */
2668 while (va < virtual_end) {
2669 /* Don't dump the buffer cache. */
2670 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2671 va = kmi.buffer_eva;
2674 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
2675 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2679 if (va < virtual_end) {
2680 dump_map[2].pa_start = va;
2682 /* Find last page in chunk. */
2683 while (va < virtual_end) {
2684 /* Don't run into the buffer cache. */
2685 if (va == kmi.buffer_sva)
2687 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF,
2690 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2694 dump_map[2].pa_size = va - dump_map[2].pa_start;