2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/msgbuf.h>
124 #include <sys/mutex.h>
125 #include <sys/proc.h>
126 #include <sys/sysctl.h>
127 #include <sys/systm.h>
128 #include <sys/vmmeter.h>
130 #include <dev/ofw/openfirm.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
143 #include <machine/cpu.h>
144 #include <machine/powerpc.h>
145 #include <machine/bat.h>
146 #include <machine/frame.h>
147 #include <machine/md_var.h>
148 #include <machine/psl.h>
149 #include <machine/pte.h>
150 #include <machine/smp.h>
151 #include <machine/sr.h>
152 #include <machine/mmuvar.h>
158 #define TODO panic("%s: not implemented", __func__);
160 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
161 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
162 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
164 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */
165 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */
166 #define PVO_WIRED 0x010 /* PVO entry is wired */
167 #define PVO_MANAGED 0x020 /* PVO entry is managed */
168 #define PVO_EXECUTABLE 0x040 /* PVO entry is executable */
169 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during
171 #define PVO_FAKE 0x100 /* fictitious phys page */
172 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
173 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
174 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
175 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
176 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
177 #define PVO_PTEGIDX_CLR(pvo) \
178 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
179 #define PVO_PTEGIDX_SET(pvo, i) \
180 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
182 #define MOEA_PVO_CHECK(pvo)
192 * Map of physical memory regions.
194 static struct mem_region *regions;
195 static struct mem_region *pregions;
196 u_int phys_avail_count;
197 int regions_sz, pregions_sz;
198 static struct ofw_map *translations;
200 extern struct pmap ofw_pmap;
203 * Lock for the pteg and pvo tables.
205 struct mtx moea_table_mutex;
207 /* tlbie instruction synchronization */
208 static struct mtx tlbie_mtx;
213 static struct pteg *moea_pteg_table;
214 u_int moea_pteg_count;
215 u_int moea_pteg_mask;
220 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
221 struct pvo_head moea_pvo_kunmanaged =
222 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
223 struct pvo_head moea_pvo_unmanaged =
224 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */
226 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
227 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
229 #define BPVO_POOL_SIZE 32768
230 static struct pvo_entry *moea_bpvo_pool;
231 static int moea_bpvo_pool_index = 0;
233 #define VSID_NBPW (sizeof(u_int32_t) * 8)
234 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
236 static boolean_t moea_initialized = FALSE;
241 u_int moea_pte_valid = 0;
242 u_int moea_pte_overflow = 0;
243 u_int moea_pte_replacements = 0;
244 u_int moea_pvo_entries = 0;
245 u_int moea_pvo_enter_calls = 0;
246 u_int moea_pvo_remove_calls = 0;
247 u_int moea_pte_spills = 0;
248 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
250 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
251 &moea_pte_overflow, 0, "");
252 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
253 &moea_pte_replacements, 0, "");
254 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
256 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
257 &moea_pvo_enter_calls, 0, "");
258 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
259 &moea_pvo_remove_calls, 0, "");
260 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
261 &moea_pte_spills, 0, "");
264 * Allocate physical memory for use in moea_bootstrap.
266 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
271 static int moea_pte_insert(u_int, struct pte *);
276 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
277 vm_offset_t, vm_offset_t, u_int, int);
278 static void moea_pvo_remove(struct pvo_entry *, int);
279 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
280 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
285 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
286 vm_prot_t, boolean_t);
287 static void moea_syncicache(vm_offset_t, vm_size_t);
288 static boolean_t moea_query_bit(vm_page_t, int);
289 static u_int moea_clear_bit(vm_page_t, int, int *);
290 static void moea_kremove(mmu_t, vm_offset_t);
291 int moea_pte_spill(vm_offset_t);
294 * Kernel MMU interface
296 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
297 void moea_clear_modify(mmu_t, vm_page_t);
298 void moea_clear_reference(mmu_t, vm_page_t);
299 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
300 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
301 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
303 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
304 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
305 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
306 void moea_init(mmu_t);
307 boolean_t moea_is_modified(mmu_t, vm_page_t);
308 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
309 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
310 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
311 int moea_page_wired_mappings(mmu_t, vm_page_t);
312 void moea_pinit(mmu_t, pmap_t);
313 void moea_pinit0(mmu_t, pmap_t);
314 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
315 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
316 void moea_qremove(mmu_t, vm_offset_t, int);
317 void moea_release(mmu_t, pmap_t);
318 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
319 void moea_remove_all(mmu_t, vm_page_t);
320 void moea_remove_write(mmu_t, vm_page_t);
321 void moea_zero_page(mmu_t, vm_page_t);
322 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
323 void moea_zero_page_idle(mmu_t, vm_page_t);
324 void moea_activate(mmu_t, struct thread *);
325 void moea_deactivate(mmu_t, struct thread *);
326 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
327 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
328 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
329 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
330 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
331 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
332 boolean_t moea_page_executable(mmu_t, vm_page_t);
334 static mmu_method_t moea_methods[] = {
335 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
336 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
337 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
338 MMUMETHOD(mmu_copy_page, moea_copy_page),
339 MMUMETHOD(mmu_enter, moea_enter),
340 MMUMETHOD(mmu_enter_object, moea_enter_object),
341 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
342 MMUMETHOD(mmu_extract, moea_extract),
343 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
344 MMUMETHOD(mmu_init, moea_init),
345 MMUMETHOD(mmu_is_modified, moea_is_modified),
346 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
347 MMUMETHOD(mmu_map, moea_map),
348 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
349 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
350 MMUMETHOD(mmu_pinit, moea_pinit),
351 MMUMETHOD(mmu_pinit0, moea_pinit0),
352 MMUMETHOD(mmu_protect, moea_protect),
353 MMUMETHOD(mmu_qenter, moea_qenter),
354 MMUMETHOD(mmu_qremove, moea_qremove),
355 MMUMETHOD(mmu_release, moea_release),
356 MMUMETHOD(mmu_remove, moea_remove),
357 MMUMETHOD(mmu_remove_all, moea_remove_all),
358 MMUMETHOD(mmu_remove_write, moea_remove_write),
359 MMUMETHOD(mmu_zero_page, moea_zero_page),
360 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
361 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
362 MMUMETHOD(mmu_activate, moea_activate),
363 MMUMETHOD(mmu_deactivate, moea_deactivate),
365 /* Internal interfaces */
366 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
367 MMUMETHOD(mmu_mapdev, moea_mapdev),
368 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
369 MMUMETHOD(mmu_kextract, moea_kextract),
370 MMUMETHOD(mmu_kenter, moea_kenter),
371 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
372 MMUMETHOD(mmu_page_executable, moea_page_executable),
377 static mmu_def_t oea_mmu = {
385 tlbie(vm_offset_t va)
388 mtx_lock_spin(&tlbie_mtx);
389 __asm __volatile("tlbie %0" :: "r"(va));
390 __asm __volatile("tlbsync");
392 mtx_unlock_spin(&tlbie_mtx);
400 for (va = 0; va < 0x00040000; va += 0x00001000) {
401 __asm __volatile("tlbie %0" :: "r"(va));
404 __asm __volatile("tlbsync");
409 va_to_sr(u_int *sr, vm_offset_t va)
411 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
414 static __inline u_int
415 va_to_pteg(u_int sr, vm_offset_t addr)
419 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
421 return (hash & moea_pteg_mask);
424 static __inline struct pvo_head *
425 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p)
429 pg = PHYS_TO_VM_PAGE(pa);
435 return (&moea_pvo_unmanaged);
437 return (&pg->md.mdpg_pvoh);
440 static __inline struct pvo_head *
441 vm_page_to_pvoh(vm_page_t m)
444 return (&m->md.mdpg_pvoh);
448 moea_attr_clear(vm_page_t m, int ptebit)
451 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
452 m->md.mdpg_attrs &= ~ptebit;
456 moea_attr_fetch(vm_page_t m)
459 return (m->md.mdpg_attrs);
463 moea_attr_save(vm_page_t m, int ptebit)
466 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
467 m->md.mdpg_attrs |= ptebit;
471 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
473 if (pt->pte_hi == pvo_pt->pte_hi)
480 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
482 return (pt->pte_hi & ~PTE_VALID) ==
483 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
484 ((va >> ADDR_API_SHFT) & PTE_API) | which);
488 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
491 mtx_assert(&moea_table_mutex, MA_OWNED);
494 * Construct a PTE. Default to IMB initially. Valid bit only gets
495 * set when the real pte is set in memory.
497 * Note: Don't set the valid bit for correct operation of tlb update.
499 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
500 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
505 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
508 mtx_assert(&moea_table_mutex, MA_OWNED);
509 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
513 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
516 mtx_assert(&moea_table_mutex, MA_OWNED);
519 * As shown in Section 7.6.3.2.3
521 pt->pte_lo &= ~ptebit;
526 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
529 mtx_assert(&moea_table_mutex, MA_OWNED);
530 pvo_pt->pte_hi |= PTE_VALID;
533 * Update the PTE as defined in section 7.6.3.1.
534 * Note that the REF/CHG bits are from pvo_pt and thus should havce
535 * been saved so this routine can restore them (if desired).
537 pt->pte_lo = pvo_pt->pte_lo;
539 pt->pte_hi = pvo_pt->pte_hi;
545 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
548 mtx_assert(&moea_table_mutex, MA_OWNED);
549 pvo_pt->pte_hi &= ~PTE_VALID;
552 * Force the reg & chg bits back into the PTEs.
557 * Invalidate the pte.
559 pt->pte_hi &= ~PTE_VALID;
564 * Save the reg & chg bits.
566 moea_pte_synch(pt, pvo_pt);
571 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
577 moea_pte_unset(pt, pvo_pt, va);
578 moea_pte_set(pt, pvo_pt);
582 * Quick sort callout for comparing memory regions.
584 static int mr_cmp(const void *a, const void *b);
585 static int om_cmp(const void *a, const void *b);
588 mr_cmp(const void *a, const void *b)
590 const struct mem_region *regiona;
591 const struct mem_region *regionb;
595 if (regiona->mr_start < regionb->mr_start)
597 else if (regiona->mr_start > regionb->mr_start)
604 om_cmp(const void *a, const void *b)
606 const struct ofw_map *mapa;
607 const struct ofw_map *mapb;
611 if (mapa->om_pa < mapb->om_pa)
613 else if (mapa->om_pa > mapb->om_pa)
620 pmap_cpu_bootstrap(int ap)
627 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
628 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
630 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
631 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
635 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
636 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
639 __asm __volatile("mtibatu 1,%0" :: "r"(0));
640 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
641 __asm __volatile("mtibatu 2,%0" :: "r"(0));
642 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
643 __asm __volatile("mtibatu 3,%0" :: "r"(0));
646 for (i = 0; i < 16; i++)
647 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
649 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
650 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
653 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
654 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
661 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
664 phandle_t chosen, mmu;
668 vm_size_t size, physsz, hwphyssz;
669 vm_offset_t pa, va, off;
672 * Set up BAT0 to map the lowest 256 MB area
674 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
675 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
678 * Map PCI memory space.
680 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
681 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
683 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
684 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
686 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
687 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
689 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
690 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
695 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
696 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
699 * Use an IBAT and a DBAT to map the bottom segment of memory
702 __asm (".balign 32; \n"
703 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
704 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
705 :: "r"(battable[0].batu), "r"(battable[0].batl));
708 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
709 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
712 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
713 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
715 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
716 for (i = 0; i < pregions_sz; i++) {
720 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
721 pregions[i].mr_start,
722 pregions[i].mr_start + pregions[i].mr_size,
723 pregions[i].mr_size);
725 * Install entries into the BAT table to allow all
726 * of physmem to be convered by on-demand BAT entries.
727 * The loop will sometimes set the same battable element
728 * twice, but that's fine since they won't be used for
731 pa = pregions[i].mr_start & 0xf0000000;
732 end = pregions[i].mr_start + pregions[i].mr_size;
734 u_int n = pa >> ADDR_SR_SHFT;
736 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
737 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
738 pa += SEGMENT_LENGTH;
742 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
743 panic("moea_bootstrap: phys_avail too small");
744 qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
745 phys_avail_count = 0;
748 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
749 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
750 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
751 regions[i].mr_start + regions[i].mr_size,
754 (physsz + regions[i].mr_size) >= hwphyssz) {
755 if (physsz < hwphyssz) {
756 phys_avail[j] = regions[i].mr_start;
757 phys_avail[j + 1] = regions[i].mr_start +
764 phys_avail[j] = regions[i].mr_start;
765 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
767 physsz += regions[i].mr_size;
769 physmem = btoc(physsz);
772 * Allocate PTEG table.
775 moea_pteg_count = PTEGCOUNT;
777 moea_pteg_count = 0x1000;
779 while (moea_pteg_count < physmem)
780 moea_pteg_count <<= 1;
782 moea_pteg_count >>= 1;
783 #endif /* PTEGCOUNT */
785 size = moea_pteg_count * sizeof(struct pteg);
786 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
788 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
789 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
790 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
791 moea_pteg_mask = moea_pteg_count - 1;
794 * Allocate pv/overflow lists.
796 size = sizeof(struct pvo_head) * moea_pteg_count;
797 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
799 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
800 for (i = 0; i < moea_pteg_count; i++)
801 LIST_INIT(&moea_pvo_table[i]);
804 * Initialize the lock that synchronizes access to the pteg and pvo
807 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
810 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
813 * Initialise the unmanaged pvo pool.
815 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
816 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
817 moea_bpvo_pool_index = 0;
820 * Make sure kernel vsid is allocated as well as VSID 0.
822 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
823 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
824 moea_vsid_bitmap[0] |= 1;
827 * Set up the Open Firmware pmap and add it's mappings.
829 moea_pinit(mmup, &ofw_pmap);
830 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
831 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
832 if ((chosen = OF_finddevice("/chosen")) == -1)
833 panic("moea_bootstrap: can't find /chosen");
834 OF_getprop(chosen, "mmu", &mmui, 4);
835 if ((mmu = OF_instance_to_package(mmui)) == -1)
836 panic("moea_bootstrap: can't get mmu package");
837 if ((sz = OF_getproplen(mmu, "translations")) == -1)
838 panic("moea_bootstrap: can't get ofw translation count");
840 for (i = 0; phys_avail[i] != 0; i += 2) {
841 if (phys_avail[i + 1] >= sz) {
842 translations = (struct ofw_map *)phys_avail[i];
846 if (translations == NULL)
847 panic("moea_bootstrap: no space to copy translations");
848 bzero(translations, sz);
849 if (OF_getprop(mmu, "translations", translations, sz) == -1)
850 panic("moea_bootstrap: can't get ofw translations");
851 CTR0(KTR_PMAP, "moea_bootstrap: translations");
852 sz /= sizeof(*translations);
853 qsort(translations, sz, sizeof (*translations), om_cmp);
854 for (i = 0, ofw_mappings = 0; i < sz; i++) {
855 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
856 translations[i].om_pa, translations[i].om_va,
857 translations[i].om_len);
860 * If the mapping is 1:1, let the RAM and device on-demand
861 * BAT tables take care of the translation.
863 if (translations[i].om_va == translations[i].om_pa)
866 /* Enter the pages */
867 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
870 m.phys_addr = translations[i].om_pa + off;
871 PMAP_LOCK(&ofw_pmap);
872 moea_enter_locked(&ofw_pmap,
873 translations[i].om_va + off, &m,
875 PMAP_UNLOCK(&ofw_pmap);
881 * Calculate the last available physical address.
883 for (i = 0; phys_avail[i + 2] != 0; i += 2)
885 Maxmem = powerpc_btop(phys_avail[i + 1]);
888 * Initialize the kernel pmap (which is statically allocated).
890 PMAP_LOCK_INIT(kernel_pmap);
891 for (i = 0; i < 16; i++) {
892 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
894 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
895 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
896 kernel_pmap->pm_active = ~0;
898 pmap_cpu_bootstrap(0);
903 * Set the start and end of kva.
905 virtual_avail = VM_MIN_KERNEL_ADDRESS;
906 virtual_end = VM_MAX_KERNEL_ADDRESS;
909 * Allocate a kernel stack with a guard page for thread0 and map it
910 * into the kernel page map.
912 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
913 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
914 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
915 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
916 thread0.td_kstack = va;
917 thread0.td_kstack_pages = KSTACK_PAGES;
918 for (i = 0; i < KSTACK_PAGES; i++) {
919 moea_kenter(mmup, va, pa);;
925 * Allocate virtual address space for the message buffer.
927 pa = msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, PAGE_SIZE);
928 msgbufp = (struct msgbuf *)virtual_avail;
930 virtual_avail += round_page(MSGBUF_SIZE);
931 while (va < virtual_avail) {
932 moea_kenter(mmup, va, pa);;
939 * Activate a user pmap. The pmap must be activated before it's address
940 * space can be accessed in any way.
943 moea_activate(mmu_t mmu, struct thread *td)
948 * Load all the data we need up front to encourage the compiler to
949 * not issue any loads while we have interrupts disabled below.
951 pm = &td->td_proc->p_vmspace->vm_pmap;
954 pm->pm_active |= PCPU_GET(cpumask);
955 PCPU_SET(curpmap, pmr);
959 moea_deactivate(mmu_t mmu, struct thread *td)
963 pm = &td->td_proc->p_vmspace->vm_pmap;
964 pm->pm_active &= ~PCPU_GET(cpumask);
965 PCPU_SET(curpmap, NULL);
969 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
971 struct pvo_entry *pvo;
974 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
978 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
979 pm->pm_stats.wired_count++;
980 pvo->pvo_vaddr |= PVO_WIRED;
982 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
983 pm->pm_stats.wired_count--;
984 pvo->pvo_vaddr &= ~PVO_WIRED;
991 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
996 dst = VM_PAGE_TO_PHYS(mdst);
997 src = VM_PAGE_TO_PHYS(msrc);
999 kcopy((void *)src, (void *)dst, PAGE_SIZE);
1003 * Zero a page of physical memory by temporarily mapping it into the tlb.
1006 moea_zero_page(mmu_t mmu, vm_page_t m)
1008 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1009 void *va = (void *)pa;
1011 bzero(va, PAGE_SIZE);
1015 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1017 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1018 void *va = (void *)(pa + off);
1024 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1026 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1027 void *va = (void *)pa;
1029 bzero(va, PAGE_SIZE);
1033 * Map the given physical page at the specified virtual address in the
1034 * target pmap with the protection requested. If specified the page
1035 * will be wired down.
1038 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1042 vm_page_lock_queues();
1044 moea_enter_locked(pmap, va, m, prot, wired);
1045 vm_page_unlock_queues();
1050 * Map the given physical page at the specified virtual address in the
1051 * target pmap with the protection requested. If specified the page
1052 * will be wired down.
1054 * The page queues and pmap must be locked.
1057 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1060 struct pvo_head *pvo_head;
1063 u_int pte_lo, pvo_flags, was_exec, i;
1066 if (!moea_initialized) {
1067 pvo_head = &moea_pvo_kunmanaged;
1068 zone = moea_upvo_zone;
1071 was_exec = PTE_EXEC;
1073 pvo_head = vm_page_to_pvoh(m);
1075 zone = moea_mpvo_zone;
1076 pvo_flags = PVO_MANAGED;
1079 if (pmap_bootstrapped)
1080 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1081 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1083 /* XXX change the pvo head for fake pages */
1084 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS)
1085 pvo_head = &moea_pvo_kunmanaged;
1088 * If this is a managed page, and it's the first reference to the page,
1089 * clear the execness of the page. Otherwise fetch the execness.
1091 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) {
1092 if (LIST_EMPTY(pvo_head)) {
1093 moea_attr_clear(pg, PTE_EXEC);
1095 was_exec = moea_attr_fetch(pg) & PTE_EXEC;
1100 * Assume the page is cache inhibited and access is guarded unless
1101 * it's in our available memory array.
1103 pte_lo = PTE_I | PTE_G;
1104 for (i = 0; i < pregions_sz; i++) {
1105 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) &&
1106 (VM_PAGE_TO_PHYS(m) <
1107 (pregions[i].mr_start + pregions[i].mr_size))) {
1113 if (prot & VM_PROT_WRITE) {
1115 if (pmap_bootstrapped)
1116 vm_page_flag_set(m, PG_WRITEABLE);
1120 if (prot & VM_PROT_EXECUTE)
1121 pvo_flags |= PVO_EXECUTABLE;
1124 pvo_flags |= PVO_WIRED;
1126 if ((m->flags & PG_FICTITIOUS) != 0)
1127 pvo_flags |= PVO_FAKE;
1129 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1133 * Flush the real page from the instruction cache if this page is
1134 * mapped executable and cacheable and was not previously mapped (or
1135 * was not mapped executable).
1137 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
1138 (pte_lo & PTE_I) == 0 && was_exec == 0) {
1140 * Flush the real memory from the cache.
1142 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1144 moea_attr_save(pg, PTE_EXEC);
1147 /* XXX syncicache always until problems are sorted */
1148 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1152 * Maps a sequence of resident pages belonging to the same object.
1153 * The sequence begins with the given page m_start. This page is
1154 * mapped at the given virtual address start. Each subsequent page is
1155 * mapped at a virtual address that is offset from start by the same
1156 * amount as the page is offset from m_start within the object. The
1157 * last page in the sequence is the page with the largest offset from
1158 * m_start that can be mapped at a virtual address less than the given
1159 * virtual address end. Not every virtual page between start and end
1160 * is mapped; only those for which a resident page exists with the
1161 * corresponding offset from m_start are mapped.
1164 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1165 vm_page_t m_start, vm_prot_t prot)
1168 vm_pindex_t diff, psize;
1170 psize = atop(end - start);
1173 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1174 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1175 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1176 m = TAILQ_NEXT(m, listq);
1182 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1187 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1194 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1196 struct pvo_entry *pvo;
1200 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1204 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1210 * Atomically extract and hold the physical page with the given
1211 * pmap and virtual address pair if that mapping permits the given
1215 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1217 struct pvo_entry *pvo;
1221 vm_page_lock_queues();
1223 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1224 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1225 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1226 (prot & VM_PROT_WRITE) == 0)) {
1227 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1230 vm_page_unlock_queues();
1236 moea_init(mmu_t mmu)
1239 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1240 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1241 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1242 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1243 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1244 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1245 moea_initialized = TRUE;
1249 moea_is_modified(mmu_t mmu, vm_page_t m)
1252 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0)
1255 return (moea_query_bit(m, PTE_CHG));
1259 moea_clear_reference(mmu_t mmu, vm_page_t m)
1262 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1264 moea_clear_bit(m, PTE_REF, NULL);
1268 moea_clear_modify(mmu_t mmu, vm_page_t m)
1271 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1273 moea_clear_bit(m, PTE_CHG, NULL);
1277 * Clear the write and modified bits in each of the given page's mappings.
1280 moea_remove_write(mmu_t mmu, vm_page_t m)
1282 struct pvo_entry *pvo;
1287 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1288 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1289 (m->flags & PG_WRITEABLE) == 0)
1291 lo = moea_attr_fetch(m);
1293 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1294 pmap = pvo->pvo_pmap;
1296 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1297 pt = moea_pvo_to_pte(pvo, -1);
1298 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1299 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1301 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1302 lo |= pvo->pvo_pte.pte.pte_lo;
1303 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1304 moea_pte_change(pt, &pvo->pvo_pte.pte,
1306 mtx_unlock(&moea_table_mutex);
1311 if ((lo & PTE_CHG) != 0) {
1312 moea_attr_clear(m, PTE_CHG);
1315 vm_page_flag_clear(m, PG_WRITEABLE);
1319 * moea_ts_referenced:
1321 * Return a count of reference bits for a page, clearing those bits.
1322 * It is not necessary for every reference bit to be cleared, but it
1323 * is necessary that 0 only be returned when there are truly no
1324 * reference bits set.
1326 * XXX: The exact number of bits to check and clear is a matter that
1327 * should be tested and standardized at some point in the future for
1328 * optimal aging of shared pages.
1331 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1335 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1338 count = moea_clear_bit(m, PTE_REF, NULL);
1344 * Map a wired page into kernel virtual address space.
1347 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1354 if (va < VM_MIN_KERNEL_ADDRESS)
1355 panic("moea_kenter: attempt to enter non-kernel address %#x",
1359 pte_lo = PTE_I | PTE_G;
1360 for (i = 0; i < pregions_sz; i++) {
1361 if ((pa >= pregions[i].mr_start) &&
1362 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
1368 PMAP_LOCK(kernel_pmap);
1369 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1370 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1372 if (error != 0 && error != ENOENT)
1373 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1377 * Flush the real memory from the instruction cache.
1379 if ((pte_lo & (PTE_I | PTE_G)) == 0) {
1380 moea_syncicache(pa, PAGE_SIZE);
1382 PMAP_UNLOCK(kernel_pmap);
1386 * Extract the physical page address associated with the given kernel virtual
1390 moea_kextract(mmu_t mmu, vm_offset_t va)
1392 struct pvo_entry *pvo;
1396 * Allow direct mappings on 32-bit OEA
1398 if (va < VM_MIN_KERNEL_ADDRESS) {
1402 PMAP_LOCK(kernel_pmap);
1403 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1404 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1405 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1406 PMAP_UNLOCK(kernel_pmap);
1411 * Remove a wired page from kernel virtual address space.
1414 moea_kremove(mmu_t mmu, vm_offset_t va)
1417 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1421 * Map a range of physical addresses into kernel virtual address space.
1423 * The value passed in *virt is a suggested virtual address for the mapping.
1424 * Architectures which can support a direct-mapped physical to virtual region
1425 * can return the appropriate address within that region, leaving '*virt'
1426 * unchanged. We cannot and therefore do not; *virt is updated with the
1427 * first usable address after the mapped region.
1430 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1431 vm_offset_t pa_end, int prot)
1433 vm_offset_t sva, va;
1437 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1438 moea_kenter(mmu, va, pa_start);
1444 * Returns true if the pmap's pv is one of the first
1445 * 16 pvs linked to from this page. This count may
1446 * be changed upwards or downwards in the future; it
1447 * is only necessary that true be returned for a small
1448 * subset of pmaps for proper page aging.
1451 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1454 struct pvo_entry *pvo;
1456 if (!moea_initialized || (m->flags & PG_FICTITIOUS))
1460 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1461 if (pvo->pvo_pmap == pmap)
1471 * Return the number of managed mappings to the given physical page
1475 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1477 struct pvo_entry *pvo;
1481 if (!moea_initialized || (m->flags & PG_FICTITIOUS) != 0)
1483 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1484 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1485 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1490 static u_int moea_vsidcontext;
1493 moea_pinit(mmu_t mmu, pmap_t pmap)
1498 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1499 PMAP_LOCK_INIT(pmap);
1502 __asm __volatile("mftb %0" : "=r"(entropy));
1504 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1506 pmap->pmap_phys = pmap;
1511 * Allocate some segment registers for this pmap.
1513 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1517 * Create a new value by mutiplying by a prime and adding in
1518 * entropy from the timebase register. This is to make the
1519 * VSID more random so that the PT hash function collides
1520 * less often. (Note that the prime casues gcc to do shifts
1521 * instead of a multiply.)
1523 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1524 hash = moea_vsidcontext & (NPMAPS - 1);
1525 if (hash == 0) /* 0 is special, avoid it */
1528 mask = 1 << (hash & (VSID_NBPW - 1));
1529 hash = (moea_vsidcontext & 0xfffff);
1530 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1531 /* anything free in this bucket? */
1532 if (moea_vsid_bitmap[n] == 0xffffffff) {
1533 entropy = (moea_vsidcontext >> 20);
1536 i = ffs(~moea_vsid_bitmap[i]) - 1;
1538 hash &= 0xfffff & ~(VSID_NBPW - 1);
1541 moea_vsid_bitmap[n] |= mask;
1542 for (i = 0; i < 16; i++)
1543 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1547 panic("moea_pinit: out of segments");
1551 * Initialize the pmap associated with process 0.
1554 moea_pinit0(mmu_t mmu, pmap_t pm)
1557 moea_pinit(mmu, pm);
1558 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1562 * Set the physical protection on the specified range of this map as requested.
1565 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1568 struct pvo_entry *pvo;
1572 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1573 ("moea_protect: non current pmap"));
1575 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1576 moea_remove(mmu, pm, sva, eva);
1580 vm_page_lock_queues();
1582 for (; sva < eva; sva += PAGE_SIZE) {
1583 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1587 if ((prot & VM_PROT_EXECUTE) == 0)
1588 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1591 * Grab the PTE pointer before we diddle with the cached PTE
1594 pt = moea_pvo_to_pte(pvo, pteidx);
1596 * Change the protection of the page.
1598 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1599 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1602 * If the PVO is in the page table, update that pte as well.
1605 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1606 mtx_unlock(&moea_table_mutex);
1609 vm_page_unlock_queues();
1614 * Map a list of wired pages into kernel virtual address space. This is
1615 * intended for temporary mappings which do not need page modification or
1616 * references recorded. Existing mappings in the region are overwritten.
1619 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1624 while (count-- > 0) {
1625 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1632 * Remove page mappings from kernel virtual address space. Intended for
1633 * temporary mappings entered by moea_qenter.
1636 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1641 while (count-- > 0) {
1642 moea_kremove(mmu, va);
1648 moea_release(mmu_t mmu, pmap_t pmap)
1653 * Free segment register's VSID
1655 if (pmap->pm_sr[0] == 0)
1656 panic("moea_release");
1658 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1659 mask = 1 << (idx % VSID_NBPW);
1661 moea_vsid_bitmap[idx] &= ~mask;
1662 PMAP_LOCK_DESTROY(pmap);
1666 * Remove the given range of addresses from the specified map.
1669 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1671 struct pvo_entry *pvo;
1674 vm_page_lock_queues();
1676 for (; sva < eva; sva += PAGE_SIZE) {
1677 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1679 moea_pvo_remove(pvo, pteidx);
1683 vm_page_unlock_queues();
1687 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1688 * will reflect changes in pte's back to the vm_page.
1691 moea_remove_all(mmu_t mmu, vm_page_t m)
1693 struct pvo_head *pvo_head;
1694 struct pvo_entry *pvo, *next_pvo;
1697 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1699 pvo_head = vm_page_to_pvoh(m);
1700 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1701 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1703 MOEA_PVO_CHECK(pvo); /* sanity check */
1704 pmap = pvo->pvo_pmap;
1706 moea_pvo_remove(pvo, -1);
1709 vm_page_flag_clear(m, PG_WRITEABLE);
1713 * Allocate a physical page of memory directly from the phys_avail map.
1714 * Can only be called from moea_bootstrap before avail start and end are
1718 moea_bootstrap_alloc(vm_size_t size, u_int align)
1723 size = round_page(size);
1724 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1726 s = (phys_avail[i] + align - 1) & ~(align - 1);
1731 if (s < phys_avail[i] || e > phys_avail[i + 1])
1734 if (s == phys_avail[i]) {
1735 phys_avail[i] += size;
1736 } else if (e == phys_avail[i + 1]) {
1737 phys_avail[i + 1] -= size;
1739 for (j = phys_avail_count * 2; j > i; j -= 2) {
1740 phys_avail[j] = phys_avail[j - 2];
1741 phys_avail[j + 1] = phys_avail[j - 1];
1744 phys_avail[i + 3] = phys_avail[i + 1];
1745 phys_avail[i + 1] = s;
1746 phys_avail[i + 2] = e;
1752 panic("moea_bootstrap_alloc: could not allocate memory");
1756 moea_syncicache(vm_offset_t pa, vm_size_t len)
1758 __syncicache((void *)pa, len);
1762 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1763 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1765 struct pvo_entry *pvo;
1772 moea_pvo_enter_calls++;
1777 * Compute the PTE Group index.
1780 sr = va_to_sr(pm->pm_sr, va);
1781 ptegidx = va_to_pteg(sr, va);
1784 * Remove any existing mapping for this page. Reuse the pvo entry if
1785 * there is a mapping.
1787 mtx_lock(&moea_table_mutex);
1788 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1789 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1790 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1791 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1792 (pte_lo & PTE_PP)) {
1793 mtx_unlock(&moea_table_mutex);
1796 moea_pvo_remove(pvo, -1);
1802 * If we aren't overwriting a mapping, try to allocate.
1804 if (moea_initialized) {
1805 pvo = uma_zalloc(zone, M_NOWAIT);
1807 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1808 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1809 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1810 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1812 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1813 moea_bpvo_pool_index++;
1818 mtx_unlock(&moea_table_mutex);
1823 pvo->pvo_vaddr = va;
1825 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1826 pvo->pvo_vaddr &= ~ADDR_POFF;
1827 if (flags & VM_PROT_EXECUTE)
1828 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1829 if (flags & PVO_WIRED)
1830 pvo->pvo_vaddr |= PVO_WIRED;
1831 if (pvo_head != &moea_pvo_kunmanaged)
1832 pvo->pvo_vaddr |= PVO_MANAGED;
1834 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1835 if (flags & PVO_FAKE)
1836 pvo->pvo_vaddr |= PVO_FAKE;
1838 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1841 * Remember if the list was empty and therefore will be the first
1844 if (LIST_FIRST(pvo_head) == NULL)
1846 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1848 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1849 pm->pm_stats.wired_count++;
1850 pm->pm_stats.resident_count++;
1853 * We hope this succeeds but it isn't required.
1855 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1857 PVO_PTEGIDX_SET(pvo, i);
1859 panic("moea_pvo_enter: overflow");
1860 moea_pte_overflow++;
1862 mtx_unlock(&moea_table_mutex);
1864 return (first ? ENOENT : 0);
1868 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1873 * If there is an active pte entry, we need to deactivate it (and
1874 * save the ref & cfg bits).
1876 pt = moea_pvo_to_pte(pvo, pteidx);
1878 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1879 mtx_unlock(&moea_table_mutex);
1880 PVO_PTEGIDX_CLR(pvo);
1882 moea_pte_overflow--;
1886 * Update our statistics.
1888 pvo->pvo_pmap->pm_stats.resident_count--;
1889 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1890 pvo->pvo_pmap->pm_stats.wired_count--;
1893 * Save the REF/CHG bits into their cache if the page is managed.
1895 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
1898 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1900 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
1901 (PTE_REF | PTE_CHG));
1906 * Remove this PVO from the PV list.
1908 LIST_REMOVE(pvo, pvo_vlink);
1911 * Remove this from the overflow list and return it to the pool
1912 * if we aren't going to reuse it.
1914 LIST_REMOVE(pvo, pvo_olink);
1915 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
1916 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
1917 moea_upvo_zone, pvo);
1919 moea_pvo_remove_calls++;
1923 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
1928 * We can find the actual pte entry without searching by grabbing
1929 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
1930 * noticing the HID bit.
1932 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
1933 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
1934 pteidx ^= moea_pteg_mask * 8;
1939 static struct pvo_entry *
1940 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
1942 struct pvo_entry *pvo;
1947 sr = va_to_sr(pm->pm_sr, va);
1948 ptegidx = va_to_pteg(sr, va);
1950 mtx_lock(&moea_table_mutex);
1951 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1952 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1954 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
1958 mtx_unlock(&moea_table_mutex);
1964 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
1969 * If we haven't been supplied the ptegidx, calculate it.
1975 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
1976 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
1977 pteidx = moea_pvo_pte_index(pvo, ptegidx);
1980 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
1981 mtx_lock(&moea_table_mutex);
1983 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
1984 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
1985 "valid pte index", pvo);
1988 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
1989 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
1990 "pvo but no valid pte", pvo);
1993 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
1994 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
1995 panic("moea_pvo_to_pte: pvo %p has valid pte in "
1996 "moea_pteg_table %p but invalid in pvo", pvo, pt);
1999 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2001 panic("moea_pvo_to_pte: pvo %p pte does not match "
2002 "pte %p in moea_pteg_table", pvo, pt);
2005 mtx_assert(&moea_table_mutex, MA_OWNED);
2009 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2010 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2011 "moea_pteg_table but valid in pvo", pvo, pt);
2014 mtx_unlock(&moea_table_mutex);
2019 * XXX: THIS STUFF SHOULD BE IN pte.c?
2022 moea_pte_spill(vm_offset_t addr)
2024 struct pvo_entry *source_pvo, *victim_pvo;
2025 struct pvo_entry *pvo;
2034 ptegidx = va_to_pteg(sr, addr);
2037 * Have to substitute some entry. Use the primary hash for this.
2038 * Use low bits of timebase as random generator.
2040 pteg = &moea_pteg_table[ptegidx];
2041 mtx_lock(&moea_table_mutex);
2042 __asm __volatile("mftb %0" : "=r"(i));
2048 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2050 * We need to find a pvo entry for this address.
2052 MOEA_PVO_CHECK(pvo);
2053 if (source_pvo == NULL &&
2054 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2055 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2057 * Now found an entry to be spilled into the pteg.
2058 * The PTE is now valid, so we know it's active.
2060 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2063 PVO_PTEGIDX_SET(pvo, j);
2064 moea_pte_overflow--;
2065 MOEA_PVO_CHECK(pvo);
2066 mtx_unlock(&moea_table_mutex);
2072 if (victim_pvo != NULL)
2077 * We also need the pvo entry of the victim we are replacing
2078 * so save the R & C bits of the PTE.
2080 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2081 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2083 if (source_pvo != NULL)
2088 if (source_pvo == NULL) {
2089 mtx_unlock(&moea_table_mutex);
2093 if (victim_pvo == NULL) {
2094 if ((pt->pte_hi & PTE_HID) == 0)
2095 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2099 * If this is a secondary PTE, we need to search it's primary
2100 * pvo bucket for the matching PVO.
2102 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2104 MOEA_PVO_CHECK(pvo);
2106 * We also need the pvo entry of the victim we are
2107 * replacing so save the R & C bits of the PTE.
2109 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2115 if (victim_pvo == NULL)
2116 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2121 * We are invalidating the TLB entry for the EA we are replacing even
2122 * though it's valid. If we don't, we lose any ref/chg bit changes
2123 * contained in the TLB entry.
2125 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2127 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2128 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2130 PVO_PTEGIDX_CLR(victim_pvo);
2131 PVO_PTEGIDX_SET(source_pvo, i);
2132 moea_pte_replacements++;
2134 MOEA_PVO_CHECK(victim_pvo);
2135 MOEA_PVO_CHECK(source_pvo);
2137 mtx_unlock(&moea_table_mutex);
2142 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2147 mtx_assert(&moea_table_mutex, MA_OWNED);
2150 * First try primary hash.
2152 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2153 if ((pt->pte_hi & PTE_VALID) == 0) {
2154 pvo_pt->pte_hi &= ~PTE_HID;
2155 moea_pte_set(pt, pvo_pt);
2161 * Now try secondary hash.
2163 ptegidx ^= moea_pteg_mask;
2165 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2166 if ((pt->pte_hi & PTE_VALID) == 0) {
2167 pvo_pt->pte_hi |= PTE_HID;
2168 moea_pte_set(pt, pvo_pt);
2173 panic("moea_pte_insert: overflow");
2178 moea_query_bit(vm_page_t m, int ptebit)
2180 struct pvo_entry *pvo;
2184 if (moea_attr_fetch(m) & ptebit)
2188 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2189 MOEA_PVO_CHECK(pvo); /* sanity check */
2192 * See if we saved the bit off. If so, cache it and return
2195 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2196 moea_attr_save(m, ptebit);
2197 MOEA_PVO_CHECK(pvo); /* sanity check */
2203 * No luck, now go through the hard part of looking at the PTEs
2204 * themselves. Sync so that any pending REF/CHG bits are flushed to
2208 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2209 MOEA_PVO_CHECK(pvo); /* sanity check */
2212 * See if this pvo has a valid PTE. if so, fetch the
2213 * REF/CHG bits from the valid PTE. If the appropriate
2214 * ptebit is set, cache it and return success.
2216 pt = moea_pvo_to_pte(pvo, -1);
2218 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2219 mtx_unlock(&moea_table_mutex);
2220 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2221 moea_attr_save(m, ptebit);
2222 MOEA_PVO_CHECK(pvo); /* sanity check */
2232 moea_clear_bit(vm_page_t m, int ptebit, int *origbit)
2235 struct pvo_entry *pvo;
2240 * Clear the cached value.
2242 rv = moea_attr_fetch(m);
2243 moea_attr_clear(m, ptebit);
2246 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2247 * we can reset the right ones). note that since the pvo entries and
2248 * list heads are accessed via BAT0 and are never placed in the page
2249 * table, we don't have to worry about further accesses setting the
2255 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2256 * valid pte clear the ptebit from the valid pte.
2259 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2260 MOEA_PVO_CHECK(pvo); /* sanity check */
2261 pt = moea_pvo_to_pte(pvo, -1);
2263 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2264 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2266 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2268 mtx_unlock(&moea_table_mutex);
2270 rv |= pvo->pvo_pte.pte.pte_lo;
2271 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2272 MOEA_PVO_CHECK(pvo); /* sanity check */
2275 if (origbit != NULL) {
2283 * Return true if the physical range is encompassed by the battable[idx]
2286 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2294 * Return immediately if not a valid mapping
2296 if (!battable[idx].batu & BAT_Vs)
2300 * The BAT entry must be cache-inhibited, guarded, and r/w
2301 * so it can function as an i/o page
2303 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2304 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2308 * The address should be within the BAT range. Assume that the
2309 * start address in the BAT has the correct alignment (thus
2310 * not requiring masking)
2312 start = battable[idx].batl & BAT_PBS;
2313 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2314 end = start | (bat_ble << 15) | 0x7fff;
2316 if ((pa < start) || ((pa + size) > end))
2323 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2328 * This currently does not work for entries that
2329 * overlap 256M BAT segments.
2332 for(i = 0; i < 16; i++)
2333 if (moea_bat_mapped(i, pa, size) == 0)
2340 moea_page_executable(mmu_t mmu, vm_page_t pg)
2342 return ((moea_attr_fetch(pg) & PTE_EXEC) == PTE_EXEC);
2346 * Map a set of physical memory pages into the kernel virtual
2347 * address space. Return a pointer to where it is mapped. This
2348 * routine is intended to be used for mapping device memory,
2352 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2354 vm_offset_t va, tmpva, ppa, offset;
2357 ppa = trunc_page(pa);
2358 offset = pa & PAGE_MASK;
2359 size = roundup(offset + size, PAGE_SIZE);
2364 * If the physical address lies within a valid BAT table entry,
2365 * return the 1:1 mapping. This currently doesn't work
2366 * for regions that overlap 256M BAT segments.
2368 for (i = 0; i < 16; i++) {
2369 if (moea_bat_mapped(i, pa, size) == 0)
2370 return ((void *) pa);
2373 va = kmem_alloc_nofault(kernel_map, size);
2375 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2377 for (tmpva = va; size > 0;) {
2378 moea_kenter(mmu, tmpva, ppa);
2385 return ((void *)(va + offset));
2389 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2391 vm_offset_t base, offset;
2394 * If this is outside kernel virtual space, then it's a
2395 * battable entry and doesn't require unmapping
2397 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2398 base = trunc_page(va);
2399 offset = va & PAGE_MASK;
2400 size = roundup(offset + size, PAGE_SIZE);
2401 kmem_free(kernel_map, base, size);