2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
121 #include <sys/queue.h>
122 #include <sys/cpuset.h>
124 #include <sys/lock.h>
125 #include <sys/msgbuf.h>
126 #include <sys/mutex.h>
127 #include <sys/proc.h>
128 #include <sys/sched.h>
129 #include <sys/sysctl.h>
130 #include <sys/systm.h>
131 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
143 #include <vm/vm_pager.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/bat.h>
149 #include <machine/frame.h>
150 #include <machine/md_var.h>
151 #include <machine/psl.h>
152 #include <machine/pte.h>
153 #include <machine/smp.h>
154 #include <machine/sr.h>
155 #include <machine/mmuvar.h>
156 #include <machine/trap_aim.h>
162 #define TODO panic("%s: not implemented", __func__);
164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
165 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
176 * Map of physical memory regions.
178 static struct mem_region *regions;
179 static struct mem_region *pregions;
180 static u_int phys_avail_count;
181 static int regions_sz, pregions_sz;
182 static struct ofw_map *translations;
185 * Lock for the pteg and pvo tables.
187 struct mtx moea_table_mutex;
188 struct mtx moea_vsid_mutex;
190 /* tlbie instruction synchronization */
191 static struct mtx tlbie_mtx;
196 static struct pteg *moea_pteg_table;
197 u_int moea_pteg_count;
198 u_int moea_pteg_mask;
203 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
204 struct pvo_head moea_pvo_kunmanaged =
205 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
207 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
208 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
210 #define BPVO_POOL_SIZE 32768
211 static struct pvo_entry *moea_bpvo_pool;
212 static int moea_bpvo_pool_index = 0;
214 #define VSID_NBPW (sizeof(u_int32_t) * 8)
215 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
217 static boolean_t moea_initialized = FALSE;
222 u_int moea_pte_valid = 0;
223 u_int moea_pte_overflow = 0;
224 u_int moea_pte_replacements = 0;
225 u_int moea_pvo_entries = 0;
226 u_int moea_pvo_enter_calls = 0;
227 u_int moea_pvo_remove_calls = 0;
228 u_int moea_pte_spills = 0;
229 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
232 &moea_pte_overflow, 0, "");
233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
234 &moea_pte_replacements, 0, "");
235 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
238 &moea_pvo_enter_calls, 0, "");
239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
240 &moea_pvo_remove_calls, 0, "");
241 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
242 &moea_pte_spills, 0, "");
245 * Allocate physical memory for use in moea_bootstrap.
247 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
252 static int moea_pte_insert(u_int, struct pte *);
257 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
258 vm_offset_t, vm_offset_t, u_int, int);
259 static void moea_pvo_remove(struct pvo_entry *, int);
260 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
261 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
266 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
267 vm_prot_t, boolean_t);
268 static void moea_syncicache(vm_offset_t, vm_size_t);
269 static boolean_t moea_query_bit(vm_page_t, int);
270 static u_int moea_clear_bit(vm_page_t, int);
271 static void moea_kremove(mmu_t, vm_offset_t);
272 int moea_pte_spill(vm_offset_t);
275 * Kernel MMU interface
277 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
278 void moea_clear_modify(mmu_t, vm_page_t);
279 void moea_clear_reference(mmu_t, vm_page_t);
280 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
281 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
287 void moea_init(mmu_t);
288 boolean_t moea_is_modified(mmu_t, vm_page_t);
289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
290 boolean_t moea_is_referenced(mmu_t, vm_page_t);
291 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
294 int moea_page_wired_mappings(mmu_t, vm_page_t);
295 void moea_pinit(mmu_t, pmap_t);
296 void moea_pinit0(mmu_t, pmap_t);
297 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
298 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
299 void moea_qremove(mmu_t, vm_offset_t, int);
300 void moea_release(mmu_t, pmap_t);
301 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
302 void moea_remove_all(mmu_t, vm_page_t);
303 void moea_remove_write(mmu_t, vm_page_t);
304 void moea_zero_page(mmu_t, vm_page_t);
305 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
306 void moea_zero_page_idle(mmu_t, vm_page_t);
307 void moea_activate(mmu_t, struct thread *);
308 void moea_deactivate(mmu_t, struct thread *);
309 void moea_cpu_bootstrap(mmu_t, int);
310 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
311 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
312 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
313 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
314 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
315 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
316 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
317 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
318 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
319 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
321 static mmu_method_t moea_methods[] = {
322 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
323 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
324 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
325 MMUMETHOD(mmu_copy_page, moea_copy_page),
326 MMUMETHOD(mmu_enter, moea_enter),
327 MMUMETHOD(mmu_enter_object, moea_enter_object),
328 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
329 MMUMETHOD(mmu_extract, moea_extract),
330 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
331 MMUMETHOD(mmu_init, moea_init),
332 MMUMETHOD(mmu_is_modified, moea_is_modified),
333 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
334 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
335 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
336 MMUMETHOD(mmu_map, moea_map),
337 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
338 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
339 MMUMETHOD(mmu_pinit, moea_pinit),
340 MMUMETHOD(mmu_pinit0, moea_pinit0),
341 MMUMETHOD(mmu_protect, moea_protect),
342 MMUMETHOD(mmu_qenter, moea_qenter),
343 MMUMETHOD(mmu_qremove, moea_qremove),
344 MMUMETHOD(mmu_release, moea_release),
345 MMUMETHOD(mmu_remove, moea_remove),
346 MMUMETHOD(mmu_remove_all, moea_remove_all),
347 MMUMETHOD(mmu_remove_write, moea_remove_write),
348 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
349 MMUMETHOD(mmu_zero_page, moea_zero_page),
350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
351 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
352 MMUMETHOD(mmu_activate, moea_activate),
353 MMUMETHOD(mmu_deactivate, moea_deactivate),
354 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
356 /* Internal interfaces */
357 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
358 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
359 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
360 MMUMETHOD(mmu_mapdev, moea_mapdev),
361 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
362 MMUMETHOD(mmu_kextract, moea_kextract),
363 MMUMETHOD(mmu_kenter, moea_kenter),
364 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
365 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
370 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
372 static __inline uint32_t
373 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
378 if (ma != VM_MEMATTR_DEFAULT) {
380 case VM_MEMATTR_UNCACHEABLE:
381 return (PTE_I | PTE_G);
382 case VM_MEMATTR_WRITE_COMBINING:
383 case VM_MEMATTR_WRITE_BACK:
384 case VM_MEMATTR_PREFETCHABLE:
386 case VM_MEMATTR_WRITE_THROUGH:
387 return (PTE_W | PTE_M);
392 * Assume the page is cache inhibited and access is guarded unless
393 * it's in our available memory array.
395 pte_lo = PTE_I | PTE_G;
396 for (i = 0; i < pregions_sz; i++) {
397 if ((pa >= pregions[i].mr_start) &&
398 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
408 tlbie(vm_offset_t va)
411 mtx_lock_spin(&tlbie_mtx);
412 __asm __volatile("ptesync");
413 __asm __volatile("tlbie %0" :: "r"(va));
414 __asm __volatile("eieio; tlbsync; ptesync");
415 mtx_unlock_spin(&tlbie_mtx);
423 for (va = 0; va < 0x00040000; va += 0x00001000) {
424 __asm __volatile("tlbie %0" :: "r"(va));
427 __asm __volatile("tlbsync");
432 va_to_sr(u_int *sr, vm_offset_t va)
434 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
437 static __inline u_int
438 va_to_pteg(u_int sr, vm_offset_t addr)
442 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
444 return (hash & moea_pteg_mask);
447 static __inline struct pvo_head *
448 vm_page_to_pvoh(vm_page_t m)
451 return (&m->md.mdpg_pvoh);
455 moea_attr_clear(vm_page_t m, int ptebit)
458 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
459 m->md.mdpg_attrs &= ~ptebit;
463 moea_attr_fetch(vm_page_t m)
466 return (m->md.mdpg_attrs);
470 moea_attr_save(vm_page_t m, int ptebit)
473 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
474 m->md.mdpg_attrs |= ptebit;
478 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
480 if (pt->pte_hi == pvo_pt->pte_hi)
487 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
489 return (pt->pte_hi & ~PTE_VALID) ==
490 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
491 ((va >> ADDR_API_SHFT) & PTE_API) | which);
495 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
498 mtx_assert(&moea_table_mutex, MA_OWNED);
501 * Construct a PTE. Default to IMB initially. Valid bit only gets
502 * set when the real pte is set in memory.
504 * Note: Don't set the valid bit for correct operation of tlb update.
506 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
507 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
512 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
515 mtx_assert(&moea_table_mutex, MA_OWNED);
516 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
520 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
523 mtx_assert(&moea_table_mutex, MA_OWNED);
526 * As shown in Section 7.6.3.2.3
528 pt->pte_lo &= ~ptebit;
533 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
536 mtx_assert(&moea_table_mutex, MA_OWNED);
537 pvo_pt->pte_hi |= PTE_VALID;
540 * Update the PTE as defined in section 7.6.3.1.
541 * Note that the REF/CHG bits are from pvo_pt and thus should havce
542 * been saved so this routine can restore them (if desired).
544 pt->pte_lo = pvo_pt->pte_lo;
546 pt->pte_hi = pvo_pt->pte_hi;
552 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
555 mtx_assert(&moea_table_mutex, MA_OWNED);
556 pvo_pt->pte_hi &= ~PTE_VALID;
559 * Force the reg & chg bits back into the PTEs.
564 * Invalidate the pte.
566 pt->pte_hi &= ~PTE_VALID;
571 * Save the reg & chg bits.
573 moea_pte_synch(pt, pvo_pt);
578 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
584 moea_pte_unset(pt, pvo_pt, va);
585 moea_pte_set(pt, pvo_pt);
589 * Quick sort callout for comparing memory regions.
591 static int om_cmp(const void *a, const void *b);
594 om_cmp(const void *a, const void *b)
596 const struct ofw_map *mapa;
597 const struct ofw_map *mapb;
601 if (mapa->om_pa < mapb->om_pa)
603 else if (mapa->om_pa > mapb->om_pa)
610 moea_cpu_bootstrap(mmu_t mmup, int ap)
617 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
618 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
620 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
621 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
625 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
626 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
629 __asm __volatile("mtibatu 1,%0" :: "r"(0));
630 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
631 __asm __volatile("mtibatu 2,%0" :: "r"(0));
632 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
633 __asm __volatile("mtibatu 3,%0" :: "r"(0));
636 for (i = 0; i < 16; i++)
637 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
640 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
641 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
648 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
651 phandle_t chosen, mmu;
654 vm_size_t size, physsz, hwphyssz;
655 vm_offset_t pa, va, off;
660 * Set up BAT0 to map the lowest 256 MB area
662 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
663 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
666 * Map PCI memory space.
668 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
669 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
671 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
672 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
674 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
675 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
677 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
678 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
683 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
684 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
687 * Use an IBAT and a DBAT to map the bottom segment of memory
688 * where we are. Turn off instruction relocation temporarily
689 * to prevent faults while reprogramming the IBAT.
692 mtmsr(msr & ~PSL_IR);
693 __asm (".balign 32; \n"
694 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
695 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
696 :: "r"(battable[0].batu), "r"(battable[0].batl));
700 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
701 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
704 /* set global direct map flag */
707 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
708 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
710 for (i = 0; i < pregions_sz; i++) {
714 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
715 pregions[i].mr_start,
716 pregions[i].mr_start + pregions[i].mr_size,
717 pregions[i].mr_size);
719 * Install entries into the BAT table to allow all
720 * of physmem to be convered by on-demand BAT entries.
721 * The loop will sometimes set the same battable element
722 * twice, but that's fine since they won't be used for
725 pa = pregions[i].mr_start & 0xf0000000;
726 end = pregions[i].mr_start + pregions[i].mr_size;
728 u_int n = pa >> ADDR_SR_SHFT;
730 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
731 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
732 pa += SEGMENT_LENGTH;
736 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
737 panic("moea_bootstrap: phys_avail too small");
739 phys_avail_count = 0;
742 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
743 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
744 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
745 regions[i].mr_start + regions[i].mr_size,
748 (physsz + regions[i].mr_size) >= hwphyssz) {
749 if (physsz < hwphyssz) {
750 phys_avail[j] = regions[i].mr_start;
751 phys_avail[j + 1] = regions[i].mr_start +
758 phys_avail[j] = regions[i].mr_start;
759 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
761 physsz += regions[i].mr_size;
764 /* Check for overlap with the kernel and exception vectors */
765 for (j = 0; j < 2*phys_avail_count; j+=2) {
766 if (phys_avail[j] < EXC_LAST)
767 phys_avail[j] += EXC_LAST;
769 if (kernelstart >= phys_avail[j] &&
770 kernelstart < phys_avail[j+1]) {
771 if (kernelend < phys_avail[j+1]) {
772 phys_avail[2*phys_avail_count] =
773 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
774 phys_avail[2*phys_avail_count + 1] =
779 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
782 if (kernelend >= phys_avail[j] &&
783 kernelend < phys_avail[j+1]) {
784 if (kernelstart > phys_avail[j]) {
785 phys_avail[2*phys_avail_count] = phys_avail[j];
786 phys_avail[2*phys_avail_count + 1] =
787 kernelstart & ~PAGE_MASK;
791 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
795 physmem = btoc(physsz);
798 * Allocate PTEG table.
801 moea_pteg_count = PTEGCOUNT;
803 moea_pteg_count = 0x1000;
805 while (moea_pteg_count < physmem)
806 moea_pteg_count <<= 1;
808 moea_pteg_count >>= 1;
809 #endif /* PTEGCOUNT */
811 size = moea_pteg_count * sizeof(struct pteg);
812 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
814 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
815 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
816 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
817 moea_pteg_mask = moea_pteg_count - 1;
820 * Allocate pv/overflow lists.
822 size = sizeof(struct pvo_head) * moea_pteg_count;
823 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
825 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
826 for (i = 0; i < moea_pteg_count; i++)
827 LIST_INIT(&moea_pvo_table[i]);
830 * Initialize the lock that synchronizes access to the pteg and pvo
833 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
835 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
837 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
840 * Initialise the unmanaged pvo pool.
842 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
843 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
844 moea_bpvo_pool_index = 0;
847 * Make sure kernel vsid is allocated as well as VSID 0.
849 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
850 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
851 moea_vsid_bitmap[0] |= 1;
854 * Initialize the kernel pmap (which is statically allocated).
856 PMAP_LOCK_INIT(kernel_pmap);
857 for (i = 0; i < 16; i++)
858 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
859 CPU_FILL(&kernel_pmap->pm_active);
860 RB_INIT(&kernel_pmap->pmap_pvo);
863 * Set up the Open Firmware mappings
865 chosen = OF_finddevice("/chosen");
866 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
867 (mmu = OF_instance_to_package(mmui)) != -1 &&
868 (sz = OF_getproplen(mmu, "translations")) != -1) {
870 for (i = 0; phys_avail[i] != 0; i += 2) {
871 if (phys_avail[i + 1] >= sz) {
872 translations = (struct ofw_map *)phys_avail[i];
876 if (translations == NULL)
877 panic("moea_bootstrap: no space to copy translations");
878 bzero(translations, sz);
879 if (OF_getprop(mmu, "translations", translations, sz) == -1)
880 panic("moea_bootstrap: can't get ofw translations");
881 CTR0(KTR_PMAP, "moea_bootstrap: translations");
882 sz /= sizeof(*translations);
883 qsort(translations, sz, sizeof (*translations), om_cmp);
884 for (i = 0; i < sz; i++) {
885 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
886 translations[i].om_pa, translations[i].om_va,
887 translations[i].om_len);
890 * If the mapping is 1:1, let the RAM and device
891 * on-demand BAT tables take care of the translation.
893 if (translations[i].om_va == translations[i].om_pa)
896 /* Enter the pages */
897 for (off = 0; off < translations[i].om_len;
899 moea_kenter(mmup, translations[i].om_va + off,
900 translations[i].om_pa + off);
905 * Calculate the last available physical address.
907 for (i = 0; phys_avail[i + 2] != 0; i += 2)
909 Maxmem = powerpc_btop(phys_avail[i + 1]);
911 moea_cpu_bootstrap(mmup,0);
916 * Set the start and end of kva.
918 virtual_avail = VM_MIN_KERNEL_ADDRESS;
919 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
922 * Allocate a kernel stack with a guard page for thread0 and map it
923 * into the kernel page map.
925 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
926 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
927 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
928 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
929 thread0.td_kstack = va;
930 thread0.td_kstack_pages = KSTACK_PAGES;
931 for (i = 0; i < KSTACK_PAGES; i++) {
932 moea_kenter(mmup, va, pa);
938 * Allocate virtual address space for the message buffer.
940 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
941 msgbufp = (struct msgbuf *)virtual_avail;
943 virtual_avail += round_page(msgbufsize);
944 while (va < virtual_avail) {
945 moea_kenter(mmup, va, pa);
951 * Allocate virtual address space for the dynamic percpu area.
953 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
954 dpcpu = (void *)virtual_avail;
956 virtual_avail += DPCPU_SIZE;
957 while (va < virtual_avail) {
958 moea_kenter(mmup, va, pa);
962 dpcpu_init(dpcpu, 0);
966 * Activate a user pmap. The pmap must be activated before it's address
967 * space can be accessed in any way.
970 moea_activate(mmu_t mmu, struct thread *td)
975 * Load all the data we need up front to encourage the compiler to
976 * not issue any loads while we have interrupts disabled below.
978 pm = &td->td_proc->p_vmspace->vm_pmap;
981 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
982 PCPU_SET(curpmap, pmr);
986 moea_deactivate(mmu_t mmu, struct thread *td)
990 pm = &td->td_proc->p_vmspace->vm_pmap;
991 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
992 PCPU_SET(curpmap, NULL);
996 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
998 struct pvo_entry *pvo;
1001 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1005 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1006 pm->pm_stats.wired_count++;
1007 pvo->pvo_vaddr |= PVO_WIRED;
1009 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1010 pm->pm_stats.wired_count--;
1011 pvo->pvo_vaddr &= ~PVO_WIRED;
1018 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1023 dst = VM_PAGE_TO_PHYS(mdst);
1024 src = VM_PAGE_TO_PHYS(msrc);
1026 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1030 * Zero a page of physical memory by temporarily mapping it into the tlb.
1033 moea_zero_page(mmu_t mmu, vm_page_t m)
1035 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1036 void *va = (void *)pa;
1038 bzero(va, PAGE_SIZE);
1042 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1044 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1045 void *va = (void *)(pa + off);
1051 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1053 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1054 void *va = (void *)pa;
1056 bzero(va, PAGE_SIZE);
1060 * Map the given physical page at the specified virtual address in the
1061 * target pmap with the protection requested. If specified the page
1062 * will be wired down.
1065 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1069 vm_page_lock_queues();
1071 moea_enter_locked(pmap, va, m, prot, wired);
1072 vm_page_unlock_queues();
1077 * Map the given physical page at the specified virtual address in the
1078 * target pmap with the protection requested. If specified the page
1079 * will be wired down.
1081 * The page queues and pmap must be locked.
1084 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1087 struct pvo_head *pvo_head;
1090 u_int pte_lo, pvo_flags;
1093 if (!moea_initialized) {
1094 pvo_head = &moea_pvo_kunmanaged;
1095 zone = moea_upvo_zone;
1099 pvo_head = vm_page_to_pvoh(m);
1101 zone = moea_mpvo_zone;
1102 pvo_flags = PVO_MANAGED;
1104 if (pmap_bootstrapped)
1105 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1106 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1107 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1108 VM_OBJECT_LOCKED(m->object),
1109 ("moea_enter_locked: page %p is not busy", m));
1111 /* XXX change the pvo head for fake pages */
1112 if ((m->oflags & VPO_UNMANAGED) != 0) {
1113 pvo_flags &= ~PVO_MANAGED;
1114 pvo_head = &moea_pvo_kunmanaged;
1115 zone = moea_upvo_zone;
1118 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1120 if (prot & VM_PROT_WRITE) {
1122 if (pmap_bootstrapped &&
1123 (m->oflags & VPO_UNMANAGED) == 0)
1124 vm_page_aflag_set(m, PGA_WRITEABLE);
1128 if (prot & VM_PROT_EXECUTE)
1129 pvo_flags |= PVO_EXECUTABLE;
1132 pvo_flags |= PVO_WIRED;
1134 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1138 * Flush the real page from the instruction cache. This has be done
1139 * for all user mappings to prevent information leakage via the
1140 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1141 * mapping for a page.
1143 if (pmap != kernel_pmap && error == ENOENT &&
1144 (pte_lo & (PTE_I | PTE_G)) == 0)
1145 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1149 * Maps a sequence of resident pages belonging to the same object.
1150 * The sequence begins with the given page m_start. This page is
1151 * mapped at the given virtual address start. Each subsequent page is
1152 * mapped at a virtual address that is offset from start by the same
1153 * amount as the page is offset from m_start within the object. The
1154 * last page in the sequence is the page with the largest offset from
1155 * m_start that can be mapped at a virtual address less than the given
1156 * virtual address end. Not every virtual page between start and end
1157 * is mapped; only those for which a resident page exists with the
1158 * corresponding offset from m_start are mapped.
1161 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1162 vm_page_t m_start, vm_prot_t prot)
1165 vm_pindex_t diff, psize;
1167 psize = atop(end - start);
1169 vm_page_lock_queues();
1171 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1172 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1173 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1174 m = TAILQ_NEXT(m, listq);
1176 vm_page_unlock_queues();
1181 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1185 vm_page_lock_queues();
1187 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1189 vm_page_unlock_queues();
1194 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1196 struct pvo_entry *pvo;
1200 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1204 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1210 * Atomically extract and hold the physical page with the given
1211 * pmap and virtual address pair if that mapping permits the given
1215 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1217 struct pvo_entry *pvo;
1225 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1226 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1227 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1228 (prot & VM_PROT_WRITE) == 0)) {
1229 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1231 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1240 moea_init(mmu_t mmu)
1243 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1244 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1245 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1246 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1247 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1248 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1249 moea_initialized = TRUE;
1253 moea_is_referenced(mmu_t mmu, vm_page_t m)
1256 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1257 ("moea_is_referenced: page %p is not managed", m));
1258 return (moea_query_bit(m, PTE_REF));
1262 moea_is_modified(mmu_t mmu, vm_page_t m)
1265 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1266 ("moea_is_modified: page %p is not managed", m));
1269 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1270 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1271 * is clear, no PTEs can have PTE_CHG set.
1273 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1274 if ((m->oflags & VPO_BUSY) == 0 &&
1275 (m->aflags & PGA_WRITEABLE) == 0)
1277 return (moea_query_bit(m, PTE_CHG));
1281 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1283 struct pvo_entry *pvo;
1287 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1288 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1294 moea_clear_reference(mmu_t mmu, vm_page_t m)
1297 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1298 ("moea_clear_reference: page %p is not managed", m));
1299 moea_clear_bit(m, PTE_REF);
1303 moea_clear_modify(mmu_t mmu, vm_page_t m)
1306 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1307 ("moea_clear_modify: page %p is not managed", m));
1308 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1309 KASSERT((m->oflags & VPO_BUSY) == 0,
1310 ("moea_clear_modify: page %p is busy", m));
1313 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1314 * set. If the object containing the page is locked and the page is
1315 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1317 if ((m->aflags & PGA_WRITEABLE) == 0)
1319 moea_clear_bit(m, PTE_CHG);
1323 * Clear the write and modified bits in each of the given page's mappings.
1326 moea_remove_write(mmu_t mmu, vm_page_t m)
1328 struct pvo_entry *pvo;
1333 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1334 ("moea_remove_write: page %p is not managed", m));
1337 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1338 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1339 * is clear, no page table entries need updating.
1341 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1342 if ((m->oflags & VPO_BUSY) == 0 &&
1343 (m->aflags & PGA_WRITEABLE) == 0)
1345 vm_page_lock_queues();
1346 lo = moea_attr_fetch(m);
1348 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1349 pmap = pvo->pvo_pmap;
1351 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1352 pt = moea_pvo_to_pte(pvo, -1);
1353 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1354 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1356 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1357 lo |= pvo->pvo_pte.pte.pte_lo;
1358 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1359 moea_pte_change(pt, &pvo->pvo_pte.pte,
1361 mtx_unlock(&moea_table_mutex);
1366 if ((lo & PTE_CHG) != 0) {
1367 moea_attr_clear(m, PTE_CHG);
1370 vm_page_aflag_clear(m, PGA_WRITEABLE);
1371 vm_page_unlock_queues();
1375 * moea_ts_referenced:
1377 * Return a count of reference bits for a page, clearing those bits.
1378 * It is not necessary for every reference bit to be cleared, but it
1379 * is necessary that 0 only be returned when there are truly no
1380 * reference bits set.
1382 * XXX: The exact number of bits to check and clear is a matter that
1383 * should be tested and standardized at some point in the future for
1384 * optimal aging of shared pages.
1387 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1390 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1391 ("moea_ts_referenced: page %p is not managed", m));
1392 return (moea_clear_bit(m, PTE_REF));
1396 * Modify the WIMG settings of all mappings for a page.
1399 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1401 struct pvo_entry *pvo;
1402 struct pvo_head *pvo_head;
1407 if ((m->oflags & VPO_UNMANAGED) != 0) {
1408 m->md.mdpg_cache_attrs = ma;
1412 vm_page_lock_queues();
1413 pvo_head = vm_page_to_pvoh(m);
1414 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1416 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1417 pmap = pvo->pvo_pmap;
1419 pt = moea_pvo_to_pte(pvo, -1);
1420 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1421 pvo->pvo_pte.pte.pte_lo |= lo;
1423 moea_pte_change(pt, &pvo->pvo_pte.pte,
1425 if (pvo->pvo_pmap == kernel_pmap)
1428 mtx_unlock(&moea_table_mutex);
1431 m->md.mdpg_cache_attrs = ma;
1432 vm_page_unlock_queues();
1436 * Map a wired page into kernel virtual address space.
1439 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1442 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1446 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1452 if (va < VM_MIN_KERNEL_ADDRESS)
1453 panic("moea_kenter: attempt to enter non-kernel address %#x",
1457 pte_lo = moea_calc_wimg(pa, ma);
1459 PMAP_LOCK(kernel_pmap);
1460 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1461 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1463 if (error != 0 && error != ENOENT)
1464 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1467 PMAP_UNLOCK(kernel_pmap);
1471 * Extract the physical page address associated with the given kernel virtual
1475 moea_kextract(mmu_t mmu, vm_offset_t va)
1477 struct pvo_entry *pvo;
1481 * Allow direct mappings on 32-bit OEA
1483 if (va < VM_MIN_KERNEL_ADDRESS) {
1487 PMAP_LOCK(kernel_pmap);
1488 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1489 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1490 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1491 PMAP_UNLOCK(kernel_pmap);
1496 * Remove a wired page from kernel virtual address space.
1499 moea_kremove(mmu_t mmu, vm_offset_t va)
1502 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1506 * Map a range of physical addresses into kernel virtual address space.
1508 * The value passed in *virt is a suggested virtual address for the mapping.
1509 * Architectures which can support a direct-mapped physical to virtual region
1510 * can return the appropriate address within that region, leaving '*virt'
1511 * unchanged. We cannot and therefore do not; *virt is updated with the
1512 * first usable address after the mapped region.
1515 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1516 vm_paddr_t pa_end, int prot)
1518 vm_offset_t sva, va;
1522 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1523 moea_kenter(mmu, va, pa_start);
1529 * Returns true if the pmap's pv is one of the first
1530 * 16 pvs linked to from this page. This count may
1531 * be changed upwards or downwards in the future; it
1532 * is only necessary that true be returned for a small
1533 * subset of pmaps for proper page aging.
1536 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1539 struct pvo_entry *pvo;
1542 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1543 ("moea_page_exists_quick: page %p is not managed", m));
1546 vm_page_lock_queues();
1547 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1548 if (pvo->pvo_pmap == pmap) {
1555 vm_page_unlock_queues();
1560 * Return the number of managed mappings to the given physical page
1564 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1566 struct pvo_entry *pvo;
1570 if ((m->oflags & VPO_UNMANAGED) != 0)
1572 vm_page_lock_queues();
1573 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1574 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1576 vm_page_unlock_queues();
1580 static u_int moea_vsidcontext;
1583 moea_pinit(mmu_t mmu, pmap_t pmap)
1588 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1589 PMAP_LOCK_INIT(pmap);
1590 RB_INIT(&pmap->pmap_pvo);
1593 __asm __volatile("mftb %0" : "=r"(entropy));
1595 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1597 pmap->pmap_phys = pmap;
1601 mtx_lock(&moea_vsid_mutex);
1603 * Allocate some segment registers for this pmap.
1605 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1609 * Create a new value by mutiplying by a prime and adding in
1610 * entropy from the timebase register. This is to make the
1611 * VSID more random so that the PT hash function collides
1612 * less often. (Note that the prime casues gcc to do shifts
1613 * instead of a multiply.)
1615 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1616 hash = moea_vsidcontext & (NPMAPS - 1);
1617 if (hash == 0) /* 0 is special, avoid it */
1620 mask = 1 << (hash & (VSID_NBPW - 1));
1621 hash = (moea_vsidcontext & 0xfffff);
1622 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1623 /* anything free in this bucket? */
1624 if (moea_vsid_bitmap[n] == 0xffffffff) {
1625 entropy = (moea_vsidcontext >> 20);
1628 i = ffs(~moea_vsid_bitmap[n]) - 1;
1630 hash &= 0xfffff & ~(VSID_NBPW - 1);
1633 KASSERT(!(moea_vsid_bitmap[n] & mask),
1634 ("Allocating in-use VSID group %#x\n", hash));
1635 moea_vsid_bitmap[n] |= mask;
1636 for (i = 0; i < 16; i++)
1637 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1638 mtx_unlock(&moea_vsid_mutex);
1642 mtx_unlock(&moea_vsid_mutex);
1643 panic("moea_pinit: out of segments");
1647 * Initialize the pmap associated with process 0.
1650 moea_pinit0(mmu_t mmu, pmap_t pm)
1653 moea_pinit(mmu, pm);
1654 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1658 * Set the physical protection on the specified range of this map as requested.
1661 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1664 struct pvo_entry *pvo, *tpvo, key;
1667 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1668 ("moea_protect: non current pmap"));
1670 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1671 moea_remove(mmu, pm, sva, eva);
1675 vm_page_lock_queues();
1677 key.pvo_vaddr = sva;
1678 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1679 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1680 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1681 if ((prot & VM_PROT_EXECUTE) == 0)
1682 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1685 * Grab the PTE pointer before we diddle with the cached PTE
1688 pt = moea_pvo_to_pte(pvo, -1);
1690 * Change the protection of the page.
1692 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1693 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1696 * If the PVO is in the page table, update that pte as well.
1699 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1700 mtx_unlock(&moea_table_mutex);
1703 vm_page_unlock_queues();
1708 * Map a list of wired pages into kernel virtual address space. This is
1709 * intended for temporary mappings which do not need page modification or
1710 * references recorded. Existing mappings in the region are overwritten.
1713 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1718 while (count-- > 0) {
1719 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1726 * Remove page mappings from kernel virtual address space. Intended for
1727 * temporary mappings entered by moea_qenter.
1730 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1735 while (count-- > 0) {
1736 moea_kremove(mmu, va);
1742 moea_release(mmu_t mmu, pmap_t pmap)
1747 * Free segment register's VSID
1749 if (pmap->pm_sr[0] == 0)
1750 panic("moea_release");
1752 mtx_lock(&moea_vsid_mutex);
1753 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1754 mask = 1 << (idx % VSID_NBPW);
1756 moea_vsid_bitmap[idx] &= ~mask;
1757 mtx_unlock(&moea_vsid_mutex);
1758 PMAP_LOCK_DESTROY(pmap);
1762 * Remove the given range of addresses from the specified map.
1765 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1767 struct pvo_entry *pvo, *tpvo, key;
1769 vm_page_lock_queues();
1771 key.pvo_vaddr = sva;
1772 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1773 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1774 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1775 moea_pvo_remove(pvo, -1);
1778 vm_page_unlock_queues();
1782 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1783 * will reflect changes in pte's back to the vm_page.
1786 moea_remove_all(mmu_t mmu, vm_page_t m)
1788 struct pvo_head *pvo_head;
1789 struct pvo_entry *pvo, *next_pvo;
1792 vm_page_lock_queues();
1793 pvo_head = vm_page_to_pvoh(m);
1794 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1795 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1797 pmap = pvo->pvo_pmap;
1799 moea_pvo_remove(pvo, -1);
1802 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) {
1803 moea_attr_clear(m, PTE_CHG);
1806 vm_page_aflag_clear(m, PGA_WRITEABLE);
1807 vm_page_unlock_queues();
1811 * Allocate a physical page of memory directly from the phys_avail map.
1812 * Can only be called from moea_bootstrap before avail start and end are
1816 moea_bootstrap_alloc(vm_size_t size, u_int align)
1821 size = round_page(size);
1822 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1824 s = (phys_avail[i] + align - 1) & ~(align - 1);
1829 if (s < phys_avail[i] || e > phys_avail[i + 1])
1832 if (s == phys_avail[i]) {
1833 phys_avail[i] += size;
1834 } else if (e == phys_avail[i + 1]) {
1835 phys_avail[i + 1] -= size;
1837 for (j = phys_avail_count * 2; j > i; j -= 2) {
1838 phys_avail[j] = phys_avail[j - 2];
1839 phys_avail[j + 1] = phys_avail[j - 1];
1842 phys_avail[i + 3] = phys_avail[i + 1];
1843 phys_avail[i + 1] = s;
1844 phys_avail[i + 2] = e;
1850 panic("moea_bootstrap_alloc: could not allocate memory");
1854 moea_syncicache(vm_offset_t pa, vm_size_t len)
1856 __syncicache((void *)pa, len);
1860 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1861 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1863 struct pvo_entry *pvo;
1870 moea_pvo_enter_calls++;
1875 * Compute the PTE Group index.
1878 sr = va_to_sr(pm->pm_sr, va);
1879 ptegidx = va_to_pteg(sr, va);
1882 * Remove any existing mapping for this page. Reuse the pvo entry if
1883 * there is a mapping.
1885 mtx_lock(&moea_table_mutex);
1886 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1887 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1888 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1889 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1890 (pte_lo & PTE_PP)) {
1891 mtx_unlock(&moea_table_mutex);
1894 moea_pvo_remove(pvo, -1);
1900 * If we aren't overwriting a mapping, try to allocate.
1902 if (moea_initialized) {
1903 pvo = uma_zalloc(zone, M_NOWAIT);
1905 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1906 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1907 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1908 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1910 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1911 moea_bpvo_pool_index++;
1916 mtx_unlock(&moea_table_mutex);
1921 pvo->pvo_vaddr = va;
1923 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1924 pvo->pvo_vaddr &= ~ADDR_POFF;
1925 if (flags & VM_PROT_EXECUTE)
1926 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1927 if (flags & PVO_WIRED)
1928 pvo->pvo_vaddr |= PVO_WIRED;
1929 if (pvo_head != &moea_pvo_kunmanaged)
1930 pvo->pvo_vaddr |= PVO_MANAGED;
1932 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1934 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1939 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
1942 * Remember if the list was empty and therefore will be the first
1945 if (LIST_FIRST(pvo_head) == NULL)
1947 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1949 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1950 pm->pm_stats.wired_count++;
1951 pm->pm_stats.resident_count++;
1954 * We hope this succeeds but it isn't required.
1956 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1958 PVO_PTEGIDX_SET(pvo, i);
1960 panic("moea_pvo_enter: overflow");
1961 moea_pte_overflow++;
1963 mtx_unlock(&moea_table_mutex);
1965 return (first ? ENOENT : 0);
1969 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1974 * If there is an active pte entry, we need to deactivate it (and
1975 * save the ref & cfg bits).
1977 pt = moea_pvo_to_pte(pvo, pteidx);
1979 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1980 mtx_unlock(&moea_table_mutex);
1981 PVO_PTEGIDX_CLR(pvo);
1983 moea_pte_overflow--;
1987 * Update our statistics.
1989 pvo->pvo_pmap->pm_stats.resident_count--;
1990 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1991 pvo->pvo_pmap->pm_stats.wired_count--;
1994 * Save the REF/CHG bits into their cache if the page is managed.
1996 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
1999 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2001 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2002 (PTE_REF | PTE_CHG));
2007 * Remove this PVO from the PV and pmap lists.
2009 LIST_REMOVE(pvo, pvo_vlink);
2010 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2013 * Remove this from the overflow list and return it to the pool
2014 * if we aren't going to reuse it.
2016 LIST_REMOVE(pvo, pvo_olink);
2017 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2018 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2019 moea_upvo_zone, pvo);
2021 moea_pvo_remove_calls++;
2025 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2030 * We can find the actual pte entry without searching by grabbing
2031 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2032 * noticing the HID bit.
2034 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2035 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2036 pteidx ^= moea_pteg_mask * 8;
2041 static struct pvo_entry *
2042 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2044 struct pvo_entry *pvo;
2049 sr = va_to_sr(pm->pm_sr, va);
2050 ptegidx = va_to_pteg(sr, va);
2052 mtx_lock(&moea_table_mutex);
2053 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2054 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2056 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2060 mtx_unlock(&moea_table_mutex);
2066 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2071 * If we haven't been supplied the ptegidx, calculate it.
2077 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2078 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2079 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2082 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2083 mtx_lock(&moea_table_mutex);
2085 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2086 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2087 "valid pte index", pvo);
2090 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2091 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2092 "pvo but no valid pte", pvo);
2095 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2096 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2097 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2098 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2101 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2103 panic("moea_pvo_to_pte: pvo %p pte does not match "
2104 "pte %p in moea_pteg_table", pvo, pt);
2107 mtx_assert(&moea_table_mutex, MA_OWNED);
2111 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2112 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2113 "moea_pteg_table but valid in pvo", pvo, pt);
2116 mtx_unlock(&moea_table_mutex);
2121 * XXX: THIS STUFF SHOULD BE IN pte.c?
2124 moea_pte_spill(vm_offset_t addr)
2126 struct pvo_entry *source_pvo, *victim_pvo;
2127 struct pvo_entry *pvo;
2136 ptegidx = va_to_pteg(sr, addr);
2139 * Have to substitute some entry. Use the primary hash for this.
2140 * Use low bits of timebase as random generator.
2142 pteg = &moea_pteg_table[ptegidx];
2143 mtx_lock(&moea_table_mutex);
2144 __asm __volatile("mftb %0" : "=r"(i));
2150 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2152 * We need to find a pvo entry for this address.
2154 if (source_pvo == NULL &&
2155 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2156 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2158 * Now found an entry to be spilled into the pteg.
2159 * The PTE is now valid, so we know it's active.
2161 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2164 PVO_PTEGIDX_SET(pvo, j);
2165 moea_pte_overflow--;
2166 mtx_unlock(&moea_table_mutex);
2172 if (victim_pvo != NULL)
2177 * We also need the pvo entry of the victim we are replacing
2178 * so save the R & C bits of the PTE.
2180 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2181 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2183 if (source_pvo != NULL)
2188 if (source_pvo == NULL) {
2189 mtx_unlock(&moea_table_mutex);
2193 if (victim_pvo == NULL) {
2194 if ((pt->pte_hi & PTE_HID) == 0)
2195 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2199 * If this is a secondary PTE, we need to search it's primary
2200 * pvo bucket for the matching PVO.
2202 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2205 * We also need the pvo entry of the victim we are
2206 * replacing so save the R & C bits of the PTE.
2208 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2214 if (victim_pvo == NULL)
2215 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2220 * We are invalidating the TLB entry for the EA we are replacing even
2221 * though it's valid. If we don't, we lose any ref/chg bit changes
2222 * contained in the TLB entry.
2224 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2226 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2227 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2229 PVO_PTEGIDX_CLR(victim_pvo);
2230 PVO_PTEGIDX_SET(source_pvo, i);
2231 moea_pte_replacements++;
2233 mtx_unlock(&moea_table_mutex);
2238 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2243 mtx_assert(&moea_table_mutex, MA_OWNED);
2246 * First try primary hash.
2248 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2249 if ((pt->pte_hi & PTE_VALID) == 0) {
2250 pvo_pt->pte_hi &= ~PTE_HID;
2251 moea_pte_set(pt, pvo_pt);
2257 * Now try secondary hash.
2259 ptegidx ^= moea_pteg_mask;
2261 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2262 if ((pt->pte_hi & PTE_VALID) == 0) {
2263 pvo_pt->pte_hi |= PTE_HID;
2264 moea_pte_set(pt, pvo_pt);
2269 panic("moea_pte_insert: overflow");
2274 moea_query_bit(vm_page_t m, int ptebit)
2276 struct pvo_entry *pvo;
2279 if (moea_attr_fetch(m) & ptebit)
2282 vm_page_lock_queues();
2283 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2286 * See if we saved the bit off. If so, cache it and return
2289 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2290 moea_attr_save(m, ptebit);
2291 vm_page_unlock_queues();
2297 * No luck, now go through the hard part of looking at the PTEs
2298 * themselves. Sync so that any pending REF/CHG bits are flushed to
2302 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2305 * See if this pvo has a valid PTE. if so, fetch the
2306 * REF/CHG bits from the valid PTE. If the appropriate
2307 * ptebit is set, cache it and return success.
2309 pt = moea_pvo_to_pte(pvo, -1);
2311 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2312 mtx_unlock(&moea_table_mutex);
2313 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2314 moea_attr_save(m, ptebit);
2315 vm_page_unlock_queues();
2321 vm_page_unlock_queues();
2326 moea_clear_bit(vm_page_t m, int ptebit)
2329 struct pvo_entry *pvo;
2332 vm_page_lock_queues();
2335 * Clear the cached value.
2337 moea_attr_clear(m, ptebit);
2340 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2341 * we can reset the right ones). note that since the pvo entries and
2342 * list heads are accessed via BAT0 and are never placed in the page
2343 * table, we don't have to worry about further accesses setting the
2349 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2350 * valid pte clear the ptebit from the valid pte.
2353 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2354 pt = moea_pvo_to_pte(pvo, -1);
2356 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2357 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2359 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2361 mtx_unlock(&moea_table_mutex);
2363 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2366 vm_page_unlock_queues();
2371 * Return true if the physical range is encompassed by the battable[idx]
2374 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2382 * Return immediately if not a valid mapping
2384 if (!(battable[idx].batu & BAT_Vs))
2388 * The BAT entry must be cache-inhibited, guarded, and r/w
2389 * so it can function as an i/o page
2391 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2392 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2396 * The address should be within the BAT range. Assume that the
2397 * start address in the BAT has the correct alignment (thus
2398 * not requiring masking)
2400 start = battable[idx].batl & BAT_PBS;
2401 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2402 end = start | (bat_ble << 15) | 0x7fff;
2404 if ((pa < start) || ((pa + size) > end))
2411 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2416 * This currently does not work for entries that
2417 * overlap 256M BAT segments.
2420 for(i = 0; i < 16; i++)
2421 if (moea_bat_mapped(i, pa, size) == 0)
2428 * Map a set of physical memory pages into the kernel virtual
2429 * address space. Return a pointer to where it is mapped. This
2430 * routine is intended to be used for mapping device memory,
2434 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2437 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2441 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2443 vm_offset_t va, tmpva, ppa, offset;
2446 ppa = trunc_page(pa);
2447 offset = pa & PAGE_MASK;
2448 size = roundup(offset + size, PAGE_SIZE);
2451 * If the physical address lies within a valid BAT table entry,
2452 * return the 1:1 mapping. This currently doesn't work
2453 * for regions that overlap 256M BAT segments.
2455 for (i = 0; i < 16; i++) {
2456 if (moea_bat_mapped(i, pa, size) == 0)
2457 return ((void *) pa);
2460 va = kmem_alloc_nofault(kernel_map, size);
2462 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2464 for (tmpva = va; size > 0;) {
2465 moea_kenter_attr(mmu, tmpva, ppa, ma);
2472 return ((void *)(va + offset));
2476 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2478 vm_offset_t base, offset;
2481 * If this is outside kernel virtual space, then it's a
2482 * battable entry and doesn't require unmapping
2484 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2485 base = trunc_page(va);
2486 offset = va & PAGE_MASK;
2487 size = roundup(offset + size, PAGE_SIZE);
2488 kmem_free(kernel_map, base, size);
2493 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2495 struct pvo_entry *pvo;
2502 lim = round_page(va);
2503 len = MIN(lim - va, sz);
2504 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2506 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2508 moea_syncicache(pa, len);