2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
33 * Copyright (C) 1995, 1996 TooLs GmbH.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. All advertising materials mentioning features or use of this software
45 * must display the following acknowledgement:
46 * This product includes software developed by TooLs GmbH.
47 * 4. The name of TooLs GmbH may not be used to endorse or promote products
48 * derived from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
64 * Copyright (C) 2001 Benno Rice.
65 * All rights reserved.
67 * Redistribution and use in source and binary forms, with or without
68 * modification, are permitted provided that the following conditions
70 * 1. Redistributions of source code must retain the above copyright
71 * notice, this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright
73 * notice, this list of conditions and the following disclaimer in the
74 * documentation and/or other materials provided with the distribution.
76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is also stored by the
95 * logical address mapping module, this module may throw away valid virtual
96 * to physical mappings at almost any time. However, invalidations of
97 * mappings must be done as requested.
99 * In order to cope with hardware architectures which make virtual to
100 * physical map invalidates expensive, this module may delay invalidate
101 * reduced protection operations until such time as they are actually
102 * necessary. This module is given full information as to which processors
103 * are currently using which maps, and to when physical maps must be made
107 #include "opt_kstack_pages.h"
109 #include <sys/param.h>
110 #include <sys/kernel.h>
111 #include <sys/conf.h>
112 #include <sys/queue.h>
113 #include <sys/cpuset.h>
114 #include <sys/kerneldump.h>
116 #include <sys/lock.h>
117 #include <sys/msgbuf.h>
118 #include <sys/mutex.h>
119 #include <sys/proc.h>
120 #include <sys/rwlock.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
123 #include <sys/systm.h>
124 #include <sys/vmmeter.h>
126 #include <dev/ofw/openfirm.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_phys.h>
137 #include <vm/vm_pageout.h>
140 #include <machine/cpu.h>
141 #include <machine/platform.h>
142 #include <machine/bat.h>
143 #include <machine/frame.h>
144 #include <machine/md_var.h>
145 #include <machine/psl.h>
146 #include <machine/pte.h>
147 #include <machine/smp.h>
148 #include <machine/sr.h>
149 #include <machine/mmuvar.h>
150 #include <machine/trap.h>
156 #define TODO panic("%s: not implemented", __func__);
158 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
159 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
160 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
169 extern unsigned char _etext[];
170 extern unsigned char _end[];
173 * Map of physical memory regions.
175 static struct mem_region *regions;
176 static struct mem_region *pregions;
177 static u_int phys_avail_count;
178 static int regions_sz, pregions_sz;
179 static struct ofw_map *translations;
182 * Lock for the pteg and pvo tables.
184 struct mtx moea_table_mutex;
185 struct mtx moea_vsid_mutex;
187 /* tlbie instruction synchronization */
188 static struct mtx tlbie_mtx;
193 static struct pteg *moea_pteg_table;
194 u_int moea_pteg_count;
195 u_int moea_pteg_mask;
200 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
201 struct pvo_head moea_pvo_kunmanaged =
202 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
204 static struct rwlock_padalign pvh_global_lock;
206 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
207 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
209 #define BPVO_POOL_SIZE 32768
210 static struct pvo_entry *moea_bpvo_pool;
211 static int moea_bpvo_pool_index = 0;
213 #define VSID_NBPW (sizeof(u_int32_t) * 8)
214 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
216 static boolean_t moea_initialized = FALSE;
221 u_int moea_pte_valid = 0;
222 u_int moea_pte_overflow = 0;
223 u_int moea_pte_replacements = 0;
224 u_int moea_pvo_entries = 0;
225 u_int moea_pvo_enter_calls = 0;
226 u_int moea_pvo_remove_calls = 0;
227 u_int moea_pte_spills = 0;
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
231 &moea_pte_overflow, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
233 &moea_pte_replacements, 0, "");
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
237 &moea_pvo_enter_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
239 &moea_pvo_remove_calls, 0, "");
240 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
241 &moea_pte_spills, 0, "");
244 * Allocate physical memory for use in moea_bootstrap.
246 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
251 static int moea_pte_insert(u_int, struct pte *);
256 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
257 vm_offset_t, vm_paddr_t, u_int, int);
258 static void moea_pvo_remove(struct pvo_entry *, int);
259 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
260 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
265 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
266 vm_prot_t, u_int, int8_t);
267 static void moea_syncicache(vm_paddr_t, vm_size_t);
268 static boolean_t moea_query_bit(vm_page_t, int);
269 static u_int moea_clear_bit(vm_page_t, int);
270 static void moea_kremove(mmu_t, vm_offset_t);
271 int moea_pte_spill(vm_offset_t);
274 * Kernel MMU interface
276 void moea_clear_modify(mmu_t, vm_page_t);
277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
278 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
279 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
280 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int,
282 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
284 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
285 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
286 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
287 void moea_init(mmu_t);
288 boolean_t moea_is_modified(mmu_t, vm_page_t);
289 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
290 boolean_t moea_is_referenced(mmu_t, vm_page_t);
291 int moea_ts_referenced(mmu_t, vm_page_t);
292 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
293 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
294 void moea_page_init(mmu_t, vm_page_t);
295 int moea_page_wired_mappings(mmu_t, vm_page_t);
296 void moea_pinit(mmu_t, pmap_t);
297 void moea_pinit0(mmu_t, pmap_t);
298 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
299 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
300 void moea_qremove(mmu_t, vm_offset_t, int);
301 void moea_release(mmu_t, pmap_t);
302 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
303 void moea_remove_all(mmu_t, vm_page_t);
304 void moea_remove_write(mmu_t, vm_page_t);
305 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
306 void moea_zero_page(mmu_t, vm_page_t);
307 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
308 void moea_activate(mmu_t, struct thread *);
309 void moea_deactivate(mmu_t, struct thread *);
310 void moea_cpu_bootstrap(mmu_t, int);
311 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
312 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
313 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
314 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
315 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
316 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
317 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
318 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
319 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
320 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
321 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va);
322 void moea_scan_init(mmu_t mmu);
323 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m);
324 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr);
325 static int moea_map_user_ptr(mmu_t mmu, pmap_t pm,
326 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
327 static int moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
328 int *is_user, vm_offset_t *decoded_addr);
331 static mmu_method_t moea_methods[] = {
332 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
333 MMUMETHOD(mmu_copy_page, moea_copy_page),
334 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
335 MMUMETHOD(mmu_enter, moea_enter),
336 MMUMETHOD(mmu_enter_object, moea_enter_object),
337 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
338 MMUMETHOD(mmu_extract, moea_extract),
339 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
340 MMUMETHOD(mmu_init, moea_init),
341 MMUMETHOD(mmu_is_modified, moea_is_modified),
342 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
343 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
344 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
345 MMUMETHOD(mmu_map, moea_map),
346 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
347 MMUMETHOD(mmu_page_init, moea_page_init),
348 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
349 MMUMETHOD(mmu_pinit, moea_pinit),
350 MMUMETHOD(mmu_pinit0, moea_pinit0),
351 MMUMETHOD(mmu_protect, moea_protect),
352 MMUMETHOD(mmu_qenter, moea_qenter),
353 MMUMETHOD(mmu_qremove, moea_qremove),
354 MMUMETHOD(mmu_release, moea_release),
355 MMUMETHOD(mmu_remove, moea_remove),
356 MMUMETHOD(mmu_remove_all, moea_remove_all),
357 MMUMETHOD(mmu_remove_write, moea_remove_write),
358 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
359 MMUMETHOD(mmu_unwire, moea_unwire),
360 MMUMETHOD(mmu_zero_page, moea_zero_page),
361 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
362 MMUMETHOD(mmu_activate, moea_activate),
363 MMUMETHOD(mmu_deactivate, moea_deactivate),
364 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
365 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page),
366 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page),
368 /* Internal interfaces */
369 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
370 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
371 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
372 MMUMETHOD(mmu_mapdev, moea_mapdev),
373 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
374 MMUMETHOD(mmu_kextract, moea_kextract),
375 MMUMETHOD(mmu_kenter, moea_kenter),
376 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
377 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
378 MMUMETHOD(mmu_scan_init, moea_scan_init),
379 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
380 MMUMETHOD(mmu_map_user_ptr, moea_map_user_ptr),
381 MMUMETHOD(mmu_decode_kernel_ptr, moea_decode_kernel_ptr),
386 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
388 static __inline uint32_t
389 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
394 if (ma != VM_MEMATTR_DEFAULT) {
396 case VM_MEMATTR_UNCACHEABLE:
397 return (PTE_I | PTE_G);
398 case VM_MEMATTR_CACHEABLE:
400 case VM_MEMATTR_WRITE_COMBINING:
401 case VM_MEMATTR_WRITE_BACK:
402 case VM_MEMATTR_PREFETCHABLE:
404 case VM_MEMATTR_WRITE_THROUGH:
405 return (PTE_W | PTE_M);
410 * Assume the page is cache inhibited and access is guarded unless
411 * it's in our available memory array.
413 pte_lo = PTE_I | PTE_G;
414 for (i = 0; i < pregions_sz; i++) {
415 if ((pa >= pregions[i].mr_start) &&
416 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
426 tlbie(vm_offset_t va)
429 mtx_lock_spin(&tlbie_mtx);
430 __asm __volatile("ptesync");
431 __asm __volatile("tlbie %0" :: "r"(va));
432 __asm __volatile("eieio; tlbsync; ptesync");
433 mtx_unlock_spin(&tlbie_mtx);
441 for (va = 0; va < 0x00040000; va += 0x00001000) {
442 __asm __volatile("tlbie %0" :: "r"(va));
445 __asm __volatile("tlbsync");
450 va_to_sr(u_int *sr, vm_offset_t va)
452 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
455 static __inline u_int
456 va_to_pteg(u_int sr, vm_offset_t addr)
460 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
462 return (hash & moea_pteg_mask);
465 static __inline struct pvo_head *
466 vm_page_to_pvoh(vm_page_t m)
469 return (&m->md.mdpg_pvoh);
473 moea_attr_clear(vm_page_t m, int ptebit)
476 rw_assert(&pvh_global_lock, RA_WLOCKED);
477 m->md.mdpg_attrs &= ~ptebit;
481 moea_attr_fetch(vm_page_t m)
484 return (m->md.mdpg_attrs);
488 moea_attr_save(vm_page_t m, int ptebit)
491 rw_assert(&pvh_global_lock, RA_WLOCKED);
492 m->md.mdpg_attrs |= ptebit;
496 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
498 if (pt->pte_hi == pvo_pt->pte_hi)
505 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
507 return (pt->pte_hi & ~PTE_VALID) ==
508 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
509 ((va >> ADDR_API_SHFT) & PTE_API) | which);
513 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
516 mtx_assert(&moea_table_mutex, MA_OWNED);
519 * Construct a PTE. Default to IMB initially. Valid bit only gets
520 * set when the real pte is set in memory.
522 * Note: Don't set the valid bit for correct operation of tlb update.
524 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
525 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
530 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
533 mtx_assert(&moea_table_mutex, MA_OWNED);
534 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
538 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
541 mtx_assert(&moea_table_mutex, MA_OWNED);
544 * As shown in Section 7.6.3.2.3
546 pt->pte_lo &= ~ptebit;
551 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
554 mtx_assert(&moea_table_mutex, MA_OWNED);
555 pvo_pt->pte_hi |= PTE_VALID;
558 * Update the PTE as defined in section 7.6.3.1.
559 * Note that the REF/CHG bits are from pvo_pt and thus should have
560 * been saved so this routine can restore them (if desired).
562 pt->pte_lo = pvo_pt->pte_lo;
564 pt->pte_hi = pvo_pt->pte_hi;
570 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
573 mtx_assert(&moea_table_mutex, MA_OWNED);
574 pvo_pt->pte_hi &= ~PTE_VALID;
577 * Force the reg & chg bits back into the PTEs.
582 * Invalidate the pte.
584 pt->pte_hi &= ~PTE_VALID;
589 * Save the reg & chg bits.
591 moea_pte_synch(pt, pvo_pt);
596 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
602 moea_pte_unset(pt, pvo_pt, va);
603 moea_pte_set(pt, pvo_pt);
607 * Quick sort callout for comparing memory regions.
609 static int om_cmp(const void *a, const void *b);
612 om_cmp(const void *a, const void *b)
614 const struct ofw_map *mapa;
615 const struct ofw_map *mapb;
619 if (mapa->om_pa < mapb->om_pa)
621 else if (mapa->om_pa > mapb->om_pa)
628 moea_cpu_bootstrap(mmu_t mmup, int ap)
635 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
636 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
638 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
639 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
643 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
644 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
647 __asm __volatile("mtibatu 1,%0" :: "r"(0));
648 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
649 __asm __volatile("mtibatu 2,%0" :: "r"(0));
650 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
651 __asm __volatile("mtibatu 3,%0" :: "r"(0));
654 for (i = 0; i < 16; i++)
655 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
658 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
659 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
666 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
669 phandle_t chosen, mmu;
672 vm_size_t size, physsz, hwphyssz;
673 vm_offset_t pa, va, off;
678 * Set up BAT0 to map the lowest 256 MB area
680 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
681 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
684 * Map PCI memory space.
686 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
687 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
689 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
690 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
692 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
693 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
695 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
696 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
701 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
702 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
705 * Use an IBAT and a DBAT to map the bottom segment of memory
706 * where we are. Turn off instruction relocation temporarily
707 * to prevent faults while reprogramming the IBAT.
710 mtmsr(msr & ~PSL_IR);
711 __asm (".balign 32; \n"
712 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
713 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
714 :: "r"(battable[0].batu), "r"(battable[0].batl));
718 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
719 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
722 /* set global direct map flag */
725 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
726 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
728 for (i = 0; i < pregions_sz; i++) {
732 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
733 pregions[i].mr_start,
734 pregions[i].mr_start + pregions[i].mr_size,
735 pregions[i].mr_size);
737 * Install entries into the BAT table to allow all
738 * of physmem to be convered by on-demand BAT entries.
739 * The loop will sometimes set the same battable element
740 * twice, but that's fine since they won't be used for
743 pa = pregions[i].mr_start & 0xf0000000;
744 end = pregions[i].mr_start + pregions[i].mr_size;
746 u_int n = pa >> ADDR_SR_SHFT;
748 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
749 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
750 pa += SEGMENT_LENGTH;
754 if (PHYS_AVAIL_ENTRIES < regions_sz)
755 panic("moea_bootstrap: phys_avail too small");
757 phys_avail_count = 0;
760 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
761 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
762 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
763 regions[i].mr_start + regions[i].mr_size,
766 (physsz + regions[i].mr_size) >= hwphyssz) {
767 if (physsz < hwphyssz) {
768 phys_avail[j] = regions[i].mr_start;
769 phys_avail[j + 1] = regions[i].mr_start +
776 phys_avail[j] = regions[i].mr_start;
777 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
779 physsz += regions[i].mr_size;
782 /* Check for overlap with the kernel and exception vectors */
783 for (j = 0; j < 2*phys_avail_count; j+=2) {
784 if (phys_avail[j] < EXC_LAST)
785 phys_avail[j] += EXC_LAST;
787 if (kernelstart >= phys_avail[j] &&
788 kernelstart < phys_avail[j+1]) {
789 if (kernelend < phys_avail[j+1]) {
790 phys_avail[2*phys_avail_count] =
791 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
792 phys_avail[2*phys_avail_count + 1] =
797 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
800 if (kernelend >= phys_avail[j] &&
801 kernelend < phys_avail[j+1]) {
802 if (kernelstart > phys_avail[j]) {
803 phys_avail[2*phys_avail_count] = phys_avail[j];
804 phys_avail[2*phys_avail_count + 1] =
805 kernelstart & ~PAGE_MASK;
809 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
813 physmem = btoc(physsz);
816 * Allocate PTEG table.
819 moea_pteg_count = PTEGCOUNT;
821 moea_pteg_count = 0x1000;
823 while (moea_pteg_count < physmem)
824 moea_pteg_count <<= 1;
826 moea_pteg_count >>= 1;
827 #endif /* PTEGCOUNT */
829 size = moea_pteg_count * sizeof(struct pteg);
830 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
832 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
833 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
834 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
835 moea_pteg_mask = moea_pteg_count - 1;
838 * Allocate pv/overflow lists.
840 size = sizeof(struct pvo_head) * moea_pteg_count;
841 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
843 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
844 for (i = 0; i < moea_pteg_count; i++)
845 LIST_INIT(&moea_pvo_table[i]);
848 * Initialize the lock that synchronizes access to the pteg and pvo
851 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
853 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
855 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
858 * Initialise the unmanaged pvo pool.
860 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
861 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
862 moea_bpvo_pool_index = 0;
865 * Make sure kernel vsid is allocated as well as VSID 0.
867 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
868 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
869 moea_vsid_bitmap[0] |= 1;
872 * Initialize the kernel pmap (which is statically allocated).
874 PMAP_LOCK_INIT(kernel_pmap);
875 for (i = 0; i < 16; i++)
876 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
877 CPU_FILL(&kernel_pmap->pm_active);
878 RB_INIT(&kernel_pmap->pmap_pvo);
881 * Initialize the global pv list lock.
883 rw_init(&pvh_global_lock, "pmap pv global");
886 * Set up the Open Firmware mappings
888 chosen = OF_finddevice("/chosen");
889 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
890 (mmu = OF_instance_to_package(mmui)) != -1 &&
891 (sz = OF_getproplen(mmu, "translations")) != -1) {
893 for (i = 0; phys_avail[i] != 0; i += 2) {
894 if (phys_avail[i + 1] >= sz) {
895 translations = (struct ofw_map *)phys_avail[i];
899 if (translations == NULL)
900 panic("moea_bootstrap: no space to copy translations");
901 bzero(translations, sz);
902 if (OF_getprop(mmu, "translations", translations, sz) == -1)
903 panic("moea_bootstrap: can't get ofw translations");
904 CTR0(KTR_PMAP, "moea_bootstrap: translations");
905 sz /= sizeof(*translations);
906 qsort(translations, sz, sizeof (*translations), om_cmp);
907 for (i = 0; i < sz; i++) {
908 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
909 translations[i].om_pa, translations[i].om_va,
910 translations[i].om_len);
913 * If the mapping is 1:1, let the RAM and device
914 * on-demand BAT tables take care of the translation.
916 if (translations[i].om_va == translations[i].om_pa)
919 /* Enter the pages */
920 for (off = 0; off < translations[i].om_len;
922 moea_kenter(mmup, translations[i].om_va + off,
923 translations[i].om_pa + off);
928 * Calculate the last available physical address.
930 for (i = 0; phys_avail[i + 2] != 0; i += 2)
932 Maxmem = powerpc_btop(phys_avail[i + 1]);
934 moea_cpu_bootstrap(mmup,0);
935 mtmsr(mfmsr() | PSL_DR | PSL_IR);
939 * Set the start and end of kva.
941 virtual_avail = VM_MIN_KERNEL_ADDRESS;
942 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
945 * Allocate a kernel stack with a guard page for thread0 and map it
946 * into the kernel page map.
948 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
949 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
950 virtual_avail = va + kstack_pages * PAGE_SIZE;
951 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
952 thread0.td_kstack = va;
953 thread0.td_kstack_pages = kstack_pages;
954 for (i = 0; i < kstack_pages; i++) {
955 moea_kenter(mmup, va, pa);
961 * Allocate virtual address space for the message buffer.
963 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
964 msgbufp = (struct msgbuf *)virtual_avail;
966 virtual_avail += round_page(msgbufsize);
967 while (va < virtual_avail) {
968 moea_kenter(mmup, va, pa);
974 * Allocate virtual address space for the dynamic percpu area.
976 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
977 dpcpu = (void *)virtual_avail;
979 virtual_avail += DPCPU_SIZE;
980 while (va < virtual_avail) {
981 moea_kenter(mmup, va, pa);
985 dpcpu_init(dpcpu, 0);
989 * Activate a user pmap. The pmap must be activated before it's address
990 * space can be accessed in any way.
993 moea_activate(mmu_t mmu, struct thread *td)
998 * Load all the data we need up front to encourage the compiler to
999 * not issue any loads while we have interrupts disabled below.
1001 pm = &td->td_proc->p_vmspace->vm_pmap;
1002 pmr = pm->pmap_phys;
1004 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1005 PCPU_SET(curpmap, pmr);
1007 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1011 moea_deactivate(mmu_t mmu, struct thread *td)
1015 pm = &td->td_proc->p_vmspace->vm_pmap;
1016 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1017 PCPU_SET(curpmap, NULL);
1021 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1023 struct pvo_entry key, *pvo;
1026 key.pvo_vaddr = sva;
1027 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1028 pvo != NULL && PVO_VADDR(pvo) < eva;
1029 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1030 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1031 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo);
1032 pvo->pvo_vaddr &= ~PVO_WIRED;
1033 pm->pm_stats.wired_count--;
1039 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1044 dst = VM_PAGE_TO_PHYS(mdst);
1045 src = VM_PAGE_TO_PHYS(msrc);
1047 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1051 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1052 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1055 vm_offset_t a_pg_offset, b_pg_offset;
1058 while (xfersize > 0) {
1059 a_pg_offset = a_offset & PAGE_MASK;
1060 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1061 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1063 b_pg_offset = b_offset & PAGE_MASK;
1064 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1065 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1067 bcopy(a_cp, b_cp, cnt);
1075 * Zero a page of physical memory by temporarily mapping it into the tlb.
1078 moea_zero_page(mmu_t mmu, vm_page_t m)
1080 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1082 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1083 __asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1087 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1089 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1090 void *va = (void *)(pa + off);
1096 moea_quick_enter_page(mmu_t mmu, vm_page_t m)
1099 return (VM_PAGE_TO_PHYS(m));
1103 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1108 * Map the given physical page at the specified virtual address in the
1109 * target pmap with the protection requested. If specified the page
1110 * will be wired down.
1113 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1114 u_int flags, int8_t psind)
1119 rw_wlock(&pvh_global_lock);
1121 error = moea_enter_locked(pmap, va, m, prot, flags, psind);
1122 rw_wunlock(&pvh_global_lock);
1124 if (error != ENOMEM)
1125 return (KERN_SUCCESS);
1126 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1127 return (KERN_RESOURCE_SHORTAGE);
1128 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1134 * Map the given physical page at the specified virtual address in the
1135 * target pmap with the protection requested. If specified the page
1136 * will be wired down.
1138 * The global pvh and pmap must be locked.
1141 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1142 u_int flags, int8_t psind __unused)
1144 struct pvo_head *pvo_head;
1146 u_int pte_lo, pvo_flags;
1149 if (pmap_bootstrapped)
1150 rw_assert(&pvh_global_lock, RA_WLOCKED);
1151 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1152 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1153 VM_OBJECT_ASSERT_LOCKED(m->object);
1155 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) {
1156 pvo_head = &moea_pvo_kunmanaged;
1157 zone = moea_upvo_zone;
1160 pvo_head = vm_page_to_pvoh(m);
1161 zone = moea_mpvo_zone;
1162 pvo_flags = PVO_MANAGED;
1165 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1167 if (prot & VM_PROT_WRITE) {
1169 if (pmap_bootstrapped &&
1170 (m->oflags & VPO_UNMANAGED) == 0)
1171 vm_page_aflag_set(m, PGA_WRITEABLE);
1175 if ((flags & PMAP_ENTER_WIRED) != 0)
1176 pvo_flags |= PVO_WIRED;
1178 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1182 * Flush the real page from the instruction cache. This has be done
1183 * for all user mappings to prevent information leakage via the
1184 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1185 * mapping for a page.
1187 if (pmap != kernel_pmap && error == ENOENT &&
1188 (pte_lo & (PTE_I | PTE_G)) == 0)
1189 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1195 * Maps a sequence of resident pages belonging to the same object.
1196 * The sequence begins with the given page m_start. This page is
1197 * mapped at the given virtual address start. Each subsequent page is
1198 * mapped at a virtual address that is offset from start by the same
1199 * amount as the page is offset from m_start within the object. The
1200 * last page in the sequence is the page with the largest offset from
1201 * m_start that can be mapped at a virtual address less than the given
1202 * virtual address end. Not every virtual page between start and end
1203 * is mapped; only those for which a resident page exists with the
1204 * corresponding offset from m_start are mapped.
1207 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1208 vm_page_t m_start, vm_prot_t prot)
1211 vm_pindex_t diff, psize;
1213 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1215 psize = atop(end - start);
1217 rw_wlock(&pvh_global_lock);
1219 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1220 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1221 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1222 m = TAILQ_NEXT(m, listq);
1224 rw_wunlock(&pvh_global_lock);
1229 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1233 rw_wlock(&pvh_global_lock);
1235 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1237 rw_wunlock(&pvh_global_lock);
1242 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1244 struct pvo_entry *pvo;
1248 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1252 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1258 * Atomically extract and hold the physical page with the given
1259 * pmap and virtual address pair if that mapping permits the given
1263 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1265 struct pvo_entry *pvo;
1270 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1271 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1272 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1273 (prot & VM_PROT_WRITE) == 0)) {
1274 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1275 if (!vm_page_wire_mapped(m))
1283 moea_init(mmu_t mmu)
1286 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1287 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1288 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1289 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1290 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1291 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1292 moea_initialized = TRUE;
1296 moea_is_referenced(mmu_t mmu, vm_page_t m)
1300 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1301 ("moea_is_referenced: page %p is not managed", m));
1302 rw_wlock(&pvh_global_lock);
1303 rv = moea_query_bit(m, PTE_REF);
1304 rw_wunlock(&pvh_global_lock);
1309 moea_is_modified(mmu_t mmu, vm_page_t m)
1313 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1314 ("moea_is_modified: page %p is not managed", m));
1317 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1318 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1319 * is clear, no PTEs can have PTE_CHG set.
1321 VM_OBJECT_ASSERT_WLOCKED(m->object);
1322 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1324 rw_wlock(&pvh_global_lock);
1325 rv = moea_query_bit(m, PTE_CHG);
1326 rw_wunlock(&pvh_global_lock);
1331 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1333 struct pvo_entry *pvo;
1337 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1338 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1344 moea_clear_modify(mmu_t mmu, vm_page_t m)
1347 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1348 ("moea_clear_modify: page %p is not managed", m));
1349 VM_OBJECT_ASSERT_WLOCKED(m->object);
1350 KASSERT(!vm_page_xbusied(m),
1351 ("moea_clear_modify: page %p is exclusive busy", m));
1354 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1355 * set. If the object containing the page is locked and the page is
1356 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1358 if ((m->aflags & PGA_WRITEABLE) == 0)
1360 rw_wlock(&pvh_global_lock);
1361 moea_clear_bit(m, PTE_CHG);
1362 rw_wunlock(&pvh_global_lock);
1366 * Clear the write and modified bits in each of the given page's mappings.
1369 moea_remove_write(mmu_t mmu, vm_page_t m)
1371 struct pvo_entry *pvo;
1376 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1377 ("moea_remove_write: page %p is not managed", m));
1380 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1381 * set by another thread while the object is locked. Thus,
1382 * if PGA_WRITEABLE is clear, no page table entries need updating.
1384 VM_OBJECT_ASSERT_WLOCKED(m->object);
1385 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1387 rw_wlock(&pvh_global_lock);
1388 lo = moea_attr_fetch(m);
1390 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1391 pmap = pvo->pvo_pmap;
1393 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1394 pt = moea_pvo_to_pte(pvo, -1);
1395 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1396 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1398 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1399 lo |= pvo->pvo_pte.pte.pte_lo;
1400 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1401 moea_pte_change(pt, &pvo->pvo_pte.pte,
1403 mtx_unlock(&moea_table_mutex);
1408 if ((lo & PTE_CHG) != 0) {
1409 moea_attr_clear(m, PTE_CHG);
1412 vm_page_aflag_clear(m, PGA_WRITEABLE);
1413 rw_wunlock(&pvh_global_lock);
1417 * moea_ts_referenced:
1419 * Return a count of reference bits for a page, clearing those bits.
1420 * It is not necessary for every reference bit to be cleared, but it
1421 * is necessary that 0 only be returned when there are truly no
1422 * reference bits set.
1424 * XXX: The exact number of bits to check and clear is a matter that
1425 * should be tested and standardized at some point in the future for
1426 * optimal aging of shared pages.
1429 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1433 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1434 ("moea_ts_referenced: page %p is not managed", m));
1435 rw_wlock(&pvh_global_lock);
1436 count = moea_clear_bit(m, PTE_REF);
1437 rw_wunlock(&pvh_global_lock);
1442 * Modify the WIMG settings of all mappings for a page.
1445 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1447 struct pvo_entry *pvo;
1448 struct pvo_head *pvo_head;
1453 if ((m->oflags & VPO_UNMANAGED) != 0) {
1454 m->md.mdpg_cache_attrs = ma;
1458 rw_wlock(&pvh_global_lock);
1459 pvo_head = vm_page_to_pvoh(m);
1460 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1462 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1463 pmap = pvo->pvo_pmap;
1465 pt = moea_pvo_to_pte(pvo, -1);
1466 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1467 pvo->pvo_pte.pte.pte_lo |= lo;
1469 moea_pte_change(pt, &pvo->pvo_pte.pte,
1471 if (pvo->pvo_pmap == kernel_pmap)
1474 mtx_unlock(&moea_table_mutex);
1477 m->md.mdpg_cache_attrs = ma;
1478 rw_wunlock(&pvh_global_lock);
1482 * Map a wired page into kernel virtual address space.
1485 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1488 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1492 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1498 if (va < VM_MIN_KERNEL_ADDRESS)
1499 panic("moea_kenter: attempt to enter non-kernel address %#x",
1503 pte_lo = moea_calc_wimg(pa, ma);
1505 PMAP_LOCK(kernel_pmap);
1506 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1507 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1509 if (error != 0 && error != ENOENT)
1510 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1513 PMAP_UNLOCK(kernel_pmap);
1517 * Extract the physical page address associated with the given kernel virtual
1521 moea_kextract(mmu_t mmu, vm_offset_t va)
1523 struct pvo_entry *pvo;
1527 * Allow direct mappings on 32-bit OEA
1529 if (va < VM_MIN_KERNEL_ADDRESS) {
1533 PMAP_LOCK(kernel_pmap);
1534 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1535 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1536 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1537 PMAP_UNLOCK(kernel_pmap);
1542 * Remove a wired page from kernel virtual address space.
1545 moea_kremove(mmu_t mmu, vm_offset_t va)
1548 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1552 * Provide a kernel pointer corresponding to a given userland pointer.
1553 * The returned pointer is valid until the next time this function is
1554 * called in this thread. This is used internally in copyin/copyout.
1557 moea_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1558 void **kaddr, size_t ulen, size_t *klen)
1563 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1564 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1572 vsid = va_to_vsid(pm, (vm_offset_t)uaddr);
1574 /* Mark segment no-execute */
1577 /* If we have already set this VSID, we can just return */
1578 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid)
1581 __asm __volatile("isync");
1582 curthread->td_pcb->pcb_cpu.aim.usr_segm =
1583 (uintptr_t)uaddr >> ADDR_SR_SHFT;
1584 curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid;
1585 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid));
1591 * Figure out where a given kernel pointer (usually in a fault) points
1592 * to from the VM's perspective, potentially remapping into userland's
1596 moea_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
1597 vm_offset_t *decoded_addr)
1599 vm_offset_t user_sr;
1601 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
1602 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm;
1603 addr &= ADDR_PIDX | ADDR_POFF;
1604 addr |= user_sr << ADDR_SR_SHFT;
1605 *decoded_addr = addr;
1608 *decoded_addr = addr;
1616 * Map a range of physical addresses into kernel virtual address space.
1618 * The value passed in *virt is a suggested virtual address for the mapping.
1619 * Architectures which can support a direct-mapped physical to virtual region
1620 * can return the appropriate address within that region, leaving '*virt'
1621 * unchanged. We cannot and therefore do not; *virt is updated with the
1622 * first usable address after the mapped region.
1625 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1626 vm_paddr_t pa_end, int prot)
1628 vm_offset_t sva, va;
1632 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1633 moea_kenter(mmu, va, pa_start);
1639 * Returns true if the pmap's pv is one of the first
1640 * 16 pvs linked to from this page. This count may
1641 * be changed upwards or downwards in the future; it
1642 * is only necessary that true be returned for a small
1643 * subset of pmaps for proper page aging.
1646 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1649 struct pvo_entry *pvo;
1652 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1653 ("moea_page_exists_quick: page %p is not managed", m));
1656 rw_wlock(&pvh_global_lock);
1657 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1658 if (pvo->pvo_pmap == pmap) {
1665 rw_wunlock(&pvh_global_lock);
1670 moea_page_init(mmu_t mmu __unused, vm_page_t m)
1673 m->md.mdpg_attrs = 0;
1674 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
1675 LIST_INIT(&m->md.mdpg_pvoh);
1679 * Return the number of managed mappings to the given physical page
1683 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1685 struct pvo_entry *pvo;
1689 if ((m->oflags & VPO_UNMANAGED) != 0)
1691 rw_wlock(&pvh_global_lock);
1692 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1693 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1695 rw_wunlock(&pvh_global_lock);
1699 static u_int moea_vsidcontext;
1702 moea_pinit(mmu_t mmu, pmap_t pmap)
1707 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1708 RB_INIT(&pmap->pmap_pvo);
1711 __asm __volatile("mftb %0" : "=r"(entropy));
1713 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1715 pmap->pmap_phys = pmap;
1719 mtx_lock(&moea_vsid_mutex);
1721 * Allocate some segment registers for this pmap.
1723 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1727 * Create a new value by mutiplying by a prime and adding in
1728 * entropy from the timebase register. This is to make the
1729 * VSID more random so that the PT hash function collides
1730 * less often. (Note that the prime casues gcc to do shifts
1731 * instead of a multiply.)
1733 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1734 hash = moea_vsidcontext & (NPMAPS - 1);
1735 if (hash == 0) /* 0 is special, avoid it */
1738 mask = 1 << (hash & (VSID_NBPW - 1));
1739 hash = (moea_vsidcontext & 0xfffff);
1740 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1741 /* anything free in this bucket? */
1742 if (moea_vsid_bitmap[n] == 0xffffffff) {
1743 entropy = (moea_vsidcontext >> 20);
1746 i = ffs(~moea_vsid_bitmap[n]) - 1;
1748 hash &= rounddown2(0xfffff, VSID_NBPW);
1751 KASSERT(!(moea_vsid_bitmap[n] & mask),
1752 ("Allocating in-use VSID group %#x\n", hash));
1753 moea_vsid_bitmap[n] |= mask;
1754 for (i = 0; i < 16; i++)
1755 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1756 mtx_unlock(&moea_vsid_mutex);
1760 mtx_unlock(&moea_vsid_mutex);
1761 panic("moea_pinit: out of segments");
1765 * Initialize the pmap associated with process 0.
1768 moea_pinit0(mmu_t mmu, pmap_t pm)
1772 moea_pinit(mmu, pm);
1773 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1777 * Set the physical protection on the specified range of this map as requested.
1780 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1783 struct pvo_entry *pvo, *tpvo, key;
1786 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1787 ("moea_protect: non current pmap"));
1789 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1790 moea_remove(mmu, pm, sva, eva);
1794 rw_wlock(&pvh_global_lock);
1796 key.pvo_vaddr = sva;
1797 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1798 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1799 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1802 * Grab the PTE pointer before we diddle with the cached PTE
1805 pt = moea_pvo_to_pte(pvo, -1);
1807 * Change the protection of the page.
1809 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1810 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1813 * If the PVO is in the page table, update that pte as well.
1816 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1817 mtx_unlock(&moea_table_mutex);
1820 rw_wunlock(&pvh_global_lock);
1825 * Map a list of wired pages into kernel virtual address space. This is
1826 * intended for temporary mappings which do not need page modification or
1827 * references recorded. Existing mappings in the region are overwritten.
1830 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1835 while (count-- > 0) {
1836 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1843 * Remove page mappings from kernel virtual address space. Intended for
1844 * temporary mappings entered by moea_qenter.
1847 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1852 while (count-- > 0) {
1853 moea_kremove(mmu, va);
1859 moea_release(mmu_t mmu, pmap_t pmap)
1864 * Free segment register's VSID
1866 if (pmap->pm_sr[0] == 0)
1867 panic("moea_release");
1869 mtx_lock(&moea_vsid_mutex);
1870 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1871 mask = 1 << (idx % VSID_NBPW);
1873 moea_vsid_bitmap[idx] &= ~mask;
1874 mtx_unlock(&moea_vsid_mutex);
1878 * Remove the given range of addresses from the specified map.
1881 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1883 struct pvo_entry *pvo, *tpvo, key;
1885 rw_wlock(&pvh_global_lock);
1887 key.pvo_vaddr = sva;
1888 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1889 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1890 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1891 moea_pvo_remove(pvo, -1);
1894 rw_wunlock(&pvh_global_lock);
1898 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1899 * will reflect changes in pte's back to the vm_page.
1902 moea_remove_all(mmu_t mmu, vm_page_t m)
1904 struct pvo_head *pvo_head;
1905 struct pvo_entry *pvo, *next_pvo;
1908 rw_wlock(&pvh_global_lock);
1909 pvo_head = vm_page_to_pvoh(m);
1910 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1911 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1913 pmap = pvo->pvo_pmap;
1915 moea_pvo_remove(pvo, -1);
1918 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1919 moea_attr_clear(m, PTE_CHG);
1922 vm_page_aflag_clear(m, PGA_WRITEABLE);
1923 rw_wunlock(&pvh_global_lock);
1927 * Allocate a physical page of memory directly from the phys_avail map.
1928 * Can only be called from moea_bootstrap before avail start and end are
1932 moea_bootstrap_alloc(vm_size_t size, u_int align)
1937 size = round_page(size);
1938 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1940 s = roundup2(phys_avail[i], align);
1945 if (s < phys_avail[i] || e > phys_avail[i + 1])
1948 if (s == phys_avail[i]) {
1949 phys_avail[i] += size;
1950 } else if (e == phys_avail[i + 1]) {
1951 phys_avail[i + 1] -= size;
1953 for (j = phys_avail_count * 2; j > i; j -= 2) {
1954 phys_avail[j] = phys_avail[j - 2];
1955 phys_avail[j + 1] = phys_avail[j - 1];
1958 phys_avail[i + 3] = phys_avail[i + 1];
1959 phys_avail[i + 1] = s;
1960 phys_avail[i + 2] = e;
1966 panic("moea_bootstrap_alloc: could not allocate memory");
1970 moea_syncicache(vm_paddr_t pa, vm_size_t len)
1972 __syncicache((void *)pa, len);
1976 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1977 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags)
1979 struct pvo_entry *pvo;
1986 moea_pvo_enter_calls++;
1991 * Compute the PTE Group index.
1994 sr = va_to_sr(pm->pm_sr, va);
1995 ptegidx = va_to_pteg(sr, va);
1998 * Remove any existing mapping for this page. Reuse the pvo entry if
1999 * there is a mapping.
2001 mtx_lock(&moea_table_mutex);
2002 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2003 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2004 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
2005 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
2006 (pte_lo & PTE_PP)) {
2008 * The PTE is not changing. Instead, this may
2009 * be a request to change the mapping's wired
2012 mtx_unlock(&moea_table_mutex);
2013 if ((flags & PVO_WIRED) != 0 &&
2014 (pvo->pvo_vaddr & PVO_WIRED) == 0) {
2015 pvo->pvo_vaddr |= PVO_WIRED;
2016 pm->pm_stats.wired_count++;
2017 } else if ((flags & PVO_WIRED) == 0 &&
2018 (pvo->pvo_vaddr & PVO_WIRED) != 0) {
2019 pvo->pvo_vaddr &= ~PVO_WIRED;
2020 pm->pm_stats.wired_count--;
2024 moea_pvo_remove(pvo, -1);
2030 * If we aren't overwriting a mapping, try to allocate.
2032 if (moea_initialized) {
2033 pvo = uma_zalloc(zone, M_NOWAIT);
2035 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
2036 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
2037 moea_bpvo_pool_index, BPVO_POOL_SIZE,
2038 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2040 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
2041 moea_bpvo_pool_index++;
2046 mtx_unlock(&moea_table_mutex);
2051 pvo->pvo_vaddr = va;
2053 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
2054 pvo->pvo_vaddr &= ~ADDR_POFF;
2055 if (flags & PVO_WIRED)
2056 pvo->pvo_vaddr |= PVO_WIRED;
2057 if (pvo_head != &moea_pvo_kunmanaged)
2058 pvo->pvo_vaddr |= PVO_MANAGED;
2060 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2062 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
2067 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2070 * Remember if the list was empty and therefore will be the first
2073 if (LIST_FIRST(pvo_head) == NULL)
2075 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2077 if (pvo->pvo_vaddr & PVO_WIRED)
2078 pm->pm_stats.wired_count++;
2079 pm->pm_stats.resident_count++;
2081 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2082 KASSERT(i < 8, ("Invalid PTE index"));
2084 PVO_PTEGIDX_SET(pvo, i);
2086 panic("moea_pvo_enter: overflow");
2087 moea_pte_overflow++;
2089 mtx_unlock(&moea_table_mutex);
2091 return (first ? ENOENT : 0);
2095 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2100 * If there is an active pte entry, we need to deactivate it (and
2101 * save the ref & cfg bits).
2103 pt = moea_pvo_to_pte(pvo, pteidx);
2105 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2106 mtx_unlock(&moea_table_mutex);
2107 PVO_PTEGIDX_CLR(pvo);
2109 moea_pte_overflow--;
2113 * Update our statistics.
2115 pvo->pvo_pmap->pm_stats.resident_count--;
2116 if (pvo->pvo_vaddr & PVO_WIRED)
2117 pvo->pvo_pmap->pm_stats.wired_count--;
2120 * Save the REF/CHG bits into their cache if the page is managed.
2122 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2125 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2127 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2128 (PTE_REF | PTE_CHG));
2133 * Remove this PVO from the PV and pmap lists.
2135 LIST_REMOVE(pvo, pvo_vlink);
2136 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2139 * Remove this from the overflow list and return it to the pool
2140 * if we aren't going to reuse it.
2142 LIST_REMOVE(pvo, pvo_olink);
2143 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2144 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2145 moea_upvo_zone, pvo);
2147 moea_pvo_remove_calls++;
2151 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2156 * We can find the actual pte entry without searching by grabbing
2157 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2158 * noticing the HID bit.
2160 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2161 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2162 pteidx ^= moea_pteg_mask * 8;
2167 static struct pvo_entry *
2168 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2170 struct pvo_entry *pvo;
2175 sr = va_to_sr(pm->pm_sr, va);
2176 ptegidx = va_to_pteg(sr, va);
2178 mtx_lock(&moea_table_mutex);
2179 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2180 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2182 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2186 mtx_unlock(&moea_table_mutex);
2192 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2197 * If we haven't been supplied the ptegidx, calculate it.
2203 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2204 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2205 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2208 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2209 mtx_lock(&moea_table_mutex);
2211 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2212 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2213 "valid pte index", pvo);
2216 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2217 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2218 "pvo but no valid pte", pvo);
2221 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2222 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2223 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2224 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2227 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2229 panic("moea_pvo_to_pte: pvo %p pte does not match "
2230 "pte %p in moea_pteg_table", pvo, pt);
2233 mtx_assert(&moea_table_mutex, MA_OWNED);
2237 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2238 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2239 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2242 mtx_unlock(&moea_table_mutex);
2247 * XXX: THIS STUFF SHOULD BE IN pte.c?
2250 moea_pte_spill(vm_offset_t addr)
2252 struct pvo_entry *source_pvo, *victim_pvo;
2253 struct pvo_entry *pvo;
2262 ptegidx = va_to_pteg(sr, addr);
2265 * Have to substitute some entry. Use the primary hash for this.
2266 * Use low bits of timebase as random generator.
2268 pteg = &moea_pteg_table[ptegidx];
2269 mtx_lock(&moea_table_mutex);
2270 __asm __volatile("mftb %0" : "=r"(i));
2276 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2278 * We need to find a pvo entry for this address.
2280 if (source_pvo == NULL &&
2281 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2282 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2284 * Now found an entry to be spilled into the pteg.
2285 * The PTE is now valid, so we know it's active.
2287 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2290 PVO_PTEGIDX_SET(pvo, j);
2291 moea_pte_overflow--;
2292 mtx_unlock(&moea_table_mutex);
2298 if (victim_pvo != NULL)
2303 * We also need the pvo entry of the victim we are replacing
2304 * so save the R & C bits of the PTE.
2306 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2307 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2309 if (source_pvo != NULL)
2314 if (source_pvo == NULL) {
2315 mtx_unlock(&moea_table_mutex);
2319 if (victim_pvo == NULL) {
2320 if ((pt->pte_hi & PTE_HID) == 0)
2321 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2325 * If this is a secondary PTE, we need to search it's primary
2326 * pvo bucket for the matching PVO.
2328 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2331 * We also need the pvo entry of the victim we are
2332 * replacing so save the R & C bits of the PTE.
2334 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2340 if (victim_pvo == NULL)
2341 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2346 * We are invalidating the TLB entry for the EA we are replacing even
2347 * though it's valid. If we don't, we lose any ref/chg bit changes
2348 * contained in the TLB entry.
2350 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2352 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2353 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2355 PVO_PTEGIDX_CLR(victim_pvo);
2356 PVO_PTEGIDX_SET(source_pvo, i);
2357 moea_pte_replacements++;
2359 mtx_unlock(&moea_table_mutex);
2363 static __inline struct pvo_entry *
2364 moea_pte_spillable_ident(u_int ptegidx)
2367 struct pvo_entry *pvo_walk, *pvo = NULL;
2369 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2370 if (pvo_walk->pvo_vaddr & PVO_WIRED)
2373 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2376 pt = moea_pvo_to_pte(pvo_walk, -1);
2383 mtx_unlock(&moea_table_mutex);
2384 if (!(pt->pte_lo & PTE_REF))
2392 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2395 struct pvo_entry *victim_pvo;
2398 u_int pteg_bkpidx = ptegidx;
2400 mtx_assert(&moea_table_mutex, MA_OWNED);
2403 * First try primary hash.
2405 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2406 if ((pt->pte_hi & PTE_VALID) == 0) {
2407 pvo_pt->pte_hi &= ~PTE_HID;
2408 moea_pte_set(pt, pvo_pt);
2414 * Now try secondary hash.
2416 ptegidx ^= moea_pteg_mask;
2418 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2419 if ((pt->pte_hi & PTE_VALID) == 0) {
2420 pvo_pt->pte_hi |= PTE_HID;
2421 moea_pte_set(pt, pvo_pt);
2426 /* Try again, but this time try to force a PTE out. */
2427 ptegidx = pteg_bkpidx;
2429 victim_pvo = moea_pte_spillable_ident(ptegidx);
2430 if (victim_pvo == NULL) {
2431 ptegidx ^= moea_pteg_mask;
2432 victim_pvo = moea_pte_spillable_ident(ptegidx);
2435 if (victim_pvo == NULL) {
2436 panic("moea_pte_insert: overflow");
2440 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2442 if (pteg_bkpidx == ptegidx)
2443 pvo_pt->pte_hi &= ~PTE_HID;
2445 pvo_pt->pte_hi |= PTE_HID;
2448 * Synchronize the sacrifice PTE with its PVO, then mark both
2449 * invalid. The PVO will be reused when/if the VM system comes
2450 * here after a fault.
2452 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2454 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2455 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2460 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2461 PVO_PTEGIDX_CLR(victim_pvo);
2462 moea_pte_overflow++;
2463 moea_pte_set(pt, pvo_pt);
2465 return (victim_idx & 7);
2469 moea_query_bit(vm_page_t m, int ptebit)
2471 struct pvo_entry *pvo;
2474 rw_assert(&pvh_global_lock, RA_WLOCKED);
2475 if (moea_attr_fetch(m) & ptebit)
2478 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2481 * See if we saved the bit off. If so, cache it and return
2484 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2485 moea_attr_save(m, ptebit);
2491 * No luck, now go through the hard part of looking at the PTEs
2492 * themselves. Sync so that any pending REF/CHG bits are flushed to
2496 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2499 * See if this pvo has a valid PTE. if so, fetch the
2500 * REF/CHG bits from the valid PTE. If the appropriate
2501 * ptebit is set, cache it and return success.
2503 pt = moea_pvo_to_pte(pvo, -1);
2505 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2506 mtx_unlock(&moea_table_mutex);
2507 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2508 moea_attr_save(m, ptebit);
2518 moea_clear_bit(vm_page_t m, int ptebit)
2521 struct pvo_entry *pvo;
2524 rw_assert(&pvh_global_lock, RA_WLOCKED);
2527 * Clear the cached value.
2529 moea_attr_clear(m, ptebit);
2532 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2533 * we can reset the right ones). note that since the pvo entries and
2534 * list heads are accessed via BAT0 and are never placed in the page
2535 * table, we don't have to worry about further accesses setting the
2541 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2542 * valid pte clear the ptebit from the valid pte.
2545 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2546 pt = moea_pvo_to_pte(pvo, -1);
2548 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2549 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2551 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2553 mtx_unlock(&moea_table_mutex);
2555 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2562 * Return true if the physical range is encompassed by the battable[idx]
2565 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size)
2573 * Return immediately if not a valid mapping
2575 if (!(battable[idx].batu & BAT_Vs))
2579 * The BAT entry must be cache-inhibited, guarded, and r/w
2580 * so it can function as an i/o page
2582 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2583 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2587 * The address should be within the BAT range. Assume that the
2588 * start address in the BAT has the correct alignment (thus
2589 * not requiring masking)
2591 start = battable[idx].batl & BAT_PBS;
2592 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2593 end = start | (bat_ble << 15) | 0x7fff;
2595 if ((pa < start) || ((pa + size) > end))
2602 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2607 * This currently does not work for entries that
2608 * overlap 256M BAT segments.
2611 for(i = 0; i < 16; i++)
2612 if (moea_bat_mapped(i, pa, size) == 0)
2619 * Map a set of physical memory pages into the kernel virtual
2620 * address space. Return a pointer to where it is mapped. This
2621 * routine is intended to be used for mapping device memory,
2625 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2628 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2632 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2634 vm_offset_t va, tmpva, ppa, offset;
2637 ppa = trunc_page(pa);
2638 offset = pa & PAGE_MASK;
2639 size = roundup(offset + size, PAGE_SIZE);
2642 * If the physical address lies within a valid BAT table entry,
2643 * return the 1:1 mapping. This currently doesn't work
2644 * for regions that overlap 256M BAT segments.
2646 for (i = 0; i < 16; i++) {
2647 if (moea_bat_mapped(i, pa, size) == 0)
2648 return ((void *) pa);
2651 va = kva_alloc(size);
2653 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2655 for (tmpva = va; size > 0;) {
2656 moea_kenter_attr(mmu, tmpva, ppa, ma);
2663 return ((void *)(va + offset));
2667 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2669 vm_offset_t base, offset;
2672 * If this is outside kernel virtual space, then it's a
2673 * battable entry and doesn't require unmapping
2675 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2676 base = trunc_page(va);
2677 offset = va & PAGE_MASK;
2678 size = roundup(offset + size, PAGE_SIZE);
2679 kva_free(base, size);
2684 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2686 struct pvo_entry *pvo;
2693 lim = round_page(va);
2694 len = MIN(lim - va, sz);
2695 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2697 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2699 moea_syncicache(pa, len);
2708 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2714 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2717 moea_scan_init(mmu_t mmu)
2719 struct pvo_entry *pvo;
2724 /* Initialize phys. segments for dumpsys(). */
2725 memset(&dump_map, 0, sizeof(dump_map));
2726 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2727 for (i = 0; i < pregions_sz; i++) {
2728 dump_map[i].pa_start = pregions[i].mr_start;
2729 dump_map[i].pa_size = pregions[i].mr_size;
2734 /* Virtual segments for minidumps: */
2735 memset(&dump_map, 0, sizeof(dump_map));
2737 /* 1st: kernel .data and .bss. */
2738 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2739 dump_map[0].pa_size =
2740 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2742 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2743 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
2744 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2746 /* 3rd: kernel VM. */
2747 va = dump_map[1].pa_start + dump_map[1].pa_size;
2748 /* Find start of next chunk (from va). */
2749 while (va < virtual_end) {
2750 /* Don't dump the buffer cache. */
2751 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2752 va = kmi.buffer_eva;
2755 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
2756 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2760 if (va < virtual_end) {
2761 dump_map[2].pa_start = va;
2763 /* Find last page in chunk. */
2764 while (va < virtual_end) {
2765 /* Don't run into the buffer cache. */
2766 if (va == kmi.buffer_sva)
2768 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF,
2771 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2775 dump_map[2].pa_size = va - dump_map[2].pa_start;