2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_kstack_pages.h"
114 #include <sys/param.h>
115 #include <sys/kernel.h>
116 #include <sys/queue.h>
117 #include <sys/cpuset.h>
119 #include <sys/lock.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #include <sys/systm.h>
127 #include <sys/vmmeter.h>
129 #include <dev/ofw/openfirm.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
141 #include <machine/cpu.h>
142 #include <machine/platform.h>
143 #include <machine/bat.h>
144 #include <machine/frame.h>
145 #include <machine/md_var.h>
146 #include <machine/psl.h>
147 #include <machine/pte.h>
148 #include <machine/smp.h>
149 #include <machine/sr.h>
150 #include <machine/mmuvar.h>
151 #include <machine/trap_aim.h>
157 #define TODO panic("%s: not implemented", __func__);
159 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
160 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
161 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
171 * Map of physical memory regions.
173 static struct mem_region *regions;
174 static struct mem_region *pregions;
175 static u_int phys_avail_count;
176 static int regions_sz, pregions_sz;
177 static struct ofw_map *translations;
180 * Lock for the pteg and pvo tables.
182 struct mtx moea_table_mutex;
183 struct mtx moea_vsid_mutex;
185 /* tlbie instruction synchronization */
186 static struct mtx tlbie_mtx;
191 static struct pteg *moea_pteg_table;
192 u_int moea_pteg_count;
193 u_int moea_pteg_mask;
198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
199 struct pvo_head moea_pvo_kunmanaged =
200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
202 static struct rwlock_padalign pvh_global_lock;
204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
207 #define BPVO_POOL_SIZE 32768
208 static struct pvo_entry *moea_bpvo_pool;
209 static int moea_bpvo_pool_index = 0;
211 #define VSID_NBPW (sizeof(u_int32_t) * 8)
212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
214 static boolean_t moea_initialized = FALSE;
219 u_int moea_pte_valid = 0;
220 u_int moea_pte_overflow = 0;
221 u_int moea_pte_replacements = 0;
222 u_int moea_pvo_entries = 0;
223 u_int moea_pvo_enter_calls = 0;
224 u_int moea_pvo_remove_calls = 0;
225 u_int moea_pte_spills = 0;
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
229 &moea_pte_overflow, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
231 &moea_pte_replacements, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
235 &moea_pvo_enter_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
237 &moea_pvo_remove_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
239 &moea_pte_spills, 0, "");
242 * Allocate physical memory for use in moea_bootstrap.
244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
249 static int moea_pte_insert(u_int, struct pte *);
254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
255 vm_offset_t, vm_offset_t, u_int, int);
256 static void moea_pvo_remove(struct pvo_entry *, int);
257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
263 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
264 vm_prot_t, boolean_t);
265 static void moea_syncicache(vm_offset_t, vm_size_t);
266 static boolean_t moea_query_bit(vm_page_t, int);
267 static u_int moea_clear_bit(vm_page_t, int);
268 static void moea_kremove(mmu_t, vm_offset_t);
269 int moea_pte_spill(vm_offset_t);
272 * Kernel MMU interface
274 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
275 void moea_clear_modify(mmu_t, vm_page_t);
276 void moea_clear_reference(mmu_t, vm_page_t);
277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
278 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
279 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
281 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
282 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
283 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
284 void moea_init(mmu_t);
285 boolean_t moea_is_modified(mmu_t, vm_page_t);
286 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
287 boolean_t moea_is_referenced(mmu_t, vm_page_t);
288 int moea_ts_referenced(mmu_t, vm_page_t);
289 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
290 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
291 int moea_page_wired_mappings(mmu_t, vm_page_t);
292 void moea_pinit(mmu_t, pmap_t);
293 void moea_pinit0(mmu_t, pmap_t);
294 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
295 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
296 void moea_qremove(mmu_t, vm_offset_t, int);
297 void moea_release(mmu_t, pmap_t);
298 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
299 void moea_remove_all(mmu_t, vm_page_t);
300 void moea_remove_write(mmu_t, vm_page_t);
301 void moea_zero_page(mmu_t, vm_page_t);
302 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
303 void moea_zero_page_idle(mmu_t, vm_page_t);
304 void moea_activate(mmu_t, struct thread *);
305 void moea_deactivate(mmu_t, struct thread *);
306 void moea_cpu_bootstrap(mmu_t, int);
307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
318 static mmu_method_t moea_methods[] = {
319 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
320 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
321 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
322 MMUMETHOD(mmu_copy_page, moea_copy_page),
323 MMUMETHOD(mmu_enter, moea_enter),
324 MMUMETHOD(mmu_enter_object, moea_enter_object),
325 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
326 MMUMETHOD(mmu_extract, moea_extract),
327 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
328 MMUMETHOD(mmu_init, moea_init),
329 MMUMETHOD(mmu_is_modified, moea_is_modified),
330 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
331 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
332 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
333 MMUMETHOD(mmu_map, moea_map),
334 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
335 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
336 MMUMETHOD(mmu_pinit, moea_pinit),
337 MMUMETHOD(mmu_pinit0, moea_pinit0),
338 MMUMETHOD(mmu_protect, moea_protect),
339 MMUMETHOD(mmu_qenter, moea_qenter),
340 MMUMETHOD(mmu_qremove, moea_qremove),
341 MMUMETHOD(mmu_release, moea_release),
342 MMUMETHOD(mmu_remove, moea_remove),
343 MMUMETHOD(mmu_remove_all, moea_remove_all),
344 MMUMETHOD(mmu_remove_write, moea_remove_write),
345 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
346 MMUMETHOD(mmu_zero_page, moea_zero_page),
347 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
348 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
349 MMUMETHOD(mmu_activate, moea_activate),
350 MMUMETHOD(mmu_deactivate, moea_deactivate),
351 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
353 /* Internal interfaces */
354 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
355 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
356 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
357 MMUMETHOD(mmu_mapdev, moea_mapdev),
358 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
359 MMUMETHOD(mmu_kextract, moea_kextract),
360 MMUMETHOD(mmu_kenter, moea_kenter),
361 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
362 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
367 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
369 static __inline uint32_t
370 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
375 if (ma != VM_MEMATTR_DEFAULT) {
377 case VM_MEMATTR_UNCACHEABLE:
378 return (PTE_I | PTE_G);
379 case VM_MEMATTR_WRITE_COMBINING:
380 case VM_MEMATTR_WRITE_BACK:
381 case VM_MEMATTR_PREFETCHABLE:
383 case VM_MEMATTR_WRITE_THROUGH:
384 return (PTE_W | PTE_M);
389 * Assume the page is cache inhibited and access is guarded unless
390 * it's in our available memory array.
392 pte_lo = PTE_I | PTE_G;
393 for (i = 0; i < pregions_sz; i++) {
394 if ((pa >= pregions[i].mr_start) &&
395 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
405 tlbie(vm_offset_t va)
408 mtx_lock_spin(&tlbie_mtx);
409 __asm __volatile("ptesync");
410 __asm __volatile("tlbie %0" :: "r"(va));
411 __asm __volatile("eieio; tlbsync; ptesync");
412 mtx_unlock_spin(&tlbie_mtx);
420 for (va = 0; va < 0x00040000; va += 0x00001000) {
421 __asm __volatile("tlbie %0" :: "r"(va));
424 __asm __volatile("tlbsync");
429 va_to_sr(u_int *sr, vm_offset_t va)
431 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
434 static __inline u_int
435 va_to_pteg(u_int sr, vm_offset_t addr)
439 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
441 return (hash & moea_pteg_mask);
444 static __inline struct pvo_head *
445 vm_page_to_pvoh(vm_page_t m)
448 return (&m->md.mdpg_pvoh);
452 moea_attr_clear(vm_page_t m, int ptebit)
455 rw_assert(&pvh_global_lock, RA_WLOCKED);
456 m->md.mdpg_attrs &= ~ptebit;
460 moea_attr_fetch(vm_page_t m)
463 return (m->md.mdpg_attrs);
467 moea_attr_save(vm_page_t m, int ptebit)
470 rw_assert(&pvh_global_lock, RA_WLOCKED);
471 m->md.mdpg_attrs |= ptebit;
475 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
477 if (pt->pte_hi == pvo_pt->pte_hi)
484 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
486 return (pt->pte_hi & ~PTE_VALID) ==
487 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
488 ((va >> ADDR_API_SHFT) & PTE_API) | which);
492 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
495 mtx_assert(&moea_table_mutex, MA_OWNED);
498 * Construct a PTE. Default to IMB initially. Valid bit only gets
499 * set when the real pte is set in memory.
501 * Note: Don't set the valid bit for correct operation of tlb update.
503 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
504 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
509 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
512 mtx_assert(&moea_table_mutex, MA_OWNED);
513 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
517 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
520 mtx_assert(&moea_table_mutex, MA_OWNED);
523 * As shown in Section 7.6.3.2.3
525 pt->pte_lo &= ~ptebit;
530 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
533 mtx_assert(&moea_table_mutex, MA_OWNED);
534 pvo_pt->pte_hi |= PTE_VALID;
537 * Update the PTE as defined in section 7.6.3.1.
538 * Note that the REF/CHG bits are from pvo_pt and thus should havce
539 * been saved so this routine can restore them (if desired).
541 pt->pte_lo = pvo_pt->pte_lo;
543 pt->pte_hi = pvo_pt->pte_hi;
549 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
552 mtx_assert(&moea_table_mutex, MA_OWNED);
553 pvo_pt->pte_hi &= ~PTE_VALID;
556 * Force the reg & chg bits back into the PTEs.
561 * Invalidate the pte.
563 pt->pte_hi &= ~PTE_VALID;
568 * Save the reg & chg bits.
570 moea_pte_synch(pt, pvo_pt);
575 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
581 moea_pte_unset(pt, pvo_pt, va);
582 moea_pte_set(pt, pvo_pt);
586 * Quick sort callout for comparing memory regions.
588 static int om_cmp(const void *a, const void *b);
591 om_cmp(const void *a, const void *b)
593 const struct ofw_map *mapa;
594 const struct ofw_map *mapb;
598 if (mapa->om_pa < mapb->om_pa)
600 else if (mapa->om_pa > mapb->om_pa)
607 moea_cpu_bootstrap(mmu_t mmup, int ap)
614 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
615 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
617 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
618 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
624 * Special case for the Wii: don't install the PCI BAT.
626 if (strcmp(installed_platform(), "wii") != 0) {
628 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
629 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
635 __asm __volatile("mtibatu 1,%0" :: "r"(0));
636 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
637 __asm __volatile("mtibatu 2,%0" :: "r"(0));
638 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
639 __asm __volatile("mtibatu 3,%0" :: "r"(0));
642 for (i = 0; i < 16; i++)
643 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
646 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
647 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
654 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
657 phandle_t chosen, mmu;
660 vm_size_t size, physsz, hwphyssz;
661 vm_offset_t pa, va, off;
666 * Set up BAT0 to map the lowest 256 MB area
668 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
669 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
672 * Map PCI memory space.
674 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
675 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
677 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
678 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
680 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
681 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
683 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
684 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
689 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
690 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
693 * Use an IBAT and a DBAT to map the bottom segment of memory
694 * where we are. Turn off instruction relocation temporarily
695 * to prevent faults while reprogramming the IBAT.
698 mtmsr(msr & ~PSL_IR);
699 __asm (".balign 32; \n"
700 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
701 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
702 :: "r"(battable[0].batu), "r"(battable[0].batl));
706 if (strcmp(installed_platform(), "wii") != 0) {
709 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
710 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
716 /* set global direct map flag */
719 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
720 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
722 for (i = 0; i < pregions_sz; i++) {
726 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
727 pregions[i].mr_start,
728 pregions[i].mr_start + pregions[i].mr_size,
729 pregions[i].mr_size);
731 * Install entries into the BAT table to allow all
732 * of physmem to be convered by on-demand BAT entries.
733 * The loop will sometimes set the same battable element
734 * twice, but that's fine since they won't be used for
737 pa = pregions[i].mr_start & 0xf0000000;
738 end = pregions[i].mr_start + pregions[i].mr_size;
740 u_int n = pa >> ADDR_SR_SHFT;
742 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
743 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
744 pa += SEGMENT_LENGTH;
748 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
749 panic("moea_bootstrap: phys_avail too small");
751 phys_avail_count = 0;
754 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
755 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
756 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
757 regions[i].mr_start + regions[i].mr_size,
760 (physsz + regions[i].mr_size) >= hwphyssz) {
761 if (physsz < hwphyssz) {
762 phys_avail[j] = regions[i].mr_start;
763 phys_avail[j + 1] = regions[i].mr_start +
770 phys_avail[j] = regions[i].mr_start;
771 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
773 physsz += regions[i].mr_size;
776 /* Check for overlap with the kernel and exception vectors */
777 for (j = 0; j < 2*phys_avail_count; j+=2) {
778 if (phys_avail[j] < EXC_LAST)
779 phys_avail[j] += EXC_LAST;
781 if (kernelstart >= phys_avail[j] &&
782 kernelstart < phys_avail[j+1]) {
783 if (kernelend < phys_avail[j+1]) {
784 phys_avail[2*phys_avail_count] =
785 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
786 phys_avail[2*phys_avail_count + 1] =
791 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
794 if (kernelend >= phys_avail[j] &&
795 kernelend < phys_avail[j+1]) {
796 if (kernelstart > phys_avail[j]) {
797 phys_avail[2*phys_avail_count] = phys_avail[j];
798 phys_avail[2*phys_avail_count + 1] =
799 kernelstart & ~PAGE_MASK;
803 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
807 physmem = btoc(physsz);
810 * Allocate PTEG table.
813 moea_pteg_count = PTEGCOUNT;
815 moea_pteg_count = 0x1000;
817 while (moea_pteg_count < physmem)
818 moea_pteg_count <<= 1;
820 moea_pteg_count >>= 1;
821 #endif /* PTEGCOUNT */
823 size = moea_pteg_count * sizeof(struct pteg);
824 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
826 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
827 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
828 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
829 moea_pteg_mask = moea_pteg_count - 1;
832 * Allocate pv/overflow lists.
834 size = sizeof(struct pvo_head) * moea_pteg_count;
835 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
837 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
838 for (i = 0; i < moea_pteg_count; i++)
839 LIST_INIT(&moea_pvo_table[i]);
842 * Initialize the lock that synchronizes access to the pteg and pvo
845 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
847 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
849 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
852 * Initialise the unmanaged pvo pool.
854 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
855 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
856 moea_bpvo_pool_index = 0;
859 * Make sure kernel vsid is allocated as well as VSID 0.
861 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
862 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
863 moea_vsid_bitmap[0] |= 1;
866 * Initialize the kernel pmap (which is statically allocated).
868 PMAP_LOCK_INIT(kernel_pmap);
869 for (i = 0; i < 16; i++)
870 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
871 CPU_FILL(&kernel_pmap->pm_active);
872 RB_INIT(&kernel_pmap->pmap_pvo);
875 * Initialize the global pv list lock.
877 rw_init(&pvh_global_lock, "pmap pv global");
880 * Set up the Open Firmware mappings
882 chosen = OF_finddevice("/chosen");
883 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
884 (mmu = OF_instance_to_package(mmui)) != -1 &&
885 (sz = OF_getproplen(mmu, "translations")) != -1) {
887 for (i = 0; phys_avail[i] != 0; i += 2) {
888 if (phys_avail[i + 1] >= sz) {
889 translations = (struct ofw_map *)phys_avail[i];
893 if (translations == NULL)
894 panic("moea_bootstrap: no space to copy translations");
895 bzero(translations, sz);
896 if (OF_getprop(mmu, "translations", translations, sz) == -1)
897 panic("moea_bootstrap: can't get ofw translations");
898 CTR0(KTR_PMAP, "moea_bootstrap: translations");
899 sz /= sizeof(*translations);
900 qsort(translations, sz, sizeof (*translations), om_cmp);
901 for (i = 0; i < sz; i++) {
902 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
903 translations[i].om_pa, translations[i].om_va,
904 translations[i].om_len);
907 * If the mapping is 1:1, let the RAM and device
908 * on-demand BAT tables take care of the translation.
910 if (translations[i].om_va == translations[i].om_pa)
913 /* Enter the pages */
914 for (off = 0; off < translations[i].om_len;
916 moea_kenter(mmup, translations[i].om_va + off,
917 translations[i].om_pa + off);
922 * Calculate the last available physical address.
924 for (i = 0; phys_avail[i + 2] != 0; i += 2)
926 Maxmem = powerpc_btop(phys_avail[i + 1]);
928 moea_cpu_bootstrap(mmup,0);
933 * Set the start and end of kva.
935 virtual_avail = VM_MIN_KERNEL_ADDRESS;
936 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
939 * Allocate a kernel stack with a guard page for thread0 and map it
940 * into the kernel page map.
942 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
943 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
944 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
945 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
946 thread0.td_kstack = va;
947 thread0.td_kstack_pages = KSTACK_PAGES;
948 for (i = 0; i < KSTACK_PAGES; i++) {
949 moea_kenter(mmup, va, pa);
955 * Allocate virtual address space for the message buffer.
957 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
958 msgbufp = (struct msgbuf *)virtual_avail;
960 virtual_avail += round_page(msgbufsize);
961 while (va < virtual_avail) {
962 moea_kenter(mmup, va, pa);
968 * Allocate virtual address space for the dynamic percpu area.
970 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
971 dpcpu = (void *)virtual_avail;
973 virtual_avail += DPCPU_SIZE;
974 while (va < virtual_avail) {
975 moea_kenter(mmup, va, pa);
979 dpcpu_init(dpcpu, 0);
983 * Activate a user pmap. The pmap must be activated before it's address
984 * space can be accessed in any way.
987 moea_activate(mmu_t mmu, struct thread *td)
992 * Load all the data we need up front to encourage the compiler to
993 * not issue any loads while we have interrupts disabled below.
995 pm = &td->td_proc->p_vmspace->vm_pmap;
998 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
999 PCPU_SET(curpmap, pmr);
1003 moea_deactivate(mmu_t mmu, struct thread *td)
1007 pm = &td->td_proc->p_vmspace->vm_pmap;
1008 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1009 PCPU_SET(curpmap, NULL);
1013 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1015 struct pvo_entry *pvo;
1018 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1022 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1023 pm->pm_stats.wired_count++;
1024 pvo->pvo_vaddr |= PVO_WIRED;
1026 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1027 pm->pm_stats.wired_count--;
1028 pvo->pvo_vaddr &= ~PVO_WIRED;
1035 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1040 dst = VM_PAGE_TO_PHYS(mdst);
1041 src = VM_PAGE_TO_PHYS(msrc);
1043 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1047 * Zero a page of physical memory by temporarily mapping it into the tlb.
1050 moea_zero_page(mmu_t mmu, vm_page_t m)
1052 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1053 void *va = (void *)pa;
1055 bzero(va, PAGE_SIZE);
1059 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1061 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1062 void *va = (void *)(pa + off);
1068 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1070 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1071 void *va = (void *)pa;
1073 bzero(va, PAGE_SIZE);
1077 * Map the given physical page at the specified virtual address in the
1078 * target pmap with the protection requested. If specified the page
1079 * will be wired down.
1082 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1086 rw_wlock(&pvh_global_lock);
1088 moea_enter_locked(pmap, va, m, prot, wired);
1089 rw_wunlock(&pvh_global_lock);
1094 * Map the given physical page at the specified virtual address in the
1095 * target pmap with the protection requested. If specified the page
1096 * will be wired down.
1098 * The page queues and pmap must be locked.
1101 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1104 struct pvo_head *pvo_head;
1107 u_int pte_lo, pvo_flags;
1110 if (!moea_initialized) {
1111 pvo_head = &moea_pvo_kunmanaged;
1112 zone = moea_upvo_zone;
1116 pvo_head = vm_page_to_pvoh(m);
1118 zone = moea_mpvo_zone;
1119 pvo_flags = PVO_MANAGED;
1121 if (pmap_bootstrapped)
1122 rw_assert(&pvh_global_lock, RA_WLOCKED);
1123 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1124 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0)
1125 VM_OBJECT_ASSERT_WLOCKED(m->object);
1127 /* XXX change the pvo head for fake pages */
1128 if ((m->oflags & VPO_UNMANAGED) != 0) {
1129 pvo_flags &= ~PVO_MANAGED;
1130 pvo_head = &moea_pvo_kunmanaged;
1131 zone = moea_upvo_zone;
1134 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1136 if (prot & VM_PROT_WRITE) {
1138 if (pmap_bootstrapped &&
1139 (m->oflags & VPO_UNMANAGED) == 0)
1140 vm_page_aflag_set(m, PGA_WRITEABLE);
1144 if (prot & VM_PROT_EXECUTE)
1145 pvo_flags |= PVO_EXECUTABLE;
1148 pvo_flags |= PVO_WIRED;
1150 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1154 * Flush the real page from the instruction cache. This has be done
1155 * for all user mappings to prevent information leakage via the
1156 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1157 * mapping for a page.
1159 if (pmap != kernel_pmap && error == ENOENT &&
1160 (pte_lo & (PTE_I | PTE_G)) == 0)
1161 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1165 * Maps a sequence of resident pages belonging to the same object.
1166 * The sequence begins with the given page m_start. This page is
1167 * mapped at the given virtual address start. Each subsequent page is
1168 * mapped at a virtual address that is offset from start by the same
1169 * amount as the page is offset from m_start within the object. The
1170 * last page in the sequence is the page with the largest offset from
1171 * m_start that can be mapped at a virtual address less than the given
1172 * virtual address end. Not every virtual page between start and end
1173 * is mapped; only those for which a resident page exists with the
1174 * corresponding offset from m_start are mapped.
1177 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1178 vm_page_t m_start, vm_prot_t prot)
1181 vm_pindex_t diff, psize;
1183 psize = atop(end - start);
1185 rw_wlock(&pvh_global_lock);
1187 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1188 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1189 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1190 m = TAILQ_NEXT(m, listq);
1192 rw_wunlock(&pvh_global_lock);
1197 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1201 rw_wlock(&pvh_global_lock);
1203 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1205 rw_wunlock(&pvh_global_lock);
1210 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1212 struct pvo_entry *pvo;
1216 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1220 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1226 * Atomically extract and hold the physical page with the given
1227 * pmap and virtual address pair if that mapping permits the given
1231 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1233 struct pvo_entry *pvo;
1241 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1242 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1243 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1244 (prot & VM_PROT_WRITE) == 0)) {
1245 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1247 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1256 moea_init(mmu_t mmu)
1259 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1260 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1261 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1262 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1263 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1264 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1265 moea_initialized = TRUE;
1269 moea_is_referenced(mmu_t mmu, vm_page_t m)
1273 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1274 ("moea_is_referenced: page %p is not managed", m));
1275 rw_wlock(&pvh_global_lock);
1276 rv = moea_query_bit(m, PTE_REF);
1277 rw_wunlock(&pvh_global_lock);
1282 moea_is_modified(mmu_t mmu, vm_page_t m)
1286 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1287 ("moea_is_modified: page %p is not managed", m));
1290 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1291 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1292 * is clear, no PTEs can have PTE_CHG set.
1294 VM_OBJECT_ASSERT_WLOCKED(m->object);
1295 if ((m->oflags & VPO_BUSY) == 0 &&
1296 (m->aflags & PGA_WRITEABLE) == 0)
1298 rw_wlock(&pvh_global_lock);
1299 rv = moea_query_bit(m, PTE_CHG);
1300 rw_wunlock(&pvh_global_lock);
1305 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1307 struct pvo_entry *pvo;
1311 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1312 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1318 moea_clear_reference(mmu_t mmu, vm_page_t m)
1321 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1322 ("moea_clear_reference: page %p is not managed", m));
1323 rw_wlock(&pvh_global_lock);
1324 moea_clear_bit(m, PTE_REF);
1325 rw_wunlock(&pvh_global_lock);
1329 moea_clear_modify(mmu_t mmu, vm_page_t m)
1332 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1333 ("moea_clear_modify: page %p is not managed", m));
1334 VM_OBJECT_ASSERT_WLOCKED(m->object);
1335 KASSERT((m->oflags & VPO_BUSY) == 0,
1336 ("moea_clear_modify: page %p is busy", m));
1339 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1340 * set. If the object containing the page is locked and the page is
1341 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1343 if ((m->aflags & PGA_WRITEABLE) == 0)
1345 rw_wlock(&pvh_global_lock);
1346 moea_clear_bit(m, PTE_CHG);
1347 rw_wunlock(&pvh_global_lock);
1351 * Clear the write and modified bits in each of the given page's mappings.
1354 moea_remove_write(mmu_t mmu, vm_page_t m)
1356 struct pvo_entry *pvo;
1361 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1362 ("moea_remove_write: page %p is not managed", m));
1365 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1366 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1367 * is clear, no page table entries need updating.
1369 VM_OBJECT_ASSERT_WLOCKED(m->object);
1370 if ((m->oflags & VPO_BUSY) == 0 &&
1371 (m->aflags & PGA_WRITEABLE) == 0)
1373 rw_wlock(&pvh_global_lock);
1374 lo = moea_attr_fetch(m);
1376 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1377 pmap = pvo->pvo_pmap;
1379 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1380 pt = moea_pvo_to_pte(pvo, -1);
1381 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1382 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1384 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1385 lo |= pvo->pvo_pte.pte.pte_lo;
1386 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1387 moea_pte_change(pt, &pvo->pvo_pte.pte,
1389 mtx_unlock(&moea_table_mutex);
1394 if ((lo & PTE_CHG) != 0) {
1395 moea_attr_clear(m, PTE_CHG);
1398 vm_page_aflag_clear(m, PGA_WRITEABLE);
1399 rw_wunlock(&pvh_global_lock);
1403 * moea_ts_referenced:
1405 * Return a count of reference bits for a page, clearing those bits.
1406 * It is not necessary for every reference bit to be cleared, but it
1407 * is necessary that 0 only be returned when there are truly no
1408 * reference bits set.
1410 * XXX: The exact number of bits to check and clear is a matter that
1411 * should be tested and standardized at some point in the future for
1412 * optimal aging of shared pages.
1415 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1419 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1420 ("moea_ts_referenced: page %p is not managed", m));
1421 rw_wlock(&pvh_global_lock);
1422 count = moea_clear_bit(m, PTE_REF);
1423 rw_wunlock(&pvh_global_lock);
1428 * Modify the WIMG settings of all mappings for a page.
1431 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1433 struct pvo_entry *pvo;
1434 struct pvo_head *pvo_head;
1439 if ((m->oflags & VPO_UNMANAGED) != 0) {
1440 m->md.mdpg_cache_attrs = ma;
1444 rw_wlock(&pvh_global_lock);
1445 pvo_head = vm_page_to_pvoh(m);
1446 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1448 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1449 pmap = pvo->pvo_pmap;
1451 pt = moea_pvo_to_pte(pvo, -1);
1452 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1453 pvo->pvo_pte.pte.pte_lo |= lo;
1455 moea_pte_change(pt, &pvo->pvo_pte.pte,
1457 if (pvo->pvo_pmap == kernel_pmap)
1460 mtx_unlock(&moea_table_mutex);
1463 m->md.mdpg_cache_attrs = ma;
1464 rw_wunlock(&pvh_global_lock);
1468 * Map a wired page into kernel virtual address space.
1471 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1474 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1478 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1484 if (va < VM_MIN_KERNEL_ADDRESS)
1485 panic("moea_kenter: attempt to enter non-kernel address %#x",
1489 pte_lo = moea_calc_wimg(pa, ma);
1491 PMAP_LOCK(kernel_pmap);
1492 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1493 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1495 if (error != 0 && error != ENOENT)
1496 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1499 PMAP_UNLOCK(kernel_pmap);
1503 * Extract the physical page address associated with the given kernel virtual
1507 moea_kextract(mmu_t mmu, vm_offset_t va)
1509 struct pvo_entry *pvo;
1513 * Allow direct mappings on 32-bit OEA
1515 if (va < VM_MIN_KERNEL_ADDRESS) {
1519 PMAP_LOCK(kernel_pmap);
1520 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1521 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1522 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1523 PMAP_UNLOCK(kernel_pmap);
1528 * Remove a wired page from kernel virtual address space.
1531 moea_kremove(mmu_t mmu, vm_offset_t va)
1534 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1538 * Map a range of physical addresses into kernel virtual address space.
1540 * The value passed in *virt is a suggested virtual address for the mapping.
1541 * Architectures which can support a direct-mapped physical to virtual region
1542 * can return the appropriate address within that region, leaving '*virt'
1543 * unchanged. We cannot and therefore do not; *virt is updated with the
1544 * first usable address after the mapped region.
1547 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1548 vm_paddr_t pa_end, int prot)
1550 vm_offset_t sva, va;
1554 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1555 moea_kenter(mmu, va, pa_start);
1561 * Returns true if the pmap's pv is one of the first
1562 * 16 pvs linked to from this page. This count may
1563 * be changed upwards or downwards in the future; it
1564 * is only necessary that true be returned for a small
1565 * subset of pmaps for proper page aging.
1568 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1571 struct pvo_entry *pvo;
1574 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1575 ("moea_page_exists_quick: page %p is not managed", m));
1578 rw_wlock(&pvh_global_lock);
1579 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1580 if (pvo->pvo_pmap == pmap) {
1587 rw_wunlock(&pvh_global_lock);
1592 * Return the number of managed mappings to the given physical page
1596 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1598 struct pvo_entry *pvo;
1602 if ((m->oflags & VPO_UNMANAGED) != 0)
1604 rw_wlock(&pvh_global_lock);
1605 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1606 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1608 rw_wunlock(&pvh_global_lock);
1612 static u_int moea_vsidcontext;
1615 moea_pinit(mmu_t mmu, pmap_t pmap)
1620 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1621 PMAP_LOCK_INIT(pmap);
1622 RB_INIT(&pmap->pmap_pvo);
1625 __asm __volatile("mftb %0" : "=r"(entropy));
1627 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1629 pmap->pmap_phys = pmap;
1633 mtx_lock(&moea_vsid_mutex);
1635 * Allocate some segment registers for this pmap.
1637 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1641 * Create a new value by mutiplying by a prime and adding in
1642 * entropy from the timebase register. This is to make the
1643 * VSID more random so that the PT hash function collides
1644 * less often. (Note that the prime casues gcc to do shifts
1645 * instead of a multiply.)
1647 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1648 hash = moea_vsidcontext & (NPMAPS - 1);
1649 if (hash == 0) /* 0 is special, avoid it */
1652 mask = 1 << (hash & (VSID_NBPW - 1));
1653 hash = (moea_vsidcontext & 0xfffff);
1654 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1655 /* anything free in this bucket? */
1656 if (moea_vsid_bitmap[n] == 0xffffffff) {
1657 entropy = (moea_vsidcontext >> 20);
1660 i = ffs(~moea_vsid_bitmap[n]) - 1;
1662 hash &= 0xfffff & ~(VSID_NBPW - 1);
1665 KASSERT(!(moea_vsid_bitmap[n] & mask),
1666 ("Allocating in-use VSID group %#x\n", hash));
1667 moea_vsid_bitmap[n] |= mask;
1668 for (i = 0; i < 16; i++)
1669 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1670 mtx_unlock(&moea_vsid_mutex);
1674 mtx_unlock(&moea_vsid_mutex);
1675 panic("moea_pinit: out of segments");
1679 * Initialize the pmap associated with process 0.
1682 moea_pinit0(mmu_t mmu, pmap_t pm)
1685 moea_pinit(mmu, pm);
1686 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1690 * Set the physical protection on the specified range of this map as requested.
1693 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1696 struct pvo_entry *pvo, *tpvo, key;
1699 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1700 ("moea_protect: non current pmap"));
1702 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1703 moea_remove(mmu, pm, sva, eva);
1707 rw_wlock(&pvh_global_lock);
1709 key.pvo_vaddr = sva;
1710 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1711 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1712 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1713 if ((prot & VM_PROT_EXECUTE) == 0)
1714 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1717 * Grab the PTE pointer before we diddle with the cached PTE
1720 pt = moea_pvo_to_pte(pvo, -1);
1722 * Change the protection of the page.
1724 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1725 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1728 * If the PVO is in the page table, update that pte as well.
1731 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1732 mtx_unlock(&moea_table_mutex);
1735 rw_wunlock(&pvh_global_lock);
1740 * Map a list of wired pages into kernel virtual address space. This is
1741 * intended for temporary mappings which do not need page modification or
1742 * references recorded. Existing mappings in the region are overwritten.
1745 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1750 while (count-- > 0) {
1751 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1758 * Remove page mappings from kernel virtual address space. Intended for
1759 * temporary mappings entered by moea_qenter.
1762 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1767 while (count-- > 0) {
1768 moea_kremove(mmu, va);
1774 moea_release(mmu_t mmu, pmap_t pmap)
1779 * Free segment register's VSID
1781 if (pmap->pm_sr[0] == 0)
1782 panic("moea_release");
1784 mtx_lock(&moea_vsid_mutex);
1785 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1786 mask = 1 << (idx % VSID_NBPW);
1788 moea_vsid_bitmap[idx] &= ~mask;
1789 mtx_unlock(&moea_vsid_mutex);
1790 PMAP_LOCK_DESTROY(pmap);
1794 * Remove the given range of addresses from the specified map.
1797 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1799 struct pvo_entry *pvo, *tpvo, key;
1801 rw_wlock(&pvh_global_lock);
1803 key.pvo_vaddr = sva;
1804 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1805 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1806 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1807 moea_pvo_remove(pvo, -1);
1810 rw_wunlock(&pvh_global_lock);
1814 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1815 * will reflect changes in pte's back to the vm_page.
1818 moea_remove_all(mmu_t mmu, vm_page_t m)
1820 struct pvo_head *pvo_head;
1821 struct pvo_entry *pvo, *next_pvo;
1824 rw_wlock(&pvh_global_lock);
1825 pvo_head = vm_page_to_pvoh(m);
1826 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1827 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1829 pmap = pvo->pvo_pmap;
1831 moea_pvo_remove(pvo, -1);
1834 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1835 moea_attr_clear(m, PTE_CHG);
1838 vm_page_aflag_clear(m, PGA_WRITEABLE);
1839 rw_wunlock(&pvh_global_lock);
1843 * Allocate a physical page of memory directly from the phys_avail map.
1844 * Can only be called from moea_bootstrap before avail start and end are
1848 moea_bootstrap_alloc(vm_size_t size, u_int align)
1853 size = round_page(size);
1854 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1856 s = (phys_avail[i] + align - 1) & ~(align - 1);
1861 if (s < phys_avail[i] || e > phys_avail[i + 1])
1864 if (s == phys_avail[i]) {
1865 phys_avail[i] += size;
1866 } else if (e == phys_avail[i + 1]) {
1867 phys_avail[i + 1] -= size;
1869 for (j = phys_avail_count * 2; j > i; j -= 2) {
1870 phys_avail[j] = phys_avail[j - 2];
1871 phys_avail[j + 1] = phys_avail[j - 1];
1874 phys_avail[i + 3] = phys_avail[i + 1];
1875 phys_avail[i + 1] = s;
1876 phys_avail[i + 2] = e;
1882 panic("moea_bootstrap_alloc: could not allocate memory");
1886 moea_syncicache(vm_offset_t pa, vm_size_t len)
1888 __syncicache((void *)pa, len);
1892 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1893 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1895 struct pvo_entry *pvo;
1902 moea_pvo_enter_calls++;
1907 * Compute the PTE Group index.
1910 sr = va_to_sr(pm->pm_sr, va);
1911 ptegidx = va_to_pteg(sr, va);
1914 * Remove any existing mapping for this page. Reuse the pvo entry if
1915 * there is a mapping.
1917 mtx_lock(&moea_table_mutex);
1918 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1919 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1920 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1921 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1922 (pte_lo & PTE_PP)) {
1923 mtx_unlock(&moea_table_mutex);
1926 moea_pvo_remove(pvo, -1);
1932 * If we aren't overwriting a mapping, try to allocate.
1934 if (moea_initialized) {
1935 pvo = uma_zalloc(zone, M_NOWAIT);
1937 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1938 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1939 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1940 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1942 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1943 moea_bpvo_pool_index++;
1948 mtx_unlock(&moea_table_mutex);
1953 pvo->pvo_vaddr = va;
1955 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1956 pvo->pvo_vaddr &= ~ADDR_POFF;
1957 if (flags & VM_PROT_EXECUTE)
1958 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1959 if (flags & PVO_WIRED)
1960 pvo->pvo_vaddr |= PVO_WIRED;
1961 if (pvo_head != &moea_pvo_kunmanaged)
1962 pvo->pvo_vaddr |= PVO_MANAGED;
1964 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1966 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1971 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
1974 * Remember if the list was empty and therefore will be the first
1977 if (LIST_FIRST(pvo_head) == NULL)
1979 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1981 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1982 pm->pm_stats.wired_count++;
1983 pm->pm_stats.resident_count++;
1986 * We hope this succeeds but it isn't required.
1988 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1990 PVO_PTEGIDX_SET(pvo, i);
1992 panic("moea_pvo_enter: overflow");
1993 moea_pte_overflow++;
1995 mtx_unlock(&moea_table_mutex);
1997 return (first ? ENOENT : 0);
2001 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2006 * If there is an active pte entry, we need to deactivate it (and
2007 * save the ref & cfg bits).
2009 pt = moea_pvo_to_pte(pvo, pteidx);
2011 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2012 mtx_unlock(&moea_table_mutex);
2013 PVO_PTEGIDX_CLR(pvo);
2015 moea_pte_overflow--;
2019 * Update our statistics.
2021 pvo->pvo_pmap->pm_stats.resident_count--;
2022 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2023 pvo->pvo_pmap->pm_stats.wired_count--;
2026 * Save the REF/CHG bits into their cache if the page is managed.
2028 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2031 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2033 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2034 (PTE_REF | PTE_CHG));
2039 * Remove this PVO from the PV and pmap lists.
2041 LIST_REMOVE(pvo, pvo_vlink);
2042 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2045 * Remove this from the overflow list and return it to the pool
2046 * if we aren't going to reuse it.
2048 LIST_REMOVE(pvo, pvo_olink);
2049 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2050 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2051 moea_upvo_zone, pvo);
2053 moea_pvo_remove_calls++;
2057 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2062 * We can find the actual pte entry without searching by grabbing
2063 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2064 * noticing the HID bit.
2066 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2067 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2068 pteidx ^= moea_pteg_mask * 8;
2073 static struct pvo_entry *
2074 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2076 struct pvo_entry *pvo;
2081 sr = va_to_sr(pm->pm_sr, va);
2082 ptegidx = va_to_pteg(sr, va);
2084 mtx_lock(&moea_table_mutex);
2085 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2086 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2088 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2092 mtx_unlock(&moea_table_mutex);
2098 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2103 * If we haven't been supplied the ptegidx, calculate it.
2109 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2110 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2111 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2114 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2115 mtx_lock(&moea_table_mutex);
2117 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2118 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2119 "valid pte index", pvo);
2122 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2123 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2124 "pvo but no valid pte", pvo);
2127 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2128 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2129 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2130 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2133 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2135 panic("moea_pvo_to_pte: pvo %p pte does not match "
2136 "pte %p in moea_pteg_table", pvo, pt);
2139 mtx_assert(&moea_table_mutex, MA_OWNED);
2143 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2144 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2145 "moea_pteg_table but valid in pvo", pvo, pt);
2148 mtx_unlock(&moea_table_mutex);
2153 * XXX: THIS STUFF SHOULD BE IN pte.c?
2156 moea_pte_spill(vm_offset_t addr)
2158 struct pvo_entry *source_pvo, *victim_pvo;
2159 struct pvo_entry *pvo;
2168 ptegidx = va_to_pteg(sr, addr);
2171 * Have to substitute some entry. Use the primary hash for this.
2172 * Use low bits of timebase as random generator.
2174 pteg = &moea_pteg_table[ptegidx];
2175 mtx_lock(&moea_table_mutex);
2176 __asm __volatile("mftb %0" : "=r"(i));
2182 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2184 * We need to find a pvo entry for this address.
2186 if (source_pvo == NULL &&
2187 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2188 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2190 * Now found an entry to be spilled into the pteg.
2191 * The PTE is now valid, so we know it's active.
2193 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2196 PVO_PTEGIDX_SET(pvo, j);
2197 moea_pte_overflow--;
2198 mtx_unlock(&moea_table_mutex);
2204 if (victim_pvo != NULL)
2209 * We also need the pvo entry of the victim we are replacing
2210 * so save the R & C bits of the PTE.
2212 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2213 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2215 if (source_pvo != NULL)
2220 if (source_pvo == NULL) {
2221 mtx_unlock(&moea_table_mutex);
2225 if (victim_pvo == NULL) {
2226 if ((pt->pte_hi & PTE_HID) == 0)
2227 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2231 * If this is a secondary PTE, we need to search it's primary
2232 * pvo bucket for the matching PVO.
2234 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2237 * We also need the pvo entry of the victim we are
2238 * replacing so save the R & C bits of the PTE.
2240 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2246 if (victim_pvo == NULL)
2247 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2252 * We are invalidating the TLB entry for the EA we are replacing even
2253 * though it's valid. If we don't, we lose any ref/chg bit changes
2254 * contained in the TLB entry.
2256 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2258 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2259 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2261 PVO_PTEGIDX_CLR(victim_pvo);
2262 PVO_PTEGIDX_SET(source_pvo, i);
2263 moea_pte_replacements++;
2265 mtx_unlock(&moea_table_mutex);
2270 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2275 mtx_assert(&moea_table_mutex, MA_OWNED);
2278 * First try primary hash.
2280 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2281 if ((pt->pte_hi & PTE_VALID) == 0) {
2282 pvo_pt->pte_hi &= ~PTE_HID;
2283 moea_pte_set(pt, pvo_pt);
2289 * Now try secondary hash.
2291 ptegidx ^= moea_pteg_mask;
2293 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2294 if ((pt->pte_hi & PTE_VALID) == 0) {
2295 pvo_pt->pte_hi |= PTE_HID;
2296 moea_pte_set(pt, pvo_pt);
2301 panic("moea_pte_insert: overflow");
2306 moea_query_bit(vm_page_t m, int ptebit)
2308 struct pvo_entry *pvo;
2311 rw_assert(&pvh_global_lock, RA_WLOCKED);
2312 if (moea_attr_fetch(m) & ptebit)
2315 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2318 * See if we saved the bit off. If so, cache it and return
2321 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2322 moea_attr_save(m, ptebit);
2328 * No luck, now go through the hard part of looking at the PTEs
2329 * themselves. Sync so that any pending REF/CHG bits are flushed to
2333 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2336 * See if this pvo has a valid PTE. if so, fetch the
2337 * REF/CHG bits from the valid PTE. If the appropriate
2338 * ptebit is set, cache it and return success.
2340 pt = moea_pvo_to_pte(pvo, -1);
2342 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2343 mtx_unlock(&moea_table_mutex);
2344 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2345 moea_attr_save(m, ptebit);
2355 moea_clear_bit(vm_page_t m, int ptebit)
2358 struct pvo_entry *pvo;
2361 rw_assert(&pvh_global_lock, RA_WLOCKED);
2364 * Clear the cached value.
2366 moea_attr_clear(m, ptebit);
2369 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2370 * we can reset the right ones). note that since the pvo entries and
2371 * list heads are accessed via BAT0 and are never placed in the page
2372 * table, we don't have to worry about further accesses setting the
2378 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2379 * valid pte clear the ptebit from the valid pte.
2382 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2383 pt = moea_pvo_to_pte(pvo, -1);
2385 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2386 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2388 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2390 mtx_unlock(&moea_table_mutex);
2392 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2399 * Return true if the physical range is encompassed by the battable[idx]
2402 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2410 * Return immediately if not a valid mapping
2412 if (!(battable[idx].batu & BAT_Vs))
2416 * The BAT entry must be cache-inhibited, guarded, and r/w
2417 * so it can function as an i/o page
2419 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2420 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2424 * The address should be within the BAT range. Assume that the
2425 * start address in the BAT has the correct alignment (thus
2426 * not requiring masking)
2428 start = battable[idx].batl & BAT_PBS;
2429 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2430 end = start | (bat_ble << 15) | 0x7fff;
2432 if ((pa < start) || ((pa + size) > end))
2439 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2444 * This currently does not work for entries that
2445 * overlap 256M BAT segments.
2448 for(i = 0; i < 16; i++)
2449 if (moea_bat_mapped(i, pa, size) == 0)
2456 * Map a set of physical memory pages into the kernel virtual
2457 * address space. Return a pointer to where it is mapped. This
2458 * routine is intended to be used for mapping device memory,
2462 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2465 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2469 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2471 vm_offset_t va, tmpva, ppa, offset;
2474 ppa = trunc_page(pa);
2475 offset = pa & PAGE_MASK;
2476 size = roundup(offset + size, PAGE_SIZE);
2479 * If the physical address lies within a valid BAT table entry,
2480 * return the 1:1 mapping. This currently doesn't work
2481 * for regions that overlap 256M BAT segments.
2483 for (i = 0; i < 16; i++) {
2484 if (moea_bat_mapped(i, pa, size) == 0)
2485 return ((void *) pa);
2488 va = kmem_alloc_nofault(kernel_map, size);
2490 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2492 for (tmpva = va; size > 0;) {
2493 moea_kenter_attr(mmu, tmpva, ppa, ma);
2500 return ((void *)(va + offset));
2504 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2506 vm_offset_t base, offset;
2509 * If this is outside kernel virtual space, then it's a
2510 * battable entry and doesn't require unmapping
2512 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2513 base = trunc_page(va);
2514 offset = va & PAGE_MASK;
2515 size = roundup(offset + size, PAGE_SIZE);
2516 kmem_free(kernel_map, base, size);
2521 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2523 struct pvo_entry *pvo;
2530 lim = round_page(va);
2531 len = MIN(lim - va, sz);
2532 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2534 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2536 moea_syncicache(pa, len);