2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_kstack_pages.h"
114 #include <sys/param.h>
115 #include <sys/kernel.h>
116 #include <sys/queue.h>
117 #include <sys/cpuset.h>
119 #include <sys/lock.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #include <sys/systm.h>
127 #include <sys/vmmeter.h>
129 #include <dev/ofw/openfirm.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
141 #include <machine/cpu.h>
142 #include <machine/platform.h>
143 #include <machine/bat.h>
144 #include <machine/frame.h>
145 #include <machine/md_var.h>
146 #include <machine/psl.h>
147 #include <machine/pte.h>
148 #include <machine/smp.h>
149 #include <machine/sr.h>
150 #include <machine/mmuvar.h>
151 #include <machine/trap_aim.h>
157 #define TODO panic("%s: not implemented", __func__);
159 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
160 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
161 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
171 * Map of physical memory regions.
173 static struct mem_region *regions;
174 static struct mem_region *pregions;
175 static u_int phys_avail_count;
176 static int regions_sz, pregions_sz;
177 static struct ofw_map *translations;
180 * Lock for the pteg and pvo tables.
182 struct mtx moea_table_mutex;
183 struct mtx moea_vsid_mutex;
185 /* tlbie instruction synchronization */
186 static struct mtx tlbie_mtx;
191 static struct pteg *moea_pteg_table;
192 u_int moea_pteg_count;
193 u_int moea_pteg_mask;
198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
199 struct pvo_head moea_pvo_kunmanaged =
200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
202 static struct rwlock_padalign pvh_global_lock;
204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
207 #define BPVO_POOL_SIZE 32768
208 static struct pvo_entry *moea_bpvo_pool;
209 static int moea_bpvo_pool_index = 0;
211 #define VSID_NBPW (sizeof(u_int32_t) * 8)
212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
214 static boolean_t moea_initialized = FALSE;
219 u_int moea_pte_valid = 0;
220 u_int moea_pte_overflow = 0;
221 u_int moea_pte_replacements = 0;
222 u_int moea_pvo_entries = 0;
223 u_int moea_pvo_enter_calls = 0;
224 u_int moea_pvo_remove_calls = 0;
225 u_int moea_pte_spills = 0;
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
229 &moea_pte_overflow, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
231 &moea_pte_replacements, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
235 &moea_pvo_enter_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
237 &moea_pvo_remove_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
239 &moea_pte_spills, 0, "");
242 * Allocate physical memory for use in moea_bootstrap.
244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
249 static int moea_pte_insert(u_int, struct pte *);
254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
255 vm_offset_t, vm_offset_t, u_int, int);
256 static void moea_pvo_remove(struct pvo_entry *, int);
257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
263 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
264 vm_prot_t, boolean_t);
265 static void moea_syncicache(vm_offset_t, vm_size_t);
266 static boolean_t moea_query_bit(vm_page_t, int);
267 static u_int moea_clear_bit(vm_page_t, int);
268 static void moea_kremove(mmu_t, vm_offset_t);
269 int moea_pte_spill(vm_offset_t);
272 * Kernel MMU interface
274 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
275 void moea_clear_modify(mmu_t, vm_page_t);
276 void moea_clear_reference(mmu_t, vm_page_t);
277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
278 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
279 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
280 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
281 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
283 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
284 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
285 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
286 void moea_init(mmu_t);
287 boolean_t moea_is_modified(mmu_t, vm_page_t);
288 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
289 boolean_t moea_is_referenced(mmu_t, vm_page_t);
290 int moea_ts_referenced(mmu_t, vm_page_t);
291 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
292 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
293 int moea_page_wired_mappings(mmu_t, vm_page_t);
294 void moea_pinit(mmu_t, pmap_t);
295 void moea_pinit0(mmu_t, pmap_t);
296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
298 void moea_qremove(mmu_t, vm_offset_t, int);
299 void moea_release(mmu_t, pmap_t);
300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_remove_all(mmu_t, vm_page_t);
302 void moea_remove_write(mmu_t, vm_page_t);
303 void moea_zero_page(mmu_t, vm_page_t);
304 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
305 void moea_zero_page_idle(mmu_t, vm_page_t);
306 void moea_activate(mmu_t, struct thread *);
307 void moea_deactivate(mmu_t, struct thread *);
308 void moea_cpu_bootstrap(mmu_t, int);
309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
310 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
311 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
313 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
315 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
317 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
320 static mmu_method_t moea_methods[] = {
321 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
322 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
323 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
324 MMUMETHOD(mmu_copy_page, moea_copy_page),
325 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
326 MMUMETHOD(mmu_enter, moea_enter),
327 MMUMETHOD(mmu_enter_object, moea_enter_object),
328 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
329 MMUMETHOD(mmu_extract, moea_extract),
330 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
331 MMUMETHOD(mmu_init, moea_init),
332 MMUMETHOD(mmu_is_modified, moea_is_modified),
333 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
334 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
335 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
336 MMUMETHOD(mmu_map, moea_map),
337 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
338 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
339 MMUMETHOD(mmu_pinit, moea_pinit),
340 MMUMETHOD(mmu_pinit0, moea_pinit0),
341 MMUMETHOD(mmu_protect, moea_protect),
342 MMUMETHOD(mmu_qenter, moea_qenter),
343 MMUMETHOD(mmu_qremove, moea_qremove),
344 MMUMETHOD(mmu_release, moea_release),
345 MMUMETHOD(mmu_remove, moea_remove),
346 MMUMETHOD(mmu_remove_all, moea_remove_all),
347 MMUMETHOD(mmu_remove_write, moea_remove_write),
348 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
349 MMUMETHOD(mmu_zero_page, moea_zero_page),
350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
351 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
352 MMUMETHOD(mmu_activate, moea_activate),
353 MMUMETHOD(mmu_deactivate, moea_deactivate),
354 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
356 /* Internal interfaces */
357 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
358 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
359 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
360 MMUMETHOD(mmu_mapdev, moea_mapdev),
361 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
362 MMUMETHOD(mmu_kextract, moea_kextract),
363 MMUMETHOD(mmu_kenter, moea_kenter),
364 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
365 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
370 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
372 static __inline uint32_t
373 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
378 if (ma != VM_MEMATTR_DEFAULT) {
380 case VM_MEMATTR_UNCACHEABLE:
381 return (PTE_I | PTE_G);
382 case VM_MEMATTR_WRITE_COMBINING:
383 case VM_MEMATTR_WRITE_BACK:
384 case VM_MEMATTR_PREFETCHABLE:
386 case VM_MEMATTR_WRITE_THROUGH:
387 return (PTE_W | PTE_M);
392 * Assume the page is cache inhibited and access is guarded unless
393 * it's in our available memory array.
395 pte_lo = PTE_I | PTE_G;
396 for (i = 0; i < pregions_sz; i++) {
397 if ((pa >= pregions[i].mr_start) &&
398 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
408 tlbie(vm_offset_t va)
411 mtx_lock_spin(&tlbie_mtx);
412 __asm __volatile("ptesync");
413 __asm __volatile("tlbie %0" :: "r"(va));
414 __asm __volatile("eieio; tlbsync; ptesync");
415 mtx_unlock_spin(&tlbie_mtx);
423 for (va = 0; va < 0x00040000; va += 0x00001000) {
424 __asm __volatile("tlbie %0" :: "r"(va));
427 __asm __volatile("tlbsync");
432 va_to_sr(u_int *sr, vm_offset_t va)
434 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
437 static __inline u_int
438 va_to_pteg(u_int sr, vm_offset_t addr)
442 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
444 return (hash & moea_pteg_mask);
447 static __inline struct pvo_head *
448 vm_page_to_pvoh(vm_page_t m)
451 return (&m->md.mdpg_pvoh);
455 moea_attr_clear(vm_page_t m, int ptebit)
458 rw_assert(&pvh_global_lock, RA_WLOCKED);
459 m->md.mdpg_attrs &= ~ptebit;
463 moea_attr_fetch(vm_page_t m)
466 return (m->md.mdpg_attrs);
470 moea_attr_save(vm_page_t m, int ptebit)
473 rw_assert(&pvh_global_lock, RA_WLOCKED);
474 m->md.mdpg_attrs |= ptebit;
478 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
480 if (pt->pte_hi == pvo_pt->pte_hi)
487 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
489 return (pt->pte_hi & ~PTE_VALID) ==
490 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
491 ((va >> ADDR_API_SHFT) & PTE_API) | which);
495 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
498 mtx_assert(&moea_table_mutex, MA_OWNED);
501 * Construct a PTE. Default to IMB initially. Valid bit only gets
502 * set when the real pte is set in memory.
504 * Note: Don't set the valid bit for correct operation of tlb update.
506 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
507 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
512 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
515 mtx_assert(&moea_table_mutex, MA_OWNED);
516 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
520 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
523 mtx_assert(&moea_table_mutex, MA_OWNED);
526 * As shown in Section 7.6.3.2.3
528 pt->pte_lo &= ~ptebit;
533 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
536 mtx_assert(&moea_table_mutex, MA_OWNED);
537 pvo_pt->pte_hi |= PTE_VALID;
540 * Update the PTE as defined in section 7.6.3.1.
541 * Note that the REF/CHG bits are from pvo_pt and thus should havce
542 * been saved so this routine can restore them (if desired).
544 pt->pte_lo = pvo_pt->pte_lo;
546 pt->pte_hi = pvo_pt->pte_hi;
552 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
555 mtx_assert(&moea_table_mutex, MA_OWNED);
556 pvo_pt->pte_hi &= ~PTE_VALID;
559 * Force the reg & chg bits back into the PTEs.
564 * Invalidate the pte.
566 pt->pte_hi &= ~PTE_VALID;
571 * Save the reg & chg bits.
573 moea_pte_synch(pt, pvo_pt);
578 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
584 moea_pte_unset(pt, pvo_pt, va);
585 moea_pte_set(pt, pvo_pt);
589 * Quick sort callout for comparing memory regions.
591 static int om_cmp(const void *a, const void *b);
594 om_cmp(const void *a, const void *b)
596 const struct ofw_map *mapa;
597 const struct ofw_map *mapb;
601 if (mapa->om_pa < mapb->om_pa)
603 else if (mapa->om_pa > mapb->om_pa)
610 moea_cpu_bootstrap(mmu_t mmup, int ap)
617 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
618 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
620 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
621 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
627 * Special case for the Wii: don't install the PCI BAT.
629 if (strcmp(installed_platform(), "wii") != 0) {
631 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
632 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
638 __asm __volatile("mtibatu 1,%0" :: "r"(0));
639 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
640 __asm __volatile("mtibatu 2,%0" :: "r"(0));
641 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
642 __asm __volatile("mtibatu 3,%0" :: "r"(0));
645 for (i = 0; i < 16; i++)
646 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
649 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
650 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
657 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
660 phandle_t chosen, mmu;
663 vm_size_t size, physsz, hwphyssz;
664 vm_offset_t pa, va, off;
669 * Set up BAT0 to map the lowest 256 MB area
671 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
672 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
675 * Map PCI memory space.
677 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
678 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
680 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
681 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
683 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
684 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
686 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
687 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
692 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
693 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
696 * Use an IBAT and a DBAT to map the bottom segment of memory
697 * where we are. Turn off instruction relocation temporarily
698 * to prevent faults while reprogramming the IBAT.
701 mtmsr(msr & ~PSL_IR);
702 __asm (".balign 32; \n"
703 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
704 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
705 :: "r"(battable[0].batu), "r"(battable[0].batl));
709 if (strcmp(installed_platform(), "wii") != 0) {
712 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
713 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
719 /* set global direct map flag */
722 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
723 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
725 for (i = 0; i < pregions_sz; i++) {
729 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
730 pregions[i].mr_start,
731 pregions[i].mr_start + pregions[i].mr_size,
732 pregions[i].mr_size);
734 * Install entries into the BAT table to allow all
735 * of physmem to be convered by on-demand BAT entries.
736 * The loop will sometimes set the same battable element
737 * twice, but that's fine since they won't be used for
740 pa = pregions[i].mr_start & 0xf0000000;
741 end = pregions[i].mr_start + pregions[i].mr_size;
743 u_int n = pa >> ADDR_SR_SHFT;
745 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
746 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
747 pa += SEGMENT_LENGTH;
751 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
752 panic("moea_bootstrap: phys_avail too small");
754 phys_avail_count = 0;
757 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
758 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
759 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
760 regions[i].mr_start + regions[i].mr_size,
763 (physsz + regions[i].mr_size) >= hwphyssz) {
764 if (physsz < hwphyssz) {
765 phys_avail[j] = regions[i].mr_start;
766 phys_avail[j + 1] = regions[i].mr_start +
773 phys_avail[j] = regions[i].mr_start;
774 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
776 physsz += regions[i].mr_size;
779 /* Check for overlap with the kernel and exception vectors */
780 for (j = 0; j < 2*phys_avail_count; j+=2) {
781 if (phys_avail[j] < EXC_LAST)
782 phys_avail[j] += EXC_LAST;
784 if (kernelstart >= phys_avail[j] &&
785 kernelstart < phys_avail[j+1]) {
786 if (kernelend < phys_avail[j+1]) {
787 phys_avail[2*phys_avail_count] =
788 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
789 phys_avail[2*phys_avail_count + 1] =
794 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
797 if (kernelend >= phys_avail[j] &&
798 kernelend < phys_avail[j+1]) {
799 if (kernelstart > phys_avail[j]) {
800 phys_avail[2*phys_avail_count] = phys_avail[j];
801 phys_avail[2*phys_avail_count + 1] =
802 kernelstart & ~PAGE_MASK;
806 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
810 physmem = btoc(physsz);
813 * Allocate PTEG table.
816 moea_pteg_count = PTEGCOUNT;
818 moea_pteg_count = 0x1000;
820 while (moea_pteg_count < physmem)
821 moea_pteg_count <<= 1;
823 moea_pteg_count >>= 1;
824 #endif /* PTEGCOUNT */
826 size = moea_pteg_count * sizeof(struct pteg);
827 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
829 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
830 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
831 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
832 moea_pteg_mask = moea_pteg_count - 1;
835 * Allocate pv/overflow lists.
837 size = sizeof(struct pvo_head) * moea_pteg_count;
838 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
840 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
841 for (i = 0; i < moea_pteg_count; i++)
842 LIST_INIT(&moea_pvo_table[i]);
845 * Initialize the lock that synchronizes access to the pteg and pvo
848 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
850 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
852 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
855 * Initialise the unmanaged pvo pool.
857 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
858 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
859 moea_bpvo_pool_index = 0;
862 * Make sure kernel vsid is allocated as well as VSID 0.
864 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
865 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
866 moea_vsid_bitmap[0] |= 1;
869 * Initialize the kernel pmap (which is statically allocated).
871 PMAP_LOCK_INIT(kernel_pmap);
872 for (i = 0; i < 16; i++)
873 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
874 CPU_FILL(&kernel_pmap->pm_active);
875 RB_INIT(&kernel_pmap->pmap_pvo);
878 * Initialize the global pv list lock.
880 rw_init(&pvh_global_lock, "pmap pv global");
883 * Set up the Open Firmware mappings
885 chosen = OF_finddevice("/chosen");
886 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
887 (mmu = OF_instance_to_package(mmui)) != -1 &&
888 (sz = OF_getproplen(mmu, "translations")) != -1) {
890 for (i = 0; phys_avail[i] != 0; i += 2) {
891 if (phys_avail[i + 1] >= sz) {
892 translations = (struct ofw_map *)phys_avail[i];
896 if (translations == NULL)
897 panic("moea_bootstrap: no space to copy translations");
898 bzero(translations, sz);
899 if (OF_getprop(mmu, "translations", translations, sz) == -1)
900 panic("moea_bootstrap: can't get ofw translations");
901 CTR0(KTR_PMAP, "moea_bootstrap: translations");
902 sz /= sizeof(*translations);
903 qsort(translations, sz, sizeof (*translations), om_cmp);
904 for (i = 0; i < sz; i++) {
905 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
906 translations[i].om_pa, translations[i].om_va,
907 translations[i].om_len);
910 * If the mapping is 1:1, let the RAM and device
911 * on-demand BAT tables take care of the translation.
913 if (translations[i].om_va == translations[i].om_pa)
916 /* Enter the pages */
917 for (off = 0; off < translations[i].om_len;
919 moea_kenter(mmup, translations[i].om_va + off,
920 translations[i].om_pa + off);
925 * Calculate the last available physical address.
927 for (i = 0; phys_avail[i + 2] != 0; i += 2)
929 Maxmem = powerpc_btop(phys_avail[i + 1]);
931 moea_cpu_bootstrap(mmup,0);
936 * Set the start and end of kva.
938 virtual_avail = VM_MIN_KERNEL_ADDRESS;
939 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
942 * Allocate a kernel stack with a guard page for thread0 and map it
943 * into the kernel page map.
945 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
946 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
947 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
948 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
949 thread0.td_kstack = va;
950 thread0.td_kstack_pages = KSTACK_PAGES;
951 for (i = 0; i < KSTACK_PAGES; i++) {
952 moea_kenter(mmup, va, pa);
958 * Allocate virtual address space for the message buffer.
960 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
961 msgbufp = (struct msgbuf *)virtual_avail;
963 virtual_avail += round_page(msgbufsize);
964 while (va < virtual_avail) {
965 moea_kenter(mmup, va, pa);
971 * Allocate virtual address space for the dynamic percpu area.
973 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
974 dpcpu = (void *)virtual_avail;
976 virtual_avail += DPCPU_SIZE;
977 while (va < virtual_avail) {
978 moea_kenter(mmup, va, pa);
982 dpcpu_init(dpcpu, 0);
986 * Activate a user pmap. The pmap must be activated before it's address
987 * space can be accessed in any way.
990 moea_activate(mmu_t mmu, struct thread *td)
995 * Load all the data we need up front to encourage the compiler to
996 * not issue any loads while we have interrupts disabled below.
998 pm = &td->td_proc->p_vmspace->vm_pmap;
1001 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1002 PCPU_SET(curpmap, pmr);
1006 moea_deactivate(mmu_t mmu, struct thread *td)
1010 pm = &td->td_proc->p_vmspace->vm_pmap;
1011 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1012 PCPU_SET(curpmap, NULL);
1016 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1018 struct pvo_entry *pvo;
1021 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1025 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1026 pm->pm_stats.wired_count++;
1027 pvo->pvo_vaddr |= PVO_WIRED;
1029 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1030 pm->pm_stats.wired_count--;
1031 pvo->pvo_vaddr &= ~PVO_WIRED;
1038 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1043 dst = VM_PAGE_TO_PHYS(mdst);
1044 src = VM_PAGE_TO_PHYS(msrc);
1046 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1050 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1051 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1054 vm_offset_t a_pg_offset, b_pg_offset;
1057 while (xfersize > 0) {
1058 a_pg_offset = a_offset & PAGE_MASK;
1059 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1060 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1062 b_pg_offset = b_offset & PAGE_MASK;
1063 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1064 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1066 bcopy(a_cp, b_cp, cnt);
1074 * Zero a page of physical memory by temporarily mapping it into the tlb.
1077 moea_zero_page(mmu_t mmu, vm_page_t m)
1079 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1080 void *va = (void *)pa;
1082 bzero(va, PAGE_SIZE);
1086 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1088 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1089 void *va = (void *)(pa + off);
1095 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1097 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1098 void *va = (void *)pa;
1100 bzero(va, PAGE_SIZE);
1104 * Map the given physical page at the specified virtual address in the
1105 * target pmap with the protection requested. If specified the page
1106 * will be wired down.
1109 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1113 rw_wlock(&pvh_global_lock);
1115 moea_enter_locked(pmap, va, m, prot, wired);
1116 rw_wunlock(&pvh_global_lock);
1121 * Map the given physical page at the specified virtual address in the
1122 * target pmap with the protection requested. If specified the page
1123 * will be wired down.
1125 * The page queues and pmap must be locked.
1128 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1131 struct pvo_head *pvo_head;
1134 u_int pte_lo, pvo_flags;
1137 if (!moea_initialized) {
1138 pvo_head = &moea_pvo_kunmanaged;
1139 zone = moea_upvo_zone;
1143 pvo_head = vm_page_to_pvoh(m);
1145 zone = moea_mpvo_zone;
1146 pvo_flags = PVO_MANAGED;
1148 if (pmap_bootstrapped)
1149 rw_assert(&pvh_global_lock, RA_WLOCKED);
1150 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1151 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0)
1152 VM_OBJECT_ASSERT_WLOCKED(m->object);
1154 /* XXX change the pvo head for fake pages */
1155 if ((m->oflags & VPO_UNMANAGED) != 0) {
1156 pvo_flags &= ~PVO_MANAGED;
1157 pvo_head = &moea_pvo_kunmanaged;
1158 zone = moea_upvo_zone;
1161 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1163 if (prot & VM_PROT_WRITE) {
1165 if (pmap_bootstrapped &&
1166 (m->oflags & VPO_UNMANAGED) == 0)
1167 vm_page_aflag_set(m, PGA_WRITEABLE);
1171 if (prot & VM_PROT_EXECUTE)
1172 pvo_flags |= PVO_EXECUTABLE;
1175 pvo_flags |= PVO_WIRED;
1177 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1181 * Flush the real page from the instruction cache. This has be done
1182 * for all user mappings to prevent information leakage via the
1183 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1184 * mapping for a page.
1186 if (pmap != kernel_pmap && error == ENOENT &&
1187 (pte_lo & (PTE_I | PTE_G)) == 0)
1188 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1192 * Maps a sequence of resident pages belonging to the same object.
1193 * The sequence begins with the given page m_start. This page is
1194 * mapped at the given virtual address start. Each subsequent page is
1195 * mapped at a virtual address that is offset from start by the same
1196 * amount as the page is offset from m_start within the object. The
1197 * last page in the sequence is the page with the largest offset from
1198 * m_start that can be mapped at a virtual address less than the given
1199 * virtual address end. Not every virtual page between start and end
1200 * is mapped; only those for which a resident page exists with the
1201 * corresponding offset from m_start are mapped.
1204 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1205 vm_page_t m_start, vm_prot_t prot)
1208 vm_pindex_t diff, psize;
1210 psize = atop(end - start);
1212 rw_wlock(&pvh_global_lock);
1214 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1215 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1216 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1217 m = TAILQ_NEXT(m, listq);
1219 rw_wunlock(&pvh_global_lock);
1224 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1228 rw_wlock(&pvh_global_lock);
1230 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1232 rw_wunlock(&pvh_global_lock);
1237 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1239 struct pvo_entry *pvo;
1243 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1247 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1253 * Atomically extract and hold the physical page with the given
1254 * pmap and virtual address pair if that mapping permits the given
1258 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1260 struct pvo_entry *pvo;
1268 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1269 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1270 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1271 (prot & VM_PROT_WRITE) == 0)) {
1272 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1274 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1283 moea_init(mmu_t mmu)
1286 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1287 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1288 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1289 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1290 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1291 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1292 moea_initialized = TRUE;
1296 moea_is_referenced(mmu_t mmu, vm_page_t m)
1300 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1301 ("moea_is_referenced: page %p is not managed", m));
1302 rw_wlock(&pvh_global_lock);
1303 rv = moea_query_bit(m, PTE_REF);
1304 rw_wunlock(&pvh_global_lock);
1309 moea_is_modified(mmu_t mmu, vm_page_t m)
1313 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1314 ("moea_is_modified: page %p is not managed", m));
1317 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1318 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1319 * is clear, no PTEs can have PTE_CHG set.
1321 VM_OBJECT_ASSERT_WLOCKED(m->object);
1322 if ((m->oflags & VPO_BUSY) == 0 &&
1323 (m->aflags & PGA_WRITEABLE) == 0)
1325 rw_wlock(&pvh_global_lock);
1326 rv = moea_query_bit(m, PTE_CHG);
1327 rw_wunlock(&pvh_global_lock);
1332 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1334 struct pvo_entry *pvo;
1338 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1339 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1345 moea_clear_reference(mmu_t mmu, vm_page_t m)
1348 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1349 ("moea_clear_reference: page %p is not managed", m));
1350 rw_wlock(&pvh_global_lock);
1351 moea_clear_bit(m, PTE_REF);
1352 rw_wunlock(&pvh_global_lock);
1356 moea_clear_modify(mmu_t mmu, vm_page_t m)
1359 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1360 ("moea_clear_modify: page %p is not managed", m));
1361 VM_OBJECT_ASSERT_WLOCKED(m->object);
1362 KASSERT((m->oflags & VPO_BUSY) == 0,
1363 ("moea_clear_modify: page %p is busy", m));
1366 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1367 * set. If the object containing the page is locked and the page is
1368 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1370 if ((m->aflags & PGA_WRITEABLE) == 0)
1372 rw_wlock(&pvh_global_lock);
1373 moea_clear_bit(m, PTE_CHG);
1374 rw_wunlock(&pvh_global_lock);
1378 * Clear the write and modified bits in each of the given page's mappings.
1381 moea_remove_write(mmu_t mmu, vm_page_t m)
1383 struct pvo_entry *pvo;
1388 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1389 ("moea_remove_write: page %p is not managed", m));
1392 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1393 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1394 * is clear, no page table entries need updating.
1396 VM_OBJECT_ASSERT_WLOCKED(m->object);
1397 if ((m->oflags & VPO_BUSY) == 0 &&
1398 (m->aflags & PGA_WRITEABLE) == 0)
1400 rw_wlock(&pvh_global_lock);
1401 lo = moea_attr_fetch(m);
1403 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1404 pmap = pvo->pvo_pmap;
1406 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1407 pt = moea_pvo_to_pte(pvo, -1);
1408 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1409 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1411 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1412 lo |= pvo->pvo_pte.pte.pte_lo;
1413 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1414 moea_pte_change(pt, &pvo->pvo_pte.pte,
1416 mtx_unlock(&moea_table_mutex);
1421 if ((lo & PTE_CHG) != 0) {
1422 moea_attr_clear(m, PTE_CHG);
1425 vm_page_aflag_clear(m, PGA_WRITEABLE);
1426 rw_wunlock(&pvh_global_lock);
1430 * moea_ts_referenced:
1432 * Return a count of reference bits for a page, clearing those bits.
1433 * It is not necessary for every reference bit to be cleared, but it
1434 * is necessary that 0 only be returned when there are truly no
1435 * reference bits set.
1437 * XXX: The exact number of bits to check and clear is a matter that
1438 * should be tested and standardized at some point in the future for
1439 * optimal aging of shared pages.
1442 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1446 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1447 ("moea_ts_referenced: page %p is not managed", m));
1448 rw_wlock(&pvh_global_lock);
1449 count = moea_clear_bit(m, PTE_REF);
1450 rw_wunlock(&pvh_global_lock);
1455 * Modify the WIMG settings of all mappings for a page.
1458 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1460 struct pvo_entry *pvo;
1461 struct pvo_head *pvo_head;
1466 if ((m->oflags & VPO_UNMANAGED) != 0) {
1467 m->md.mdpg_cache_attrs = ma;
1471 rw_wlock(&pvh_global_lock);
1472 pvo_head = vm_page_to_pvoh(m);
1473 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1475 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1476 pmap = pvo->pvo_pmap;
1478 pt = moea_pvo_to_pte(pvo, -1);
1479 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1480 pvo->pvo_pte.pte.pte_lo |= lo;
1482 moea_pte_change(pt, &pvo->pvo_pte.pte,
1484 if (pvo->pvo_pmap == kernel_pmap)
1487 mtx_unlock(&moea_table_mutex);
1490 m->md.mdpg_cache_attrs = ma;
1491 rw_wunlock(&pvh_global_lock);
1495 * Map a wired page into kernel virtual address space.
1498 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1501 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1505 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1511 if (va < VM_MIN_KERNEL_ADDRESS)
1512 panic("moea_kenter: attempt to enter non-kernel address %#x",
1516 pte_lo = moea_calc_wimg(pa, ma);
1518 PMAP_LOCK(kernel_pmap);
1519 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1520 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1522 if (error != 0 && error != ENOENT)
1523 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1526 PMAP_UNLOCK(kernel_pmap);
1530 * Extract the physical page address associated with the given kernel virtual
1534 moea_kextract(mmu_t mmu, vm_offset_t va)
1536 struct pvo_entry *pvo;
1540 * Allow direct mappings on 32-bit OEA
1542 if (va < VM_MIN_KERNEL_ADDRESS) {
1546 PMAP_LOCK(kernel_pmap);
1547 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1548 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1549 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1550 PMAP_UNLOCK(kernel_pmap);
1555 * Remove a wired page from kernel virtual address space.
1558 moea_kremove(mmu_t mmu, vm_offset_t va)
1561 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1565 * Map a range of physical addresses into kernel virtual address space.
1567 * The value passed in *virt is a suggested virtual address for the mapping.
1568 * Architectures which can support a direct-mapped physical to virtual region
1569 * can return the appropriate address within that region, leaving '*virt'
1570 * unchanged. We cannot and therefore do not; *virt is updated with the
1571 * first usable address after the mapped region.
1574 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1575 vm_paddr_t pa_end, int prot)
1577 vm_offset_t sva, va;
1581 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1582 moea_kenter(mmu, va, pa_start);
1588 * Returns true if the pmap's pv is one of the first
1589 * 16 pvs linked to from this page. This count may
1590 * be changed upwards or downwards in the future; it
1591 * is only necessary that true be returned for a small
1592 * subset of pmaps for proper page aging.
1595 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1598 struct pvo_entry *pvo;
1601 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1602 ("moea_page_exists_quick: page %p is not managed", m));
1605 rw_wlock(&pvh_global_lock);
1606 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1607 if (pvo->pvo_pmap == pmap) {
1614 rw_wunlock(&pvh_global_lock);
1619 * Return the number of managed mappings to the given physical page
1623 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1625 struct pvo_entry *pvo;
1629 if ((m->oflags & VPO_UNMANAGED) != 0)
1631 rw_wlock(&pvh_global_lock);
1632 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1633 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1635 rw_wunlock(&pvh_global_lock);
1639 static u_int moea_vsidcontext;
1642 moea_pinit(mmu_t mmu, pmap_t pmap)
1647 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1648 PMAP_LOCK_INIT(pmap);
1649 RB_INIT(&pmap->pmap_pvo);
1652 __asm __volatile("mftb %0" : "=r"(entropy));
1654 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1656 pmap->pmap_phys = pmap;
1660 mtx_lock(&moea_vsid_mutex);
1662 * Allocate some segment registers for this pmap.
1664 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1668 * Create a new value by mutiplying by a prime and adding in
1669 * entropy from the timebase register. This is to make the
1670 * VSID more random so that the PT hash function collides
1671 * less often. (Note that the prime casues gcc to do shifts
1672 * instead of a multiply.)
1674 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1675 hash = moea_vsidcontext & (NPMAPS - 1);
1676 if (hash == 0) /* 0 is special, avoid it */
1679 mask = 1 << (hash & (VSID_NBPW - 1));
1680 hash = (moea_vsidcontext & 0xfffff);
1681 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1682 /* anything free in this bucket? */
1683 if (moea_vsid_bitmap[n] == 0xffffffff) {
1684 entropy = (moea_vsidcontext >> 20);
1687 i = ffs(~moea_vsid_bitmap[n]) - 1;
1689 hash &= 0xfffff & ~(VSID_NBPW - 1);
1692 KASSERT(!(moea_vsid_bitmap[n] & mask),
1693 ("Allocating in-use VSID group %#x\n", hash));
1694 moea_vsid_bitmap[n] |= mask;
1695 for (i = 0; i < 16; i++)
1696 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1697 mtx_unlock(&moea_vsid_mutex);
1701 mtx_unlock(&moea_vsid_mutex);
1702 panic("moea_pinit: out of segments");
1706 * Initialize the pmap associated with process 0.
1709 moea_pinit0(mmu_t mmu, pmap_t pm)
1712 moea_pinit(mmu, pm);
1713 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1717 * Set the physical protection on the specified range of this map as requested.
1720 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1723 struct pvo_entry *pvo, *tpvo, key;
1726 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1727 ("moea_protect: non current pmap"));
1729 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1730 moea_remove(mmu, pm, sva, eva);
1734 rw_wlock(&pvh_global_lock);
1736 key.pvo_vaddr = sva;
1737 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1738 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1739 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1740 if ((prot & VM_PROT_EXECUTE) == 0)
1741 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1744 * Grab the PTE pointer before we diddle with the cached PTE
1747 pt = moea_pvo_to_pte(pvo, -1);
1749 * Change the protection of the page.
1751 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1752 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1755 * If the PVO is in the page table, update that pte as well.
1758 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1759 mtx_unlock(&moea_table_mutex);
1762 rw_wunlock(&pvh_global_lock);
1767 * Map a list of wired pages into kernel virtual address space. This is
1768 * intended for temporary mappings which do not need page modification or
1769 * references recorded. Existing mappings in the region are overwritten.
1772 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1777 while (count-- > 0) {
1778 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1785 * Remove page mappings from kernel virtual address space. Intended for
1786 * temporary mappings entered by moea_qenter.
1789 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1794 while (count-- > 0) {
1795 moea_kremove(mmu, va);
1801 moea_release(mmu_t mmu, pmap_t pmap)
1806 * Free segment register's VSID
1808 if (pmap->pm_sr[0] == 0)
1809 panic("moea_release");
1811 mtx_lock(&moea_vsid_mutex);
1812 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1813 mask = 1 << (idx % VSID_NBPW);
1815 moea_vsid_bitmap[idx] &= ~mask;
1816 mtx_unlock(&moea_vsid_mutex);
1817 PMAP_LOCK_DESTROY(pmap);
1821 * Remove the given range of addresses from the specified map.
1824 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1826 struct pvo_entry *pvo, *tpvo, key;
1828 rw_wlock(&pvh_global_lock);
1830 key.pvo_vaddr = sva;
1831 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1832 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1833 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1834 moea_pvo_remove(pvo, -1);
1837 rw_wunlock(&pvh_global_lock);
1841 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1842 * will reflect changes in pte's back to the vm_page.
1845 moea_remove_all(mmu_t mmu, vm_page_t m)
1847 struct pvo_head *pvo_head;
1848 struct pvo_entry *pvo, *next_pvo;
1851 rw_wlock(&pvh_global_lock);
1852 pvo_head = vm_page_to_pvoh(m);
1853 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1854 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1856 pmap = pvo->pvo_pmap;
1858 moea_pvo_remove(pvo, -1);
1861 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1862 moea_attr_clear(m, PTE_CHG);
1865 vm_page_aflag_clear(m, PGA_WRITEABLE);
1866 rw_wunlock(&pvh_global_lock);
1870 * Allocate a physical page of memory directly from the phys_avail map.
1871 * Can only be called from moea_bootstrap before avail start and end are
1875 moea_bootstrap_alloc(vm_size_t size, u_int align)
1880 size = round_page(size);
1881 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1883 s = (phys_avail[i] + align - 1) & ~(align - 1);
1888 if (s < phys_avail[i] || e > phys_avail[i + 1])
1891 if (s == phys_avail[i]) {
1892 phys_avail[i] += size;
1893 } else if (e == phys_avail[i + 1]) {
1894 phys_avail[i + 1] -= size;
1896 for (j = phys_avail_count * 2; j > i; j -= 2) {
1897 phys_avail[j] = phys_avail[j - 2];
1898 phys_avail[j + 1] = phys_avail[j - 1];
1901 phys_avail[i + 3] = phys_avail[i + 1];
1902 phys_avail[i + 1] = s;
1903 phys_avail[i + 2] = e;
1909 panic("moea_bootstrap_alloc: could not allocate memory");
1913 moea_syncicache(vm_offset_t pa, vm_size_t len)
1915 __syncicache((void *)pa, len);
1919 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1920 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1922 struct pvo_entry *pvo;
1929 moea_pvo_enter_calls++;
1934 * Compute the PTE Group index.
1937 sr = va_to_sr(pm->pm_sr, va);
1938 ptegidx = va_to_pteg(sr, va);
1941 * Remove any existing mapping for this page. Reuse the pvo entry if
1942 * there is a mapping.
1944 mtx_lock(&moea_table_mutex);
1945 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1946 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1947 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1948 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1949 (pte_lo & PTE_PP)) {
1950 mtx_unlock(&moea_table_mutex);
1953 moea_pvo_remove(pvo, -1);
1959 * If we aren't overwriting a mapping, try to allocate.
1961 if (moea_initialized) {
1962 pvo = uma_zalloc(zone, M_NOWAIT);
1964 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1965 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1966 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1967 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1969 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1970 moea_bpvo_pool_index++;
1975 mtx_unlock(&moea_table_mutex);
1980 pvo->pvo_vaddr = va;
1982 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1983 pvo->pvo_vaddr &= ~ADDR_POFF;
1984 if (flags & VM_PROT_EXECUTE)
1985 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1986 if (flags & PVO_WIRED)
1987 pvo->pvo_vaddr |= PVO_WIRED;
1988 if (pvo_head != &moea_pvo_kunmanaged)
1989 pvo->pvo_vaddr |= PVO_MANAGED;
1991 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1993 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1998 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2001 * Remember if the list was empty and therefore will be the first
2004 if (LIST_FIRST(pvo_head) == NULL)
2006 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2008 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2009 pm->pm_stats.wired_count++;
2010 pm->pm_stats.resident_count++;
2013 * We hope this succeeds but it isn't required.
2015 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2017 PVO_PTEGIDX_SET(pvo, i);
2019 panic("moea_pvo_enter: overflow");
2020 moea_pte_overflow++;
2022 mtx_unlock(&moea_table_mutex);
2024 return (first ? ENOENT : 0);
2028 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2033 * If there is an active pte entry, we need to deactivate it (and
2034 * save the ref & cfg bits).
2036 pt = moea_pvo_to_pte(pvo, pteidx);
2038 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2039 mtx_unlock(&moea_table_mutex);
2040 PVO_PTEGIDX_CLR(pvo);
2042 moea_pte_overflow--;
2046 * Update our statistics.
2048 pvo->pvo_pmap->pm_stats.resident_count--;
2049 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2050 pvo->pvo_pmap->pm_stats.wired_count--;
2053 * Save the REF/CHG bits into their cache if the page is managed.
2055 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2058 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2060 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2061 (PTE_REF | PTE_CHG));
2066 * Remove this PVO from the PV and pmap lists.
2068 LIST_REMOVE(pvo, pvo_vlink);
2069 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2072 * Remove this from the overflow list and return it to the pool
2073 * if we aren't going to reuse it.
2075 LIST_REMOVE(pvo, pvo_olink);
2076 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2077 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2078 moea_upvo_zone, pvo);
2080 moea_pvo_remove_calls++;
2084 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2089 * We can find the actual pte entry without searching by grabbing
2090 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2091 * noticing the HID bit.
2093 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2094 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2095 pteidx ^= moea_pteg_mask * 8;
2100 static struct pvo_entry *
2101 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2103 struct pvo_entry *pvo;
2108 sr = va_to_sr(pm->pm_sr, va);
2109 ptegidx = va_to_pteg(sr, va);
2111 mtx_lock(&moea_table_mutex);
2112 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2113 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2115 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2119 mtx_unlock(&moea_table_mutex);
2125 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2130 * If we haven't been supplied the ptegidx, calculate it.
2136 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2137 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2138 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2141 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2142 mtx_lock(&moea_table_mutex);
2144 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2145 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2146 "valid pte index", pvo);
2149 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2150 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2151 "pvo but no valid pte", pvo);
2154 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2155 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2156 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2157 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2160 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2162 panic("moea_pvo_to_pte: pvo %p pte does not match "
2163 "pte %p in moea_pteg_table", pvo, pt);
2166 mtx_assert(&moea_table_mutex, MA_OWNED);
2170 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2171 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2172 "moea_pteg_table but valid in pvo", pvo, pt);
2175 mtx_unlock(&moea_table_mutex);
2180 * XXX: THIS STUFF SHOULD BE IN pte.c?
2183 moea_pte_spill(vm_offset_t addr)
2185 struct pvo_entry *source_pvo, *victim_pvo;
2186 struct pvo_entry *pvo;
2195 ptegidx = va_to_pteg(sr, addr);
2198 * Have to substitute some entry. Use the primary hash for this.
2199 * Use low bits of timebase as random generator.
2201 pteg = &moea_pteg_table[ptegidx];
2202 mtx_lock(&moea_table_mutex);
2203 __asm __volatile("mftb %0" : "=r"(i));
2209 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2211 * We need to find a pvo entry for this address.
2213 if (source_pvo == NULL &&
2214 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2215 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2217 * Now found an entry to be spilled into the pteg.
2218 * The PTE is now valid, so we know it's active.
2220 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2223 PVO_PTEGIDX_SET(pvo, j);
2224 moea_pte_overflow--;
2225 mtx_unlock(&moea_table_mutex);
2231 if (victim_pvo != NULL)
2236 * We also need the pvo entry of the victim we are replacing
2237 * so save the R & C bits of the PTE.
2239 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2240 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2242 if (source_pvo != NULL)
2247 if (source_pvo == NULL) {
2248 mtx_unlock(&moea_table_mutex);
2252 if (victim_pvo == NULL) {
2253 if ((pt->pte_hi & PTE_HID) == 0)
2254 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2258 * If this is a secondary PTE, we need to search it's primary
2259 * pvo bucket for the matching PVO.
2261 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2264 * We also need the pvo entry of the victim we are
2265 * replacing so save the R & C bits of the PTE.
2267 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2273 if (victim_pvo == NULL)
2274 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2279 * We are invalidating the TLB entry for the EA we are replacing even
2280 * though it's valid. If we don't, we lose any ref/chg bit changes
2281 * contained in the TLB entry.
2283 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2285 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2286 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2288 PVO_PTEGIDX_CLR(victim_pvo);
2289 PVO_PTEGIDX_SET(source_pvo, i);
2290 moea_pte_replacements++;
2292 mtx_unlock(&moea_table_mutex);
2297 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2302 mtx_assert(&moea_table_mutex, MA_OWNED);
2305 * First try primary hash.
2307 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2308 if ((pt->pte_hi & PTE_VALID) == 0) {
2309 pvo_pt->pte_hi &= ~PTE_HID;
2310 moea_pte_set(pt, pvo_pt);
2316 * Now try secondary hash.
2318 ptegidx ^= moea_pteg_mask;
2320 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2321 if ((pt->pte_hi & PTE_VALID) == 0) {
2322 pvo_pt->pte_hi |= PTE_HID;
2323 moea_pte_set(pt, pvo_pt);
2328 panic("moea_pte_insert: overflow");
2333 moea_query_bit(vm_page_t m, int ptebit)
2335 struct pvo_entry *pvo;
2338 rw_assert(&pvh_global_lock, RA_WLOCKED);
2339 if (moea_attr_fetch(m) & ptebit)
2342 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2345 * See if we saved the bit off. If so, cache it and return
2348 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2349 moea_attr_save(m, ptebit);
2355 * No luck, now go through the hard part of looking at the PTEs
2356 * themselves. Sync so that any pending REF/CHG bits are flushed to
2360 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2363 * See if this pvo has a valid PTE. if so, fetch the
2364 * REF/CHG bits from the valid PTE. If the appropriate
2365 * ptebit is set, cache it and return success.
2367 pt = moea_pvo_to_pte(pvo, -1);
2369 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2370 mtx_unlock(&moea_table_mutex);
2371 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2372 moea_attr_save(m, ptebit);
2382 moea_clear_bit(vm_page_t m, int ptebit)
2385 struct pvo_entry *pvo;
2388 rw_assert(&pvh_global_lock, RA_WLOCKED);
2391 * Clear the cached value.
2393 moea_attr_clear(m, ptebit);
2396 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2397 * we can reset the right ones). note that since the pvo entries and
2398 * list heads are accessed via BAT0 and are never placed in the page
2399 * table, we don't have to worry about further accesses setting the
2405 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2406 * valid pte clear the ptebit from the valid pte.
2409 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2410 pt = moea_pvo_to_pte(pvo, -1);
2412 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2413 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2415 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2417 mtx_unlock(&moea_table_mutex);
2419 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2426 * Return true if the physical range is encompassed by the battable[idx]
2429 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2437 * Return immediately if not a valid mapping
2439 if (!(battable[idx].batu & BAT_Vs))
2443 * The BAT entry must be cache-inhibited, guarded, and r/w
2444 * so it can function as an i/o page
2446 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2447 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2451 * The address should be within the BAT range. Assume that the
2452 * start address in the BAT has the correct alignment (thus
2453 * not requiring masking)
2455 start = battable[idx].batl & BAT_PBS;
2456 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2457 end = start | (bat_ble << 15) | 0x7fff;
2459 if ((pa < start) || ((pa + size) > end))
2466 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2471 * This currently does not work for entries that
2472 * overlap 256M BAT segments.
2475 for(i = 0; i < 16; i++)
2476 if (moea_bat_mapped(i, pa, size) == 0)
2483 * Map a set of physical memory pages into the kernel virtual
2484 * address space. Return a pointer to where it is mapped. This
2485 * routine is intended to be used for mapping device memory,
2489 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2492 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2496 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2498 vm_offset_t va, tmpva, ppa, offset;
2501 ppa = trunc_page(pa);
2502 offset = pa & PAGE_MASK;
2503 size = roundup(offset + size, PAGE_SIZE);
2506 * If the physical address lies within a valid BAT table entry,
2507 * return the 1:1 mapping. This currently doesn't work
2508 * for regions that overlap 256M BAT segments.
2510 for (i = 0; i < 16; i++) {
2511 if (moea_bat_mapped(i, pa, size) == 0)
2512 return ((void *) pa);
2515 va = kmem_alloc_nofault(kernel_map, size);
2517 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2519 for (tmpva = va; size > 0;) {
2520 moea_kenter_attr(mmu, tmpva, ppa, ma);
2527 return ((void *)(va + offset));
2531 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2533 vm_offset_t base, offset;
2536 * If this is outside kernel virtual space, then it's a
2537 * battable entry and doesn't require unmapping
2539 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2540 base = trunc_page(va);
2541 offset = va & PAGE_MASK;
2542 size = roundup(offset + size, PAGE_SIZE);
2543 kmem_free(kernel_map, base, size);
2548 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2550 struct pvo_entry *pvo;
2557 lim = round_page(va);
2558 len = MIN(lim - va, sz);
2559 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2561 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2563 moea_syncicache(pa, len);