2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/msgbuf.h>
124 #include <sys/mutex.h>
125 #include <sys/proc.h>
126 #include <sys/sysctl.h>
127 #include <sys/systm.h>
128 #include <sys/vmmeter.h>
130 #include <dev/ofw/openfirm.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
143 #include <machine/cpu.h>
144 #include <machine/powerpc.h>
145 #include <machine/bat.h>
146 #include <machine/frame.h>
147 #include <machine/md_var.h>
148 #include <machine/psl.h>
149 #include <machine/pte.h>
150 #include <machine/sr.h>
151 #include <machine/mmuvar.h>
157 #define TODO panic("%s: not implemented", __func__);
159 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va))
160 #define TLBSYNC() __asm __volatile("tlbsync");
161 #define SYNC() __asm __volatile("sync");
162 #define EIEIO() __asm __volatile("eieio");
164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
165 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
168 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */
169 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */
170 #define PVO_WIRED 0x010 /* PVO entry is wired */
171 #define PVO_MANAGED 0x020 /* PVO entry is managed */
172 #define PVO_EXECUTABLE 0x040 /* PVO entry is executable */
173 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during
175 #define PVO_FAKE 0x100 /* fictitious phys page */
176 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
177 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
178 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
179 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
180 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
181 #define PVO_PTEGIDX_CLR(pvo) \
182 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
183 #define PVO_PTEGIDX_SET(pvo, i) \
184 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
186 #define MOEA_PVO_CHECK(pvo)
196 * Map of physical memory regions.
198 static struct mem_region *regions;
199 static struct mem_region *pregions;
200 u_int phys_avail_count;
201 int regions_sz, pregions_sz;
202 static struct ofw_map *translations;
204 extern struct pmap ofw_pmap;
209 * Lock for the pteg and pvo tables.
211 struct mtx moea_table_mutex;
216 static struct pteg *moea_pteg_table;
217 u_int moea_pteg_count;
218 u_int moea_pteg_mask;
223 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
224 struct pvo_head moea_pvo_kunmanaged =
225 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
226 struct pvo_head moea_pvo_unmanaged =
227 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */
229 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
230 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
232 #define BPVO_POOL_SIZE 32768
233 static struct pvo_entry *moea_bpvo_pool;
234 static int moea_bpvo_pool_index = 0;
236 #define VSID_NBPW (sizeof(u_int32_t) * 8)
237 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
239 static boolean_t moea_initialized = FALSE;
244 u_int moea_pte_valid = 0;
245 u_int moea_pte_overflow = 0;
246 u_int moea_pte_replacements = 0;
247 u_int moea_pvo_entries = 0;
248 u_int moea_pvo_enter_calls = 0;
249 u_int moea_pvo_remove_calls = 0;
250 u_int moea_pte_spills = 0;
251 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
253 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
254 &moea_pte_overflow, 0, "");
255 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
256 &moea_pte_replacements, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
259 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
260 &moea_pvo_enter_calls, 0, "");
261 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
262 &moea_pvo_remove_calls, 0, "");
263 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
264 &moea_pte_spills, 0, "");
266 struct pvo_entry *moea_pvo_zeropage;
267 struct mtx moea_pvo_zeropage_mtx;
269 vm_offset_t moea_rkva_start = VM_MIN_KERNEL_ADDRESS;
270 u_int moea_rkva_count = 4;
273 * Allocate physical memory for use in moea_bootstrap.
275 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
280 static int moea_pte_insert(u_int, struct pte *);
285 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
286 vm_offset_t, vm_offset_t, u_int, int);
287 static void moea_pvo_remove(struct pvo_entry *, int);
288 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
289 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
294 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
295 vm_prot_t, boolean_t);
296 static struct pvo_entry *moea_rkva_alloc(mmu_t);
297 static void moea_pa_map(struct pvo_entry *, vm_offset_t,
298 struct pte *, int *);
299 static void moea_pa_unmap(struct pvo_entry *, struct pte *, int *);
300 static void moea_syncicache(vm_offset_t, vm_size_t);
301 static boolean_t moea_query_bit(vm_page_t, int);
302 static u_int moea_clear_bit(vm_page_t, int, int *);
303 static void moea_kremove(mmu_t, vm_offset_t);
304 static void tlbia(void);
305 int moea_pte_spill(vm_offset_t);
308 * Kernel MMU interface
310 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
311 void moea_clear_modify(mmu_t, vm_page_t);
312 void moea_clear_reference(mmu_t, vm_page_t);
313 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
314 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
315 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
317 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
318 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
319 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
320 void moea_init(mmu_t);
321 boolean_t moea_is_modified(mmu_t, vm_page_t);
322 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
323 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
324 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
325 void moea_pinit(mmu_t, pmap_t);
326 void moea_pinit0(mmu_t, pmap_t);
327 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
328 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
329 void moea_qremove(mmu_t, vm_offset_t, int);
330 void moea_release(mmu_t, pmap_t);
331 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
332 void moea_remove_all(mmu_t, vm_page_t);
333 void moea_remove_write(mmu_t, vm_page_t);
334 void moea_zero_page(mmu_t, vm_page_t);
335 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
336 void moea_zero_page_idle(mmu_t, vm_page_t);
337 void moea_activate(mmu_t, struct thread *);
338 void moea_deactivate(mmu_t, struct thread *);
339 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
340 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
341 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
342 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
343 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
344 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
346 static mmu_method_t moea_methods[] = {
347 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
348 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
349 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
350 MMUMETHOD(mmu_copy_page, moea_copy_page),
351 MMUMETHOD(mmu_enter, moea_enter),
352 MMUMETHOD(mmu_enter_object, moea_enter_object),
353 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
354 MMUMETHOD(mmu_extract, moea_extract),
355 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
356 MMUMETHOD(mmu_init, moea_init),
357 MMUMETHOD(mmu_is_modified, moea_is_modified),
358 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
359 MMUMETHOD(mmu_map, moea_map),
360 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
361 MMUMETHOD(mmu_pinit, moea_pinit),
362 MMUMETHOD(mmu_pinit0, moea_pinit0),
363 MMUMETHOD(mmu_protect, moea_protect),
364 MMUMETHOD(mmu_qenter, moea_qenter),
365 MMUMETHOD(mmu_qremove, moea_qremove),
366 MMUMETHOD(mmu_release, moea_release),
367 MMUMETHOD(mmu_remove, moea_remove),
368 MMUMETHOD(mmu_remove_all, moea_remove_all),
369 MMUMETHOD(mmu_remove_write, moea_remove_write),
370 MMUMETHOD(mmu_zero_page, moea_zero_page),
371 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
372 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
373 MMUMETHOD(mmu_activate, moea_activate),
374 MMUMETHOD(mmu_deactivate, moea_deactivate),
376 /* Internal interfaces */
377 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
378 MMUMETHOD(mmu_mapdev, moea_mapdev),
379 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
380 MMUMETHOD(mmu_kextract, moea_kextract),
381 MMUMETHOD(mmu_kenter, moea_kenter),
382 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
387 static mmu_def_t oea_mmu = {
396 va_to_sr(u_int *sr, vm_offset_t va)
398 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
401 static __inline u_int
402 va_to_pteg(u_int sr, vm_offset_t addr)
406 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
408 return (hash & moea_pteg_mask);
411 static __inline struct pvo_head *
412 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p)
416 pg = PHYS_TO_VM_PAGE(pa);
422 return (&moea_pvo_unmanaged);
424 return (&pg->md.mdpg_pvoh);
427 static __inline struct pvo_head *
428 vm_page_to_pvoh(vm_page_t m)
431 return (&m->md.mdpg_pvoh);
435 moea_attr_clear(vm_page_t m, int ptebit)
438 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
439 m->md.mdpg_attrs &= ~ptebit;
443 moea_attr_fetch(vm_page_t m)
446 return (m->md.mdpg_attrs);
450 moea_attr_save(vm_page_t m, int ptebit)
453 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
454 m->md.mdpg_attrs |= ptebit;
458 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
460 if (pt->pte_hi == pvo_pt->pte_hi)
467 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
469 return (pt->pte_hi & ~PTE_VALID) ==
470 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
471 ((va >> ADDR_API_SHFT) & PTE_API) | which);
475 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
478 mtx_assert(&moea_table_mutex, MA_OWNED);
481 * Construct a PTE. Default to IMB initially. Valid bit only gets
482 * set when the real pte is set in memory.
484 * Note: Don't set the valid bit for correct operation of tlb update.
486 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
487 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
492 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
495 mtx_assert(&moea_table_mutex, MA_OWNED);
496 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
500 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
503 mtx_assert(&moea_table_mutex, MA_OWNED);
506 * As shown in Section 7.6.3.2.3
508 pt->pte_lo &= ~ptebit;
516 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
519 mtx_assert(&moea_table_mutex, MA_OWNED);
520 pvo_pt->pte_hi |= PTE_VALID;
523 * Update the PTE as defined in section 7.6.3.1.
524 * Note that the REF/CHG bits are from pvo_pt and thus should havce
525 * been saved so this routine can restore them (if desired).
527 pt->pte_lo = pvo_pt->pte_lo;
529 pt->pte_hi = pvo_pt->pte_hi;
535 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
538 mtx_assert(&moea_table_mutex, MA_OWNED);
539 pvo_pt->pte_hi &= ~PTE_VALID;
542 * Force the reg & chg bits back into the PTEs.
547 * Invalidate the pte.
549 pt->pte_hi &= ~PTE_VALID;
558 * Save the reg & chg bits.
560 moea_pte_synch(pt, pvo_pt);
565 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
571 moea_pte_unset(pt, pvo_pt, va);
572 moea_pte_set(pt, pvo_pt);
576 * Quick sort callout for comparing memory regions.
578 static int mr_cmp(const void *a, const void *b);
579 static int om_cmp(const void *a, const void *b);
582 mr_cmp(const void *a, const void *b)
584 const struct mem_region *regiona;
585 const struct mem_region *regionb;
589 if (regiona->mr_start < regionb->mr_start)
591 else if (regiona->mr_start > regionb->mr_start)
598 om_cmp(const void *a, const void *b)
600 const struct ofw_map *mapa;
601 const struct ofw_map *mapb;
605 if (mapa->om_pa < mapb->om_pa)
607 else if (mapa->om_pa > mapb->om_pa)
614 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
617 phandle_t chosen, mmu;
621 vm_size_t size, physsz, hwphyssz;
622 vm_offset_t pa, va, off;
626 * Set up BAT0 to map the lowest 256 MB area
628 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
629 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
632 * Map PCI memory space.
634 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
635 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
637 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
638 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
640 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
641 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
643 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
644 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
649 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
650 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
653 * Use an IBAT and a DBAT to map the bottom segment of memory
656 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
657 batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
658 __asm (".balign 32; \n"
659 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
660 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
661 :: "r"(batu), "r"(batl));
664 /* map frame buffer */
665 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
666 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
667 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
668 :: "r"(batu), "r"(batl));
673 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
674 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
675 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
676 :: "r"(batu), "r"(batl));
680 * Set the start and end of kva.
682 virtual_avail = VM_MIN_KERNEL_ADDRESS;
683 virtual_end = VM_MAX_KERNEL_ADDRESS;
685 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
686 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
688 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
689 for (i = 0; i < pregions_sz; i++) {
693 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
694 pregions[i].mr_start,
695 pregions[i].mr_start + pregions[i].mr_size,
696 pregions[i].mr_size);
698 * Install entries into the BAT table to allow all
699 * of physmem to be convered by on-demand BAT entries.
700 * The loop will sometimes set the same battable element
701 * twice, but that's fine since they won't be used for
704 pa = pregions[i].mr_start & 0xf0000000;
705 end = pregions[i].mr_start + pregions[i].mr_size;
707 u_int n = pa >> ADDR_SR_SHFT;
709 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
710 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
711 pa += SEGMENT_LENGTH;
715 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
716 panic("moea_bootstrap: phys_avail too small");
717 qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
718 phys_avail_count = 0;
721 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
722 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
723 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
724 regions[i].mr_start + regions[i].mr_size,
727 (physsz + regions[i].mr_size) >= hwphyssz) {
728 if (physsz < hwphyssz) {
729 phys_avail[j] = regions[i].mr_start;
730 phys_avail[j + 1] = regions[i].mr_start +
737 phys_avail[j] = regions[i].mr_start;
738 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
740 physsz += regions[i].mr_size;
742 physmem = btoc(physsz);
745 * Allocate PTEG table.
748 moea_pteg_count = PTEGCOUNT;
750 moea_pteg_count = 0x1000;
752 while (moea_pteg_count < physmem)
753 moea_pteg_count <<= 1;
755 moea_pteg_count >>= 1;
756 #endif /* PTEGCOUNT */
758 size = moea_pteg_count * sizeof(struct pteg);
759 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
761 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
762 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
763 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
764 moea_pteg_mask = moea_pteg_count - 1;
767 * Allocate pv/overflow lists.
769 size = sizeof(struct pvo_head) * moea_pteg_count;
770 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
772 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
773 for (i = 0; i < moea_pteg_count; i++)
774 LIST_INIT(&moea_pvo_table[i]);
777 * Initialize the lock that synchronizes access to the pteg and pvo
780 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
784 * Allocate the message buffer.
786 msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, 0);
789 * Initialise the unmanaged pvo pool.
791 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
792 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
793 moea_bpvo_pool_index = 0;
796 * Make sure kernel vsid is allocated as well as VSID 0.
798 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
799 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
800 moea_vsid_bitmap[0] |= 1;
803 * Set up the Open Firmware pmap and add it's mappings.
805 moea_pinit(mmup, &ofw_pmap);
806 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
807 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
808 if ((chosen = OF_finddevice("/chosen")) == -1)
809 panic("moea_bootstrap: can't find /chosen");
810 OF_getprop(chosen, "mmu", &mmui, 4);
811 if ((mmu = OF_instance_to_package(mmui)) == -1)
812 panic("moea_bootstrap: can't get mmu package");
813 if ((sz = OF_getproplen(mmu, "translations")) == -1)
814 panic("moea_bootstrap: can't get ofw translation count");
816 for (i = 0; phys_avail[i] != 0; i += 2) {
817 if (phys_avail[i + 1] >= sz) {
818 translations = (struct ofw_map *)phys_avail[i];
822 if (translations == NULL)
823 panic("moea_bootstrap: no space to copy translations");
824 bzero(translations, sz);
825 if (OF_getprop(mmu, "translations", translations, sz) == -1)
826 panic("moea_bootstrap: can't get ofw translations");
827 CTR0(KTR_PMAP, "moea_bootstrap: translations");
828 sz /= sizeof(*translations);
829 qsort(translations, sz, sizeof (*translations), om_cmp);
830 for (i = 0, ofw_mappings = 0; i < sz; i++) {
831 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
832 translations[i].om_pa, translations[i].om_va,
833 translations[i].om_len);
836 * If the mapping is 1:1, let the RAM and device on-demand
837 * BAT tables take care of the translation.
839 if (translations[i].om_va == translations[i].om_pa)
842 /* Enter the pages */
843 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
846 m.phys_addr = translations[i].om_pa + off;
847 PMAP_LOCK(&ofw_pmap);
848 moea_enter_locked(&ofw_pmap,
849 translations[i].om_va + off, &m,
851 PMAP_UNLOCK(&ofw_pmap);
860 * Initialize the kernel pmap (which is statically allocated).
862 PMAP_LOCK_INIT(kernel_pmap);
863 for (i = 0; i < 16; i++) {
864 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
866 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
867 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
868 kernel_pmap->pm_active = ~0;
871 * Allocate a kernel stack with a guard page for thread0 and map it
872 * into the kernel page map.
874 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0);
876 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE);
877 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", kstack0_phys,
879 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE;
880 for (i = 0; i < KSTACK_PAGES; i++) {
881 pa = kstack0_phys + i * PAGE_SIZE;
882 va = kstack0 + i * PAGE_SIZE;
883 moea_kenter(mmup, va, pa);
888 * Calculate the last available physical address.
890 for (i = 0; phys_avail[i + 2] != 0; i += 2)
892 Maxmem = powerpc_btop(phys_avail[i + 1]);
895 * Allocate virtual address space for the message buffer.
897 msgbufp = (struct msgbuf *)virtual_avail;
898 virtual_avail += round_page(MSGBUF_SIZE);
901 * Initialize hardware.
903 for (i = 0; i < 16; i++) {
904 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
906 __asm __volatile ("mtsr %0,%1"
907 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
908 __asm __volatile ("mtsr %0,%1"
909 :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
910 __asm __volatile ("sync; mtsdr1 %0; isync"
911 :: "r"((u_int)moea_pteg_table | (moea_pteg_mask >> 10)));
918 * Activate a user pmap. The pmap must be activated before it's address
919 * space can be accessed in any way.
922 moea_activate(mmu_t mmu, struct thread *td)
927 * Load all the data we need up front to encourage the compiler to
928 * not issue any loads while we have interrupts disabled below.
930 pm = &td->td_proc->p_vmspace->vm_pmap;
932 if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL)
935 pm->pm_active |= PCPU_GET(cpumask);
936 PCPU_SET(curpmap, pmr);
940 moea_deactivate(mmu_t mmu, struct thread *td)
944 pm = &td->td_proc->p_vmspace->vm_pmap;
945 pm->pm_active &= ~(PCPU_GET(cpumask));
946 PCPU_SET(curpmap, NULL);
950 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
952 struct pvo_entry *pvo;
955 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
959 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
960 pm->pm_stats.wired_count++;
961 pvo->pvo_vaddr |= PVO_WIRED;
963 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
964 pm->pm_stats.wired_count--;
965 pvo->pvo_vaddr &= ~PVO_WIRED;
972 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
977 dst = VM_PAGE_TO_PHYS(mdst);
978 src = VM_PAGE_TO_PHYS(msrc);
980 kcopy((void *)src, (void *)dst, PAGE_SIZE);
984 * Zero a page of physical memory by temporarily mapping it into the tlb.
987 moea_zero_page(mmu_t mmu, vm_page_t m)
989 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
992 if (pa < SEGMENT_LENGTH) {
994 } else if (moea_initialized) {
995 if (moea_pvo_zeropage == NULL) {
996 moea_pvo_zeropage = moea_rkva_alloc(mmu);
997 mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
1000 mtx_lock(&moea_pvo_zeropage_mtx);
1001 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
1002 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
1004 panic("moea_zero_page: can't zero pa %#x", pa);
1007 bzero(va, PAGE_SIZE);
1009 if (pa >= SEGMENT_LENGTH) {
1010 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
1011 mtx_unlock(&moea_pvo_zeropage_mtx);
1016 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1018 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1021 if (pa < SEGMENT_LENGTH) {
1023 } else if (moea_initialized) {
1024 if (moea_pvo_zeropage == NULL) {
1025 moea_pvo_zeropage = moea_rkva_alloc(mmu);
1026 mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
1029 mtx_lock(&moea_pvo_zeropage_mtx);
1030 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
1031 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
1033 panic("moea_zero_page: can't zero pa %#x", pa);
1036 bzero(va + off, size);
1038 if (pa >= SEGMENT_LENGTH) {
1039 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
1040 mtx_unlock(&moea_pvo_zeropage_mtx);
1045 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1048 moea_zero_page(mmu, m);
1052 * Map the given physical page at the specified virtual address in the
1053 * target pmap with the protection requested. If specified the page
1054 * will be wired down.
1057 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1061 vm_page_lock_queues();
1063 moea_enter_locked(pmap, va, m, prot, wired);
1064 vm_page_unlock_queues();
1069 * Map the given physical page at the specified virtual address in the
1070 * target pmap with the protection requested. If specified the page
1071 * will be wired down.
1073 * The page queues and pmap must be locked.
1076 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1079 struct pvo_head *pvo_head;
1082 u_int pte_lo, pvo_flags, was_exec, i;
1085 if (!moea_initialized) {
1086 pvo_head = &moea_pvo_kunmanaged;
1087 zone = moea_upvo_zone;
1090 was_exec = PTE_EXEC;
1092 pvo_head = vm_page_to_pvoh(m);
1094 zone = moea_mpvo_zone;
1095 pvo_flags = PVO_MANAGED;
1098 if (pmap_bootstrapped)
1099 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1100 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1102 /* XXX change the pvo head for fake pages */
1103 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS)
1104 pvo_head = &moea_pvo_kunmanaged;
1107 * If this is a managed page, and it's the first reference to the page,
1108 * clear the execness of the page. Otherwise fetch the execness.
1110 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) {
1111 if (LIST_EMPTY(pvo_head)) {
1112 moea_attr_clear(pg, PTE_EXEC);
1114 was_exec = moea_attr_fetch(pg) & PTE_EXEC;
1119 * Assume the page is cache inhibited and access is guarded unless
1120 * it's in our available memory array.
1122 pte_lo = PTE_I | PTE_G;
1123 for (i = 0; i < pregions_sz; i++) {
1124 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) &&
1125 (VM_PAGE_TO_PHYS(m) <
1126 (pregions[i].mr_start + pregions[i].mr_size))) {
1127 pte_lo &= ~(PTE_I | PTE_G);
1132 if (prot & VM_PROT_WRITE)
1137 if (prot & VM_PROT_EXECUTE)
1138 pvo_flags |= PVO_EXECUTABLE;
1141 pvo_flags |= PVO_WIRED;
1143 if ((m->flags & PG_FICTITIOUS) != 0)
1144 pvo_flags |= PVO_FAKE;
1146 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1150 * Flush the real page from the instruction cache if this page is
1151 * mapped executable and cacheable and was not previously mapped (or
1152 * was not mapped executable).
1154 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
1155 (pte_lo & PTE_I) == 0 && was_exec == 0) {
1157 * Flush the real memory from the cache.
1159 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1161 moea_attr_save(pg, PTE_EXEC);
1164 /* XXX syncicache always until problems are sorted */
1165 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1169 * Maps a sequence of resident pages belonging to the same object.
1170 * The sequence begins with the given page m_start. This page is
1171 * mapped at the given virtual address start. Each subsequent page is
1172 * mapped at a virtual address that is offset from start by the same
1173 * amount as the page is offset from m_start within the object. The
1174 * last page in the sequence is the page with the largest offset from
1175 * m_start that can be mapped at a virtual address less than the given
1176 * virtual address end. Not every virtual page between start and end
1177 * is mapped; only those for which a resident page exists with the
1178 * corresponding offset from m_start are mapped.
1181 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1182 vm_page_t m_start, vm_prot_t prot)
1185 vm_pindex_t diff, psize;
1187 psize = atop(end - start);
1190 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1191 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1192 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1193 m = TAILQ_NEXT(m, listq);
1199 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1204 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1211 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1213 struct pvo_entry *pvo;
1217 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1221 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1227 * Atomically extract and hold the physical page with the given
1228 * pmap and virtual address pair if that mapping permits the given
1232 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1234 struct pvo_entry *pvo;
1238 vm_page_lock_queues();
1240 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1241 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) &&
1242 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW ||
1243 (prot & VM_PROT_WRITE) == 0)) {
1244 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
1247 vm_page_unlock_queues();
1253 moea_init(mmu_t mmu)
1256 CTR0(KTR_PMAP, "moea_init");
1258 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1259 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1260 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1261 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1262 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1263 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1264 moea_initialized = TRUE;
1268 moea_is_modified(mmu_t mmu, vm_page_t m)
1271 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0)
1274 return (moea_query_bit(m, PTE_CHG));
1278 moea_clear_reference(mmu_t mmu, vm_page_t m)
1281 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1283 moea_clear_bit(m, PTE_REF, NULL);
1287 moea_clear_modify(mmu_t mmu, vm_page_t m)
1290 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1292 moea_clear_bit(m, PTE_CHG, NULL);
1296 * Clear the write and modified bits in each of the given page's mappings.
1299 moea_remove_write(mmu_t mmu, vm_page_t m)
1301 struct pvo_entry *pvo;
1306 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1307 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1308 (m->flags & PG_WRITEABLE) == 0)
1310 lo = moea_attr_fetch(m);
1312 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1313 pmap = pvo->pvo_pmap;
1315 if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) {
1316 pt = moea_pvo_to_pte(pvo, -1);
1317 pvo->pvo_pte.pte_lo &= ~PTE_PP;
1318 pvo->pvo_pte.pte_lo |= PTE_BR;
1320 moea_pte_synch(pt, &pvo->pvo_pte);
1321 lo |= pvo->pvo_pte.pte_lo;
1322 pvo->pvo_pte.pte_lo &= ~PTE_CHG;
1323 moea_pte_change(pt, &pvo->pvo_pte,
1325 mtx_unlock(&moea_table_mutex);
1330 if ((lo & PTE_CHG) != 0) {
1331 moea_attr_clear(m, PTE_CHG);
1334 vm_page_flag_clear(m, PG_WRITEABLE);
1338 * moea_ts_referenced:
1340 * Return a count of reference bits for a page, clearing those bits.
1341 * It is not necessary for every reference bit to be cleared, but it
1342 * is necessary that 0 only be returned when there are truly no
1343 * reference bits set.
1345 * XXX: The exact number of bits to check and clear is a matter that
1346 * should be tested and standardized at some point in the future for
1347 * optimal aging of shared pages.
1350 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1354 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1357 count = moea_clear_bit(m, PTE_REF, NULL);
1363 * Map a wired page into kernel virtual address space.
1366 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1373 if (va < VM_MIN_KERNEL_ADDRESS)
1374 panic("moea_kenter: attempt to enter non-kernel address %#x",
1378 pte_lo = PTE_I | PTE_G;
1379 for (i = 0; i < pregions_sz; i++) {
1380 if ((pa >= pregions[i].mr_start) &&
1381 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
1382 pte_lo &= ~(PTE_I | PTE_G);
1387 PMAP_LOCK(kernel_pmap);
1388 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1389 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1391 if (error != 0 && error != ENOENT)
1392 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1396 * Flush the real memory from the instruction cache.
1398 if ((pte_lo & (PTE_I | PTE_G)) == 0) {
1399 moea_syncicache(pa, PAGE_SIZE);
1401 PMAP_UNLOCK(kernel_pmap);
1405 * Extract the physical page address associated with the given kernel virtual
1409 moea_kextract(mmu_t mmu, vm_offset_t va)
1411 struct pvo_entry *pvo;
1414 #ifdef UMA_MD_SMALL_ALLOC
1416 * Allow direct mappings
1418 if (va < VM_MIN_KERNEL_ADDRESS) {
1423 PMAP_LOCK(kernel_pmap);
1424 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1425 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1426 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1427 PMAP_UNLOCK(kernel_pmap);
1432 * Remove a wired page from kernel virtual address space.
1435 moea_kremove(mmu_t mmu, vm_offset_t va)
1438 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1442 * Map a range of physical addresses into kernel virtual address space.
1444 * The value passed in *virt is a suggested virtual address for the mapping.
1445 * Architectures which can support a direct-mapped physical to virtual region
1446 * can return the appropriate address within that region, leaving '*virt'
1447 * unchanged. We cannot and therefore do not; *virt is updated with the
1448 * first usable address after the mapped region.
1451 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1452 vm_offset_t pa_end, int prot)
1454 vm_offset_t sva, va;
1458 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1459 moea_kenter(mmu, va, pa_start);
1465 * Returns true if the pmap's pv is one of the first
1466 * 16 pvs linked to from this page. This count may
1467 * be changed upwards or downwards in the future; it
1468 * is only necessary that true be returned for a small
1469 * subset of pmaps for proper page aging.
1472 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1475 struct pvo_entry *pvo;
1477 if (!moea_initialized || (m->flags & PG_FICTITIOUS))
1481 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1482 if (pvo->pvo_pmap == pmap)
1491 static u_int moea_vsidcontext;
1494 moea_pinit(mmu_t mmu, pmap_t pmap)
1499 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1500 PMAP_LOCK_INIT(pmap);
1503 __asm __volatile("mftb %0" : "=r"(entropy));
1506 * Allocate some segment registers for this pmap.
1508 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1512 * Create a new value by mutiplying by a prime and adding in
1513 * entropy from the timebase register. This is to make the
1514 * VSID more random so that the PT hash function collides
1515 * less often. (Note that the prime casues gcc to do shifts
1516 * instead of a multiply.)
1518 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1519 hash = moea_vsidcontext & (NPMAPS - 1);
1520 if (hash == 0) /* 0 is special, avoid it */
1523 mask = 1 << (hash & (VSID_NBPW - 1));
1524 hash = (moea_vsidcontext & 0xfffff);
1525 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1526 /* anything free in this bucket? */
1527 if (moea_vsid_bitmap[n] == 0xffffffff) {
1528 entropy = (moea_vsidcontext >> 20);
1531 i = ffs(~moea_vsid_bitmap[i]) - 1;
1533 hash &= 0xfffff & ~(VSID_NBPW - 1);
1536 moea_vsid_bitmap[n] |= mask;
1537 for (i = 0; i < 16; i++)
1538 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1542 panic("moea_pinit: out of segments");
1546 * Initialize the pmap associated with process 0.
1549 moea_pinit0(mmu_t mmu, pmap_t pm)
1552 moea_pinit(mmu, pm);
1553 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1557 * Set the physical protection on the specified range of this map as requested.
1560 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1563 struct pvo_entry *pvo;
1567 CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva,
1571 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1572 ("moea_protect: non current pmap"));
1574 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1575 moea_remove(mmu, pm, sva, eva);
1579 vm_page_lock_queues();
1581 for (; sva < eva; sva += PAGE_SIZE) {
1582 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1586 if ((prot & VM_PROT_EXECUTE) == 0)
1587 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1590 * Grab the PTE pointer before we diddle with the cached PTE
1593 pt = moea_pvo_to_pte(pvo, pteidx);
1595 * Change the protection of the page.
1597 pvo->pvo_pte.pte_lo &= ~PTE_PP;
1598 pvo->pvo_pte.pte_lo |= PTE_BR;
1601 * If the PVO is in the page table, update that pte as well.
1604 moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1605 mtx_unlock(&moea_table_mutex);
1608 vm_page_unlock_queues();
1613 * Map a list of wired pages into kernel virtual address space. This is
1614 * intended for temporary mappings which do not need page modification or
1615 * references recorded. Existing mappings in the region are overwritten.
1618 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1623 while (count-- > 0) {
1624 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1631 * Remove page mappings from kernel virtual address space. Intended for
1632 * temporary mappings entered by moea_qenter.
1635 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1640 while (count-- > 0) {
1641 moea_kremove(mmu, va);
1647 moea_release(mmu_t mmu, pmap_t pmap)
1652 * Free segment register's VSID
1654 if (pmap->pm_sr[0] == 0)
1655 panic("moea_release");
1657 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1658 mask = 1 << (idx % VSID_NBPW);
1660 moea_vsid_bitmap[idx] &= ~mask;
1661 PMAP_LOCK_DESTROY(pmap);
1665 * Remove the given range of addresses from the specified map.
1668 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1670 struct pvo_entry *pvo;
1673 vm_page_lock_queues();
1675 for (; sva < eva; sva += PAGE_SIZE) {
1676 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1678 moea_pvo_remove(pvo, pteidx);
1682 vm_page_unlock_queues();
1686 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1687 * will reflect changes in pte's back to the vm_page.
1690 moea_remove_all(mmu_t mmu, vm_page_t m)
1692 struct pvo_head *pvo_head;
1693 struct pvo_entry *pvo, *next_pvo;
1696 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1698 pvo_head = vm_page_to_pvoh(m);
1699 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1700 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1702 MOEA_PVO_CHECK(pvo); /* sanity check */
1703 pmap = pvo->pvo_pmap;
1705 moea_pvo_remove(pvo, -1);
1708 vm_page_flag_clear(m, PG_WRITEABLE);
1712 * Allocate a physical page of memory directly from the phys_avail map.
1713 * Can only be called from moea_bootstrap before avail start and end are
1717 moea_bootstrap_alloc(vm_size_t size, u_int align)
1722 size = round_page(size);
1723 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1725 s = (phys_avail[i] + align - 1) & ~(align - 1);
1730 if (s < phys_avail[i] || e > phys_avail[i + 1])
1733 if (s == phys_avail[i]) {
1734 phys_avail[i] += size;
1735 } else if (e == phys_avail[i + 1]) {
1736 phys_avail[i + 1] -= size;
1738 for (j = phys_avail_count * 2; j > i; j -= 2) {
1739 phys_avail[j] = phys_avail[j - 2];
1740 phys_avail[j + 1] = phys_avail[j - 1];
1743 phys_avail[i + 3] = phys_avail[i + 1];
1744 phys_avail[i + 1] = s;
1745 phys_avail[i + 2] = e;
1751 panic("moea_bootstrap_alloc: could not allocate memory");
1755 * Return an unmapped pvo for a kernel virtual address.
1756 * Used by pmap functions that operate on physical pages.
1758 static struct pvo_entry *
1759 moea_rkva_alloc(mmu_t mmu)
1761 struct pvo_entry *pvo;
1766 if (moea_rkva_count == 0)
1767 panic("moea_rkva_alloc: no more reserved KVAs");
1769 kva = moea_rkva_start + (PAGE_SIZE * --moea_rkva_count);
1770 moea_kenter(mmu, kva, 0);
1772 pvo = moea_pvo_find_va(kernel_pmap, kva, &pteidx);
1775 panic("moea_kva_alloc: moea_pvo_find_va failed");
1777 pt = moea_pvo_to_pte(pvo, pteidx);
1780 panic("moea_kva_alloc: moea_pvo_to_pte failed");
1782 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1783 mtx_unlock(&moea_table_mutex);
1784 PVO_PTEGIDX_CLR(pvo);
1786 moea_pte_overflow++;
1792 moea_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt,
1798 * If this pvo already has a valid pte, we need to save it so it can
1799 * be restored later. We then just reload the new PTE over the old
1802 if (saved_pt != NULL) {
1803 pt = moea_pvo_to_pte(pvo, -1);
1806 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1807 mtx_unlock(&moea_table_mutex);
1808 PVO_PTEGIDX_CLR(pvo);
1809 moea_pte_overflow++;
1812 *saved_pt = pvo->pvo_pte;
1814 pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
1817 pvo->pvo_pte.pte_lo |= pa;
1819 if (!moea_pte_spill(pvo->pvo_vaddr))
1820 panic("moea_pa_map: could not spill pvo %p", pvo);
1822 if (depth_p != NULL)
1827 moea_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p)
1831 pt = moea_pvo_to_pte(pvo, -1);
1834 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1835 mtx_unlock(&moea_table_mutex);
1836 PVO_PTEGIDX_CLR(pvo);
1837 moea_pte_overflow++;
1840 pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
1843 * If there is a saved PTE and it's valid, restore it and return.
1845 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) {
1846 if (depth_p != NULL && --(*depth_p) == 0)
1847 panic("moea_pa_unmap: restoring but depth == 0");
1849 pvo->pvo_pte = *saved_pt;
1851 if (!moea_pte_spill(pvo->pvo_vaddr))
1852 panic("moea_pa_unmap: could not spill pvo %p", pvo);
1857 moea_syncicache(vm_offset_t pa, vm_size_t len)
1859 __syncicache((void *)pa, len);
1868 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) {
1877 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1878 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1880 struct pvo_entry *pvo;
1887 moea_pvo_enter_calls++;
1892 * Compute the PTE Group index.
1895 sr = va_to_sr(pm->pm_sr, va);
1896 ptegidx = va_to_pteg(sr, va);
1899 * Remove any existing mapping for this page. Reuse the pvo entry if
1900 * there is a mapping.
1902 mtx_lock(&moea_table_mutex);
1903 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1904 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1905 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa &&
1906 (pvo->pvo_pte.pte_lo & PTE_PP) ==
1907 (pte_lo & PTE_PP)) {
1908 mtx_unlock(&moea_table_mutex);
1911 moea_pvo_remove(pvo, -1);
1917 * If we aren't overwriting a mapping, try to allocate.
1919 if (moea_initialized) {
1920 pvo = uma_zalloc(zone, M_NOWAIT);
1922 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1923 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1924 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1925 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1927 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1928 moea_bpvo_pool_index++;
1933 mtx_unlock(&moea_table_mutex);
1938 pvo->pvo_vaddr = va;
1940 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1941 pvo->pvo_vaddr &= ~ADDR_POFF;
1942 if (flags & VM_PROT_EXECUTE)
1943 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1944 if (flags & PVO_WIRED)
1945 pvo->pvo_vaddr |= PVO_WIRED;
1946 if (pvo_head != &moea_pvo_kunmanaged)
1947 pvo->pvo_vaddr |= PVO_MANAGED;
1949 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1950 if (flags & PVO_FAKE)
1951 pvo->pvo_vaddr |= PVO_FAKE;
1953 moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo);
1956 * Remember if the list was empty and therefore will be the first
1959 if (LIST_FIRST(pvo_head) == NULL)
1961 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1963 if (pvo->pvo_pte.pte_lo & PVO_WIRED)
1964 pm->pm_stats.wired_count++;
1965 pm->pm_stats.resident_count++;
1968 * We hope this succeeds but it isn't required.
1970 i = moea_pte_insert(ptegidx, &pvo->pvo_pte);
1972 PVO_PTEGIDX_SET(pvo, i);
1974 panic("moea_pvo_enter: overflow");
1975 moea_pte_overflow++;
1977 mtx_unlock(&moea_table_mutex);
1979 return (first ? ENOENT : 0);
1983 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1988 * If there is an active pte entry, we need to deactivate it (and
1989 * save the ref & cfg bits).
1991 pt = moea_pvo_to_pte(pvo, pteidx);
1993 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1994 mtx_unlock(&moea_table_mutex);
1995 PVO_PTEGIDX_CLR(pvo);
1997 moea_pte_overflow--;
2001 * Update our statistics.
2003 pvo->pvo_pmap->pm_stats.resident_count--;
2004 if (pvo->pvo_pte.pte_lo & PVO_WIRED)
2005 pvo->pvo_pmap->pm_stats.wired_count--;
2008 * Save the REF/CHG bits into their cache if the page is managed.
2010 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
2013 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
2015 moea_attr_save(pg, pvo->pvo_pte.pte_lo &
2016 (PTE_REF | PTE_CHG));
2021 * Remove this PVO from the PV list.
2023 LIST_REMOVE(pvo, pvo_vlink);
2026 * Remove this from the overflow list and return it to the pool
2027 * if we aren't going to reuse it.
2029 LIST_REMOVE(pvo, pvo_olink);
2030 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2031 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2032 moea_upvo_zone, pvo);
2034 moea_pvo_remove_calls++;
2038 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2043 * We can find the actual pte entry without searching by grabbing
2044 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2045 * noticing the HID bit.
2047 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2048 if (pvo->pvo_pte.pte_hi & PTE_HID)
2049 pteidx ^= moea_pteg_mask * 8;
2054 static struct pvo_entry *
2055 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2057 struct pvo_entry *pvo;
2062 sr = va_to_sr(pm->pm_sr, va);
2063 ptegidx = va_to_pteg(sr, va);
2065 mtx_lock(&moea_table_mutex);
2066 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2067 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2069 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2073 mtx_unlock(&moea_table_mutex);
2079 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2084 * If we haven't been supplied the ptegidx, calculate it.
2090 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2091 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2092 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2095 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2096 mtx_lock(&moea_table_mutex);
2098 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2099 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2100 "valid pte index", pvo);
2103 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2104 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2105 "pvo but no valid pte", pvo);
2108 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2109 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) {
2110 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2111 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2114 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2116 panic("moea_pvo_to_pte: pvo %p pte does not match "
2117 "pte %p in moea_pteg_table", pvo, pt);
2120 mtx_assert(&moea_table_mutex, MA_OWNED);
2124 if (pvo->pvo_pte.pte_hi & PTE_VALID) {
2125 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2126 "moea_pteg_table but valid in pvo", pvo, pt);
2129 mtx_unlock(&moea_table_mutex);
2134 * XXX: THIS STUFF SHOULD BE IN pte.c?
2137 moea_pte_spill(vm_offset_t addr)
2139 struct pvo_entry *source_pvo, *victim_pvo;
2140 struct pvo_entry *pvo;
2149 ptegidx = va_to_pteg(sr, addr);
2152 * Have to substitute some entry. Use the primary hash for this.
2153 * Use low bits of timebase as random generator.
2155 pteg = &moea_pteg_table[ptegidx];
2156 mtx_lock(&moea_table_mutex);
2157 __asm __volatile("mftb %0" : "=r"(i));
2163 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2165 * We need to find a pvo entry for this address.
2167 MOEA_PVO_CHECK(pvo);
2168 if (source_pvo == NULL &&
2169 moea_pte_match(&pvo->pvo_pte, sr, addr,
2170 pvo->pvo_pte.pte_hi & PTE_HID)) {
2172 * Now found an entry to be spilled into the pteg.
2173 * The PTE is now valid, so we know it's active.
2175 j = moea_pte_insert(ptegidx, &pvo->pvo_pte);
2178 PVO_PTEGIDX_SET(pvo, j);
2179 moea_pte_overflow--;
2180 MOEA_PVO_CHECK(pvo);
2181 mtx_unlock(&moea_table_mutex);
2187 if (victim_pvo != NULL)
2192 * We also need the pvo entry of the victim we are replacing
2193 * so save the R & C bits of the PTE.
2195 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2196 moea_pte_compare(pt, &pvo->pvo_pte)) {
2198 if (source_pvo != NULL)
2203 if (source_pvo == NULL) {
2204 mtx_unlock(&moea_table_mutex);
2208 if (victim_pvo == NULL) {
2209 if ((pt->pte_hi & PTE_HID) == 0)
2210 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2214 * If this is a secondary PTE, we need to search it's primary
2215 * pvo bucket for the matching PVO.
2217 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2219 MOEA_PVO_CHECK(pvo);
2221 * We also need the pvo entry of the victim we are
2222 * replacing so save the R & C bits of the PTE.
2224 if (moea_pte_compare(pt, &pvo->pvo_pte)) {
2230 if (victim_pvo == NULL)
2231 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2236 * We are invalidating the TLB entry for the EA we are replacing even
2237 * though it's valid. If we don't, we lose any ref/chg bit changes
2238 * contained in the TLB entry.
2240 source_pvo->pvo_pte.pte_hi &= ~PTE_HID;
2242 moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr);
2243 moea_pte_set(pt, &source_pvo->pvo_pte);
2245 PVO_PTEGIDX_CLR(victim_pvo);
2246 PVO_PTEGIDX_SET(source_pvo, i);
2247 moea_pte_replacements++;
2249 MOEA_PVO_CHECK(victim_pvo);
2250 MOEA_PVO_CHECK(source_pvo);
2252 mtx_unlock(&moea_table_mutex);
2257 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2262 mtx_assert(&moea_table_mutex, MA_OWNED);
2265 * First try primary hash.
2267 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2268 if ((pt->pte_hi & PTE_VALID) == 0) {
2269 pvo_pt->pte_hi &= ~PTE_HID;
2270 moea_pte_set(pt, pvo_pt);
2276 * Now try secondary hash.
2278 ptegidx ^= moea_pteg_mask;
2280 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2281 if ((pt->pte_hi & PTE_VALID) == 0) {
2282 pvo_pt->pte_hi |= PTE_HID;
2283 moea_pte_set(pt, pvo_pt);
2288 panic("moea_pte_insert: overflow");
2293 moea_query_bit(vm_page_t m, int ptebit)
2295 struct pvo_entry *pvo;
2299 if (moea_attr_fetch(m) & ptebit)
2303 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2304 MOEA_PVO_CHECK(pvo); /* sanity check */
2307 * See if we saved the bit off. If so, cache it and return
2310 if (pvo->pvo_pte.pte_lo & ptebit) {
2311 moea_attr_save(m, ptebit);
2312 MOEA_PVO_CHECK(pvo); /* sanity check */
2318 * No luck, now go through the hard part of looking at the PTEs
2319 * themselves. Sync so that any pending REF/CHG bits are flushed to
2323 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2324 MOEA_PVO_CHECK(pvo); /* sanity check */
2327 * See if this pvo has a valid PTE. if so, fetch the
2328 * REF/CHG bits from the valid PTE. If the appropriate
2329 * ptebit is set, cache it and return success.
2331 pt = moea_pvo_to_pte(pvo, -1);
2333 moea_pte_synch(pt, &pvo->pvo_pte);
2334 mtx_unlock(&moea_table_mutex);
2335 if (pvo->pvo_pte.pte_lo & ptebit) {
2336 moea_attr_save(m, ptebit);
2337 MOEA_PVO_CHECK(pvo); /* sanity check */
2347 moea_clear_bit(vm_page_t m, int ptebit, int *origbit)
2350 struct pvo_entry *pvo;
2355 * Clear the cached value.
2357 rv = moea_attr_fetch(m);
2358 moea_attr_clear(m, ptebit);
2361 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2362 * we can reset the right ones). note that since the pvo entries and
2363 * list heads are accessed via BAT0 and are never placed in the page
2364 * table, we don't have to worry about further accesses setting the
2370 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2371 * valid pte clear the ptebit from the valid pte.
2374 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2375 MOEA_PVO_CHECK(pvo); /* sanity check */
2376 pt = moea_pvo_to_pte(pvo, -1);
2378 moea_pte_synch(pt, &pvo->pvo_pte);
2379 if (pvo->pvo_pte.pte_lo & ptebit) {
2381 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2383 mtx_unlock(&moea_table_mutex);
2385 rv |= pvo->pvo_pte.pte_lo;
2386 pvo->pvo_pte.pte_lo &= ~ptebit;
2387 MOEA_PVO_CHECK(pvo); /* sanity check */
2390 if (origbit != NULL) {
2398 * Return true if the physical range is encompassed by the battable[idx]
2401 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2409 * Return immediately if not a valid mapping
2411 if (!battable[idx].batu & BAT_Vs)
2415 * The BAT entry must be cache-inhibited, guarded, and r/w
2416 * so it can function as an i/o page
2418 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2419 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2423 * The address should be within the BAT range. Assume that the
2424 * start address in the BAT has the correct alignment (thus
2425 * not requiring masking)
2427 start = battable[idx].batl & BAT_PBS;
2428 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2429 end = start | (bat_ble << 15) | 0x7fff;
2431 if ((pa < start) || ((pa + size) > end))
2438 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2443 * This currently does not work for entries that
2444 * overlap 256M BAT segments.
2447 for(i = 0; i < 16; i++)
2448 if (moea_bat_mapped(i, pa, size) == 0)
2455 * Map a set of physical memory pages into the kernel virtual
2456 * address space. Return a pointer to where it is mapped. This
2457 * routine is intended to be used for mapping device memory,
2461 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2463 vm_offset_t va, tmpva, ppa, offset;
2466 ppa = trunc_page(pa);
2467 offset = pa & PAGE_MASK;
2468 size = roundup(offset + size, PAGE_SIZE);
2473 * If the physical address lies within a valid BAT table entry,
2474 * return the 1:1 mapping. This currently doesn't work
2475 * for regions that overlap 256M BAT segments.
2477 for (i = 0; i < 16; i++) {
2478 if (moea_bat_mapped(i, pa, size) == 0)
2479 return ((void *) pa);
2482 va = kmem_alloc_nofault(kernel_map, size);
2484 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2486 for (tmpva = va; size > 0;) {
2487 moea_kenter(mmu, tmpva, ppa);
2488 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */
2494 return ((void *)(va + offset));
2498 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2500 vm_offset_t base, offset;
2503 * If this is outside kernel virtual space, then it's a
2504 * battable entry and doesn't require unmapping
2506 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2507 base = trunc_page(va);
2508 offset = va & PAGE_MASK;
2509 size = roundup(offset + size, PAGE_SIZE);
2510 kmem_free(kernel_map, base, size);