2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-4-Clause
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
33 * Copyright (C) 1995, 1996 TooLs GmbH.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. All advertising materials mentioning features or use of this software
45 * must display the following acknowledgement:
46 * This product includes software developed by TooLs GmbH.
47 * 4. The name of TooLs GmbH may not be used to endorse or promote products
48 * derived from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
53 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
55 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
56 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
57 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
58 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
59 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
64 * Copyright (C) 2001 Benno Rice.
65 * All rights reserved.
67 * Redistribution and use in source and binary forms, with or without
68 * modification, are permitted provided that the following conditions
70 * 1. Redistributions of source code must retain the above copyright
71 * notice, this list of conditions and the following disclaimer.
72 * 2. Redistributions in binary form must reproduce the above copyright
73 * notice, this list of conditions and the following disclaimer in the
74 * documentation and/or other materials provided with the distribution.
76 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
77 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
78 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
79 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
80 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
81 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
82 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
83 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
84 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
85 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is also stored by the
95 * logical address mapping module, this module may throw away valid virtual
96 * to physical mappings at almost any time. However, invalidations of
97 * mappings must be done as requested.
99 * In order to cope with hardware architectures which make virtual to
100 * physical map invalidates expensive, this module may delay invalidate
101 * reduced protection operations until such time as they are actually
102 * necessary. This module is given full information as to which processors
103 * are currently using which maps, and to when physical maps must be made
107 #include "opt_kstack_pages.h"
109 #include <sys/param.h>
110 #include <sys/kernel.h>
111 #include <sys/conf.h>
112 #include <sys/queue.h>
113 #include <sys/cpuset.h>
114 #include <sys/kerneldump.h>
116 #include <sys/lock.h>
117 #include <sys/msgbuf.h>
118 #include <sys/mutex.h>
119 #include <sys/proc.h>
120 #include <sys/rwlock.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
123 #include <sys/systm.h>
124 #include <sys/vmmeter.h>
126 #include <dev/ofw/openfirm.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
138 #include <machine/cpu.h>
139 #include <machine/platform.h>
140 #include <machine/bat.h>
141 #include <machine/frame.h>
142 #include <machine/md_var.h>
143 #include <machine/psl.h>
144 #include <machine/pte.h>
145 #include <machine/smp.h>
146 #include <machine/sr.h>
147 #include <machine/mmuvar.h>
148 #include <machine/trap.h>
154 #define TODO panic("%s: not implemented", __func__);
156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
157 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
167 extern unsigned char _etext[];
168 extern unsigned char _end[];
171 * Map of physical memory regions.
173 static struct mem_region *regions;
174 static struct mem_region *pregions;
175 static u_int phys_avail_count;
176 static int regions_sz, pregions_sz;
177 static struct ofw_map *translations;
180 * Lock for the pteg and pvo tables.
182 struct mtx moea_table_mutex;
183 struct mtx moea_vsid_mutex;
185 /* tlbie instruction synchronization */
186 static struct mtx tlbie_mtx;
191 static struct pteg *moea_pteg_table;
192 u_int moea_pteg_count;
193 u_int moea_pteg_mask;
198 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
199 struct pvo_head moea_pvo_kunmanaged =
200 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
202 static struct rwlock_padalign pvh_global_lock;
204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
207 #define BPVO_POOL_SIZE 32768
208 static struct pvo_entry *moea_bpvo_pool;
209 static int moea_bpvo_pool_index = 0;
211 #define VSID_NBPW (sizeof(u_int32_t) * 8)
212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
214 static boolean_t moea_initialized = FALSE;
219 u_int moea_pte_valid = 0;
220 u_int moea_pte_overflow = 0;
221 u_int moea_pte_replacements = 0;
222 u_int moea_pvo_entries = 0;
223 u_int moea_pvo_enter_calls = 0;
224 u_int moea_pvo_remove_calls = 0;
225 u_int moea_pte_spills = 0;
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
229 &moea_pte_overflow, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
231 &moea_pte_replacements, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
235 &moea_pvo_enter_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
237 &moea_pvo_remove_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
239 &moea_pte_spills, 0, "");
242 * Allocate physical memory for use in moea_bootstrap.
244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
249 static int moea_pte_insert(u_int, struct pte *);
254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
255 vm_offset_t, vm_paddr_t, u_int, int);
256 static void moea_pvo_remove(struct pvo_entry *, int);
257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
263 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
264 vm_prot_t, u_int, int8_t);
265 static void moea_syncicache(vm_paddr_t, vm_size_t);
266 static boolean_t moea_query_bit(vm_page_t, int);
267 static u_int moea_clear_bit(vm_page_t, int);
268 static void moea_kremove(mmu_t, vm_offset_t);
269 int moea_pte_spill(vm_offset_t);
272 * Kernel MMU interface
274 void moea_clear_modify(mmu_t, vm_page_t);
275 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
276 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
277 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
278 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int,
280 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
282 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
283 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
284 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
285 void moea_init(mmu_t);
286 boolean_t moea_is_modified(mmu_t, vm_page_t);
287 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
288 boolean_t moea_is_referenced(mmu_t, vm_page_t);
289 int moea_ts_referenced(mmu_t, vm_page_t);
290 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
291 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
292 void moea_page_init(mmu_t, vm_page_t);
293 int moea_page_wired_mappings(mmu_t, vm_page_t);
294 void moea_pinit(mmu_t, pmap_t);
295 void moea_pinit0(mmu_t, pmap_t);
296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
298 void moea_qremove(mmu_t, vm_offset_t, int);
299 void moea_release(mmu_t, pmap_t);
300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_remove_all(mmu_t, vm_page_t);
302 void moea_remove_write(mmu_t, vm_page_t);
303 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
304 void moea_zero_page(mmu_t, vm_page_t);
305 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
306 void moea_activate(mmu_t, struct thread *);
307 void moea_deactivate(mmu_t, struct thread *);
308 void moea_cpu_bootstrap(mmu_t, int);
309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
310 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
311 void *moea_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
313 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
315 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
317 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
319 void moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va);
320 void moea_scan_init(mmu_t mmu);
321 vm_offset_t moea_quick_enter_page(mmu_t mmu, vm_page_t m);
322 void moea_quick_remove_page(mmu_t mmu, vm_offset_t addr);
324 static mmu_method_t moea_methods[] = {
325 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
326 MMUMETHOD(mmu_copy_page, moea_copy_page),
327 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
328 MMUMETHOD(mmu_enter, moea_enter),
329 MMUMETHOD(mmu_enter_object, moea_enter_object),
330 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
331 MMUMETHOD(mmu_extract, moea_extract),
332 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
333 MMUMETHOD(mmu_init, moea_init),
334 MMUMETHOD(mmu_is_modified, moea_is_modified),
335 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
336 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
337 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
338 MMUMETHOD(mmu_map, moea_map),
339 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
340 MMUMETHOD(mmu_page_init, moea_page_init),
341 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
342 MMUMETHOD(mmu_pinit, moea_pinit),
343 MMUMETHOD(mmu_pinit0, moea_pinit0),
344 MMUMETHOD(mmu_protect, moea_protect),
345 MMUMETHOD(mmu_qenter, moea_qenter),
346 MMUMETHOD(mmu_qremove, moea_qremove),
347 MMUMETHOD(mmu_release, moea_release),
348 MMUMETHOD(mmu_remove, moea_remove),
349 MMUMETHOD(mmu_remove_all, moea_remove_all),
350 MMUMETHOD(mmu_remove_write, moea_remove_write),
351 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
352 MMUMETHOD(mmu_unwire, moea_unwire),
353 MMUMETHOD(mmu_zero_page, moea_zero_page),
354 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
355 MMUMETHOD(mmu_activate, moea_activate),
356 MMUMETHOD(mmu_deactivate, moea_deactivate),
357 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
358 MMUMETHOD(mmu_quick_enter_page, moea_quick_enter_page),
359 MMUMETHOD(mmu_quick_remove_page, moea_quick_remove_page),
361 /* Internal interfaces */
362 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
363 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
364 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
365 MMUMETHOD(mmu_mapdev, moea_mapdev),
366 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
367 MMUMETHOD(mmu_kextract, moea_kextract),
368 MMUMETHOD(mmu_kenter, moea_kenter),
369 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
370 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
371 MMUMETHOD(mmu_scan_init, moea_scan_init),
372 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
377 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
379 static __inline uint32_t
380 moea_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
385 if (ma != VM_MEMATTR_DEFAULT) {
387 case VM_MEMATTR_UNCACHEABLE:
388 return (PTE_I | PTE_G);
389 case VM_MEMATTR_CACHEABLE:
391 case VM_MEMATTR_WRITE_COMBINING:
392 case VM_MEMATTR_WRITE_BACK:
393 case VM_MEMATTR_PREFETCHABLE:
395 case VM_MEMATTR_WRITE_THROUGH:
396 return (PTE_W | PTE_M);
401 * Assume the page is cache inhibited and access is guarded unless
402 * it's in our available memory array.
404 pte_lo = PTE_I | PTE_G;
405 for (i = 0; i < pregions_sz; i++) {
406 if ((pa >= pregions[i].mr_start) &&
407 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
417 tlbie(vm_offset_t va)
420 mtx_lock_spin(&tlbie_mtx);
421 __asm __volatile("ptesync");
422 __asm __volatile("tlbie %0" :: "r"(va));
423 __asm __volatile("eieio; tlbsync; ptesync");
424 mtx_unlock_spin(&tlbie_mtx);
432 for (va = 0; va < 0x00040000; va += 0x00001000) {
433 __asm __volatile("tlbie %0" :: "r"(va));
436 __asm __volatile("tlbsync");
441 va_to_sr(u_int *sr, vm_offset_t va)
443 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
446 static __inline u_int
447 va_to_pteg(u_int sr, vm_offset_t addr)
451 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
453 return (hash & moea_pteg_mask);
456 static __inline struct pvo_head *
457 vm_page_to_pvoh(vm_page_t m)
460 return (&m->md.mdpg_pvoh);
464 moea_attr_clear(vm_page_t m, int ptebit)
467 rw_assert(&pvh_global_lock, RA_WLOCKED);
468 m->md.mdpg_attrs &= ~ptebit;
472 moea_attr_fetch(vm_page_t m)
475 return (m->md.mdpg_attrs);
479 moea_attr_save(vm_page_t m, int ptebit)
482 rw_assert(&pvh_global_lock, RA_WLOCKED);
483 m->md.mdpg_attrs |= ptebit;
487 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
489 if (pt->pte_hi == pvo_pt->pte_hi)
496 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
498 return (pt->pte_hi & ~PTE_VALID) ==
499 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
500 ((va >> ADDR_API_SHFT) & PTE_API) | which);
504 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
507 mtx_assert(&moea_table_mutex, MA_OWNED);
510 * Construct a PTE. Default to IMB initially. Valid bit only gets
511 * set when the real pte is set in memory.
513 * Note: Don't set the valid bit for correct operation of tlb update.
515 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
516 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
521 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
524 mtx_assert(&moea_table_mutex, MA_OWNED);
525 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
529 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
532 mtx_assert(&moea_table_mutex, MA_OWNED);
535 * As shown in Section 7.6.3.2.3
537 pt->pte_lo &= ~ptebit;
542 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
545 mtx_assert(&moea_table_mutex, MA_OWNED);
546 pvo_pt->pte_hi |= PTE_VALID;
549 * Update the PTE as defined in section 7.6.3.1.
550 * Note that the REF/CHG bits are from pvo_pt and thus should have
551 * been saved so this routine can restore them (if desired).
553 pt->pte_lo = pvo_pt->pte_lo;
555 pt->pte_hi = pvo_pt->pte_hi;
561 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
564 mtx_assert(&moea_table_mutex, MA_OWNED);
565 pvo_pt->pte_hi &= ~PTE_VALID;
568 * Force the reg & chg bits back into the PTEs.
573 * Invalidate the pte.
575 pt->pte_hi &= ~PTE_VALID;
580 * Save the reg & chg bits.
582 moea_pte_synch(pt, pvo_pt);
587 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
593 moea_pte_unset(pt, pvo_pt, va);
594 moea_pte_set(pt, pvo_pt);
598 * Quick sort callout for comparing memory regions.
600 static int om_cmp(const void *a, const void *b);
603 om_cmp(const void *a, const void *b)
605 const struct ofw_map *mapa;
606 const struct ofw_map *mapb;
610 if (mapa->om_pa < mapb->om_pa)
612 else if (mapa->om_pa > mapb->om_pa)
619 moea_cpu_bootstrap(mmu_t mmup, int ap)
626 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
627 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
629 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
630 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
634 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
635 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
638 __asm __volatile("mtibatu 1,%0" :: "r"(0));
639 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
640 __asm __volatile("mtibatu 2,%0" :: "r"(0));
641 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
642 __asm __volatile("mtibatu 3,%0" :: "r"(0));
645 for (i = 0; i < 16; i++)
646 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
649 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
650 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
657 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
660 phandle_t chosen, mmu;
663 vm_size_t size, physsz, hwphyssz;
664 vm_offset_t pa, va, off;
669 * Set up BAT0 to map the lowest 256 MB area
671 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
672 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
675 * Map PCI memory space.
677 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
678 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
680 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
681 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
683 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
684 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
686 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
687 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
692 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
693 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
696 * Use an IBAT and a DBAT to map the bottom segment of memory
697 * where we are. Turn off instruction relocation temporarily
698 * to prevent faults while reprogramming the IBAT.
701 mtmsr(msr & ~PSL_IR);
702 __asm (".balign 32; \n"
703 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
704 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
705 :: "r"(battable[0].batu), "r"(battable[0].batl));
709 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
710 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
713 /* set global direct map flag */
716 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
717 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
719 for (i = 0; i < pregions_sz; i++) {
723 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
724 pregions[i].mr_start,
725 pregions[i].mr_start + pregions[i].mr_size,
726 pregions[i].mr_size);
728 * Install entries into the BAT table to allow all
729 * of physmem to be convered by on-demand BAT entries.
730 * The loop will sometimes set the same battable element
731 * twice, but that's fine since they won't be used for
734 pa = pregions[i].mr_start & 0xf0000000;
735 end = pregions[i].mr_start + pregions[i].mr_size;
737 u_int n = pa >> ADDR_SR_SHFT;
739 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
740 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
741 pa += SEGMENT_LENGTH;
745 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
746 panic("moea_bootstrap: phys_avail too small");
748 phys_avail_count = 0;
751 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
752 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
753 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
754 regions[i].mr_start + regions[i].mr_size,
757 (physsz + regions[i].mr_size) >= hwphyssz) {
758 if (physsz < hwphyssz) {
759 phys_avail[j] = regions[i].mr_start;
760 phys_avail[j + 1] = regions[i].mr_start +
767 phys_avail[j] = regions[i].mr_start;
768 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
770 physsz += regions[i].mr_size;
773 /* Check for overlap with the kernel and exception vectors */
774 for (j = 0; j < 2*phys_avail_count; j+=2) {
775 if (phys_avail[j] < EXC_LAST)
776 phys_avail[j] += EXC_LAST;
778 if (kernelstart >= phys_avail[j] &&
779 kernelstart < phys_avail[j+1]) {
780 if (kernelend < phys_avail[j+1]) {
781 phys_avail[2*phys_avail_count] =
782 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
783 phys_avail[2*phys_avail_count + 1] =
788 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
791 if (kernelend >= phys_avail[j] &&
792 kernelend < phys_avail[j+1]) {
793 if (kernelstart > phys_avail[j]) {
794 phys_avail[2*phys_avail_count] = phys_avail[j];
795 phys_avail[2*phys_avail_count + 1] =
796 kernelstart & ~PAGE_MASK;
800 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
804 physmem = btoc(physsz);
807 * Allocate PTEG table.
810 moea_pteg_count = PTEGCOUNT;
812 moea_pteg_count = 0x1000;
814 while (moea_pteg_count < physmem)
815 moea_pteg_count <<= 1;
817 moea_pteg_count >>= 1;
818 #endif /* PTEGCOUNT */
820 size = moea_pteg_count * sizeof(struct pteg);
821 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
823 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
824 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
825 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
826 moea_pteg_mask = moea_pteg_count - 1;
829 * Allocate pv/overflow lists.
831 size = sizeof(struct pvo_head) * moea_pteg_count;
832 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
834 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
835 for (i = 0; i < moea_pteg_count; i++)
836 LIST_INIT(&moea_pvo_table[i]);
839 * Initialize the lock that synchronizes access to the pteg and pvo
842 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
844 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
846 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
849 * Initialise the unmanaged pvo pool.
851 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
852 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
853 moea_bpvo_pool_index = 0;
856 * Make sure kernel vsid is allocated as well as VSID 0.
858 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
859 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
860 moea_vsid_bitmap[0] |= 1;
863 * Initialize the kernel pmap (which is statically allocated).
865 PMAP_LOCK_INIT(kernel_pmap);
866 for (i = 0; i < 16; i++)
867 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
868 CPU_FILL(&kernel_pmap->pm_active);
869 RB_INIT(&kernel_pmap->pmap_pvo);
872 * Initialize the global pv list lock.
874 rw_init(&pvh_global_lock, "pmap pv global");
877 * Set up the Open Firmware mappings
879 chosen = OF_finddevice("/chosen");
880 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
881 (mmu = OF_instance_to_package(mmui)) != -1 &&
882 (sz = OF_getproplen(mmu, "translations")) != -1) {
884 for (i = 0; phys_avail[i] != 0; i += 2) {
885 if (phys_avail[i + 1] >= sz) {
886 translations = (struct ofw_map *)phys_avail[i];
890 if (translations == NULL)
891 panic("moea_bootstrap: no space to copy translations");
892 bzero(translations, sz);
893 if (OF_getprop(mmu, "translations", translations, sz) == -1)
894 panic("moea_bootstrap: can't get ofw translations");
895 CTR0(KTR_PMAP, "moea_bootstrap: translations");
896 sz /= sizeof(*translations);
897 qsort(translations, sz, sizeof (*translations), om_cmp);
898 for (i = 0; i < sz; i++) {
899 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
900 translations[i].om_pa, translations[i].om_va,
901 translations[i].om_len);
904 * If the mapping is 1:1, let the RAM and device
905 * on-demand BAT tables take care of the translation.
907 if (translations[i].om_va == translations[i].om_pa)
910 /* Enter the pages */
911 for (off = 0; off < translations[i].om_len;
913 moea_kenter(mmup, translations[i].om_va + off,
914 translations[i].om_pa + off);
919 * Calculate the last available physical address.
921 for (i = 0; phys_avail[i + 2] != 0; i += 2)
923 Maxmem = powerpc_btop(phys_avail[i + 1]);
925 moea_cpu_bootstrap(mmup,0);
926 mtmsr(mfmsr() | PSL_DR | PSL_IR);
930 * Set the start and end of kva.
932 virtual_avail = VM_MIN_KERNEL_ADDRESS;
933 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
936 * Allocate a kernel stack with a guard page for thread0 and map it
937 * into the kernel page map.
939 pa = moea_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
940 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
941 virtual_avail = va + kstack_pages * PAGE_SIZE;
942 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
943 thread0.td_kstack = va;
944 thread0.td_kstack_pages = kstack_pages;
945 for (i = 0; i < kstack_pages; i++) {
946 moea_kenter(mmup, va, pa);
952 * Allocate virtual address space for the message buffer.
954 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
955 msgbufp = (struct msgbuf *)virtual_avail;
957 virtual_avail += round_page(msgbufsize);
958 while (va < virtual_avail) {
959 moea_kenter(mmup, va, pa);
965 * Allocate virtual address space for the dynamic percpu area.
967 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
968 dpcpu = (void *)virtual_avail;
970 virtual_avail += DPCPU_SIZE;
971 while (va < virtual_avail) {
972 moea_kenter(mmup, va, pa);
976 dpcpu_init(dpcpu, 0);
980 * Activate a user pmap. The pmap must be activated before it's address
981 * space can be accessed in any way.
984 moea_activate(mmu_t mmu, struct thread *td)
989 * Load all the data we need up front to encourage the compiler to
990 * not issue any loads while we have interrupts disabled below.
992 pm = &td->td_proc->p_vmspace->vm_pmap;
995 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
996 PCPU_SET(curpmap, pmr);
998 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1002 moea_deactivate(mmu_t mmu, struct thread *td)
1006 pm = &td->td_proc->p_vmspace->vm_pmap;
1007 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1008 PCPU_SET(curpmap, NULL);
1012 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1014 struct pvo_entry key, *pvo;
1017 key.pvo_vaddr = sva;
1018 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1019 pvo != NULL && PVO_VADDR(pvo) < eva;
1020 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1021 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1022 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo);
1023 pvo->pvo_vaddr &= ~PVO_WIRED;
1024 pm->pm_stats.wired_count--;
1030 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1035 dst = VM_PAGE_TO_PHYS(mdst);
1036 src = VM_PAGE_TO_PHYS(msrc);
1038 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1042 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1043 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1046 vm_offset_t a_pg_offset, b_pg_offset;
1049 while (xfersize > 0) {
1050 a_pg_offset = a_offset & PAGE_MASK;
1051 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1052 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1054 b_pg_offset = b_offset & PAGE_MASK;
1055 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1056 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1058 bcopy(a_cp, b_cp, cnt);
1066 * Zero a page of physical memory by temporarily mapping it into the tlb.
1069 moea_zero_page(mmu_t mmu, vm_page_t m)
1071 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1073 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1074 __asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1078 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1080 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1081 void *va = (void *)(pa + off);
1087 moea_quick_enter_page(mmu_t mmu, vm_page_t m)
1090 return (VM_PAGE_TO_PHYS(m));
1094 moea_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1099 * Map the given physical page at the specified virtual address in the
1100 * target pmap with the protection requested. If specified the page
1101 * will be wired down.
1104 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1105 u_int flags, int8_t psind)
1110 rw_wlock(&pvh_global_lock);
1112 error = moea_enter_locked(pmap, va, m, prot, flags, psind);
1113 rw_wunlock(&pvh_global_lock);
1115 if (error != ENOMEM)
1116 return (KERN_SUCCESS);
1117 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1118 return (KERN_RESOURCE_SHORTAGE);
1119 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1125 * Map the given physical page at the specified virtual address in the
1126 * target pmap with the protection requested. If specified the page
1127 * will be wired down.
1129 * The global pvh and pmap must be locked.
1132 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1133 u_int flags, int8_t psind __unused)
1135 struct pvo_head *pvo_head;
1137 u_int pte_lo, pvo_flags;
1140 if (pmap_bootstrapped)
1141 rw_assert(&pvh_global_lock, RA_WLOCKED);
1142 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1143 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1144 VM_OBJECT_ASSERT_LOCKED(m->object);
1146 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea_initialized) {
1147 pvo_head = &moea_pvo_kunmanaged;
1148 zone = moea_upvo_zone;
1151 pvo_head = vm_page_to_pvoh(m);
1152 zone = moea_mpvo_zone;
1153 pvo_flags = PVO_MANAGED;
1156 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1158 if (prot & VM_PROT_WRITE) {
1160 if (pmap_bootstrapped &&
1161 (m->oflags & VPO_UNMANAGED) == 0)
1162 vm_page_aflag_set(m, PGA_WRITEABLE);
1166 if ((flags & PMAP_ENTER_WIRED) != 0)
1167 pvo_flags |= PVO_WIRED;
1169 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1173 * Flush the real page from the instruction cache. This has be done
1174 * for all user mappings to prevent information leakage via the
1175 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1176 * mapping for a page.
1178 if (pmap != kernel_pmap && error == ENOENT &&
1179 (pte_lo & (PTE_I | PTE_G)) == 0)
1180 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1186 * Maps a sequence of resident pages belonging to the same object.
1187 * The sequence begins with the given page m_start. This page is
1188 * mapped at the given virtual address start. Each subsequent page is
1189 * mapped at a virtual address that is offset from start by the same
1190 * amount as the page is offset from m_start within the object. The
1191 * last page in the sequence is the page with the largest offset from
1192 * m_start that can be mapped at a virtual address less than the given
1193 * virtual address end. Not every virtual page between start and end
1194 * is mapped; only those for which a resident page exists with the
1195 * corresponding offset from m_start are mapped.
1198 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1199 vm_page_t m_start, vm_prot_t prot)
1202 vm_pindex_t diff, psize;
1204 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1206 psize = atop(end - start);
1208 rw_wlock(&pvh_global_lock);
1210 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1211 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1212 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1213 m = TAILQ_NEXT(m, listq);
1215 rw_wunlock(&pvh_global_lock);
1220 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1224 rw_wlock(&pvh_global_lock);
1226 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1228 rw_wunlock(&pvh_global_lock);
1233 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1235 struct pvo_entry *pvo;
1239 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1243 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1249 * Atomically extract and hold the physical page with the given
1250 * pmap and virtual address pair if that mapping permits the given
1254 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1256 struct pvo_entry *pvo;
1264 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1265 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1266 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1267 (prot & VM_PROT_WRITE) == 0)) {
1268 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1270 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1279 moea_init(mmu_t mmu)
1282 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1283 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1284 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1285 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1286 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1287 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1288 moea_initialized = TRUE;
1292 moea_is_referenced(mmu_t mmu, vm_page_t m)
1296 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1297 ("moea_is_referenced: page %p is not managed", m));
1298 rw_wlock(&pvh_global_lock);
1299 rv = moea_query_bit(m, PTE_REF);
1300 rw_wunlock(&pvh_global_lock);
1305 moea_is_modified(mmu_t mmu, vm_page_t m)
1309 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1310 ("moea_is_modified: page %p is not managed", m));
1313 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1314 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1315 * is clear, no PTEs can have PTE_CHG set.
1317 VM_OBJECT_ASSERT_WLOCKED(m->object);
1318 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1320 rw_wlock(&pvh_global_lock);
1321 rv = moea_query_bit(m, PTE_CHG);
1322 rw_wunlock(&pvh_global_lock);
1327 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1329 struct pvo_entry *pvo;
1333 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1334 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1340 moea_clear_modify(mmu_t mmu, vm_page_t m)
1343 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1344 ("moea_clear_modify: page %p is not managed", m));
1345 VM_OBJECT_ASSERT_WLOCKED(m->object);
1346 KASSERT(!vm_page_xbusied(m),
1347 ("moea_clear_modify: page %p is exclusive busy", m));
1350 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1351 * set. If the object containing the page is locked and the page is
1352 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1354 if ((m->aflags & PGA_WRITEABLE) == 0)
1356 rw_wlock(&pvh_global_lock);
1357 moea_clear_bit(m, PTE_CHG);
1358 rw_wunlock(&pvh_global_lock);
1362 * Clear the write and modified bits in each of the given page's mappings.
1365 moea_remove_write(mmu_t mmu, vm_page_t m)
1367 struct pvo_entry *pvo;
1372 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1373 ("moea_remove_write: page %p is not managed", m));
1376 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1377 * set by another thread while the object is locked. Thus,
1378 * if PGA_WRITEABLE is clear, no page table entries need updating.
1380 VM_OBJECT_ASSERT_WLOCKED(m->object);
1381 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1383 rw_wlock(&pvh_global_lock);
1384 lo = moea_attr_fetch(m);
1386 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1387 pmap = pvo->pvo_pmap;
1389 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1390 pt = moea_pvo_to_pte(pvo, -1);
1391 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1392 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1394 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1395 lo |= pvo->pvo_pte.pte.pte_lo;
1396 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1397 moea_pte_change(pt, &pvo->pvo_pte.pte,
1399 mtx_unlock(&moea_table_mutex);
1404 if ((lo & PTE_CHG) != 0) {
1405 moea_attr_clear(m, PTE_CHG);
1408 vm_page_aflag_clear(m, PGA_WRITEABLE);
1409 rw_wunlock(&pvh_global_lock);
1413 * moea_ts_referenced:
1415 * Return a count of reference bits for a page, clearing those bits.
1416 * It is not necessary for every reference bit to be cleared, but it
1417 * is necessary that 0 only be returned when there are truly no
1418 * reference bits set.
1420 * XXX: The exact number of bits to check and clear is a matter that
1421 * should be tested and standardized at some point in the future for
1422 * optimal aging of shared pages.
1425 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1429 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1430 ("moea_ts_referenced: page %p is not managed", m));
1431 rw_wlock(&pvh_global_lock);
1432 count = moea_clear_bit(m, PTE_REF);
1433 rw_wunlock(&pvh_global_lock);
1438 * Modify the WIMG settings of all mappings for a page.
1441 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1443 struct pvo_entry *pvo;
1444 struct pvo_head *pvo_head;
1449 if ((m->oflags & VPO_UNMANAGED) != 0) {
1450 m->md.mdpg_cache_attrs = ma;
1454 rw_wlock(&pvh_global_lock);
1455 pvo_head = vm_page_to_pvoh(m);
1456 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1458 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1459 pmap = pvo->pvo_pmap;
1461 pt = moea_pvo_to_pte(pvo, -1);
1462 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1463 pvo->pvo_pte.pte.pte_lo |= lo;
1465 moea_pte_change(pt, &pvo->pvo_pte.pte,
1467 if (pvo->pvo_pmap == kernel_pmap)
1470 mtx_unlock(&moea_table_mutex);
1473 m->md.mdpg_cache_attrs = ma;
1474 rw_wunlock(&pvh_global_lock);
1478 * Map a wired page into kernel virtual address space.
1481 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1484 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1488 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1494 if (va < VM_MIN_KERNEL_ADDRESS)
1495 panic("moea_kenter: attempt to enter non-kernel address %#x",
1499 pte_lo = moea_calc_wimg(pa, ma);
1501 PMAP_LOCK(kernel_pmap);
1502 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1503 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1505 if (error != 0 && error != ENOENT)
1506 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1509 PMAP_UNLOCK(kernel_pmap);
1513 * Extract the physical page address associated with the given kernel virtual
1517 moea_kextract(mmu_t mmu, vm_offset_t va)
1519 struct pvo_entry *pvo;
1523 * Allow direct mappings on 32-bit OEA
1525 if (va < VM_MIN_KERNEL_ADDRESS) {
1529 PMAP_LOCK(kernel_pmap);
1530 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1531 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1532 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1533 PMAP_UNLOCK(kernel_pmap);
1538 * Remove a wired page from kernel virtual address space.
1541 moea_kremove(mmu_t mmu, vm_offset_t va)
1544 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1548 * Map a range of physical addresses into kernel virtual address space.
1550 * The value passed in *virt is a suggested virtual address for the mapping.
1551 * Architectures which can support a direct-mapped physical to virtual region
1552 * can return the appropriate address within that region, leaving '*virt'
1553 * unchanged. We cannot and therefore do not; *virt is updated with the
1554 * first usable address after the mapped region.
1557 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1558 vm_paddr_t pa_end, int prot)
1560 vm_offset_t sva, va;
1564 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1565 moea_kenter(mmu, va, pa_start);
1571 * Returns true if the pmap's pv is one of the first
1572 * 16 pvs linked to from this page. This count may
1573 * be changed upwards or downwards in the future; it
1574 * is only necessary that true be returned for a small
1575 * subset of pmaps for proper page aging.
1578 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1581 struct pvo_entry *pvo;
1584 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1585 ("moea_page_exists_quick: page %p is not managed", m));
1588 rw_wlock(&pvh_global_lock);
1589 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1590 if (pvo->pvo_pmap == pmap) {
1597 rw_wunlock(&pvh_global_lock);
1602 moea_page_init(mmu_t mmu __unused, vm_page_t m)
1605 m->md.mdpg_attrs = 0;
1606 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
1607 LIST_INIT(&m->md.mdpg_pvoh);
1611 * Return the number of managed mappings to the given physical page
1615 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1617 struct pvo_entry *pvo;
1621 if ((m->oflags & VPO_UNMANAGED) != 0)
1623 rw_wlock(&pvh_global_lock);
1624 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1625 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1627 rw_wunlock(&pvh_global_lock);
1631 static u_int moea_vsidcontext;
1634 moea_pinit(mmu_t mmu, pmap_t pmap)
1639 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1640 RB_INIT(&pmap->pmap_pvo);
1643 __asm __volatile("mftb %0" : "=r"(entropy));
1645 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1647 pmap->pmap_phys = pmap;
1651 mtx_lock(&moea_vsid_mutex);
1653 * Allocate some segment registers for this pmap.
1655 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1659 * Create a new value by mutiplying by a prime and adding in
1660 * entropy from the timebase register. This is to make the
1661 * VSID more random so that the PT hash function collides
1662 * less often. (Note that the prime casues gcc to do shifts
1663 * instead of a multiply.)
1665 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1666 hash = moea_vsidcontext & (NPMAPS - 1);
1667 if (hash == 0) /* 0 is special, avoid it */
1670 mask = 1 << (hash & (VSID_NBPW - 1));
1671 hash = (moea_vsidcontext & 0xfffff);
1672 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1673 /* anything free in this bucket? */
1674 if (moea_vsid_bitmap[n] == 0xffffffff) {
1675 entropy = (moea_vsidcontext >> 20);
1678 i = ffs(~moea_vsid_bitmap[n]) - 1;
1680 hash &= rounddown2(0xfffff, VSID_NBPW);
1683 KASSERT(!(moea_vsid_bitmap[n] & mask),
1684 ("Allocating in-use VSID group %#x\n", hash));
1685 moea_vsid_bitmap[n] |= mask;
1686 for (i = 0; i < 16; i++)
1687 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1688 mtx_unlock(&moea_vsid_mutex);
1692 mtx_unlock(&moea_vsid_mutex);
1693 panic("moea_pinit: out of segments");
1697 * Initialize the pmap associated with process 0.
1700 moea_pinit0(mmu_t mmu, pmap_t pm)
1704 moea_pinit(mmu, pm);
1705 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1709 * Set the physical protection on the specified range of this map as requested.
1712 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1715 struct pvo_entry *pvo, *tpvo, key;
1718 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1719 ("moea_protect: non current pmap"));
1721 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1722 moea_remove(mmu, pm, sva, eva);
1726 rw_wlock(&pvh_global_lock);
1728 key.pvo_vaddr = sva;
1729 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1730 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1731 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1734 * Grab the PTE pointer before we diddle with the cached PTE
1737 pt = moea_pvo_to_pte(pvo, -1);
1739 * Change the protection of the page.
1741 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1742 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1745 * If the PVO is in the page table, update that pte as well.
1748 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1749 mtx_unlock(&moea_table_mutex);
1752 rw_wunlock(&pvh_global_lock);
1757 * Map a list of wired pages into kernel virtual address space. This is
1758 * intended for temporary mappings which do not need page modification or
1759 * references recorded. Existing mappings in the region are overwritten.
1762 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1767 while (count-- > 0) {
1768 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1775 * Remove page mappings from kernel virtual address space. Intended for
1776 * temporary mappings entered by moea_qenter.
1779 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1784 while (count-- > 0) {
1785 moea_kremove(mmu, va);
1791 moea_release(mmu_t mmu, pmap_t pmap)
1796 * Free segment register's VSID
1798 if (pmap->pm_sr[0] == 0)
1799 panic("moea_release");
1801 mtx_lock(&moea_vsid_mutex);
1802 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1803 mask = 1 << (idx % VSID_NBPW);
1805 moea_vsid_bitmap[idx] &= ~mask;
1806 mtx_unlock(&moea_vsid_mutex);
1810 * Remove the given range of addresses from the specified map.
1813 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1815 struct pvo_entry *pvo, *tpvo, key;
1817 rw_wlock(&pvh_global_lock);
1819 key.pvo_vaddr = sva;
1820 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1821 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1822 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1823 moea_pvo_remove(pvo, -1);
1826 rw_wunlock(&pvh_global_lock);
1830 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1831 * will reflect changes in pte's back to the vm_page.
1834 moea_remove_all(mmu_t mmu, vm_page_t m)
1836 struct pvo_head *pvo_head;
1837 struct pvo_entry *pvo, *next_pvo;
1840 rw_wlock(&pvh_global_lock);
1841 pvo_head = vm_page_to_pvoh(m);
1842 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1843 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1845 pmap = pvo->pvo_pmap;
1847 moea_pvo_remove(pvo, -1);
1850 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1851 moea_attr_clear(m, PTE_CHG);
1854 vm_page_aflag_clear(m, PGA_WRITEABLE);
1855 rw_wunlock(&pvh_global_lock);
1859 * Allocate a physical page of memory directly from the phys_avail map.
1860 * Can only be called from moea_bootstrap before avail start and end are
1864 moea_bootstrap_alloc(vm_size_t size, u_int align)
1869 size = round_page(size);
1870 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1872 s = roundup2(phys_avail[i], align);
1877 if (s < phys_avail[i] || e > phys_avail[i + 1])
1880 if (s == phys_avail[i]) {
1881 phys_avail[i] += size;
1882 } else if (e == phys_avail[i + 1]) {
1883 phys_avail[i + 1] -= size;
1885 for (j = phys_avail_count * 2; j > i; j -= 2) {
1886 phys_avail[j] = phys_avail[j - 2];
1887 phys_avail[j + 1] = phys_avail[j - 1];
1890 phys_avail[i + 3] = phys_avail[i + 1];
1891 phys_avail[i + 1] = s;
1892 phys_avail[i + 2] = e;
1898 panic("moea_bootstrap_alloc: could not allocate memory");
1902 moea_syncicache(vm_paddr_t pa, vm_size_t len)
1904 __syncicache((void *)pa, len);
1908 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1909 vm_offset_t va, vm_paddr_t pa, u_int pte_lo, int flags)
1911 struct pvo_entry *pvo;
1918 moea_pvo_enter_calls++;
1923 * Compute the PTE Group index.
1926 sr = va_to_sr(pm->pm_sr, va);
1927 ptegidx = va_to_pteg(sr, va);
1930 * Remove any existing mapping for this page. Reuse the pvo entry if
1931 * there is a mapping.
1933 mtx_lock(&moea_table_mutex);
1934 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1935 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1936 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1937 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1938 (pte_lo & PTE_PP)) {
1940 * The PTE is not changing. Instead, this may
1941 * be a request to change the mapping's wired
1944 mtx_unlock(&moea_table_mutex);
1945 if ((flags & PVO_WIRED) != 0 &&
1946 (pvo->pvo_vaddr & PVO_WIRED) == 0) {
1947 pvo->pvo_vaddr |= PVO_WIRED;
1948 pm->pm_stats.wired_count++;
1949 } else if ((flags & PVO_WIRED) == 0 &&
1950 (pvo->pvo_vaddr & PVO_WIRED) != 0) {
1951 pvo->pvo_vaddr &= ~PVO_WIRED;
1952 pm->pm_stats.wired_count--;
1956 moea_pvo_remove(pvo, -1);
1962 * If we aren't overwriting a mapping, try to allocate.
1964 if (moea_initialized) {
1965 pvo = uma_zalloc(zone, M_NOWAIT);
1967 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1968 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1969 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1970 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1972 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1973 moea_bpvo_pool_index++;
1978 mtx_unlock(&moea_table_mutex);
1983 pvo->pvo_vaddr = va;
1985 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1986 pvo->pvo_vaddr &= ~ADDR_POFF;
1987 if (flags & PVO_WIRED)
1988 pvo->pvo_vaddr |= PVO_WIRED;
1989 if (pvo_head != &moea_pvo_kunmanaged)
1990 pvo->pvo_vaddr |= PVO_MANAGED;
1992 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1994 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1999 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2002 * Remember if the list was empty and therefore will be the first
2005 if (LIST_FIRST(pvo_head) == NULL)
2007 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2009 if (pvo->pvo_vaddr & PVO_WIRED)
2010 pm->pm_stats.wired_count++;
2011 pm->pm_stats.resident_count++;
2013 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2014 KASSERT(i < 8, ("Invalid PTE index"));
2016 PVO_PTEGIDX_SET(pvo, i);
2018 panic("moea_pvo_enter: overflow");
2019 moea_pte_overflow++;
2021 mtx_unlock(&moea_table_mutex);
2023 return (first ? ENOENT : 0);
2027 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2032 * If there is an active pte entry, we need to deactivate it (and
2033 * save the ref & cfg bits).
2035 pt = moea_pvo_to_pte(pvo, pteidx);
2037 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2038 mtx_unlock(&moea_table_mutex);
2039 PVO_PTEGIDX_CLR(pvo);
2041 moea_pte_overflow--;
2045 * Update our statistics.
2047 pvo->pvo_pmap->pm_stats.resident_count--;
2048 if (pvo->pvo_vaddr & PVO_WIRED)
2049 pvo->pvo_pmap->pm_stats.wired_count--;
2052 * Save the REF/CHG bits into their cache if the page is managed.
2054 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2057 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2059 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2060 (PTE_REF | PTE_CHG));
2065 * Remove this PVO from the PV and pmap lists.
2067 LIST_REMOVE(pvo, pvo_vlink);
2068 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2071 * Remove this from the overflow list and return it to the pool
2072 * if we aren't going to reuse it.
2074 LIST_REMOVE(pvo, pvo_olink);
2075 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2076 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2077 moea_upvo_zone, pvo);
2079 moea_pvo_remove_calls++;
2083 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2088 * We can find the actual pte entry without searching by grabbing
2089 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2090 * noticing the HID bit.
2092 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2093 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2094 pteidx ^= moea_pteg_mask * 8;
2099 static struct pvo_entry *
2100 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2102 struct pvo_entry *pvo;
2107 sr = va_to_sr(pm->pm_sr, va);
2108 ptegidx = va_to_pteg(sr, va);
2110 mtx_lock(&moea_table_mutex);
2111 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2112 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2114 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2118 mtx_unlock(&moea_table_mutex);
2124 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2129 * If we haven't been supplied the ptegidx, calculate it.
2135 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2136 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2137 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2140 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2141 mtx_lock(&moea_table_mutex);
2143 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2144 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2145 "valid pte index", pvo);
2148 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2149 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2150 "pvo but no valid pte", pvo);
2153 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2154 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2155 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2156 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2159 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2161 panic("moea_pvo_to_pte: pvo %p pte does not match "
2162 "pte %p in moea_pteg_table", pvo, pt);
2165 mtx_assert(&moea_table_mutex, MA_OWNED);
2169 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2170 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2171 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2174 mtx_unlock(&moea_table_mutex);
2179 * XXX: THIS STUFF SHOULD BE IN pte.c?
2182 moea_pte_spill(vm_offset_t addr)
2184 struct pvo_entry *source_pvo, *victim_pvo;
2185 struct pvo_entry *pvo;
2194 ptegidx = va_to_pteg(sr, addr);
2197 * Have to substitute some entry. Use the primary hash for this.
2198 * Use low bits of timebase as random generator.
2200 pteg = &moea_pteg_table[ptegidx];
2201 mtx_lock(&moea_table_mutex);
2202 __asm __volatile("mftb %0" : "=r"(i));
2208 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2210 * We need to find a pvo entry for this address.
2212 if (source_pvo == NULL &&
2213 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2214 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2216 * Now found an entry to be spilled into the pteg.
2217 * The PTE is now valid, so we know it's active.
2219 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2222 PVO_PTEGIDX_SET(pvo, j);
2223 moea_pte_overflow--;
2224 mtx_unlock(&moea_table_mutex);
2230 if (victim_pvo != NULL)
2235 * We also need the pvo entry of the victim we are replacing
2236 * so save the R & C bits of the PTE.
2238 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2239 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2241 if (source_pvo != NULL)
2246 if (source_pvo == NULL) {
2247 mtx_unlock(&moea_table_mutex);
2251 if (victim_pvo == NULL) {
2252 if ((pt->pte_hi & PTE_HID) == 0)
2253 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2257 * If this is a secondary PTE, we need to search it's primary
2258 * pvo bucket for the matching PVO.
2260 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2263 * We also need the pvo entry of the victim we are
2264 * replacing so save the R & C bits of the PTE.
2266 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2272 if (victim_pvo == NULL)
2273 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2278 * We are invalidating the TLB entry for the EA we are replacing even
2279 * though it's valid. If we don't, we lose any ref/chg bit changes
2280 * contained in the TLB entry.
2282 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2284 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2285 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2287 PVO_PTEGIDX_CLR(victim_pvo);
2288 PVO_PTEGIDX_SET(source_pvo, i);
2289 moea_pte_replacements++;
2291 mtx_unlock(&moea_table_mutex);
2295 static __inline struct pvo_entry *
2296 moea_pte_spillable_ident(u_int ptegidx)
2299 struct pvo_entry *pvo_walk, *pvo = NULL;
2301 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2302 if (pvo_walk->pvo_vaddr & PVO_WIRED)
2305 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2308 pt = moea_pvo_to_pte(pvo_walk, -1);
2315 mtx_unlock(&moea_table_mutex);
2316 if (!(pt->pte_lo & PTE_REF))
2324 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2327 struct pvo_entry *victim_pvo;
2330 u_int pteg_bkpidx = ptegidx;
2332 mtx_assert(&moea_table_mutex, MA_OWNED);
2335 * First try primary hash.
2337 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2338 if ((pt->pte_hi & PTE_VALID) == 0) {
2339 pvo_pt->pte_hi &= ~PTE_HID;
2340 moea_pte_set(pt, pvo_pt);
2346 * Now try secondary hash.
2348 ptegidx ^= moea_pteg_mask;
2350 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2351 if ((pt->pte_hi & PTE_VALID) == 0) {
2352 pvo_pt->pte_hi |= PTE_HID;
2353 moea_pte_set(pt, pvo_pt);
2358 /* Try again, but this time try to force a PTE out. */
2359 ptegidx = pteg_bkpidx;
2361 victim_pvo = moea_pte_spillable_ident(ptegidx);
2362 if (victim_pvo == NULL) {
2363 ptegidx ^= moea_pteg_mask;
2364 victim_pvo = moea_pte_spillable_ident(ptegidx);
2367 if (victim_pvo == NULL) {
2368 panic("moea_pte_insert: overflow");
2372 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2374 if (pteg_bkpidx == ptegidx)
2375 pvo_pt->pte_hi &= ~PTE_HID;
2377 pvo_pt->pte_hi |= PTE_HID;
2380 * Synchronize the sacrifice PTE with its PVO, then mark both
2381 * invalid. The PVO will be reused when/if the VM system comes
2382 * here after a fault.
2384 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2386 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2387 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2392 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2393 PVO_PTEGIDX_CLR(victim_pvo);
2394 moea_pte_overflow++;
2395 moea_pte_set(pt, pvo_pt);
2397 return (victim_idx & 7);
2401 moea_query_bit(vm_page_t m, int ptebit)
2403 struct pvo_entry *pvo;
2406 rw_assert(&pvh_global_lock, RA_WLOCKED);
2407 if (moea_attr_fetch(m) & ptebit)
2410 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2413 * See if we saved the bit off. If so, cache it and return
2416 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2417 moea_attr_save(m, ptebit);
2423 * No luck, now go through the hard part of looking at the PTEs
2424 * themselves. Sync so that any pending REF/CHG bits are flushed to
2428 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2431 * See if this pvo has a valid PTE. if so, fetch the
2432 * REF/CHG bits from the valid PTE. If the appropriate
2433 * ptebit is set, cache it and return success.
2435 pt = moea_pvo_to_pte(pvo, -1);
2437 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2438 mtx_unlock(&moea_table_mutex);
2439 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2440 moea_attr_save(m, ptebit);
2450 moea_clear_bit(vm_page_t m, int ptebit)
2453 struct pvo_entry *pvo;
2456 rw_assert(&pvh_global_lock, RA_WLOCKED);
2459 * Clear the cached value.
2461 moea_attr_clear(m, ptebit);
2464 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2465 * we can reset the right ones). note that since the pvo entries and
2466 * list heads are accessed via BAT0 and are never placed in the page
2467 * table, we don't have to worry about further accesses setting the
2473 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2474 * valid pte clear the ptebit from the valid pte.
2477 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2478 pt = moea_pvo_to_pte(pvo, -1);
2480 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2481 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2483 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2485 mtx_unlock(&moea_table_mutex);
2487 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2494 * Return true if the physical range is encompassed by the battable[idx]
2497 moea_bat_mapped(int idx, vm_paddr_t pa, vm_size_t size)
2505 * Return immediately if not a valid mapping
2507 if (!(battable[idx].batu & BAT_Vs))
2511 * The BAT entry must be cache-inhibited, guarded, and r/w
2512 * so it can function as an i/o page
2514 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2515 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2519 * The address should be within the BAT range. Assume that the
2520 * start address in the BAT has the correct alignment (thus
2521 * not requiring masking)
2523 start = battable[idx].batl & BAT_PBS;
2524 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2525 end = start | (bat_ble << 15) | 0x7fff;
2527 if ((pa < start) || ((pa + size) > end))
2534 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2539 * This currently does not work for entries that
2540 * overlap 256M BAT segments.
2543 for(i = 0; i < 16; i++)
2544 if (moea_bat_mapped(i, pa, size) == 0)
2551 * Map a set of physical memory pages into the kernel virtual
2552 * address space. Return a pointer to where it is mapped. This
2553 * routine is intended to be used for mapping device memory,
2557 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2560 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2564 moea_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2566 vm_offset_t va, tmpva, ppa, offset;
2569 ppa = trunc_page(pa);
2570 offset = pa & PAGE_MASK;
2571 size = roundup(offset + size, PAGE_SIZE);
2574 * If the physical address lies within a valid BAT table entry,
2575 * return the 1:1 mapping. This currently doesn't work
2576 * for regions that overlap 256M BAT segments.
2578 for (i = 0; i < 16; i++) {
2579 if (moea_bat_mapped(i, pa, size) == 0)
2580 return ((void *) pa);
2583 va = kva_alloc(size);
2585 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2587 for (tmpva = va; size > 0;) {
2588 moea_kenter_attr(mmu, tmpva, ppa, ma);
2595 return ((void *)(va + offset));
2599 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2601 vm_offset_t base, offset;
2604 * If this is outside kernel virtual space, then it's a
2605 * battable entry and doesn't require unmapping
2607 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2608 base = trunc_page(va);
2609 offset = va & PAGE_MASK;
2610 size = roundup(offset + size, PAGE_SIZE);
2611 kva_free(base, size);
2616 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2618 struct pvo_entry *pvo;
2625 lim = round_page(va);
2626 len = MIN(lim - va, sz);
2627 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2629 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2631 moea_syncicache(pa, len);
2640 moea_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2646 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2649 moea_scan_init(mmu_t mmu)
2651 struct pvo_entry *pvo;
2656 /* Initialize phys. segments for dumpsys(). */
2657 memset(&dump_map, 0, sizeof(dump_map));
2658 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2659 for (i = 0; i < pregions_sz; i++) {
2660 dump_map[i].pa_start = pregions[i].mr_start;
2661 dump_map[i].pa_size = pregions[i].mr_size;
2666 /* Virtual segments for minidumps: */
2667 memset(&dump_map, 0, sizeof(dump_map));
2669 /* 1st: kernel .data and .bss. */
2670 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2671 dump_map[0].pa_size =
2672 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2674 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2675 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
2676 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2678 /* 3rd: kernel VM. */
2679 va = dump_map[1].pa_start + dump_map[1].pa_size;
2680 /* Find start of next chunk (from va). */
2681 while (va < virtual_end) {
2682 /* Don't dump the buffer cache. */
2683 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2684 va = kmi.buffer_eva;
2687 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
2688 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2692 if (va < virtual_end) {
2693 dump_map[2].pa_start = va;
2695 /* Find last page in chunk. */
2696 while (va < virtual_end) {
2697 /* Don't run into the buffer cache. */
2698 if (va == kmi.buffer_sva)
2700 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF,
2703 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2707 dump_map[2].pa_size = va - dump_map[2].pa_start;