2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008-2015 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Manages physical address maps.
35 * Since the information managed by this module is also stored by the
36 * logical address mapping module, this module may throw away valid virtual
37 * to physical mappings at almost any time. However, invalidations of
38 * mappings must be done as requested.
40 * In order to cope with hardware architectures which make virtual to
41 * physical map invalidates expensive, this module may delay invalidate
42 * reduced protection operations until such time as they are actually
43 * necessary. This module is given full information as to which processors
44 * are currently using which maps, and to when physical maps must be made
48 #include "opt_kstack_pages.h"
50 #include <sys/param.h>
51 #include <sys/kernel.h>
53 #include <sys/queue.h>
54 #include <sys/cpuset.h>
55 #include <sys/kerneldump.h>
58 #include <sys/msgbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/mutex.h>
62 #include <sys/rwlock.h>
63 #include <sys/sched.h>
64 #include <sys/sysctl.h>
65 #include <sys/systm.h>
66 #include <sys/vmmeter.h>
71 #include <dev/ofw/openfirm.h>
74 #include <vm/vm_param.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_page.h>
77 #include <vm/vm_phys.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_object.h>
80 #include <vm/vm_extern.h>
81 #include <vm/vm_pageout.h>
84 #include <machine/_inttypes.h>
85 #include <machine/cpu.h>
86 #include <machine/platform.h>
87 #include <machine/frame.h>
88 #include <machine/md_var.h>
89 #include <machine/psl.h>
90 #include <machine/bat.h>
91 #include <machine/hid.h>
92 #include <machine/pte.h>
93 #include <machine/sr.h>
94 #include <machine/trap.h>
95 #include <machine/mmuvar.h>
97 #include "mmu_oea64.h"
99 #include "moea64_if.h"
101 void moea64_release_vsid(uint64_t vsid);
102 uintptr_t moea64_get_unique_vsid(void);
104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
105 #define ENABLE_TRANS(msr) mtmsr(msr)
107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
109 #define VSID_HASH_MASK 0x0000007fffffffffULL
114 * There are two locks of interest: the page locks and the pmap locks, which
115 * protect their individual PVO lists and are locked in that order. The contents
116 * of all PVO entries are protected by the locks of their respective pmaps.
117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
122 #define PV_LOCK_PER_DOM (PA_LOCK_COUNT * 3)
123 #define PV_LOCK_COUNT (PV_LOCK_PER_DOM * MAXMEMDOM)
124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains.
128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the
129 * index at (N << 45).
132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \
133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM)
135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT)
137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)]))
138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa))
139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa))
140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m))
142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m))
143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
152 extern unsigned char _etext[];
153 extern unsigned char _end[];
155 extern void *slbtrap, *slbtrapend;
158 * Map of physical memory regions.
160 static struct mem_region *regions;
161 static struct mem_region *pregions;
162 static struct numa_mem_region *numa_pregions;
163 static u_int phys_avail_count;
164 static int regions_sz, pregions_sz, numapregions_sz;
166 extern void bs_remap_earlyboot(void);
169 * Lock for the SLB tables.
171 struct mtx moea64_slb_mutex;
176 u_long moea64_pteg_count;
177 u_long moea64_pteg_mask;
183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */
185 static struct pvo_entry *moea64_bpvo_pool;
186 static int moea64_bpvo_pool_index = 0;
187 static int moea64_bpvo_pool_size = 327680;
188 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
190 &moea64_bpvo_pool_index, 0, "");
192 #define VSID_NBPW (sizeof(u_int32_t) * 8)
194 #define NVSIDS (NPMAPS * 16)
195 #define VSID_HASHMASK 0xffffffffUL
197 #define NVSIDS NPMAPS
198 #define VSID_HASHMASK 0xfffffUL
200 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
202 static boolean_t moea64_initialized = FALSE;
208 u_int moea64_pte_valid = 0;
209 u_int moea64_pte_overflow = 0;
210 u_int moea64_pvo_entries = 0;
211 u_int moea64_pvo_enter_calls = 0;
212 u_int moea64_pvo_remove_calls = 0;
213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
214 &moea64_pte_valid, 0, "");
215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
216 &moea64_pte_overflow, 0, "");
217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
218 &moea64_pvo_entries, 0, "");
219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
220 &moea64_pvo_enter_calls, 0, "");
221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
222 &moea64_pvo_remove_calls, 0, "");
225 vm_offset_t moea64_scratchpage_va[2];
226 struct pvo_entry *moea64_scratchpage_pvo[2];
227 struct mtx moea64_scratchpage_mtx;
229 uint64_t moea64_large_page_mask = 0;
230 uint64_t moea64_large_page_size = 0;
231 int moea64_large_page_shift = 0;
236 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo,
237 struct pvo_head *pvo_head, struct pvo_entry **oldpvo);
238 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo);
239 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo);
240 static void moea64_pvo_remove_from_page_locked(mmu_t mmu,
241 struct pvo_entry *pvo, vm_page_t m);
242 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
247 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t);
248 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t);
249 static void moea64_kremove(mmu_t, vm_offset_t);
250 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
251 vm_paddr_t pa, vm_size_t sz);
252 static void moea64_pmap_init_qpages(void);
255 * Kernel MMU interface
257 void moea64_clear_modify(mmu_t, vm_page_t);
258 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
259 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
260 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
261 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
262 u_int flags, int8_t psind);
263 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
265 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
266 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
267 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
268 void moea64_init(mmu_t);
269 boolean_t moea64_is_modified(mmu_t, vm_page_t);
270 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
271 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
272 int moea64_ts_referenced(mmu_t, vm_page_t);
273 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
274 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
275 void moea64_page_init(mmu_t, vm_page_t);
276 int moea64_page_wired_mappings(mmu_t, vm_page_t);
277 void moea64_pinit(mmu_t, pmap_t);
278 void moea64_pinit0(mmu_t, pmap_t);
279 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
280 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
281 void moea64_qremove(mmu_t, vm_offset_t, int);
282 void moea64_release(mmu_t, pmap_t);
283 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
284 void moea64_remove_pages(mmu_t, pmap_t);
285 void moea64_remove_all(mmu_t, vm_page_t);
286 void moea64_remove_write(mmu_t, vm_page_t);
287 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
288 void moea64_zero_page(mmu_t, vm_page_t);
289 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
290 void moea64_activate(mmu_t, struct thread *);
291 void moea64_deactivate(mmu_t, struct thread *);
292 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
293 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
294 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
295 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
296 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
297 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma);
298 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
299 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
300 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
301 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz,
303 void moea64_scan_init(mmu_t mmu);
304 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m);
305 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr);
306 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm,
307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
308 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
309 int *is_user, vm_offset_t *decoded_addr);
310 static size_t moea64_scan_pmap(mmu_t mmu);
311 static void *moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs);
312 static void moea64_page_array_startup(mmu_t, long);
315 static mmu_method_t moea64_methods[] = {
316 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
317 MMUMETHOD(mmu_copy_page, moea64_copy_page),
318 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
319 MMUMETHOD(mmu_enter, moea64_enter),
320 MMUMETHOD(mmu_enter_object, moea64_enter_object),
321 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
322 MMUMETHOD(mmu_extract, moea64_extract),
323 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
324 MMUMETHOD(mmu_init, moea64_init),
325 MMUMETHOD(mmu_is_modified, moea64_is_modified),
326 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
327 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
328 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
329 MMUMETHOD(mmu_map, moea64_map),
330 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
331 MMUMETHOD(mmu_page_init, moea64_page_init),
332 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
333 MMUMETHOD(mmu_pinit, moea64_pinit),
334 MMUMETHOD(mmu_pinit0, moea64_pinit0),
335 MMUMETHOD(mmu_protect, moea64_protect),
336 MMUMETHOD(mmu_qenter, moea64_qenter),
337 MMUMETHOD(mmu_qremove, moea64_qremove),
338 MMUMETHOD(mmu_release, moea64_release),
339 MMUMETHOD(mmu_remove, moea64_remove),
340 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
341 MMUMETHOD(mmu_remove_all, moea64_remove_all),
342 MMUMETHOD(mmu_remove_write, moea64_remove_write),
343 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
344 MMUMETHOD(mmu_unwire, moea64_unwire),
345 MMUMETHOD(mmu_zero_page, moea64_zero_page),
346 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
347 MMUMETHOD(mmu_activate, moea64_activate),
348 MMUMETHOD(mmu_deactivate, moea64_deactivate),
349 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
350 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page),
351 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page),
352 MMUMETHOD(mmu_page_array_startup, moea64_page_array_startup),
354 /* Internal interfaces */
355 MMUMETHOD(mmu_mapdev, moea64_mapdev),
356 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
357 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
358 MMUMETHOD(mmu_kextract, moea64_kextract),
359 MMUMETHOD(mmu_kenter, moea64_kenter),
360 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
361 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
362 MMUMETHOD(mmu_scan_init, moea64_scan_init),
363 MMUMETHOD(mmu_scan_pmap, moea64_scan_pmap),
364 MMUMETHOD(mmu_dump_pmap_init, moea64_dump_pmap_init),
365 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
366 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr),
367 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr),
372 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
374 static struct pvo_head *
375 vm_page_to_pvoh(vm_page_t m)
378 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
379 return (&m->md.mdpg_pvoh);
382 static struct pvo_entry *
383 alloc_pvo_entry(int bootstrap)
385 struct pvo_entry *pvo;
387 if (!moea64_initialized || bootstrap) {
388 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
389 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
390 moea64_bpvo_pool_index, moea64_bpvo_pool_size,
391 moea64_bpvo_pool_size * sizeof(struct pvo_entry));
393 pvo = &moea64_bpvo_pool[
394 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
395 bzero(pvo, sizeof(*pvo));
396 pvo->pvo_vaddr = PVO_BOOTSTRAP;
398 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO);
405 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
411 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
413 pvo->pvo_pmap = pmap;
415 pvo->pvo_vaddr |= va;
416 vsid = va_to_vsid(pmap, va);
417 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
420 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift :
422 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
423 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
427 free_pvo_entry(struct pvo_entry *pvo)
430 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
431 uma_zfree(moea64_pvo_zone, pvo);
435 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
438 lpte->pte_hi = moea64_pte_vpn_from_pvo_vpn(pvo);
439 lpte->pte_hi |= LPTE_VALID;
441 if (pvo->pvo_vaddr & PVO_LARGE)
442 lpte->pte_hi |= LPTE_BIG;
443 if (pvo->pvo_vaddr & PVO_WIRED)
444 lpte->pte_hi |= LPTE_WIRED;
445 if (pvo->pvo_vaddr & PVO_HID)
446 lpte->pte_hi |= LPTE_HID;
448 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
449 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
450 lpte->pte_lo |= LPTE_BW;
452 lpte->pte_lo |= LPTE_BR;
454 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
455 lpte->pte_lo |= LPTE_NOEXEC;
458 static __inline uint64_t
459 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
464 if (ma != VM_MEMATTR_DEFAULT) {
466 case VM_MEMATTR_UNCACHEABLE:
467 return (LPTE_I | LPTE_G);
468 case VM_MEMATTR_CACHEABLE:
470 case VM_MEMATTR_WRITE_COMBINING:
471 case VM_MEMATTR_WRITE_BACK:
472 case VM_MEMATTR_PREFETCHABLE:
474 case VM_MEMATTR_WRITE_THROUGH:
475 return (LPTE_W | LPTE_M);
480 * Assume the page is cache inhibited and access is guarded unless
481 * it's in our available memory array.
483 pte_lo = LPTE_I | LPTE_G;
484 for (i = 0; i < pregions_sz; i++) {
485 if ((pa >= pregions[i].mr_start) &&
486 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
487 pte_lo &= ~(LPTE_I | LPTE_G);
497 * Quick sort callout for comparing memory regions.
499 static int om_cmp(const void *a, const void *b);
502 om_cmp(const void *a, const void *b)
504 const struct ofw_map *mapa;
505 const struct ofw_map *mapb;
509 if (mapa->om_pa < mapb->om_pa)
511 else if (mapa->om_pa > mapb->om_pa)
518 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
520 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
521 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
522 struct pvo_entry *pvo;
528 bzero(translations, sz);
529 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
531 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
532 panic("moea64_bootstrap: can't get ofw translations");
534 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
535 sz /= sizeof(cell_t);
536 for (i = 0, j = 0; i < sz; j++) {
537 translations[j].om_va = trans_cells[i++];
538 translations[j].om_len = trans_cells[i++];
539 translations[j].om_pa = trans_cells[i++];
541 translations[j].om_pa <<= 32;
542 translations[j].om_pa |= trans_cells[i++];
544 translations[j].om_mode = trans_cells[i++];
546 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
550 qsort(translations, sz, sizeof (*translations), om_cmp);
552 for (i = 0; i < sz; i++) {
553 pa_base = translations[i].om_pa;
554 #ifndef __powerpc64__
555 if ((translations[i].om_pa >> 32) != 0)
556 panic("OFW translations above 32-bit boundary!");
559 if (pa_base % PAGE_SIZE)
560 panic("OFW translation not page-aligned (phys)!");
561 if (translations[i].om_va % PAGE_SIZE)
562 panic("OFW translation not page-aligned (virt)!");
564 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
565 pa_base, translations[i].om_va, translations[i].om_len);
567 /* Now enter the pages for this mapping */
570 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
571 /* If this address is direct-mapped, skip remapping */
573 translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
574 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT)
578 PMAP_LOCK(kernel_pmap);
579 pvo = moea64_pvo_find_va(kernel_pmap,
580 translations[i].om_va + off);
581 PMAP_UNLOCK(kernel_pmap);
585 moea64_kenter(mmup, translations[i].om_va + off,
594 moea64_probe_large_page(void)
596 uint16_t pvr = mfpvr() >> 16;
602 powerpc_sync(); isync();
603 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
604 powerpc_sync(); isync();
608 if (moea64_large_page_size == 0) {
609 moea64_large_page_size = 0x1000000; /* 16 MB */
610 moea64_large_page_shift = 24;
614 moea64_large_page_mask = moea64_large_page_size - 1;
618 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
625 cache = PCPU_GET(aim.slb);
626 esid = va >> ADDR_SR_SHFT;
627 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
629 for (i = 0; i < 64; i++) {
630 if (cache[i].slbe == (slbe | i))
635 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
637 entry.slbv |= SLBV_L;
639 slb_insert_kernel(entry.slbe, entry.slbv);
644 moea64_kenter_large(mmu_t mmup, vm_offset_t va, vm_paddr_t pa, uint64_t attr, int bootstrap)
646 struct pvo_entry *pvo;
653 pvo = alloc_pvo_entry(bootstrap);
654 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
655 init_pvo_entry(pvo, kernel_pmap, va);
657 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
659 pvo->pvo_pte.pa = pa | pte_lo;
660 error = moea64_pvo_enter(mmup, pvo, NULL, NULL);
662 panic("Error %d inserting large page\n", error);
667 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
668 vm_offset_t kernelend)
671 vm_paddr_t pa, pkernelstart, pkernelend;
672 vm_offset_t size, off;
676 if (moea64_large_page_size == 0)
681 PMAP_LOCK(kernel_pmap);
682 for (i = 0; i < pregions_sz; i++) {
683 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
684 pregions[i].mr_size; pa += moea64_large_page_size) {
686 if (pa & moea64_large_page_mask) {
687 pa &= moea64_large_page_mask;
690 if (pa + moea64_large_page_size >
691 pregions[i].mr_start + pregions[i].mr_size)
694 moea64_kenter_large(mmup, PHYS_TO_DMAP(pa), pa, pte_lo, 1);
697 PMAP_UNLOCK(kernel_pmap);
701 * Make sure the kernel and BPVO pool stay mapped on systems either
702 * without a direct map or on which the kernel is not already executing
703 * out of the direct-mapped region.
705 if (kernelstart < DMAP_BASE_ADDRESS) {
707 * For pre-dmap execution, we need to use identity mapping
708 * because we will be operating with the mmu on but in the
709 * wrong address configuration until we __restartkernel().
711 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
713 moea64_kenter(mmup, pa, pa);
714 } else if (!hw_direct_map) {
715 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS;
716 pkernelend = kernelend & ~DMAP_BASE_ADDRESS;
717 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend;
719 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa);
722 if (!hw_direct_map) {
723 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
724 off = (vm_offset_t)(moea64_bpvo_pool);
725 for (pa = off; pa < off + size; pa += PAGE_SIZE)
726 moea64_kenter(mmup, pa, pa);
728 /* Map exception vectors */
729 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE)
730 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa);
735 * Allow user to override unmapped_buf_allowed for testing.
736 * XXXKIB Only direct map implementation was tested.
738 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
739 &unmapped_buf_allowed))
740 unmapped_buf_allowed = hw_direct_map;
743 /* Quick sort callout for comparing physical addresses. */
745 pa_cmp(const void *a, const void *b)
747 const vm_paddr_t *pa = a, *pb = b;
758 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
761 vm_size_t physsz, hwphyssz;
762 vm_paddr_t kernelphysstart, kernelphysend;
765 #ifndef __powerpc64__
766 /* We don't have a direct map since there is no BAT */
769 /* Make sure battable is zero, since we have no BAT */
770 for (i = 0; i < 16; i++) {
771 battable[i].batu = 0;
772 battable[i].batl = 0;
775 moea64_probe_large_page();
777 /* Use a direct map if we have large page support */
778 if (moea64_large_page_size > 0)
783 /* Install trap handlers for SLBs */
784 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
785 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
786 __syncicache((void *)EXC_DSE, 0x80);
787 __syncicache((void *)EXC_ISE, 0x80);
790 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS;
791 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS;
793 /* Get physical memory regions from firmware */
794 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
795 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
797 if (PHYS_AVAIL_ENTRIES < regions_sz)
798 panic("moea64_bootstrap: phys_avail too small");
800 phys_avail_count = 0;
803 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
804 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
805 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
806 regions[i].mr_start, regions[i].mr_start +
807 regions[i].mr_size, regions[i].mr_size);
809 (physsz + regions[i].mr_size) >= hwphyssz) {
810 if (physsz < hwphyssz) {
811 phys_avail[j] = regions[i].mr_start;
812 phys_avail[j + 1] = regions[i].mr_start +
816 dump_avail[j] = phys_avail[j];
817 dump_avail[j + 1] = phys_avail[j + 1];
821 phys_avail[j] = regions[i].mr_start;
822 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
824 physsz += regions[i].mr_size;
825 dump_avail[j] = phys_avail[j];
826 dump_avail[j + 1] = phys_avail[j + 1];
829 /* Check for overlap with the kernel and exception vectors */
831 for (j = 0; j < 2*phys_avail_count; j+=2) {
832 if (phys_avail[j] < EXC_LAST)
833 phys_avail[j] += EXC_LAST;
835 if (phys_avail[j] >= kernelphysstart &&
836 phys_avail[j+1] <= kernelphysend) {
837 phys_avail[j] = phys_avail[j+1] = ~0;
842 if (kernelphysstart >= phys_avail[j] &&
843 kernelphysstart < phys_avail[j+1]) {
844 if (kernelphysend < phys_avail[j+1]) {
845 phys_avail[2*phys_avail_count] =
846 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE;
847 phys_avail[2*phys_avail_count + 1] =
852 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK;
855 if (kernelphysend >= phys_avail[j] &&
856 kernelphysend < phys_avail[j+1]) {
857 if (kernelphysstart > phys_avail[j]) {
858 phys_avail[2*phys_avail_count] = phys_avail[j];
859 phys_avail[2*phys_avail_count + 1] =
860 kernelphysstart & ~PAGE_MASK;
864 phys_avail[j] = (kernelphysend & ~PAGE_MASK) +
869 /* Remove physical available regions marked for removal (~0) */
871 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]),
873 phys_avail_count -= rm_pavail;
874 for (i = 2*phys_avail_count;
875 i < 2*(phys_avail_count + rm_pavail); i+=2)
876 phys_avail[i] = phys_avail[i+1] = 0;
879 physmem = btoc(physsz);
882 moea64_pteg_count = PTEGCOUNT;
884 moea64_pteg_count = 0x1000;
886 while (moea64_pteg_count < physmem)
887 moea64_pteg_count <<= 1;
889 moea64_pteg_count >>= 1;
890 #endif /* PTEGCOUNT */
894 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
901 moea64_pteg_mask = moea64_pteg_count - 1;
904 * Initialize SLB table lock and page locks
906 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
907 for (i = 0; i < PV_LOCK_COUNT; i++)
908 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
911 * Initialise the bootstrap pvo pool.
913 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
914 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE);
915 moea64_bpvo_pool_index = 0;
917 /* Place at address usable through the direct map */
919 moea64_bpvo_pool = (struct pvo_entry *)
920 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool);
923 * Make sure kernel vsid is allocated as well as VSID 0.
925 #ifndef __powerpc64__
926 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
927 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
928 moea64_vsid_bitmap[0] |= 1;
932 * Initialize the kernel pmap (which is statically allocated).
935 for (i = 0; i < 64; i++) {
936 pcpup->pc_aim.slb[i].slbv = 0;
937 pcpup->pc_aim.slb[i].slbe = 0;
940 for (i = 0; i < 16; i++)
941 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
944 kernel_pmap->pmap_phys = kernel_pmap;
945 CPU_FILL(&kernel_pmap->pm_active);
946 RB_INIT(&kernel_pmap->pmap_pvo);
948 PMAP_LOCK_INIT(kernel_pmap);
951 * Now map in all the other buffers we allocated earlier
954 moea64_setup_direct_map(mmup, kernelstart, kernelend);
958 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
969 * Set up the Open Firmware pmap and add its mappings if not in real
973 chosen = OF_finddevice("/chosen");
974 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
975 mmu = OF_instance_to_package(mmui);
977 (sz = OF_getproplen(mmu, "translations")) == -1)
979 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
980 panic("moea64_bootstrap: too many ofw translations");
983 moea64_add_ofw_mappings(mmup, mmu, sz);
987 * Calculate the last available physical address.
990 for (i = 0; phys_avail[i + 2] != 0; i += 2)
991 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1]));
996 MMU_CPU_BOOTSTRAP(mmup,0);
997 mtmsr(mfmsr() | PSL_DR | PSL_IR);
1001 * Set the start and end of kva.
1003 virtual_avail = VM_MIN_KERNEL_ADDRESS;
1004 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
1007 * Map the entire KVA range into the SLB. We must not fault there.
1009 #ifdef __powerpc64__
1010 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
1011 moea64_bootstrap_slb_prefault(va, 0);
1015 * Remap any early IO mappings (console framebuffer, etc.)
1017 bs_remap_earlyboot();
1020 * Figure out how far we can extend virtual_end into segment 16
1021 * without running into existing mappings. Segment 16 is guaranteed
1022 * to contain neither RAM nor devices (at least on Apple hardware),
1023 * but will generally contain some OFW mappings we should not
1027 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
1028 PMAP_LOCK(kernel_pmap);
1029 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
1030 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
1031 virtual_end += PAGE_SIZE;
1032 PMAP_UNLOCK(kernel_pmap);
1036 * Allocate a kernel stack with a guard page for thread0 and map it
1037 * into the kernel page map.
1039 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
1040 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1041 virtual_avail = va + kstack_pages * PAGE_SIZE;
1042 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
1043 thread0.td_kstack = va;
1044 thread0.td_kstack_pages = kstack_pages;
1045 for (i = 0; i < kstack_pages; i++) {
1046 moea64_kenter(mmup, va, pa);
1052 * Allocate virtual address space for the message buffer.
1054 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
1055 msgbufp = (struct msgbuf *)virtual_avail;
1057 virtual_avail += round_page(msgbufsize);
1058 while (va < virtual_avail) {
1059 moea64_kenter(mmup, va, pa);
1065 * Allocate virtual address space for the dynamic percpu area.
1067 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
1068 dpcpu = (void *)virtual_avail;
1070 virtual_avail += DPCPU_SIZE;
1071 while (va < virtual_avail) {
1072 moea64_kenter(mmup, va, pa);
1076 dpcpu_init(dpcpu, curcpu);
1078 crashdumpmap = (caddr_t)virtual_avail;
1079 virtual_avail += MAXDUMPPGS * PAGE_SIZE;
1082 * Allocate some things for page zeroing. We put this directly
1083 * in the page table and use MOEA64_PTE_REPLACE to avoid any
1084 * of the PVO book-keeping or other parts of the VM system
1085 * from even knowing that this hack exists.
1088 if (!hw_direct_map) {
1089 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
1091 for (i = 0; i < 2; i++) {
1092 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
1093 virtual_end -= PAGE_SIZE;
1095 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
1097 PMAP_LOCK(kernel_pmap);
1098 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
1099 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
1100 PMAP_UNLOCK(kernel_pmap);
1104 numa_mem_regions(&numa_pregions, &numapregions_sz);
1108 moea64_pmap_init_qpages(void)
1118 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1119 if (pc->pc_qmap_addr == 0)
1120 panic("pmap_init_qpages: unable to allocate KVA");
1121 PMAP_LOCK(kernel_pmap);
1122 pc->pc_aim.qmap_pvo =
1123 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1124 PMAP_UNLOCK(kernel_pmap);
1125 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF);
1129 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1132 * Activate a user pmap. This mostly involves setting some non-CPU
1136 moea64_activate(mmu_t mmu, struct thread *td)
1140 pm = &td->td_proc->p_vmspace->vm_pmap;
1141 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1143 #ifdef __powerpc64__
1144 PCPU_SET(aim.userslb, pm->pm_slb);
1145 __asm __volatile("slbmte %0, %1; isync" ::
1146 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1148 PCPU_SET(curpmap, pm->pmap_phys);
1149 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1154 moea64_deactivate(mmu_t mmu, struct thread *td)
1158 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1160 pm = &td->td_proc->p_vmspace->vm_pmap;
1161 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1162 #ifdef __powerpc64__
1163 PCPU_SET(aim.userslb, NULL);
1165 PCPU_SET(curpmap, NULL);
1170 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1172 struct pvo_entry key, *pvo;
1176 key.pvo_vaddr = sva;
1178 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1179 pvo != NULL && PVO_VADDR(pvo) < eva;
1180 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1181 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1182 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1184 pvo->pvo_vaddr &= ~PVO_WIRED;
1185 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */);
1186 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1187 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1190 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1192 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1193 if (refchg & LPTE_CHG)
1195 if (refchg & LPTE_REF)
1196 vm_page_aflag_set(m, PGA_REFERENCED);
1198 pm->pm_stats.wired_count--;
1204 * This goes through and sets the physical address of our
1205 * special scratch PTE to the PA we want to zero or copy. Because
1206 * of locking issues (this can get called in pvo_enter() by
1207 * the UMA allocator), we can't use most other utility functions here
1211 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa)
1213 struct pvo_entry *pvo;
1215 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1216 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1218 pvo = moea64_scratchpage_pvo[which];
1219 PMAP_LOCK(pvo->pvo_pmap);
1221 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1222 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE);
1223 PMAP_UNLOCK(pvo->pvo_pmap);
1228 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1233 dst = VM_PAGE_TO_PHYS(mdst);
1234 src = VM_PAGE_TO_PHYS(msrc);
1236 if (hw_direct_map) {
1237 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1240 mtx_lock(&moea64_scratchpage_mtx);
1242 moea64_set_scratchpage_pa(mmu, 0, src);
1243 moea64_set_scratchpage_pa(mmu, 1, dst);
1245 bcopy((void *)moea64_scratchpage_va[0],
1246 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1248 mtx_unlock(&moea64_scratchpage_mtx);
1253 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1254 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1257 vm_offset_t a_pg_offset, b_pg_offset;
1260 while (xfersize > 0) {
1261 a_pg_offset = a_offset & PAGE_MASK;
1262 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1263 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1264 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1266 b_pg_offset = b_offset & PAGE_MASK;
1267 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1268 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1269 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1271 bcopy(a_cp, b_cp, cnt);
1279 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1280 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1283 vm_offset_t a_pg_offset, b_pg_offset;
1286 mtx_lock(&moea64_scratchpage_mtx);
1287 while (xfersize > 0) {
1288 a_pg_offset = a_offset & PAGE_MASK;
1289 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1290 moea64_set_scratchpage_pa(mmu, 0,
1291 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1292 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1293 b_pg_offset = b_offset & PAGE_MASK;
1294 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1295 moea64_set_scratchpage_pa(mmu, 1,
1296 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1297 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1298 bcopy(a_cp, b_cp, cnt);
1303 mtx_unlock(&moea64_scratchpage_mtx);
1307 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1308 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1311 if (hw_direct_map) {
1312 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1315 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1321 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1323 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1325 if (size + off > PAGE_SIZE)
1326 panic("moea64_zero_page: size + off > PAGE_SIZE");
1328 if (hw_direct_map) {
1329 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size);
1331 mtx_lock(&moea64_scratchpage_mtx);
1332 moea64_set_scratchpage_pa(mmu, 0, pa);
1333 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1334 mtx_unlock(&moea64_scratchpage_mtx);
1339 * Zero a page of physical memory by temporarily mapping it
1342 moea64_zero_page(mmu_t mmu, vm_page_t m)
1344 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1345 vm_offset_t va, off;
1347 if (!hw_direct_map) {
1348 mtx_lock(&moea64_scratchpage_mtx);
1350 moea64_set_scratchpage_pa(mmu, 0, pa);
1351 va = moea64_scratchpage_va[0];
1353 va = PHYS_TO_DMAP(pa);
1356 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1357 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1360 mtx_unlock(&moea64_scratchpage_mtx);
1364 moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
1366 struct pvo_entry *pvo;
1367 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1370 return (PHYS_TO_DMAP(pa));
1373 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1374 * a critical section and access the PCPU data like on i386.
1375 * Instead, pin the thread and grab the PCPU lock to prevent
1376 * a preempting thread from using the same PCPU data.
1380 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED);
1381 pvo = PCPU_GET(aim.qmap_pvo);
1383 mtx_lock(PCPU_PTR(aim.qmap_lock));
1384 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1386 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
1389 return (PCPU_GET(qmap_addr));
1393 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1398 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED);
1399 KASSERT(PCPU_GET(qmap_addr) == addr,
1400 ("moea64_quick_remove_page: invalid address"));
1401 mtx_unlock(PCPU_PTR(aim.qmap_lock));
1406 * Map the given physical page at the specified virtual address in the
1407 * target pmap with the protection requested. If specified the page
1408 * will be wired down.
1412 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1413 vm_prot_t prot, u_int flags, int8_t psind)
1415 struct pvo_entry *pvo, *oldpvo;
1416 struct pvo_head *pvo_head;
1420 if ((m->oflags & VPO_UNMANAGED) == 0) {
1421 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1422 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1424 VM_OBJECT_ASSERT_LOCKED(m->object);
1427 pvo = alloc_pvo_entry(0);
1429 return (KERN_RESOURCE_SHORTAGE);
1430 pvo->pvo_pmap = NULL; /* to be filled in later */
1431 pvo->pvo_pte.prot = prot;
1433 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1434 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo;
1436 if ((flags & PMAP_ENTER_WIRED) != 0)
1437 pvo->pvo_vaddr |= PVO_WIRED;
1439 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1442 pvo_head = &m->md.mdpg_pvoh;
1443 pvo->pvo_vaddr |= PVO_MANAGED;
1448 if (pvo->pvo_pmap == NULL)
1449 init_pvo_entry(pvo, pmap, va);
1450 if (prot & VM_PROT_WRITE)
1451 if (pmap_bootstrapped &&
1452 (m->oflags & VPO_UNMANAGED) == 0)
1453 vm_page_aflag_set(m, PGA_WRITEABLE);
1455 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo);
1456 if (error == EEXIST) {
1457 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1458 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1459 oldpvo->pvo_pte.prot == prot) {
1460 /* Identical mapping already exists */
1463 /* If not in page table, reinsert it */
1464 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) {
1465 STAT_MOEA64(moea64_pte_overflow--);
1466 MOEA64_PTE_INSERT(mmu, oldpvo);
1469 /* Then just clean up and go home */
1472 free_pvo_entry(pvo);
1475 /* Otherwise, need to kill it first */
1476 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1477 "mapping does not match new mapping"));
1478 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1479 moea64_pvo_enter(mmu, pvo, pvo_head, NULL);
1485 /* Free any dead pages */
1486 if (error == EEXIST) {
1487 moea64_pvo_remove_from_page(mmu, oldpvo);
1488 free_pvo_entry(oldpvo);
1493 * Flush the page from the instruction cache if this page is
1494 * mapped executable and cacheable.
1496 if (pmap != kernel_pmap && (m->a.flags & PGA_EXECUTABLE) == 0 &&
1497 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1498 vm_page_aflag_set(m, PGA_EXECUTABLE);
1499 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1501 return (KERN_SUCCESS);
1505 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1510 * This is much trickier than on older systems because
1511 * we can't sync the icache on physical addresses directly
1512 * without a direct map. Instead we check a couple of cases
1513 * where the memory is already mapped in and, failing that,
1514 * use the same trick we use for page zeroing to create
1515 * a temporary mapping for this physical address.
1518 if (!pmap_bootstrapped) {
1520 * If PMAP is not bootstrapped, we are likely to be
1523 __syncicache((void *)(uintptr_t)pa, sz);
1524 } else if (pmap == kernel_pmap) {
1525 __syncicache((void *)va, sz);
1526 } else if (hw_direct_map) {
1527 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz);
1529 /* Use the scratch page to set up a temp mapping */
1531 mtx_lock(&moea64_scratchpage_mtx);
1533 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1534 __syncicache((void *)(moea64_scratchpage_va[1] +
1535 (va & ADDR_POFF)), sz);
1537 mtx_unlock(&moea64_scratchpage_mtx);
1542 * Maps a sequence of resident pages belonging to the same object.
1543 * The sequence begins with the given page m_start. This page is
1544 * mapped at the given virtual address start. Each subsequent page is
1545 * mapped at a virtual address that is offset from start by the same
1546 * amount as the page is offset from m_start within the object. The
1547 * last page in the sequence is the page with the largest offset from
1548 * m_start that can be mapped at a virtual address less than the given
1549 * virtual address end. Not every virtual page between start and end
1550 * is mapped; only those for which a resident page exists with the
1551 * corresponding offset from m_start are mapped.
1554 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1555 vm_page_t m_start, vm_prot_t prot)
1558 vm_pindex_t diff, psize;
1560 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1562 psize = atop(end - start);
1564 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1565 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1566 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1567 PMAP_ENTER_QUICK_LOCKED, 0);
1568 m = TAILQ_NEXT(m, listq);
1573 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1577 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1578 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1582 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1584 struct pvo_entry *pvo;
1588 pvo = moea64_pvo_find_va(pm, va);
1592 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1599 * Atomically extract and hold the physical page with the given
1600 * pmap and virtual address pair if that mapping permits the given
1604 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1606 struct pvo_entry *pvo;
1611 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1612 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1613 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1614 if (!vm_page_wire_mapped(m))
1621 static mmu_t installed_mmu;
1624 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1625 uint8_t *flags, int wait)
1627 struct pvo_entry *pvo;
1633 * This entire routine is a horrible hack to avoid bothering kmem
1634 * for new KVA addresses. Because this can get called from inside
1635 * kmem allocation routines, calling kmem for a new address here
1636 * can lead to multiply locking non-recursive mutexes.
1639 *flags = UMA_SLAB_PRIV;
1640 needed_lock = !PMAP_LOCKED(kernel_pmap);
1642 m = vm_page_alloc_domain(NULL, 0, domain,
1643 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ);
1647 va = VM_PAGE_TO_PHYS(m);
1649 pvo = alloc_pvo_entry(1 /* bootstrap */);
1651 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1652 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1655 PMAP_LOCK(kernel_pmap);
1657 init_pvo_entry(pvo, kernel_pmap, va);
1658 pvo->pvo_vaddr |= PVO_WIRED;
1660 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL);
1663 PMAP_UNLOCK(kernel_pmap);
1665 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1666 bzero((void *)va, PAGE_SIZE);
1671 extern int elf32_nxstack;
1674 moea64_init(mmu_t mmu)
1677 CTR0(KTR_PMAP, "moea64_init");
1679 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1680 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1681 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1683 if (!hw_direct_map) {
1684 installed_mmu = mmu;
1685 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1688 #ifdef COMPAT_FREEBSD32
1692 moea64_initialized = TRUE;
1696 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1699 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1700 ("moea64_is_referenced: page %p is not managed", m));
1702 return (moea64_query_bit(mmu, m, LPTE_REF));
1706 moea64_is_modified(mmu_t mmu, vm_page_t m)
1709 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1710 ("moea64_is_modified: page %p is not managed", m));
1713 * If the page is not busied then this check is racy.
1715 if (!pmap_page_is_write_mapped(m))
1718 return (moea64_query_bit(mmu, m, LPTE_CHG));
1722 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1724 struct pvo_entry *pvo;
1725 boolean_t rv = TRUE;
1728 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1736 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1739 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1740 ("moea64_clear_modify: page %p is not managed", m));
1741 vm_page_assert_busied(m);
1743 if (!pmap_page_is_write_mapped(m))
1745 moea64_clear_bit(mmu, m, LPTE_CHG);
1749 * Clear the write and modified bits in each of the given page's mappings.
1752 moea64_remove_write(mmu_t mmu, vm_page_t m)
1754 struct pvo_entry *pvo;
1755 int64_t refchg, ret;
1758 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1759 ("moea64_remove_write: page %p is not managed", m));
1760 vm_page_assert_busied(m);
1762 if (!pmap_page_is_write_mapped(m))
1768 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1769 pmap = pvo->pvo_pmap;
1771 if (!(pvo->pvo_vaddr & PVO_DEAD) &&
1772 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1773 pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
1774 ret = MOEA64_PTE_REPLACE(mmu, pvo,
1775 MOEA64_PTE_PROT_UPDATE);
1779 if (pvo->pvo_pmap == kernel_pmap)
1784 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
1786 vm_page_aflag_clear(m, PGA_WRITEABLE);
1791 * moea64_ts_referenced:
1793 * Return a count of reference bits for a page, clearing those bits.
1794 * It is not necessary for every reference bit to be cleared, but it
1795 * is necessary that 0 only be returned when there are truly no
1796 * reference bits set.
1798 * XXX: The exact number of bits to check and clear is a matter that
1799 * should be tested and standardized at some point in the future for
1800 * optimal aging of shared pages.
1803 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1806 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1807 ("moea64_ts_referenced: page %p is not managed", m));
1808 return (moea64_clear_bit(mmu, m, LPTE_REF));
1812 * Modify the WIMG settings of all mappings for a page.
1815 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1817 struct pvo_entry *pvo;
1822 if ((m->oflags & VPO_UNMANAGED) != 0) {
1823 m->md.mdpg_cache_attrs = ma;
1827 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1830 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1831 pmap = pvo->pvo_pmap;
1833 if (!(pvo->pvo_vaddr & PVO_DEAD)) {
1834 pvo->pvo_pte.pa &= ~LPTE_WIMG;
1835 pvo->pvo_pte.pa |= lo;
1836 refchg = MOEA64_PTE_REPLACE(mmu, pvo,
1837 MOEA64_PTE_INVALIDATE);
1839 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
1841 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1842 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1844 atomic_readandclear_32(&m->md.mdpg_attrs);
1845 if (refchg & LPTE_CHG)
1847 if (refchg & LPTE_REF)
1848 vm_page_aflag_set(m, PGA_REFERENCED);
1850 if (pvo->pvo_pmap == kernel_pmap)
1855 m->md.mdpg_cache_attrs = ma;
1860 * Map a wired page into kernel virtual address space.
1863 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1866 struct pvo_entry *pvo, *oldpvo;
1869 pvo = alloc_pvo_entry(0);
1872 } while (pvo == NULL);
1873 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
1874 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
1875 pvo->pvo_vaddr |= PVO_WIRED;
1877 PMAP_LOCK(kernel_pmap);
1878 oldpvo = moea64_pvo_find_va(kernel_pmap, va);
1880 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1881 init_pvo_entry(pvo, kernel_pmap, va);
1882 error = moea64_pvo_enter(mmu, pvo, NULL, NULL);
1883 PMAP_UNLOCK(kernel_pmap);
1885 /* Free any dead pages */
1886 if (oldpvo != NULL) {
1887 moea64_pvo_remove_from_page(mmu, oldpvo);
1888 free_pvo_entry(oldpvo);
1892 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va,
1893 (uintmax_t)pa, error);
1897 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1900 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1904 * Extract the physical page address associated with the given kernel virtual
1908 moea64_kextract(mmu_t mmu, vm_offset_t va)
1910 struct pvo_entry *pvo;
1914 * Shortcut the direct-mapped case when applicable. We never put
1915 * anything but 1:1 (or 62-bit aliased) mappings below
1916 * VM_MIN_KERNEL_ADDRESS.
1918 if (va < VM_MIN_KERNEL_ADDRESS)
1919 return (va & ~DMAP_BASE_ADDRESS);
1921 PMAP_LOCK(kernel_pmap);
1922 pvo = moea64_pvo_find_va(kernel_pmap, va);
1923 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1925 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1926 PMAP_UNLOCK(kernel_pmap);
1931 * Remove a wired page from kernel virtual address space.
1934 moea64_kremove(mmu_t mmu, vm_offset_t va)
1936 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1940 * Provide a kernel pointer corresponding to a given userland pointer.
1941 * The returned pointer is valid until the next time this function is
1942 * called in this thread. This is used internally in copyin/copyout.
1945 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1946 void **kaddr, size_t ulen, size_t *klen)
1949 #ifdef __powerpc64__
1954 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1955 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1963 #ifdef __powerpc64__
1964 /* Try lockless look-up first */
1965 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
1968 /* If it isn't there, we need to pre-fault the VSID */
1970 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
1976 /* Mark segment no-execute */
1979 slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
1981 /* Mark segment no-execute */
1985 /* If we have already set this VSID, we can just return */
1986 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
1989 __asm __volatile("isync");
1990 curthread->td_pcb->pcb_cpu.aim.usr_segm =
1991 (uintptr_t)uaddr >> ADDR_SR_SHFT;
1992 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
1993 #ifdef __powerpc64__
1994 __asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
1995 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
1997 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
2004 * Figure out where a given kernel pointer (usually in a fault) points
2005 * to from the VM's perspective, potentially remapping into userland's
2009 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
2010 vm_offset_t *decoded_addr)
2012 vm_offset_t user_sr;
2014 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
2015 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm;
2016 addr &= ADDR_PIDX | ADDR_POFF;
2017 addr |= user_sr << ADDR_SR_SHFT;
2018 *decoded_addr = addr;
2021 *decoded_addr = addr;
2029 * Map a range of physical addresses into kernel virtual address space.
2031 * The value passed in *virt is a suggested virtual address for the mapping.
2032 * Architectures which can support a direct-mapped physical to virtual region
2033 * can return the appropriate address within that region, leaving '*virt'
2034 * unchanged. Other architectures should map the pages starting at '*virt' and
2035 * update '*virt' with the first usable address after the mapped region.
2038 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2039 vm_paddr_t pa_end, int prot)
2041 vm_offset_t sva, va;
2043 if (hw_direct_map) {
2045 * Check if every page in the region is covered by the direct
2046 * map. The direct map covers all of physical memory. Use
2047 * moea64_calc_wimg() as a shortcut to see if the page is in
2048 * physical memory as a way to see if the direct map covers it.
2050 for (va = pa_start; va < pa_end; va += PAGE_SIZE)
2051 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
2054 return (PHYS_TO_DMAP(pa_start));
2058 /* XXX respect prot argument */
2059 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
2060 moea64_kenter(mmu, va, pa_start);
2067 * Returns true if the pmap's pv is one of the first
2068 * 16 pvs linked to from this page. This count may
2069 * be changed upwards or downwards in the future; it
2070 * is only necessary that true be returned for a small
2071 * subset of pmaps for proper page aging.
2074 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2077 struct pvo_entry *pvo;
2080 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2081 ("moea64_page_exists_quick: page %p is not managed", m));
2085 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2086 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
2098 moea64_page_init(mmu_t mmu __unused, vm_page_t m)
2101 m->md.mdpg_attrs = 0;
2102 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
2103 LIST_INIT(&m->md.mdpg_pvoh);
2107 * Return the number of managed mappings to the given physical page
2111 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
2113 struct pvo_entry *pvo;
2117 if ((m->oflags & VPO_UNMANAGED) != 0)
2120 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
2121 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2127 static uintptr_t moea64_vsidcontext;
2130 moea64_get_unique_vsid(void) {
2137 __asm __volatile("mftb %0" : "=r"(entropy));
2139 mtx_lock(&moea64_slb_mutex);
2140 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2144 * Create a new value by mutiplying by a prime and adding in
2145 * entropy from the timebase register. This is to make the
2146 * VSID more random so that the PT hash function collides
2147 * less often. (Note that the prime casues gcc to do shifts
2148 * instead of a multiply.)
2150 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2151 hash = moea64_vsidcontext & (NVSIDS - 1);
2152 if (hash == 0) /* 0 is special, avoid it */
2155 mask = 1 << (hash & (VSID_NBPW - 1));
2156 hash = (moea64_vsidcontext & VSID_HASHMASK);
2157 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
2158 /* anything free in this bucket? */
2159 if (moea64_vsid_bitmap[n] == 0xffffffff) {
2160 entropy = (moea64_vsidcontext >> 20);
2163 i = ffs(~moea64_vsid_bitmap[n]) - 1;
2165 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2168 if (hash == VSID_VRMA) /* also special, avoid this too */
2170 KASSERT(!(moea64_vsid_bitmap[n] & mask),
2171 ("Allocating in-use VSID %#zx\n", hash));
2172 moea64_vsid_bitmap[n] |= mask;
2173 mtx_unlock(&moea64_slb_mutex);
2177 mtx_unlock(&moea64_slb_mutex);
2178 panic("%s: out of segments",__func__);
2181 #ifdef __powerpc64__
2183 moea64_pinit(mmu_t mmu, pmap_t pmap)
2186 RB_INIT(&pmap->pmap_pvo);
2188 pmap->pm_slb_tree_root = slb_alloc_tree();
2189 pmap->pm_slb = slb_alloc_user_cache();
2190 pmap->pm_slb_len = 0;
2194 moea64_pinit(mmu_t mmu, pmap_t pmap)
2199 RB_INIT(&pmap->pmap_pvo);
2201 if (pmap_bootstrapped)
2202 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
2205 pmap->pmap_phys = pmap;
2208 * Allocate some segment registers for this pmap.
2210 hash = moea64_get_unique_vsid();
2212 for (i = 0; i < 16; i++)
2213 pmap->pm_sr[i] = VSID_MAKE(i, hash);
2215 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2220 * Initialize the pmap associated with process 0.
2223 moea64_pinit0(mmu_t mmu, pmap_t pm)
2227 moea64_pinit(mmu, pm);
2228 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2232 * Set the physical protection on the specified range of this map as requested.
2235 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2241 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2244 * Change the protection of the page.
2246 oldprot = pvo->pvo_pte.prot;
2247 pvo->pvo_pte.prot = prot;
2248 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2251 * If the PVO is in the page table, update mapping
2253 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE);
2255 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2257 if (pm != kernel_pmap && pg != NULL &&
2258 (pg->a.flags & PGA_EXECUTABLE) == 0 &&
2259 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2260 if ((pg->oflags & VPO_UNMANAGED) == 0)
2261 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2262 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2263 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE);
2267 * Update vm about the REF/CHG bits if the page is managed and we have
2268 * removed write access.
2270 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2271 (oldprot & VM_PROT_WRITE)) {
2272 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2273 if (refchg & LPTE_CHG)
2275 if (refchg & LPTE_REF)
2276 vm_page_aflag_set(pg, PGA_REFERENCED);
2281 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2284 struct pvo_entry *pvo, *tpvo, key;
2286 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2289 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2290 ("moea64_protect: non current pmap"));
2292 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2293 moea64_remove(mmu, pm, sva, eva);
2298 key.pvo_vaddr = sva;
2299 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2300 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2301 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2302 moea64_pvo_protect(mmu, pm, pvo, prot);
2308 * Map a list of wired pages into kernel virtual address space. This is
2309 * intended for temporary mappings which do not need page modification or
2310 * references recorded. Existing mappings in the region are overwritten.
2313 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2315 while (count-- > 0) {
2316 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2323 * Remove page mappings from kernel virtual address space. Intended for
2324 * temporary mappings entered by moea64_qenter.
2327 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2329 while (count-- > 0) {
2330 moea64_kremove(mmu, va);
2336 moea64_release_vsid(uint64_t vsid)
2340 mtx_lock(&moea64_slb_mutex);
2341 idx = vsid & (NVSIDS-1);
2342 mask = 1 << (idx % VSID_NBPW);
2344 KASSERT(moea64_vsid_bitmap[idx] & mask,
2345 ("Freeing unallocated VSID %#jx", vsid));
2346 moea64_vsid_bitmap[idx] &= ~mask;
2347 mtx_unlock(&moea64_slb_mutex);
2352 moea64_release(mmu_t mmu, pmap_t pmap)
2356 * Free segment registers' VSIDs
2358 #ifdef __powerpc64__
2359 slb_free_tree(pmap);
2360 slb_free_user_cache(pmap->pm_slb);
2362 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2364 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2369 * Remove all pages mapped by the specified pmap
2372 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2374 struct pvo_entry *pvo, *tpvo;
2375 struct pvo_dlist tofree;
2377 SLIST_INIT(&tofree);
2380 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2381 if (pvo->pvo_vaddr & PVO_WIRED)
2385 * For locking reasons, remove this from the page table and
2386 * pmap, but save delinking from the vm_page for a second
2389 moea64_pvo_remove_from_pmap(mmu, pvo);
2390 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink);
2394 while (!SLIST_EMPTY(&tofree)) {
2395 pvo = SLIST_FIRST(&tofree);
2396 SLIST_REMOVE_HEAD(&tofree, pvo_dlink);
2397 moea64_pvo_remove_from_page(mmu, pvo);
2398 free_pvo_entry(pvo);
2403 * Remove the given range of addresses from the specified map.
2406 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2408 struct pvo_entry *pvo, *tpvo, key;
2409 struct pvo_dlist tofree;
2412 * Perform an unsynchronized read. This is, however, safe.
2414 if (pm->pm_stats.resident_count == 0)
2417 key.pvo_vaddr = sva;
2419 SLIST_INIT(&tofree);
2422 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2423 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2424 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2427 * For locking reasons, remove this from the page table and
2428 * pmap, but save delinking from the vm_page for a second
2431 moea64_pvo_remove_from_pmap(mmu, pvo);
2432 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink);
2436 while (!SLIST_EMPTY(&tofree)) {
2437 pvo = SLIST_FIRST(&tofree);
2438 SLIST_REMOVE_HEAD(&tofree, pvo_dlink);
2439 moea64_pvo_remove_from_page(mmu, pvo);
2440 free_pvo_entry(pvo);
2445 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2446 * will reflect changes in pte's back to the vm_page.
2449 moea64_remove_all(mmu_t mmu, vm_page_t m)
2451 struct pvo_entry *pvo, *next_pvo;
2452 struct pvo_head freequeue;
2456 LIST_INIT(&freequeue);
2459 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2460 pmap = pvo->pvo_pmap;
2462 wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2464 moea64_pvo_remove_from_pmap(mmu, pvo);
2465 moea64_pvo_remove_from_page_locked(mmu, pvo, m);
2467 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2471 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2472 KASSERT((m->a.flags & PGA_WRITEABLE) == 0, ("Page still writable"));
2475 /* Clean up UMA allocations */
2476 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2477 free_pvo_entry(pvo);
2481 * Allocate a physical page of memory directly from the phys_avail map.
2482 * Can only be called from moea64_bootstrap before avail start and end are
2486 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align)
2491 size = round_page(size);
2492 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2494 s = roundup2(phys_avail[i], align);
2499 if (s < phys_avail[i] || e > phys_avail[i + 1])
2502 if (s + size > platform_real_maxaddr())
2505 if (s == phys_avail[i]) {
2506 phys_avail[i] += size;
2507 } else if (e == phys_avail[i + 1]) {
2508 phys_avail[i + 1] -= size;
2510 for (j = phys_avail_count * 2; j > i; j -= 2) {
2511 phys_avail[j] = phys_avail[j - 2];
2512 phys_avail[j + 1] = phys_avail[j - 1];
2515 phys_avail[i + 3] = phys_avail[i + 1];
2516 phys_avail[i + 1] = s;
2517 phys_avail[i + 2] = e;
2523 panic("moea64_bootstrap_alloc: could not allocate memory");
2527 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head,
2528 struct pvo_entry **oldpvop)
2530 struct pvo_entry *old_pvo;
2533 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2535 STAT_MOEA64(moea64_pvo_enter_calls++);
2540 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2542 if (old_pvo != NULL) {
2543 if (oldpvop != NULL)
2548 if (pvo_head != NULL) {
2549 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2552 if (pvo->pvo_vaddr & PVO_WIRED)
2553 pvo->pvo_pmap->pm_stats.wired_count++;
2554 pvo->pvo_pmap->pm_stats.resident_count++;
2557 * Insert it into the hardware page table
2559 err = MOEA64_PTE_INSERT(mmu, pvo);
2561 panic("moea64_pvo_enter: overflow");
2564 STAT_MOEA64(moea64_pvo_entries++);
2566 if (pvo->pvo_pmap == kernel_pmap)
2569 #ifdef __powerpc64__
2571 * Make sure all our bootstrap mappings are in the SLB as soon
2572 * as virtual memory is switched on.
2574 if (!pmap_bootstrapped)
2575 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2576 pvo->pvo_vaddr & PVO_LARGE);
2583 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo)
2588 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2589 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2590 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2593 * If there is an active pte entry, we need to deactivate it
2595 refchg = MOEA64_PTE_UNSET(mmu, pvo);
2598 * If it was evicted from the page table, be pessimistic and
2601 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2608 * Update our statistics.
2610 pvo->pvo_pmap->pm_stats.resident_count--;
2611 if (pvo->pvo_vaddr & PVO_WIRED)
2612 pvo->pvo_pmap->pm_stats.wired_count--;
2615 * Remove this PVO from the pmap list.
2617 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2620 * Mark this for the next sweep
2622 pvo->pvo_vaddr |= PVO_DEAD;
2624 /* Send RC bits to VM */
2625 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2626 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2627 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2629 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2630 if (refchg & LPTE_CHG)
2632 if (refchg & LPTE_REF)
2633 vm_page_aflag_set(pg, PGA_REFERENCED);
2639 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo,
2643 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
2645 /* Use NULL pmaps as a sentinel for races in page deletion */
2646 if (pvo->pvo_pmap == NULL)
2648 pvo->pvo_pmap = NULL;
2651 * Update vm about page writeability/executability if managed
2653 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN);
2654 if (pvo->pvo_vaddr & PVO_MANAGED) {
2656 LIST_REMOVE(pvo, pvo_vlink);
2657 if (LIST_EMPTY(vm_page_to_pvoh(m)))
2658 vm_page_aflag_clear(m,
2659 PGA_WRITEABLE | PGA_EXECUTABLE);
2663 STAT_MOEA64(moea64_pvo_entries--);
2664 STAT_MOEA64(moea64_pvo_remove_calls++);
2668 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo)
2670 vm_page_t pg = NULL;
2672 if (pvo->pvo_vaddr & PVO_MANAGED)
2673 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2675 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2676 moea64_pvo_remove_from_page_locked(mmu, pvo, pg);
2677 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2680 static struct pvo_entry *
2681 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2683 struct pvo_entry key;
2685 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2687 key.pvo_vaddr = va & ~ADDR_POFF;
2688 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2692 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit)
2694 struct pvo_entry *pvo;
2699 * See if this bit is stored in the page already.
2701 if (m->md.mdpg_attrs & ptebit)
2705 * Examine each PTE. Sync so that any pending REF/CHG bits are
2706 * flushed to the PTEs.
2711 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2715 * See if this pvo has a valid PTE. if so, fetch the
2716 * REF/CHG bits from the valid PTE. If the appropriate
2717 * ptebit is set, return success.
2719 PMAP_LOCK(pvo->pvo_pmap);
2720 if (!(pvo->pvo_vaddr & PVO_DEAD))
2721 ret = MOEA64_PTE_SYNCH(mmu, pvo);
2722 PMAP_UNLOCK(pvo->pvo_pmap);
2725 atomic_set_32(&m->md.mdpg_attrs,
2726 ret & (LPTE_CHG | LPTE_REF));
2739 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2742 struct pvo_entry *pvo;
2746 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2747 * we can reset the right ones).
2752 * For each pvo entry, clear the pte's ptebit.
2756 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2759 PMAP_LOCK(pvo->pvo_pmap);
2760 if (!(pvo->pvo_vaddr & PVO_DEAD))
2761 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit);
2762 PMAP_UNLOCK(pvo->pvo_pmap);
2764 if (ret > 0 && (ret & ptebit))
2767 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
2774 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2776 struct pvo_entry *pvo, key;
2780 if (hw_direct_map && mem_valid(pa, size) == 0)
2783 PMAP_LOCK(kernel_pmap);
2784 ppa = pa & ~ADDR_POFF;
2785 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa;
2786 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2787 ppa < pa + size; ppa += PAGE_SIZE,
2788 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2789 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) {
2794 PMAP_UNLOCK(kernel_pmap);
2800 * Map a set of physical memory pages into the kernel virtual
2801 * address space. Return a pointer to where it is mapped. This
2802 * routine is intended to be used for mapping device memory,
2806 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2808 vm_offset_t va, tmpva, ppa, offset;
2810 ppa = trunc_page(pa);
2811 offset = pa & PAGE_MASK;
2812 size = roundup2(offset + size, PAGE_SIZE);
2814 va = kva_alloc(size);
2817 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2819 for (tmpva = va; size > 0;) {
2820 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2826 return ((void *)(va + offset));
2830 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2833 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2837 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2839 vm_offset_t base, offset;
2841 base = trunc_page(va);
2842 offset = va & PAGE_MASK;
2843 size = roundup2(offset + size, PAGE_SIZE);
2845 kva_free(base, size);
2849 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2851 struct pvo_entry *pvo;
2856 if (__predict_false(pm == NULL))
2857 pm = &curthread->td_proc->p_vmspace->vm_pmap;
2861 lim = round_page(va+1);
2862 len = MIN(lim - va, sz);
2863 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2864 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
2865 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF);
2866 moea64_syncicache(mmu, pm, va, pa, len);
2875 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2878 *va = (void *)(uintptr_t)pa;
2881 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2884 moea64_scan_init(mmu_t mmu)
2886 struct pvo_entry *pvo;
2891 /* Initialize phys. segments for dumpsys(). */
2892 memset(&dump_map, 0, sizeof(dump_map));
2893 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2894 for (i = 0; i < pregions_sz; i++) {
2895 dump_map[i].pa_start = pregions[i].mr_start;
2896 dump_map[i].pa_size = pregions[i].mr_size;
2901 /* Virtual segments for minidumps: */
2902 memset(&dump_map, 0, sizeof(dump_map));
2904 /* 1st: kernel .data and .bss. */
2905 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2906 dump_map[0].pa_size = round_page((uintptr_t)_end) -
2907 dump_map[0].pa_start;
2909 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2910 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr;
2911 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2913 /* 3rd: kernel VM. */
2914 va = dump_map[1].pa_start + dump_map[1].pa_size;
2915 /* Find start of next chunk (from va). */
2916 while (va < virtual_end) {
2917 /* Don't dump the buffer cache. */
2918 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2919 va = kmi.buffer_eva;
2922 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2923 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2927 if (va < virtual_end) {
2928 dump_map[2].pa_start = va;
2930 /* Find last page in chunk. */
2931 while (va < virtual_end) {
2932 /* Don't run into the buffer cache. */
2933 if (va == kmi.buffer_sva)
2935 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2936 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD))
2940 dump_map[2].pa_size = va - dump_map[2].pa_start;
2944 #ifdef __powerpc64__
2947 moea64_scan_pmap(mmu_t mmu)
2949 struct pvo_entry *pvo;
2950 vm_paddr_t pa, pa_end;
2951 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp;
2954 lpsize = moea64_large_page_size;
2955 kstart = trunc_page((vm_offset_t)_etext);
2956 kend = round_page((vm_offset_t)_end);
2957 kstart_lp = kstart & ~moea64_large_page_mask;
2958 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask;
2960 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, "
2961 "kstart_lp=0x%016lx, kend_lp=0x%016lx",
2962 kstart, kend, kstart_lp, kend_lp);
2964 PMAP_LOCK(kernel_pmap);
2965 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) {
2966 va = pvo->pvo_vaddr;
2971 /* Skip DMAP (except kernel area) */
2972 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) {
2973 if (va & PVO_LARGE) {
2974 pgva = va & ~moea64_large_page_mask;
2975 if (pgva < kstart_lp || pgva >= kend_lp)
2978 pgva = trunc_page(va);
2979 if (pgva < kstart || pgva >= kend)
2984 pa = pvo->pvo_pte.pa & LPTE_RPGN;
2986 if (va & PVO_LARGE) {
2987 pa_end = pa + lpsize;
2988 for (; pa < pa_end; pa += PAGE_SIZE) {
2989 if (is_dumpable(pa))
2993 if (is_dumpable(pa))
2997 PMAP_UNLOCK(kernel_pmap);
2999 return (sizeof(struct lpte) * moea64_pteg_count * 8);
3002 static struct dump_context dump_ctx;
3005 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs)
3008 dump_ctx.ptex_end = moea64_pteg_count * 8;
3009 dump_ctx.blksz = blkpgs * PAGE_SIZE;
3016 moea64_scan_pmap(mmu_t mmu)
3022 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs)
3030 moea64_map_range(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_size_t npages)
3033 for (; npages > 0; --npages) {
3034 if (moea64_large_page_size != 0 &&
3035 (pa & moea64_large_page_mask) == 0 &&
3036 (va & moea64_large_page_mask) == 0 &&
3037 npages >= (moea64_large_page_size >> PAGE_SHIFT)) {
3038 PMAP_LOCK(kernel_pmap);
3039 moea64_kenter_large(mmu, va, pa, 0, 0);
3040 PMAP_UNLOCK(kernel_pmap);
3041 pa += moea64_large_page_size;
3042 va += moea64_large_page_size;
3043 npages -= (moea64_large_page_size >> PAGE_SHIFT) - 1;
3045 moea64_kenter(mmu, va, pa);
3053 moea64_page_array_startup(mmu_t mmu, long pages)
3055 long dom_pages[MAXMEMDOM];
3057 vm_offset_t va, vm_page_base;
3058 vm_size_t needed, size;
3063 vm_page_base = 0xd000000000000000ULL;
3065 /* Short-circuit single-domain systems. */
3066 if (vm_ndomains == 1) {
3067 size = round_page(pages * sizeof(struct vm_page));
3068 pa = vm_phys_early_alloc(0, size);
3069 vm_page_base = moea64_map(mmu, &vm_page_base,
3070 pa, pa + size, VM_PROT_READ | VM_PROT_WRITE);
3071 vm_page_array_size = pages;
3072 vm_page_array = (vm_page_t)vm_page_base;
3077 for (i = 0; i < MAXMEMDOM; i++)
3080 /* Now get the number of pages required per domain. */
3081 for (i = 0; i < vm_phys_nsegs; i++) {
3082 domain = vm_phys_segs[i].domain;
3083 KASSERT(domain < MAXMEMDOM,
3084 ("Invalid vm_phys_segs NUMA domain %d!\n", domain));
3085 /* Get size of vm_page_array needed for this segment. */
3086 size = btoc(vm_phys_segs[i].end - vm_phys_segs[i].start);
3087 dom_pages[domain] += size;
3090 for (i = 0; phys_avail[i + 1] != 0; i+= 2) {
3091 domain = _vm_phys_domain(phys_avail[i]);
3092 KASSERT(domain < MAXMEMDOM,
3093 ("Invalid phys_avail NUMA domain %d!\n", domain));
3094 size = btoc(phys_avail[i + 1] - phys_avail[i]);
3095 dom_pages[domain] += size;
3099 * Map in chunks that can get us all 16MB pages. There will be some
3100 * overlap between domains, but that's acceptable for now.
3102 vm_page_array_size = 0;
3104 for (i = 0; i < MAXMEMDOM && vm_page_array_size < pages; i++) {
3105 if (dom_pages[i] == 0)
3107 size = ulmin(pages - vm_page_array_size, dom_pages[i]);
3108 size = round_page(size * sizeof(struct vm_page));
3110 size = roundup2(size, moea64_large_page_size);
3111 pa = vm_phys_early_alloc(i, size);
3112 vm_page_array_size += size / sizeof(struct vm_page);
3113 moea64_map_range(mmu, va, pa, size >> PAGE_SHIFT);
3114 /* Scoot up domain 0, to reduce the domain page overlap. */
3116 vm_page_base += size - needed;
3119 vm_page_array = (vm_page_t)vm_page_base;
3120 vm_page_array_size = pages;