2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_compat.h"
113 #include "opt_kstack_pages.h"
115 #include <sys/param.h>
116 #include <sys/kernel.h>
117 #include <sys/queue.h>
118 #include <sys/cpuset.h>
120 #include <sys/lock.h>
121 #include <sys/msgbuf.h>
122 #include <sys/malloc.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rwlock.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/systm.h>
129 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
143 #include <vm/vm_pager.h>
146 #include <machine/_inttypes.h>
147 #include <machine/cpu.h>
148 #include <machine/platform.h>
149 #include <machine/frame.h>
150 #include <machine/md_var.h>
151 #include <machine/psl.h>
152 #include <machine/bat.h>
153 #include <machine/hid.h>
154 #include <machine/pte.h>
155 #include <machine/sr.h>
156 #include <machine/trap.h>
157 #include <machine/mmuvar.h>
159 #include "mmu_oea64.h"
161 #include "moea64_if.h"
163 void moea64_release_vsid(uint64_t vsid);
164 uintptr_t moea64_get_unique_vsid(void);
166 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
167 #define ENABLE_TRANS(msr) mtmsr(msr)
169 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
170 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
171 #define VSID_HASH_MASK 0x0000007fffffffffULL
175 * -- Read lock: if no modifications are being made to either the PVO lists
176 * or page table or if any modifications being made result in internal
177 * changes (e.g. wiring, protection) such that the existence of the PVOs
178 * is unchanged and they remain associated with the same pmap (in which
179 * case the changes should be protected by the pmap lock)
180 * -- Write lock: required if PTEs/PVOs are being inserted or removed.
183 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
184 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
185 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
186 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
197 * Map of physical memory regions.
199 static struct mem_region *regions;
200 static struct mem_region *pregions;
201 static u_int phys_avail_count;
202 static int regions_sz, pregions_sz;
204 extern void bs_remap_earlyboot(void);
207 * Lock for the pteg and pvo tables.
209 struct rwlock moea64_table_lock;
210 struct mtx moea64_slb_mutex;
215 u_int moea64_pteg_count;
216 u_int moea64_pteg_mask;
221 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
223 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
224 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
226 #define BPVO_POOL_SIZE 327680
227 static struct pvo_entry *moea64_bpvo_pool;
228 static int moea64_bpvo_pool_index = 0;
230 #define VSID_NBPW (sizeof(u_int32_t) * 8)
232 #define NVSIDS (NPMAPS * 16)
233 #define VSID_HASHMASK 0xffffffffUL
235 #define NVSIDS NPMAPS
236 #define VSID_HASHMASK 0xfffffUL
238 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
240 static boolean_t moea64_initialized = FALSE;
245 u_int moea64_pte_valid = 0;
246 u_int moea64_pte_overflow = 0;
247 u_int moea64_pvo_entries = 0;
248 u_int moea64_pvo_enter_calls = 0;
249 u_int moea64_pvo_remove_calls = 0;
250 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
251 &moea64_pte_valid, 0, "");
252 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
253 &moea64_pte_overflow, 0, "");
254 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
255 &moea64_pvo_entries, 0, "");
256 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
257 &moea64_pvo_enter_calls, 0, "");
258 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
259 &moea64_pvo_remove_calls, 0, "");
261 vm_offset_t moea64_scratchpage_va[2];
262 struct pvo_entry *moea64_scratchpage_pvo[2];
263 uintptr_t moea64_scratchpage_pte[2];
264 struct mtx moea64_scratchpage_mtx;
266 uint64_t moea64_large_page_mask = 0;
267 int moea64_large_page_size = 0;
268 int moea64_large_page_shift = 0;
273 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
274 vm_offset_t, vm_offset_t, uint64_t, int);
275 static void moea64_pvo_remove(mmu_t, struct pvo_entry *);
276 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
281 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
282 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
283 static void moea64_kremove(mmu_t, vm_offset_t);
284 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
285 vm_offset_t pa, vm_size_t sz);
288 * Kernel MMU interface
290 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
291 void moea64_clear_modify(mmu_t, vm_page_t);
292 void moea64_clear_reference(mmu_t, vm_page_t);
293 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
294 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
295 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
297 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
298 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
299 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
300 void moea64_init(mmu_t);
301 boolean_t moea64_is_modified(mmu_t, vm_page_t);
302 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
303 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
304 int moea64_ts_referenced(mmu_t, vm_page_t);
305 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
306 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
307 int moea64_page_wired_mappings(mmu_t, vm_page_t);
308 void moea64_pinit(mmu_t, pmap_t);
309 void moea64_pinit0(mmu_t, pmap_t);
310 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
311 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
312 void moea64_qremove(mmu_t, vm_offset_t, int);
313 void moea64_release(mmu_t, pmap_t);
314 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
315 void moea64_remove_pages(mmu_t, pmap_t);
316 void moea64_remove_all(mmu_t, vm_page_t);
317 void moea64_remove_write(mmu_t, vm_page_t);
318 void moea64_zero_page(mmu_t, vm_page_t);
319 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
320 void moea64_zero_page_idle(mmu_t, vm_page_t);
321 void moea64_activate(mmu_t, struct thread *);
322 void moea64_deactivate(mmu_t, struct thread *);
323 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
324 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
325 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
326 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
327 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
328 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
329 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
330 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
331 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
333 static mmu_method_t moea64_methods[] = {
334 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
335 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
336 MMUMETHOD(mmu_clear_reference, moea64_clear_reference),
337 MMUMETHOD(mmu_copy_page, moea64_copy_page),
338 MMUMETHOD(mmu_enter, moea64_enter),
339 MMUMETHOD(mmu_enter_object, moea64_enter_object),
340 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
341 MMUMETHOD(mmu_extract, moea64_extract),
342 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
343 MMUMETHOD(mmu_init, moea64_init),
344 MMUMETHOD(mmu_is_modified, moea64_is_modified),
345 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
346 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
347 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
348 MMUMETHOD(mmu_map, moea64_map),
349 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
350 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
351 MMUMETHOD(mmu_pinit, moea64_pinit),
352 MMUMETHOD(mmu_pinit0, moea64_pinit0),
353 MMUMETHOD(mmu_protect, moea64_protect),
354 MMUMETHOD(mmu_qenter, moea64_qenter),
355 MMUMETHOD(mmu_qremove, moea64_qremove),
356 MMUMETHOD(mmu_release, moea64_release),
357 MMUMETHOD(mmu_remove, moea64_remove),
358 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
359 MMUMETHOD(mmu_remove_all, moea64_remove_all),
360 MMUMETHOD(mmu_remove_write, moea64_remove_write),
361 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
362 MMUMETHOD(mmu_zero_page, moea64_zero_page),
363 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
364 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
365 MMUMETHOD(mmu_activate, moea64_activate),
366 MMUMETHOD(mmu_deactivate, moea64_deactivate),
367 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
369 /* Internal interfaces */
370 MMUMETHOD(mmu_mapdev, moea64_mapdev),
371 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
372 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
373 MMUMETHOD(mmu_kextract, moea64_kextract),
374 MMUMETHOD(mmu_kenter, moea64_kenter),
375 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
376 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
381 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
383 static __inline u_int
384 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
389 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
390 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
392 return (hash & moea64_pteg_mask);
395 static __inline struct pvo_head *
396 vm_page_to_pvoh(vm_page_t m)
399 return (&m->md.mdpg_pvoh);
403 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
404 uint64_t pte_lo, int flags)
408 * Construct a PTE. Default to IMB initially. Valid bit only gets
409 * set when the real pte is set in memory.
411 * Note: Don't set the valid bit for correct operation of tlb update.
413 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
414 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
416 if (flags & PVO_LARGE)
417 pt->pte_hi |= LPTE_BIG;
422 static __inline uint64_t
423 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
428 if (ma != VM_MEMATTR_DEFAULT) {
430 case VM_MEMATTR_UNCACHEABLE:
431 return (LPTE_I | LPTE_G);
432 case VM_MEMATTR_WRITE_COMBINING:
433 case VM_MEMATTR_WRITE_BACK:
434 case VM_MEMATTR_PREFETCHABLE:
436 case VM_MEMATTR_WRITE_THROUGH:
437 return (LPTE_W | LPTE_M);
442 * Assume the page is cache inhibited and access is guarded unless
443 * it's in our available memory array.
445 pte_lo = LPTE_I | LPTE_G;
446 for (i = 0; i < pregions_sz; i++) {
447 if ((pa >= pregions[i].mr_start) &&
448 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
449 pte_lo &= ~(LPTE_I | LPTE_G);
459 * Quick sort callout for comparing memory regions.
461 static int om_cmp(const void *a, const void *b);
464 om_cmp(const void *a, const void *b)
466 const struct ofw_map *mapa;
467 const struct ofw_map *mapb;
471 if (mapa->om_pa_hi < mapb->om_pa_hi)
473 else if (mapa->om_pa_hi > mapb->om_pa_hi)
475 else if (mapa->om_pa_lo < mapb->om_pa_lo)
477 else if (mapa->om_pa_lo > mapb->om_pa_lo)
484 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
486 struct ofw_map translations[sz/sizeof(struct ofw_map)];
492 bzero(translations, sz);
493 if (OF_getprop(mmu, "translations", translations, sz) == -1)
494 panic("moea64_bootstrap: can't get ofw translations");
496 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
497 sz /= sizeof(*translations);
498 qsort(translations, sz, sizeof (*translations), om_cmp);
500 for (i = 0; i < sz; i++) {
501 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
502 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va,
503 translations[i].om_len);
505 if (translations[i].om_pa_lo % PAGE_SIZE)
506 panic("OFW translation not page-aligned!");
508 pa_base = translations[i].om_pa_lo;
511 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32;
513 if (translations[i].om_pa_hi)
514 panic("OFW translations above 32-bit boundary!");
517 /* Now enter the pages for this mapping */
520 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
521 if (moea64_pvo_find_va(kernel_pmap,
522 translations[i].om_va + off) != NULL)
525 moea64_kenter(mmup, translations[i].om_va + off,
534 moea64_probe_large_page(void)
536 uint16_t pvr = mfpvr() >> 16;
542 powerpc_sync(); isync();
543 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
544 powerpc_sync(); isync();
548 moea64_large_page_size = 0x1000000; /* 16 MB */
549 moea64_large_page_shift = 24;
552 moea64_large_page_size = 0;
555 moea64_large_page_mask = moea64_large_page_size - 1;
559 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
566 cache = PCPU_GET(slb);
567 esid = va >> ADDR_SR_SHFT;
568 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
570 for (i = 0; i < 64; i++) {
571 if (cache[i].slbe == (slbe | i))
576 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
578 entry.slbv |= SLBV_L;
580 slb_insert_kernel(entry.slbe, entry.slbv);
585 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
586 vm_offset_t kernelend)
590 vm_offset_t size, off;
594 if (moea64_large_page_size == 0)
600 PMAP_LOCK(kernel_pmap);
601 for (i = 0; i < pregions_sz; i++) {
602 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
603 pregions[i].mr_size; pa += moea64_large_page_size) {
607 * Set memory access as guarded if prefetch within
608 * the page could exit the available physmem area.
610 if (pa & moea64_large_page_mask) {
611 pa &= moea64_large_page_mask;
614 if (pa + moea64_large_page_size >
615 pregions[i].mr_start + pregions[i].mr_size)
618 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
619 NULL, pa, pa, pte_lo,
620 PVO_WIRED | PVO_LARGE);
623 PMAP_UNLOCK(kernel_pmap);
626 size = sizeof(struct pvo_head) * moea64_pteg_count;
627 off = (vm_offset_t)(moea64_pvo_table);
628 for (pa = off; pa < off + size; pa += PAGE_SIZE)
629 moea64_kenter(mmup, pa, pa);
630 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
631 off = (vm_offset_t)(moea64_bpvo_pool);
632 for (pa = off; pa < off + size; pa += PAGE_SIZE)
633 moea64_kenter(mmup, pa, pa);
636 * Map certain important things, like ourselves.
638 * NOTE: We do not map the exception vector space. That code is
639 * used only in real mode, and leaving it unmapped allows us to
640 * catch NULL pointer deferences, instead of making NULL a valid
644 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
646 moea64_kenter(mmup, pa, pa);
652 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
655 vm_size_t physsz, hwphyssz;
657 #ifndef __powerpc64__
658 /* We don't have a direct map since there is no BAT */
661 /* Make sure battable is zero, since we have no BAT */
662 for (i = 0; i < 16; i++) {
663 battable[i].batu = 0;
664 battable[i].batl = 0;
667 moea64_probe_large_page();
669 /* Use a direct map if we have large page support */
670 if (moea64_large_page_size > 0)
676 /* Get physical memory regions from firmware */
677 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
678 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
680 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
681 panic("moea64_bootstrap: phys_avail too small");
683 phys_avail_count = 0;
686 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
687 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
688 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
689 regions[i].mr_start + regions[i].mr_size,
692 (physsz + regions[i].mr_size) >= hwphyssz) {
693 if (physsz < hwphyssz) {
694 phys_avail[j] = regions[i].mr_start;
695 phys_avail[j + 1] = regions[i].mr_start +
702 phys_avail[j] = regions[i].mr_start;
703 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
705 physsz += regions[i].mr_size;
708 /* Check for overlap with the kernel and exception vectors */
709 for (j = 0; j < 2*phys_avail_count; j+=2) {
710 if (phys_avail[j] < EXC_LAST)
711 phys_avail[j] += EXC_LAST;
713 if (kernelstart >= phys_avail[j] &&
714 kernelstart < phys_avail[j+1]) {
715 if (kernelend < phys_avail[j+1]) {
716 phys_avail[2*phys_avail_count] =
717 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
718 phys_avail[2*phys_avail_count + 1] =
723 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
726 if (kernelend >= phys_avail[j] &&
727 kernelend < phys_avail[j+1]) {
728 if (kernelstart > phys_avail[j]) {
729 phys_avail[2*phys_avail_count] = phys_avail[j];
730 phys_avail[2*phys_avail_count + 1] =
731 kernelstart & ~PAGE_MASK;
735 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
739 physmem = btoc(physsz);
742 moea64_pteg_count = PTEGCOUNT;
744 moea64_pteg_count = 0x1000;
746 while (moea64_pteg_count < physmem)
747 moea64_pteg_count <<= 1;
749 moea64_pteg_count >>= 1;
750 #endif /* PTEGCOUNT */
754 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
763 moea64_pteg_mask = moea64_pteg_count - 1;
766 * Allocate pv/overflow lists.
768 size = sizeof(struct pvo_head) * moea64_pteg_count;
770 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
772 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
775 for (i = 0; i < moea64_pteg_count; i++)
776 LIST_INIT(&moea64_pvo_table[i]);
780 * Initialize the lock that synchronizes access to the pteg and pvo
783 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
784 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
787 * Initialise the unmanaged pvo pool.
789 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
790 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
791 moea64_bpvo_pool_index = 0;
794 * Make sure kernel vsid is allocated as well as VSID 0.
796 #ifndef __powerpc64__
797 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
798 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
799 moea64_vsid_bitmap[0] |= 1;
803 * Initialize the kernel pmap (which is statically allocated).
806 for (i = 0; i < 64; i++) {
807 pcpup->pc_slb[i].slbv = 0;
808 pcpup->pc_slb[i].slbe = 0;
811 for (i = 0; i < 16; i++)
812 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
815 kernel_pmap->pmap_phys = kernel_pmap;
816 CPU_FILL(&kernel_pmap->pm_active);
817 RB_INIT(&kernel_pmap->pmap_pvo);
819 PMAP_LOCK_INIT(kernel_pmap);
822 * Now map in all the other buffers we allocated earlier
825 moea64_setup_direct_map(mmup, kernelstart, kernelend);
829 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
840 * Set up the Open Firmware pmap and add its mappings if not in real
844 chosen = OF_finddevice("/chosen");
845 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
846 mmu = OF_instance_to_package(mmui);
847 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
849 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
850 panic("moea64_bootstrap: too many ofw translations");
853 moea64_add_ofw_mappings(mmup, mmu, sz);
857 * Calculate the last available physical address.
859 for (i = 0; phys_avail[i + 2] != 0; i += 2)
861 Maxmem = powerpc_btop(phys_avail[i + 1]);
864 * Initialize MMU and remap early physical mappings
866 MMU_CPU_BOOTSTRAP(mmup,0);
867 mtmsr(mfmsr() | PSL_DR | PSL_IR);
869 bs_remap_earlyboot();
872 * Set the start and end of kva.
874 virtual_avail = VM_MIN_KERNEL_ADDRESS;
875 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
878 * Map the entire KVA range into the SLB. We must not fault there.
881 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
882 moea64_bootstrap_slb_prefault(va, 0);
886 * Figure out how far we can extend virtual_end into segment 16
887 * without running into existing mappings. Segment 16 is guaranteed
888 * to contain neither RAM nor devices (at least on Apple hardware),
889 * but will generally contain some OFW mappings we should not
893 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
894 PMAP_LOCK(kernel_pmap);
895 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
896 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
897 virtual_end += PAGE_SIZE;
898 PMAP_UNLOCK(kernel_pmap);
902 * Allocate a kernel stack with a guard page for thread0 and map it
903 * into the kernel page map.
905 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
906 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
907 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
908 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
909 thread0.td_kstack = va;
910 thread0.td_kstack_pages = KSTACK_PAGES;
911 for (i = 0; i < KSTACK_PAGES; i++) {
912 moea64_kenter(mmup, va, pa);
918 * Allocate virtual address space for the message buffer.
920 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
921 msgbufp = (struct msgbuf *)virtual_avail;
923 virtual_avail += round_page(msgbufsize);
924 while (va < virtual_avail) {
925 moea64_kenter(mmup, va, pa);
931 * Allocate virtual address space for the dynamic percpu area.
933 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
934 dpcpu = (void *)virtual_avail;
936 virtual_avail += DPCPU_SIZE;
937 while (va < virtual_avail) {
938 moea64_kenter(mmup, va, pa);
942 dpcpu_init(dpcpu, 0);
945 * Allocate some things for page zeroing. We put this directly
946 * in the page table, marked with LPTE_LOCKED, to avoid any
947 * of the PVO book-keeping or other parts of the VM system
948 * from even knowing that this hack exists.
951 if (!hw_direct_map) {
952 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
954 for (i = 0; i < 2; i++) {
955 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
956 virtual_end -= PAGE_SIZE;
958 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
960 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
961 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
963 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
964 mmup, moea64_scratchpage_pvo[i]);
965 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
967 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
968 &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
969 moea64_scratchpage_pvo[i]->pvo_vpn);
976 * Activate a user pmap. The pmap must be activated before its address
977 * space can be accessed in any way.
980 moea64_activate(mmu_t mmu, struct thread *td)
984 pm = &td->td_proc->p_vmspace->vm_pmap;
985 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
988 PCPU_SET(userslb, pm->pm_slb);
990 PCPU_SET(curpmap, pm->pmap_phys);
995 moea64_deactivate(mmu_t mmu, struct thread *td)
999 pm = &td->td_proc->p_vmspace->vm_pmap;
1000 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1001 #ifdef __powerpc64__
1002 PCPU_SET(userslb, NULL);
1004 PCPU_SET(curpmap, NULL);
1009 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1011 struct pvo_entry *pvo;
1018 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1021 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1024 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1025 pm->pm_stats.wired_count++;
1026 pvo->pvo_vaddr |= PVO_WIRED;
1027 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1029 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1030 pm->pm_stats.wired_count--;
1031 pvo->pvo_vaddr &= ~PVO_WIRED;
1032 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1036 /* Update wiring flag in page table. */
1037 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1041 * If we are wiring the page, and it wasn't in the
1042 * page table before, add it.
1044 vsid = PVO_VSID(pvo);
1045 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1046 pvo->pvo_vaddr & PVO_LARGE);
1048 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1051 PVO_PTEGIDX_CLR(pvo);
1052 PVO_PTEGIDX_SET(pvo, i);
1062 * This goes through and sets the physical address of our
1063 * special scratch PTE to the PA we want to zero or copy. Because
1064 * of locking issues (this can get called in pvo_enter() by
1065 * the UMA allocator), we can't use most other utility functions here
1069 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1071 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1072 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1074 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1075 ~(LPTE_WIMG | LPTE_RPGN);
1076 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1077 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1078 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1079 &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1080 moea64_scratchpage_pvo[which]->pvo_vpn);
1085 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1090 dst = VM_PAGE_TO_PHYS(mdst);
1091 src = VM_PAGE_TO_PHYS(msrc);
1093 if (hw_direct_map) {
1094 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1096 mtx_lock(&moea64_scratchpage_mtx);
1098 moea64_set_scratchpage_pa(mmu, 0, src);
1099 moea64_set_scratchpage_pa(mmu, 1, dst);
1101 bcopy((void *)moea64_scratchpage_va[0],
1102 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1104 mtx_unlock(&moea64_scratchpage_mtx);
1109 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1111 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1113 if (size + off > PAGE_SIZE)
1114 panic("moea64_zero_page: size + off > PAGE_SIZE");
1116 if (hw_direct_map) {
1117 bzero((caddr_t)pa + off, size);
1119 mtx_lock(&moea64_scratchpage_mtx);
1120 moea64_set_scratchpage_pa(mmu, 0, pa);
1121 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1122 mtx_unlock(&moea64_scratchpage_mtx);
1127 * Zero a page of physical memory by temporarily mapping it
1130 moea64_zero_page(mmu_t mmu, vm_page_t m)
1132 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1133 vm_offset_t va, off;
1135 if (!hw_direct_map) {
1136 mtx_lock(&moea64_scratchpage_mtx);
1138 moea64_set_scratchpage_pa(mmu, 0, pa);
1139 va = moea64_scratchpage_va[0];
1144 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1145 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1148 mtx_unlock(&moea64_scratchpage_mtx);
1152 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1155 moea64_zero_page(mmu, m);
1159 * Map the given physical page at the specified virtual address in the
1160 * target pmap with the protection requested. If specified the page
1161 * will be wired down.
1165 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1166 vm_prot_t prot, boolean_t wired)
1168 struct pvo_head *pvo_head;
1175 if (!moea64_initialized) {
1178 zone = moea64_upvo_zone;
1181 pvo_head = vm_page_to_pvoh(m);
1183 zone = moea64_mpvo_zone;
1184 pvo_flags = PVO_MANAGED;
1187 if ((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) == 0)
1188 VM_OBJECT_LOCK_ASSERT(m->object, RA_WLOCKED);
1190 /* XXX change the pvo head for fake pages */
1191 if ((m->oflags & VPO_UNMANAGED) != 0) {
1192 pvo_flags &= ~PVO_MANAGED;
1194 zone = moea64_upvo_zone;
1197 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1199 if (prot & VM_PROT_WRITE) {
1201 if (pmap_bootstrapped &&
1202 (m->oflags & VPO_UNMANAGED) == 0)
1203 vm_page_aflag_set(m, PGA_WRITEABLE);
1207 if ((prot & VM_PROT_EXECUTE) == 0)
1208 pte_lo |= LPTE_NOEXEC;
1211 pvo_flags |= PVO_WIRED;
1215 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1216 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1221 * Flush the page from the instruction cache if this page is
1222 * mapped executable and cacheable.
1224 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1225 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1226 vm_page_aflag_set(m, PGA_EXECUTABLE);
1227 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1232 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1237 * This is much trickier than on older systems because
1238 * we can't sync the icache on physical addresses directly
1239 * without a direct map. Instead we check a couple of cases
1240 * where the memory is already mapped in and, failing that,
1241 * use the same trick we use for page zeroing to create
1242 * a temporary mapping for this physical address.
1245 if (!pmap_bootstrapped) {
1247 * If PMAP is not bootstrapped, we are likely to be
1250 __syncicache((void *)pa, sz);
1251 } else if (pmap == kernel_pmap) {
1252 __syncicache((void *)va, sz);
1253 } else if (hw_direct_map) {
1254 __syncicache((void *)pa, sz);
1256 /* Use the scratch page to set up a temp mapping */
1258 mtx_lock(&moea64_scratchpage_mtx);
1260 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1261 __syncicache((void *)(moea64_scratchpage_va[1] +
1262 (va & ADDR_POFF)), sz);
1264 mtx_unlock(&moea64_scratchpage_mtx);
1269 * Maps a sequence of resident pages belonging to the same object.
1270 * The sequence begins with the given page m_start. This page is
1271 * mapped at the given virtual address start. Each subsequent page is
1272 * mapped at a virtual address that is offset from start by the same
1273 * amount as the page is offset from m_start within the object. The
1274 * last page in the sequence is the page with the largest offset from
1275 * m_start that can be mapped at a virtual address less than the given
1276 * virtual address end. Not every virtual page between start and end
1277 * is mapped; only those for which a resident page exists with the
1278 * corresponding offset from m_start are mapped.
1281 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1282 vm_page_t m_start, vm_prot_t prot)
1285 vm_pindex_t diff, psize;
1287 psize = atop(end - start);
1289 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1290 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1291 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1292 m = TAILQ_NEXT(m, listq);
1297 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1301 moea64_enter(mmu, pm, va, m,
1302 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1306 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1308 struct pvo_entry *pvo;
1312 pvo = moea64_pvo_find_va(pm, va);
1316 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1317 (va - PVO_VADDR(pvo));
1323 * Atomically extract and hold the physical page with the given
1324 * pmap and virtual address pair if that mapping permits the given
1328 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1330 struct pvo_entry *pvo;
1338 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1339 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1340 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1341 (prot & VM_PROT_WRITE) == 0)) {
1342 if (vm_page_pa_tryrelock(pmap,
1343 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1345 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1353 static mmu_t installed_mmu;
1356 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1359 * This entire routine is a horrible hack to avoid bothering kmem
1360 * for new KVA addresses. Because this can get called from inside
1361 * kmem allocation routines, calling kmem for a new address here
1362 * can lead to multiply locking non-recursive mutexes.
1367 int pflags, needed_lock;
1369 *flags = UMA_SLAB_PRIV;
1370 needed_lock = !PMAP_LOCKED(kernel_pmap);
1371 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
1374 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
1376 if (wait & M_NOWAIT)
1383 va = VM_PAGE_TO_PHYS(m);
1387 PMAP_LOCK(kernel_pmap);
1389 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1390 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP);
1393 PMAP_UNLOCK(kernel_pmap);
1396 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1397 bzero((void *)va, PAGE_SIZE);
1402 extern int elf32_nxstack;
1405 moea64_init(mmu_t mmu)
1408 CTR0(KTR_PMAP, "moea64_init");
1410 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1411 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1412 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1413 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1414 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1415 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1417 if (!hw_direct_map) {
1418 installed_mmu = mmu;
1419 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1420 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1423 #ifdef COMPAT_FREEBSD32
1427 moea64_initialized = TRUE;
1431 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1434 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1435 ("moea64_is_referenced: page %p is not managed", m));
1436 return (moea64_query_bit(mmu, m, PTE_REF));
1440 moea64_is_modified(mmu_t mmu, vm_page_t m)
1443 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1444 ("moea64_is_modified: page %p is not managed", m));
1447 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1448 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1449 * is clear, no PTEs can have LPTE_CHG set.
1451 VM_OBJECT_LOCK_ASSERT(m->object, RA_WLOCKED);
1452 if ((m->oflags & VPO_BUSY) == 0 &&
1453 (m->aflags & PGA_WRITEABLE) == 0)
1455 return (moea64_query_bit(mmu, m, LPTE_CHG));
1459 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1461 struct pvo_entry *pvo;
1465 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1466 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1472 moea64_clear_reference(mmu_t mmu, vm_page_t m)
1475 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1476 ("moea64_clear_reference: page %p is not managed", m));
1477 moea64_clear_bit(mmu, m, LPTE_REF);
1481 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1484 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1485 ("moea64_clear_modify: page %p is not managed", m));
1486 VM_OBJECT_LOCK_ASSERT(m->object, RA_WLOCKED);
1487 KASSERT((m->oflags & VPO_BUSY) == 0,
1488 ("moea64_clear_modify: page %p is busy", m));
1491 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1492 * set. If the object containing the page is locked and the page is
1493 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1495 if ((m->aflags & PGA_WRITEABLE) == 0)
1497 moea64_clear_bit(mmu, m, LPTE_CHG);
1501 * Clear the write and modified bits in each of the given page's mappings.
1504 moea64_remove_write(mmu_t mmu, vm_page_t m)
1506 struct pvo_entry *pvo;
1511 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1512 ("moea64_remove_write: page %p is not managed", m));
1515 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1516 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1517 * is clear, no page table entries need updating.
1519 VM_OBJECT_LOCK_ASSERT(m->object, RA_WLOCKED);
1520 if ((m->oflags & VPO_BUSY) == 0 &&
1521 (m->aflags & PGA_WRITEABLE) == 0)
1525 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1526 pmap = pvo->pvo_pmap;
1528 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1529 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1530 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1531 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1533 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1534 lo |= pvo->pvo_pte.lpte.pte_lo;
1535 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1536 MOEA64_PTE_CHANGE(mmu, pt,
1537 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1538 if (pvo->pvo_pmap == kernel_pmap)
1542 if ((lo & LPTE_CHG) != 0)
1547 vm_page_aflag_clear(m, PGA_WRITEABLE);
1551 * moea64_ts_referenced:
1553 * Return a count of reference bits for a page, clearing those bits.
1554 * It is not necessary for every reference bit to be cleared, but it
1555 * is necessary that 0 only be returned when there are truly no
1556 * reference bits set.
1558 * XXX: The exact number of bits to check and clear is a matter that
1559 * should be tested and standardized at some point in the future for
1560 * optimal aging of shared pages.
1563 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1566 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1567 ("moea64_ts_referenced: page %p is not managed", m));
1568 return (moea64_clear_bit(mmu, m, LPTE_REF));
1572 * Modify the WIMG settings of all mappings for a page.
1575 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1577 struct pvo_entry *pvo;
1578 struct pvo_head *pvo_head;
1583 if ((m->oflags & VPO_UNMANAGED) != 0) {
1584 m->md.mdpg_cache_attrs = ma;
1588 pvo_head = vm_page_to_pvoh(m);
1589 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1591 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1592 pmap = pvo->pvo_pmap;
1594 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1595 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1596 pvo->pvo_pte.lpte.pte_lo |= lo;
1598 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1600 if (pvo->pvo_pmap == kernel_pmap)
1606 m->md.mdpg_cache_attrs = ma;
1610 * Map a wired page into kernel virtual address space.
1613 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1618 pte_lo = moea64_calc_wimg(pa, ma);
1621 PMAP_LOCK(kernel_pmap);
1622 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1623 NULL, va, pa, pte_lo, PVO_WIRED);
1624 PMAP_UNLOCK(kernel_pmap);
1627 if (error != 0 && error != ENOENT)
1628 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1633 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1636 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1640 * Extract the physical page address associated with the given kernel virtual
1644 moea64_kextract(mmu_t mmu, vm_offset_t va)
1646 struct pvo_entry *pvo;
1650 * Shortcut the direct-mapped case when applicable. We never put
1651 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1653 if (va < VM_MIN_KERNEL_ADDRESS)
1656 PMAP_LOCK(kernel_pmap);
1657 pvo = moea64_pvo_find_va(kernel_pmap, va);
1658 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1660 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1661 PMAP_UNLOCK(kernel_pmap);
1666 * Remove a wired page from kernel virtual address space.
1669 moea64_kremove(mmu_t mmu, vm_offset_t va)
1671 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1675 * Map a range of physical addresses into kernel virtual address space.
1677 * The value passed in *virt is a suggested virtual address for the mapping.
1678 * Architectures which can support a direct-mapped physical to virtual region
1679 * can return the appropriate address within that region, leaving '*virt'
1680 * unchanged. We cannot and therefore do not; *virt is updated with the
1681 * first usable address after the mapped region.
1684 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1685 vm_paddr_t pa_end, int prot)
1687 vm_offset_t sva, va;
1691 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1692 moea64_kenter(mmu, va, pa_start);
1699 * Returns true if the pmap's pv is one of the first
1700 * 16 pvs linked to from this page. This count may
1701 * be changed upwards or downwards in the future; it
1702 * is only necessary that true be returned for a small
1703 * subset of pmaps for proper page aging.
1706 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1709 struct pvo_entry *pvo;
1712 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1713 ("moea64_page_exists_quick: page %p is not managed", m));
1717 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1718 if (pvo->pvo_pmap == pmap) {
1730 * Return the number of managed mappings to the given physical page
1734 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1736 struct pvo_entry *pvo;
1740 if ((m->oflags & VPO_UNMANAGED) != 0)
1743 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1744 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1750 static uintptr_t moea64_vsidcontext;
1753 moea64_get_unique_vsid(void) {
1760 __asm __volatile("mftb %0" : "=r"(entropy));
1762 mtx_lock(&moea64_slb_mutex);
1763 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1767 * Create a new value by mutiplying by a prime and adding in
1768 * entropy from the timebase register. This is to make the
1769 * VSID more random so that the PT hash function collides
1770 * less often. (Note that the prime casues gcc to do shifts
1771 * instead of a multiply.)
1773 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1774 hash = moea64_vsidcontext & (NVSIDS - 1);
1775 if (hash == 0) /* 0 is special, avoid it */
1778 mask = 1 << (hash & (VSID_NBPW - 1));
1779 hash = (moea64_vsidcontext & VSID_HASHMASK);
1780 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1781 /* anything free in this bucket? */
1782 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1783 entropy = (moea64_vsidcontext >> 20);
1786 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1788 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1791 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1792 ("Allocating in-use VSID %#zx\n", hash));
1793 moea64_vsid_bitmap[n] |= mask;
1794 mtx_unlock(&moea64_slb_mutex);
1798 mtx_unlock(&moea64_slb_mutex);
1799 panic("%s: out of segments",__func__);
1802 #ifdef __powerpc64__
1804 moea64_pinit(mmu_t mmu, pmap_t pmap)
1806 PMAP_LOCK_INIT(pmap);
1807 RB_INIT(&pmap->pmap_pvo);
1809 pmap->pm_slb_tree_root = slb_alloc_tree();
1810 pmap->pm_slb = slb_alloc_user_cache();
1811 pmap->pm_slb_len = 0;
1815 moea64_pinit(mmu_t mmu, pmap_t pmap)
1820 PMAP_LOCK_INIT(pmap);
1821 RB_INIT(&pmap->pmap_pvo);
1823 if (pmap_bootstrapped)
1824 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1827 pmap->pmap_phys = pmap;
1830 * Allocate some segment registers for this pmap.
1832 hash = moea64_get_unique_vsid();
1834 for (i = 0; i < 16; i++)
1835 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1837 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1842 * Initialize the pmap associated with process 0.
1845 moea64_pinit0(mmu_t mmu, pmap_t pm)
1847 moea64_pinit(mmu, pm);
1848 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1852 * Set the physical protection on the specified range of this map as requested.
1855 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1861 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1864 * Grab the PTE pointer before we diddle with the cached PTE
1867 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1870 * Change the protection of the page.
1872 oldlo = pvo->pvo_pte.lpte.pte_lo;
1873 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1874 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1875 if ((prot & VM_PROT_EXECUTE) == 0)
1876 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1877 if (prot & VM_PROT_WRITE)
1878 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
1880 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1882 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1885 * If the PVO is in the page table, update that pte as well.
1888 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1890 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
1891 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1892 if ((pg->oflags & VPO_UNMANAGED) == 0)
1893 vm_page_aflag_set(pg, PGA_EXECUTABLE);
1894 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
1895 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
1899 * Update vm about the REF/CHG bits if the page is managed and we have
1900 * removed write access.
1902 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
1903 (oldlo & LPTE_PP) != LPTE_BR && !(prot && VM_PROT_WRITE)) {
1905 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
1907 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
1908 vm_page_aflag_set(pg, PGA_REFERENCED);
1914 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1917 struct pvo_entry *pvo, *tpvo, key;
1919 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
1922 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1923 ("moea64_protect: non current pmap"));
1925 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1926 moea64_remove(mmu, pm, sva, eva);
1932 key.pvo_vaddr = sva;
1933 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1934 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1935 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1936 moea64_pvo_protect(mmu, pm, pvo, prot);
1943 * Map a list of wired pages into kernel virtual address space. This is
1944 * intended for temporary mappings which do not need page modification or
1945 * references recorded. Existing mappings in the region are overwritten.
1948 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
1950 while (count-- > 0) {
1951 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1958 * Remove page mappings from kernel virtual address space. Intended for
1959 * temporary mappings entered by moea64_qenter.
1962 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
1964 while (count-- > 0) {
1965 moea64_kremove(mmu, va);
1971 moea64_release_vsid(uint64_t vsid)
1975 mtx_lock(&moea64_slb_mutex);
1976 idx = vsid & (NVSIDS-1);
1977 mask = 1 << (idx % VSID_NBPW);
1979 KASSERT(moea64_vsid_bitmap[idx] & mask,
1980 ("Freeing unallocated VSID %#jx", vsid));
1981 moea64_vsid_bitmap[idx] &= ~mask;
1982 mtx_unlock(&moea64_slb_mutex);
1987 moea64_release(mmu_t mmu, pmap_t pmap)
1991 * Free segment registers' VSIDs
1993 #ifdef __powerpc64__
1994 slb_free_tree(pmap);
1995 slb_free_user_cache(pmap->pm_slb);
1997 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
1999 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2002 PMAP_LOCK_DESTROY(pmap);
2006 * Remove all pages mapped by the specified pmap
2009 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2011 struct pvo_entry *pvo, *tpvo;
2015 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2016 if (!(pvo->pvo_vaddr & PVO_WIRED))
2017 moea64_pvo_remove(mmu, pvo);
2024 * Remove the given range of addresses from the specified map.
2027 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2029 struct pvo_entry *pvo, *tpvo, key;
2032 * Perform an unsynchronized read. This is, however, safe.
2034 if (pm->pm_stats.resident_count == 0)
2039 key.pvo_vaddr = sva;
2040 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2041 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2042 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2043 moea64_pvo_remove(mmu, pvo);
2050 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2051 * will reflect changes in pte's back to the vm_page.
2054 moea64_remove_all(mmu_t mmu, vm_page_t m)
2056 struct pvo_entry *pvo, *next_pvo;
2060 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2061 pmap = pvo->pvo_pmap;
2063 moea64_pvo_remove(mmu, pvo);
2067 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2069 vm_page_aflag_clear(m, PGA_WRITEABLE);
2070 vm_page_aflag_clear(m, PGA_EXECUTABLE);
2074 * Allocate a physical page of memory directly from the phys_avail map.
2075 * Can only be called from moea64_bootstrap before avail start and end are
2079 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2084 size = round_page(size);
2085 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2087 s = (phys_avail[i] + align - 1) & ~(align - 1);
2092 if (s < phys_avail[i] || e > phys_avail[i + 1])
2095 if (s + size > platform_real_maxaddr())
2098 if (s == phys_avail[i]) {
2099 phys_avail[i] += size;
2100 } else if (e == phys_avail[i + 1]) {
2101 phys_avail[i + 1] -= size;
2103 for (j = phys_avail_count * 2; j > i; j -= 2) {
2104 phys_avail[j] = phys_avail[j - 2];
2105 phys_avail[j + 1] = phys_avail[j - 1];
2108 phys_avail[i + 3] = phys_avail[i + 1];
2109 phys_avail[i + 1] = s;
2110 phys_avail[i + 2] = e;
2116 panic("moea64_bootstrap_alloc: could not allocate memory");
2120 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2121 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2122 uint64_t pte_lo, int flags)
2124 struct pvo_entry *pvo;
2132 * One nasty thing that can happen here is that the UMA calls to
2133 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2134 * which calls UMA...
2136 * We break the loop by detecting recursion and allocating out of
2137 * the bootstrap pool.
2141 bootstrap = (flags & PVO_BOOTSTRAP);
2143 if (!moea64_initialized)
2146 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2147 rw_assert(&moea64_table_lock, RA_WLOCKED);
2150 * Compute the PTE Group index.
2153 vsid = va_to_vsid(pm, va);
2154 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2157 * Remove any existing mapping for this page. Reuse the pvo entry if
2158 * there is a mapping.
2160 moea64_pvo_enter_calls++;
2162 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2163 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2164 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2165 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2166 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2167 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2168 /* Re-insert if spilled */
2169 i = MOEA64_PTE_INSERT(mmu, ptegidx,
2170 &pvo->pvo_pte.lpte);
2172 PVO_PTEGIDX_SET(pvo, i);
2173 moea64_pte_overflow--;
2177 moea64_pvo_remove(mmu, pvo);
2183 * If we aren't overwriting a mapping, try to allocate.
2186 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2187 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2188 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2189 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2191 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2192 moea64_bpvo_pool_index++;
2195 pvo = uma_zalloc(zone, M_NOWAIT);
2201 moea64_pvo_entries++;
2202 pvo->pvo_vaddr = va;
2203 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2206 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2207 pvo->pvo_vaddr &= ~ADDR_POFF;
2209 if (flags & PVO_WIRED)
2210 pvo->pvo_vaddr |= PVO_WIRED;
2211 if (pvo_head != NULL)
2212 pvo->pvo_vaddr |= PVO_MANAGED;
2214 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2215 if (flags & PVO_LARGE)
2216 pvo->pvo_vaddr |= PVO_LARGE;
2218 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2219 (uint64_t)(pa) | pte_lo, flags);
2224 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2227 * Remember if the list was empty and therefore will be the first
2230 if (pvo_head != NULL) {
2231 if (LIST_FIRST(pvo_head) == NULL)
2233 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2236 if (pvo->pvo_vaddr & PVO_WIRED) {
2237 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2238 pm->pm_stats.wired_count++;
2240 pm->pm_stats.resident_count++;
2243 * We hope this succeeds but it isn't required.
2245 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2247 PVO_PTEGIDX_SET(pvo, i);
2249 panic("moea64_pvo_enter: overflow");
2250 moea64_pte_overflow++;
2253 if (pm == kernel_pmap)
2256 #ifdef __powerpc64__
2258 * Make sure all our bootstrap mappings are in the SLB as soon
2259 * as virtual memory is switched on.
2261 if (!pmap_bootstrapped)
2262 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2265 return (first ? ENOENT : 0);
2269 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2274 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2275 rw_assert(&moea64_table_lock, RA_WLOCKED);
2278 * If there is an active pte entry, we need to deactivate it (and
2279 * save the ref & cfg bits).
2281 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2283 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2284 PVO_PTEGIDX_CLR(pvo);
2286 moea64_pte_overflow--;
2290 * Update our statistics.
2292 pvo->pvo_pmap->pm_stats.resident_count--;
2293 if (pvo->pvo_vaddr & PVO_WIRED)
2294 pvo->pvo_pmap->pm_stats.wired_count--;
2297 * Remove this PVO from the pmap list.
2299 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2302 * Remove this from the overflow list and return it to the pool
2303 * if we aren't going to reuse it.
2305 LIST_REMOVE(pvo, pvo_olink);
2308 * Update vm about the REF/CHG bits if the page is managed.
2310 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2312 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2313 LIST_REMOVE(pvo, pvo_vlink);
2314 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2315 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2317 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2318 vm_page_aflag_set(pg, PGA_REFERENCED);
2319 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2320 vm_page_aflag_clear(pg, PGA_WRITEABLE);
2322 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2323 vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2326 moea64_pvo_entries--;
2327 moea64_pvo_remove_calls++;
2329 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2330 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2331 moea64_upvo_zone, pvo);
2334 static struct pvo_entry *
2335 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2337 struct pvo_entry key;
2339 key.pvo_vaddr = va & ~ADDR_POFF;
2340 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2344 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2346 struct pvo_entry *pvo;
2350 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2352 * See if we saved the bit off. If so, return success.
2354 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2361 * No luck, now go through the hard part of looking at the PTEs
2362 * themselves. Sync so that any pending REF/CHG bits are flushed to
2366 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2369 * See if this pvo has a valid PTE. if so, fetch the
2370 * REF/CHG bits from the valid PTE. If the appropriate
2371 * ptebit is set, return success.
2373 PMAP_LOCK(pvo->pvo_pmap);
2374 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2376 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2377 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2378 PMAP_UNLOCK(pvo->pvo_pmap);
2383 PMAP_UNLOCK(pvo->pvo_pmap);
2391 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2394 struct pvo_entry *pvo;
2398 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2399 * we can reset the right ones). note that since the pvo entries and
2400 * list heads are accessed via BAT0 and are never placed in the page
2401 * table, we don't have to worry about further accesses setting the
2407 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2408 * valid pte clear the ptebit from the valid pte.
2412 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2413 PMAP_LOCK(pvo->pvo_pmap);
2414 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2416 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2417 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2419 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2420 pvo->pvo_vpn, ptebit);
2423 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2424 PMAP_UNLOCK(pvo->pvo_pmap);
2432 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2434 struct pvo_entry *pvo, key;
2438 PMAP_LOCK(kernel_pmap);
2439 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2440 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2441 ppa < pa + size; ppa += PAGE_SIZE,
2442 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2444 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2449 PMAP_UNLOCK(kernel_pmap);
2455 * Map a set of physical memory pages into the kernel virtual
2456 * address space. Return a pointer to where it is mapped. This
2457 * routine is intended to be used for mapping device memory,
2461 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2463 vm_offset_t va, tmpva, ppa, offset;
2465 ppa = trunc_page(pa);
2466 offset = pa & PAGE_MASK;
2467 size = roundup2(offset + size, PAGE_SIZE);
2469 va = kmem_alloc_nofault(kernel_map, size);
2472 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2474 for (tmpva = va; size > 0;) {
2475 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2481 return ((void *)(va + offset));
2485 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2488 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2492 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2494 vm_offset_t base, offset;
2496 base = trunc_page(va);
2497 offset = va & PAGE_MASK;
2498 size = roundup2(offset + size, PAGE_SIZE);
2500 kmem_free(kernel_map, base, size);
2504 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2506 struct pvo_entry *pvo;
2513 lim = round_page(va);
2514 len = MIN(lim - va, sz);
2515 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2516 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2517 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2519 moea64_syncicache(mmu, pm, va, pa, len);