2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_compat.h"
113 #include "opt_kstack_pages.h"
115 #include <sys/param.h>
116 #include <sys/kernel.h>
117 #include <sys/queue.h>
118 #include <sys/cpuset.h>
120 #include <sys/lock.h>
121 #include <sys/msgbuf.h>
122 #include <sys/malloc.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rwlock.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/systm.h>
129 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
145 #include <machine/_inttypes.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/frame.h>
149 #include <machine/md_var.h>
150 #include <machine/psl.h>
151 #include <machine/bat.h>
152 #include <machine/hid.h>
153 #include <machine/pte.h>
154 #include <machine/sr.h>
155 #include <machine/trap.h>
156 #include <machine/mmuvar.h>
158 #include "mmu_oea64.h"
160 #include "moea64_if.h"
162 void moea64_release_vsid(uint64_t vsid);
163 uintptr_t moea64_get_unique_vsid(void);
165 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
166 #define ENABLE_TRANS(msr) mtmsr(msr)
168 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
169 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
170 #define VSID_HASH_MASK 0x0000007fffffffffULL
174 * -- Read lock: if no modifications are being made to either the PVO lists
175 * or page table or if any modifications being made result in internal
176 * changes (e.g. wiring, protection) such that the existence of the PVOs
177 * is unchanged and they remain associated with the same pmap (in which
178 * case the changes should be protected by the pmap lock)
179 * -- Write lock: required if PTEs/PVOs are being inserted or removed.
182 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
183 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
184 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
185 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
196 * Map of physical memory regions.
198 static struct mem_region *regions;
199 static struct mem_region *pregions;
200 static u_int phys_avail_count;
201 static int regions_sz, pregions_sz;
203 extern void bs_remap_earlyboot(void);
206 * Lock for the pteg and pvo tables.
208 struct rwlock moea64_table_lock;
209 struct mtx moea64_slb_mutex;
214 u_int moea64_pteg_count;
215 u_int moea64_pteg_mask;
220 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
222 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
223 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
225 #define BPVO_POOL_SIZE 327680
226 static struct pvo_entry *moea64_bpvo_pool;
227 static int moea64_bpvo_pool_index = 0;
229 #define VSID_NBPW (sizeof(u_int32_t) * 8)
231 #define NVSIDS (NPMAPS * 16)
232 #define VSID_HASHMASK 0xffffffffUL
234 #define NVSIDS NPMAPS
235 #define VSID_HASHMASK 0xfffffUL
237 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
239 static boolean_t moea64_initialized = FALSE;
244 u_int moea64_pte_valid = 0;
245 u_int moea64_pte_overflow = 0;
246 u_int moea64_pvo_entries = 0;
247 u_int moea64_pvo_enter_calls = 0;
248 u_int moea64_pvo_remove_calls = 0;
249 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
250 &moea64_pte_valid, 0, "");
251 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
252 &moea64_pte_overflow, 0, "");
253 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
254 &moea64_pvo_entries, 0, "");
255 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
256 &moea64_pvo_enter_calls, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
258 &moea64_pvo_remove_calls, 0, "");
260 vm_offset_t moea64_scratchpage_va[2];
261 struct pvo_entry *moea64_scratchpage_pvo[2];
262 uintptr_t moea64_scratchpage_pte[2];
263 struct mtx moea64_scratchpage_mtx;
265 uint64_t moea64_large_page_mask = 0;
266 uint64_t moea64_large_page_size = 0;
267 int moea64_large_page_shift = 0;
272 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
273 vm_offset_t, vm_offset_t, uint64_t, int);
274 static void moea64_pvo_remove(mmu_t, struct pvo_entry *);
275 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
280 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
281 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
282 static void moea64_kremove(mmu_t, vm_offset_t);
283 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
284 vm_offset_t pa, vm_size_t sz);
287 * Kernel MMU interface
289 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
290 void moea64_clear_modify(mmu_t, vm_page_t);
291 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
292 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
293 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
294 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
295 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
297 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
298 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
299 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
300 void moea64_init(mmu_t);
301 boolean_t moea64_is_modified(mmu_t, vm_page_t);
302 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
303 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
304 int moea64_ts_referenced(mmu_t, vm_page_t);
305 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
306 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
307 int moea64_page_wired_mappings(mmu_t, vm_page_t);
308 void moea64_pinit(mmu_t, pmap_t);
309 void moea64_pinit0(mmu_t, pmap_t);
310 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
311 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
312 void moea64_qremove(mmu_t, vm_offset_t, int);
313 void moea64_release(mmu_t, pmap_t);
314 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
315 void moea64_remove_pages(mmu_t, pmap_t);
316 void moea64_remove_all(mmu_t, vm_page_t);
317 void moea64_remove_write(mmu_t, vm_page_t);
318 void moea64_zero_page(mmu_t, vm_page_t);
319 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
320 void moea64_zero_page_idle(mmu_t, vm_page_t);
321 void moea64_activate(mmu_t, struct thread *);
322 void moea64_deactivate(mmu_t, struct thread *);
323 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
324 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
325 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
326 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
327 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
328 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
329 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
330 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
331 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
333 static mmu_method_t moea64_methods[] = {
334 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
335 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
336 MMUMETHOD(mmu_copy_page, moea64_copy_page),
337 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
338 MMUMETHOD(mmu_enter, moea64_enter),
339 MMUMETHOD(mmu_enter_object, moea64_enter_object),
340 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
341 MMUMETHOD(mmu_extract, moea64_extract),
342 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
343 MMUMETHOD(mmu_init, moea64_init),
344 MMUMETHOD(mmu_is_modified, moea64_is_modified),
345 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
346 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
347 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
348 MMUMETHOD(mmu_map, moea64_map),
349 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
350 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
351 MMUMETHOD(mmu_pinit, moea64_pinit),
352 MMUMETHOD(mmu_pinit0, moea64_pinit0),
353 MMUMETHOD(mmu_protect, moea64_protect),
354 MMUMETHOD(mmu_qenter, moea64_qenter),
355 MMUMETHOD(mmu_qremove, moea64_qremove),
356 MMUMETHOD(mmu_release, moea64_release),
357 MMUMETHOD(mmu_remove, moea64_remove),
358 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
359 MMUMETHOD(mmu_remove_all, moea64_remove_all),
360 MMUMETHOD(mmu_remove_write, moea64_remove_write),
361 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
362 MMUMETHOD(mmu_zero_page, moea64_zero_page),
363 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
364 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
365 MMUMETHOD(mmu_activate, moea64_activate),
366 MMUMETHOD(mmu_deactivate, moea64_deactivate),
367 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
369 /* Internal interfaces */
370 MMUMETHOD(mmu_mapdev, moea64_mapdev),
371 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
372 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
373 MMUMETHOD(mmu_kextract, moea64_kextract),
374 MMUMETHOD(mmu_kenter, moea64_kenter),
375 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
376 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
381 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
383 static __inline u_int
384 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
389 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
390 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
392 return (hash & moea64_pteg_mask);
395 static __inline struct pvo_head *
396 vm_page_to_pvoh(vm_page_t m)
399 return (&m->md.mdpg_pvoh);
403 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
404 uint64_t pte_lo, int flags)
408 * Construct a PTE. Default to IMB initially. Valid bit only gets
409 * set when the real pte is set in memory.
411 * Note: Don't set the valid bit for correct operation of tlb update.
413 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
414 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
416 if (flags & PVO_LARGE)
417 pt->pte_hi |= LPTE_BIG;
422 static __inline uint64_t
423 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
428 if (ma != VM_MEMATTR_DEFAULT) {
430 case VM_MEMATTR_UNCACHEABLE:
431 return (LPTE_I | LPTE_G);
432 case VM_MEMATTR_WRITE_COMBINING:
433 case VM_MEMATTR_WRITE_BACK:
434 case VM_MEMATTR_PREFETCHABLE:
436 case VM_MEMATTR_WRITE_THROUGH:
437 return (LPTE_W | LPTE_M);
442 * Assume the page is cache inhibited and access is guarded unless
443 * it's in our available memory array.
445 pte_lo = LPTE_I | LPTE_G;
446 for (i = 0; i < pregions_sz; i++) {
447 if ((pa >= pregions[i].mr_start) &&
448 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
449 pte_lo &= ~(LPTE_I | LPTE_G);
459 * Quick sort callout for comparing memory regions.
461 static int om_cmp(const void *a, const void *b);
464 om_cmp(const void *a, const void *b)
466 const struct ofw_map *mapa;
467 const struct ofw_map *mapb;
471 if (mapa->om_pa_hi < mapb->om_pa_hi)
473 else if (mapa->om_pa_hi > mapb->om_pa_hi)
475 else if (mapa->om_pa_lo < mapb->om_pa_lo)
477 else if (mapa->om_pa_lo > mapb->om_pa_lo)
484 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
486 struct ofw_map translations[sz/sizeof(struct ofw_map)];
492 bzero(translations, sz);
493 if (OF_getprop(mmu, "translations", translations, sz) == -1)
494 panic("moea64_bootstrap: can't get ofw translations");
496 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
497 sz /= sizeof(*translations);
498 qsort(translations, sz, sizeof (*translations), om_cmp);
500 for (i = 0; i < sz; i++) {
501 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
502 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va,
503 translations[i].om_len);
505 if (translations[i].om_pa_lo % PAGE_SIZE)
506 panic("OFW translation not page-aligned!");
508 pa_base = translations[i].om_pa_lo;
511 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32;
513 if (translations[i].om_pa_hi)
514 panic("OFW translations above 32-bit boundary!");
517 /* Now enter the pages for this mapping */
520 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
521 if (moea64_pvo_find_va(kernel_pmap,
522 translations[i].om_va + off) != NULL)
525 moea64_kenter(mmup, translations[i].om_va + off,
534 moea64_probe_large_page(void)
536 uint16_t pvr = mfpvr() >> 16;
542 powerpc_sync(); isync();
543 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
544 powerpc_sync(); isync();
548 moea64_large_page_size = 0x1000000; /* 16 MB */
549 moea64_large_page_shift = 24;
552 moea64_large_page_mask = moea64_large_page_size - 1;
556 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
563 cache = PCPU_GET(slb);
564 esid = va >> ADDR_SR_SHFT;
565 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
567 for (i = 0; i < 64; i++) {
568 if (cache[i].slbe == (slbe | i))
573 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
575 entry.slbv |= SLBV_L;
577 slb_insert_kernel(entry.slbe, entry.slbv);
582 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
583 vm_offset_t kernelend)
587 vm_offset_t size, off;
591 if (moea64_large_page_size == 0)
597 PMAP_LOCK(kernel_pmap);
598 for (i = 0; i < pregions_sz; i++) {
599 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
600 pregions[i].mr_size; pa += moea64_large_page_size) {
604 * Set memory access as guarded if prefetch within
605 * the page could exit the available physmem area.
607 if (pa & moea64_large_page_mask) {
608 pa &= moea64_large_page_mask;
611 if (pa + moea64_large_page_size >
612 pregions[i].mr_start + pregions[i].mr_size)
615 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
616 NULL, pa, pa, pte_lo,
617 PVO_WIRED | PVO_LARGE);
620 PMAP_UNLOCK(kernel_pmap);
623 size = sizeof(struct pvo_head) * moea64_pteg_count;
624 off = (vm_offset_t)(moea64_pvo_table);
625 for (pa = off; pa < off + size; pa += PAGE_SIZE)
626 moea64_kenter(mmup, pa, pa);
627 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
628 off = (vm_offset_t)(moea64_bpvo_pool);
629 for (pa = off; pa < off + size; pa += PAGE_SIZE)
630 moea64_kenter(mmup, pa, pa);
633 * Map certain important things, like ourselves.
635 * NOTE: We do not map the exception vector space. That code is
636 * used only in real mode, and leaving it unmapped allows us to
637 * catch NULL pointer deferences, instead of making NULL a valid
641 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
643 moea64_kenter(mmup, pa, pa);
648 * Allow user to override unmapped_buf_allowed for testing.
649 * XXXKIB Only direct map implementation was tested.
651 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
652 &unmapped_buf_allowed))
653 unmapped_buf_allowed = hw_direct_map;
657 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
660 vm_size_t physsz, hwphyssz;
662 #ifndef __powerpc64__
663 /* We don't have a direct map since there is no BAT */
666 /* Make sure battable is zero, since we have no BAT */
667 for (i = 0; i < 16; i++) {
668 battable[i].batu = 0;
669 battable[i].batl = 0;
672 moea64_probe_large_page();
674 /* Use a direct map if we have large page support */
675 if (moea64_large_page_size > 0)
681 /* Get physical memory regions from firmware */
682 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
683 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
685 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
686 panic("moea64_bootstrap: phys_avail too small");
688 phys_avail_count = 0;
691 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
692 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
693 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
694 regions[i].mr_start + regions[i].mr_size,
697 (physsz + regions[i].mr_size) >= hwphyssz) {
698 if (physsz < hwphyssz) {
699 phys_avail[j] = regions[i].mr_start;
700 phys_avail[j + 1] = regions[i].mr_start +
707 phys_avail[j] = regions[i].mr_start;
708 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
710 physsz += regions[i].mr_size;
713 /* Check for overlap with the kernel and exception vectors */
714 for (j = 0; j < 2*phys_avail_count; j+=2) {
715 if (phys_avail[j] < EXC_LAST)
716 phys_avail[j] += EXC_LAST;
718 if (kernelstart >= phys_avail[j] &&
719 kernelstart < phys_avail[j+1]) {
720 if (kernelend < phys_avail[j+1]) {
721 phys_avail[2*phys_avail_count] =
722 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
723 phys_avail[2*phys_avail_count + 1] =
728 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
731 if (kernelend >= phys_avail[j] &&
732 kernelend < phys_avail[j+1]) {
733 if (kernelstart > phys_avail[j]) {
734 phys_avail[2*phys_avail_count] = phys_avail[j];
735 phys_avail[2*phys_avail_count + 1] =
736 kernelstart & ~PAGE_MASK;
740 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
744 physmem = btoc(physsz);
747 moea64_pteg_count = PTEGCOUNT;
749 moea64_pteg_count = 0x1000;
751 while (moea64_pteg_count < physmem)
752 moea64_pteg_count <<= 1;
754 moea64_pteg_count >>= 1;
755 #endif /* PTEGCOUNT */
759 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
768 moea64_pteg_mask = moea64_pteg_count - 1;
771 * Allocate pv/overflow lists.
773 size = sizeof(struct pvo_head) * moea64_pteg_count;
775 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
777 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
780 for (i = 0; i < moea64_pteg_count; i++)
781 LIST_INIT(&moea64_pvo_table[i]);
785 * Initialize the lock that synchronizes access to the pteg and pvo
788 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
789 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
792 * Initialise the unmanaged pvo pool.
794 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
795 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
796 moea64_bpvo_pool_index = 0;
799 * Make sure kernel vsid is allocated as well as VSID 0.
801 #ifndef __powerpc64__
802 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
803 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
804 moea64_vsid_bitmap[0] |= 1;
808 * Initialize the kernel pmap (which is statically allocated).
811 for (i = 0; i < 64; i++) {
812 pcpup->pc_slb[i].slbv = 0;
813 pcpup->pc_slb[i].slbe = 0;
816 for (i = 0; i < 16; i++)
817 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
820 kernel_pmap->pmap_phys = kernel_pmap;
821 CPU_FILL(&kernel_pmap->pm_active);
822 RB_INIT(&kernel_pmap->pmap_pvo);
824 PMAP_LOCK_INIT(kernel_pmap);
827 * Now map in all the other buffers we allocated earlier
830 moea64_setup_direct_map(mmup, kernelstart, kernelend);
834 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
845 * Set up the Open Firmware pmap and add its mappings if not in real
849 chosen = OF_finddevice("/chosen");
850 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
851 mmu = OF_instance_to_package(mmui);
852 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
854 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
855 panic("moea64_bootstrap: too many ofw translations");
858 moea64_add_ofw_mappings(mmup, mmu, sz);
862 * Calculate the last available physical address.
864 for (i = 0; phys_avail[i + 2] != 0; i += 2)
866 Maxmem = powerpc_btop(phys_avail[i + 1]);
869 * Initialize MMU and remap early physical mappings
871 MMU_CPU_BOOTSTRAP(mmup,0);
872 mtmsr(mfmsr() | PSL_DR | PSL_IR);
874 bs_remap_earlyboot();
877 * Set the start and end of kva.
879 virtual_avail = VM_MIN_KERNEL_ADDRESS;
880 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
883 * Map the entire KVA range into the SLB. We must not fault there.
886 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
887 moea64_bootstrap_slb_prefault(va, 0);
891 * Figure out how far we can extend virtual_end into segment 16
892 * without running into existing mappings. Segment 16 is guaranteed
893 * to contain neither RAM nor devices (at least on Apple hardware),
894 * but will generally contain some OFW mappings we should not
898 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
899 PMAP_LOCK(kernel_pmap);
900 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
901 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
902 virtual_end += PAGE_SIZE;
903 PMAP_UNLOCK(kernel_pmap);
907 * Allocate a kernel stack with a guard page for thread0 and map it
908 * into the kernel page map.
910 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
911 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
912 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
913 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
914 thread0.td_kstack = va;
915 thread0.td_kstack_pages = KSTACK_PAGES;
916 for (i = 0; i < KSTACK_PAGES; i++) {
917 moea64_kenter(mmup, va, pa);
923 * Allocate virtual address space for the message buffer.
925 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
926 msgbufp = (struct msgbuf *)virtual_avail;
928 virtual_avail += round_page(msgbufsize);
929 while (va < virtual_avail) {
930 moea64_kenter(mmup, va, pa);
936 * Allocate virtual address space for the dynamic percpu area.
938 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
939 dpcpu = (void *)virtual_avail;
941 virtual_avail += DPCPU_SIZE;
942 while (va < virtual_avail) {
943 moea64_kenter(mmup, va, pa);
947 dpcpu_init(dpcpu, 0);
950 * Allocate some things for page zeroing. We put this directly
951 * in the page table, marked with LPTE_LOCKED, to avoid any
952 * of the PVO book-keeping or other parts of the VM system
953 * from even knowing that this hack exists.
956 if (!hw_direct_map) {
957 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
959 for (i = 0; i < 2; i++) {
960 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
961 virtual_end -= PAGE_SIZE;
963 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
965 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
966 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
968 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
969 mmup, moea64_scratchpage_pvo[i]);
970 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
972 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
973 &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
974 moea64_scratchpage_pvo[i]->pvo_vpn);
981 * Activate a user pmap. The pmap must be activated before its address
982 * space can be accessed in any way.
985 moea64_activate(mmu_t mmu, struct thread *td)
989 pm = &td->td_proc->p_vmspace->vm_pmap;
990 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
993 PCPU_SET(userslb, pm->pm_slb);
995 PCPU_SET(curpmap, pm->pmap_phys);
1000 moea64_deactivate(mmu_t mmu, struct thread *td)
1004 pm = &td->td_proc->p_vmspace->vm_pmap;
1005 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1006 #ifdef __powerpc64__
1007 PCPU_SET(userslb, NULL);
1009 PCPU_SET(curpmap, NULL);
1014 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1016 struct pvo_entry *pvo;
1023 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1026 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1029 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1030 pm->pm_stats.wired_count++;
1031 pvo->pvo_vaddr |= PVO_WIRED;
1032 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1034 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1035 pm->pm_stats.wired_count--;
1036 pvo->pvo_vaddr &= ~PVO_WIRED;
1037 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1041 /* Update wiring flag in page table. */
1042 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1046 * If we are wiring the page, and it wasn't in the
1047 * page table before, add it.
1049 vsid = PVO_VSID(pvo);
1050 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1051 pvo->pvo_vaddr & PVO_LARGE);
1053 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1056 PVO_PTEGIDX_CLR(pvo);
1057 PVO_PTEGIDX_SET(pvo, i);
1067 * This goes through and sets the physical address of our
1068 * special scratch PTE to the PA we want to zero or copy. Because
1069 * of locking issues (this can get called in pvo_enter() by
1070 * the UMA allocator), we can't use most other utility functions here
1074 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1076 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1077 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1079 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1080 ~(LPTE_WIMG | LPTE_RPGN);
1081 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1082 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1083 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1084 &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1085 moea64_scratchpage_pvo[which]->pvo_vpn);
1090 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1095 dst = VM_PAGE_TO_PHYS(mdst);
1096 src = VM_PAGE_TO_PHYS(msrc);
1098 if (hw_direct_map) {
1099 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1101 mtx_lock(&moea64_scratchpage_mtx);
1103 moea64_set_scratchpage_pa(mmu, 0, src);
1104 moea64_set_scratchpage_pa(mmu, 1, dst);
1106 bcopy((void *)moea64_scratchpage_va[0],
1107 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1109 mtx_unlock(&moea64_scratchpage_mtx);
1114 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1115 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1118 vm_offset_t a_pg_offset, b_pg_offset;
1121 while (xfersize > 0) {
1122 a_pg_offset = a_offset & PAGE_MASK;
1123 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1124 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1126 b_pg_offset = b_offset & PAGE_MASK;
1127 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1128 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1130 bcopy(a_cp, b_cp, cnt);
1138 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1139 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1142 vm_offset_t a_pg_offset, b_pg_offset;
1145 mtx_lock(&moea64_scratchpage_mtx);
1146 while (xfersize > 0) {
1147 a_pg_offset = a_offset & PAGE_MASK;
1148 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1149 moea64_set_scratchpage_pa(mmu, 0,
1150 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1151 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1152 b_pg_offset = b_offset & PAGE_MASK;
1153 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1154 moea64_set_scratchpage_pa(mmu, 1,
1155 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1156 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1157 bcopy(a_cp, b_cp, cnt);
1162 mtx_unlock(&moea64_scratchpage_mtx);
1166 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1167 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1170 if (hw_direct_map) {
1171 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1174 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1180 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1182 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1184 if (size + off > PAGE_SIZE)
1185 panic("moea64_zero_page: size + off > PAGE_SIZE");
1187 if (hw_direct_map) {
1188 bzero((caddr_t)pa + off, size);
1190 mtx_lock(&moea64_scratchpage_mtx);
1191 moea64_set_scratchpage_pa(mmu, 0, pa);
1192 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1193 mtx_unlock(&moea64_scratchpage_mtx);
1198 * Zero a page of physical memory by temporarily mapping it
1201 moea64_zero_page(mmu_t mmu, vm_page_t m)
1203 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1204 vm_offset_t va, off;
1206 if (!hw_direct_map) {
1207 mtx_lock(&moea64_scratchpage_mtx);
1209 moea64_set_scratchpage_pa(mmu, 0, pa);
1210 va = moea64_scratchpage_va[0];
1215 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1216 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1219 mtx_unlock(&moea64_scratchpage_mtx);
1223 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1226 moea64_zero_page(mmu, m);
1230 * Map the given physical page at the specified virtual address in the
1231 * target pmap with the protection requested. If specified the page
1232 * will be wired down.
1236 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1237 vm_prot_t prot, boolean_t wired)
1239 struct pvo_head *pvo_head;
1246 if (!moea64_initialized) {
1249 zone = moea64_upvo_zone;
1252 pvo_head = vm_page_to_pvoh(m);
1254 zone = moea64_mpvo_zone;
1255 pvo_flags = PVO_MANAGED;
1258 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1259 VM_OBJECT_ASSERT_LOCKED(m->object);
1261 /* XXX change the pvo head for fake pages */
1262 if ((m->oflags & VPO_UNMANAGED) != 0) {
1263 pvo_flags &= ~PVO_MANAGED;
1265 zone = moea64_upvo_zone;
1268 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1270 if (prot & VM_PROT_WRITE) {
1272 if (pmap_bootstrapped &&
1273 (m->oflags & VPO_UNMANAGED) == 0)
1274 vm_page_aflag_set(m, PGA_WRITEABLE);
1278 if ((prot & VM_PROT_EXECUTE) == 0)
1279 pte_lo |= LPTE_NOEXEC;
1282 pvo_flags |= PVO_WIRED;
1286 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1287 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1292 * Flush the page from the instruction cache if this page is
1293 * mapped executable and cacheable.
1295 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1296 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1297 vm_page_aflag_set(m, PGA_EXECUTABLE);
1298 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1303 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1308 * This is much trickier than on older systems because
1309 * we can't sync the icache on physical addresses directly
1310 * without a direct map. Instead we check a couple of cases
1311 * where the memory is already mapped in and, failing that,
1312 * use the same trick we use for page zeroing to create
1313 * a temporary mapping for this physical address.
1316 if (!pmap_bootstrapped) {
1318 * If PMAP is not bootstrapped, we are likely to be
1321 __syncicache((void *)pa, sz);
1322 } else if (pmap == kernel_pmap) {
1323 __syncicache((void *)va, sz);
1324 } else if (hw_direct_map) {
1325 __syncicache((void *)pa, sz);
1327 /* Use the scratch page to set up a temp mapping */
1329 mtx_lock(&moea64_scratchpage_mtx);
1331 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1332 __syncicache((void *)(moea64_scratchpage_va[1] +
1333 (va & ADDR_POFF)), sz);
1335 mtx_unlock(&moea64_scratchpage_mtx);
1340 * Maps a sequence of resident pages belonging to the same object.
1341 * The sequence begins with the given page m_start. This page is
1342 * mapped at the given virtual address start. Each subsequent page is
1343 * mapped at a virtual address that is offset from start by the same
1344 * amount as the page is offset from m_start within the object. The
1345 * last page in the sequence is the page with the largest offset from
1346 * m_start that can be mapped at a virtual address less than the given
1347 * virtual address end. Not every virtual page between start and end
1348 * is mapped; only those for which a resident page exists with the
1349 * corresponding offset from m_start are mapped.
1352 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1353 vm_page_t m_start, vm_prot_t prot)
1356 vm_pindex_t diff, psize;
1358 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1360 psize = atop(end - start);
1362 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1363 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1364 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1365 m = TAILQ_NEXT(m, listq);
1370 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1374 moea64_enter(mmu, pm, va, m,
1375 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1379 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1381 struct pvo_entry *pvo;
1385 pvo = moea64_pvo_find_va(pm, va);
1389 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1390 (va - PVO_VADDR(pvo));
1396 * Atomically extract and hold the physical page with the given
1397 * pmap and virtual address pair if that mapping permits the given
1401 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1403 struct pvo_entry *pvo;
1411 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1412 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1413 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1414 (prot & VM_PROT_WRITE) == 0)) {
1415 if (vm_page_pa_tryrelock(pmap,
1416 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1418 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1426 static mmu_t installed_mmu;
1429 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1432 * This entire routine is a horrible hack to avoid bothering kmem
1433 * for new KVA addresses. Because this can get called from inside
1434 * kmem allocation routines, calling kmem for a new address here
1435 * can lead to multiply locking non-recursive mutexes.
1440 int pflags, needed_lock;
1442 *flags = UMA_SLAB_PRIV;
1443 needed_lock = !PMAP_LOCKED(kernel_pmap);
1444 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
1447 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
1449 if (wait & M_NOWAIT)
1456 va = VM_PAGE_TO_PHYS(m);
1460 PMAP_LOCK(kernel_pmap);
1462 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1463 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP);
1466 PMAP_UNLOCK(kernel_pmap);
1469 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1470 bzero((void *)va, PAGE_SIZE);
1475 extern int elf32_nxstack;
1478 moea64_init(mmu_t mmu)
1481 CTR0(KTR_PMAP, "moea64_init");
1483 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1484 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1485 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1486 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1487 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1488 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1490 if (!hw_direct_map) {
1491 installed_mmu = mmu;
1492 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1493 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1496 #ifdef COMPAT_FREEBSD32
1500 moea64_initialized = TRUE;
1504 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1507 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1508 ("moea64_is_referenced: page %p is not managed", m));
1509 return (moea64_query_bit(mmu, m, PTE_REF));
1513 moea64_is_modified(mmu_t mmu, vm_page_t m)
1516 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1517 ("moea64_is_modified: page %p is not managed", m));
1520 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1521 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1522 * is clear, no PTEs can have LPTE_CHG set.
1524 VM_OBJECT_ASSERT_LOCKED(m->object);
1525 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1527 return (moea64_query_bit(mmu, m, LPTE_CHG));
1531 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1533 struct pvo_entry *pvo;
1537 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1538 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1544 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1547 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1548 ("moea64_clear_modify: page %p is not managed", m));
1549 VM_OBJECT_ASSERT_WLOCKED(m->object);
1550 KASSERT(!vm_page_xbusied(m),
1551 ("moea64_clear_modify: page %p is exclusive busied", m));
1554 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1555 * set. If the object containing the page is locked and the page is
1556 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1558 if ((m->aflags & PGA_WRITEABLE) == 0)
1560 moea64_clear_bit(mmu, m, LPTE_CHG);
1564 * Clear the write and modified bits in each of the given page's mappings.
1567 moea64_remove_write(mmu_t mmu, vm_page_t m)
1569 struct pvo_entry *pvo;
1574 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1575 ("moea64_remove_write: page %p is not managed", m));
1578 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1579 * set by another thread while the object is locked. Thus,
1580 * if PGA_WRITEABLE is clear, no page table entries need updating.
1582 VM_OBJECT_ASSERT_WLOCKED(m->object);
1583 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1587 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1588 pmap = pvo->pvo_pmap;
1590 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1591 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1592 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1593 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1595 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1596 lo |= pvo->pvo_pte.lpte.pte_lo;
1597 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1598 MOEA64_PTE_CHANGE(mmu, pt,
1599 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1600 if (pvo->pvo_pmap == kernel_pmap)
1604 if ((lo & LPTE_CHG) != 0)
1609 vm_page_aflag_clear(m, PGA_WRITEABLE);
1613 * moea64_ts_referenced:
1615 * Return a count of reference bits for a page, clearing those bits.
1616 * It is not necessary for every reference bit to be cleared, but it
1617 * is necessary that 0 only be returned when there are truly no
1618 * reference bits set.
1620 * XXX: The exact number of bits to check and clear is a matter that
1621 * should be tested and standardized at some point in the future for
1622 * optimal aging of shared pages.
1625 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1628 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1629 ("moea64_ts_referenced: page %p is not managed", m));
1630 return (moea64_clear_bit(mmu, m, LPTE_REF));
1634 * Modify the WIMG settings of all mappings for a page.
1637 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1639 struct pvo_entry *pvo;
1640 struct pvo_head *pvo_head;
1645 if ((m->oflags & VPO_UNMANAGED) != 0) {
1646 m->md.mdpg_cache_attrs = ma;
1650 pvo_head = vm_page_to_pvoh(m);
1651 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1653 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1654 pmap = pvo->pvo_pmap;
1656 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1657 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1658 pvo->pvo_pte.lpte.pte_lo |= lo;
1660 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1662 if (pvo->pvo_pmap == kernel_pmap)
1668 m->md.mdpg_cache_attrs = ma;
1672 * Map a wired page into kernel virtual address space.
1675 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1680 pte_lo = moea64_calc_wimg(pa, ma);
1683 PMAP_LOCK(kernel_pmap);
1684 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1685 NULL, va, pa, pte_lo, PVO_WIRED);
1686 PMAP_UNLOCK(kernel_pmap);
1689 if (error != 0 && error != ENOENT)
1690 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1695 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1698 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1702 * Extract the physical page address associated with the given kernel virtual
1706 moea64_kextract(mmu_t mmu, vm_offset_t va)
1708 struct pvo_entry *pvo;
1712 * Shortcut the direct-mapped case when applicable. We never put
1713 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1715 if (va < VM_MIN_KERNEL_ADDRESS)
1718 PMAP_LOCK(kernel_pmap);
1719 pvo = moea64_pvo_find_va(kernel_pmap, va);
1720 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1722 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1723 PMAP_UNLOCK(kernel_pmap);
1728 * Remove a wired page from kernel virtual address space.
1731 moea64_kremove(mmu_t mmu, vm_offset_t va)
1733 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1737 * Map a range of physical addresses into kernel virtual address space.
1739 * The value passed in *virt is a suggested virtual address for the mapping.
1740 * Architectures which can support a direct-mapped physical to virtual region
1741 * can return the appropriate address within that region, leaving '*virt'
1742 * unchanged. We cannot and therefore do not; *virt is updated with the
1743 * first usable address after the mapped region.
1746 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1747 vm_paddr_t pa_end, int prot)
1749 vm_offset_t sva, va;
1753 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1754 moea64_kenter(mmu, va, pa_start);
1761 * Returns true if the pmap's pv is one of the first
1762 * 16 pvs linked to from this page. This count may
1763 * be changed upwards or downwards in the future; it
1764 * is only necessary that true be returned for a small
1765 * subset of pmaps for proper page aging.
1768 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1771 struct pvo_entry *pvo;
1774 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1775 ("moea64_page_exists_quick: page %p is not managed", m));
1779 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1780 if (pvo->pvo_pmap == pmap) {
1792 * Return the number of managed mappings to the given physical page
1796 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1798 struct pvo_entry *pvo;
1802 if ((m->oflags & VPO_UNMANAGED) != 0)
1805 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1806 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1812 static uintptr_t moea64_vsidcontext;
1815 moea64_get_unique_vsid(void) {
1822 __asm __volatile("mftb %0" : "=r"(entropy));
1824 mtx_lock(&moea64_slb_mutex);
1825 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1829 * Create a new value by mutiplying by a prime and adding in
1830 * entropy from the timebase register. This is to make the
1831 * VSID more random so that the PT hash function collides
1832 * less often. (Note that the prime casues gcc to do shifts
1833 * instead of a multiply.)
1835 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1836 hash = moea64_vsidcontext & (NVSIDS - 1);
1837 if (hash == 0) /* 0 is special, avoid it */
1840 mask = 1 << (hash & (VSID_NBPW - 1));
1841 hash = (moea64_vsidcontext & VSID_HASHMASK);
1842 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1843 /* anything free in this bucket? */
1844 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1845 entropy = (moea64_vsidcontext >> 20);
1848 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1850 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1853 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1854 ("Allocating in-use VSID %#zx\n", hash));
1855 moea64_vsid_bitmap[n] |= mask;
1856 mtx_unlock(&moea64_slb_mutex);
1860 mtx_unlock(&moea64_slb_mutex);
1861 panic("%s: out of segments",__func__);
1864 #ifdef __powerpc64__
1866 moea64_pinit(mmu_t mmu, pmap_t pmap)
1869 RB_INIT(&pmap->pmap_pvo);
1871 pmap->pm_slb_tree_root = slb_alloc_tree();
1872 pmap->pm_slb = slb_alloc_user_cache();
1873 pmap->pm_slb_len = 0;
1877 moea64_pinit(mmu_t mmu, pmap_t pmap)
1882 RB_INIT(&pmap->pmap_pvo);
1884 if (pmap_bootstrapped)
1885 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1888 pmap->pmap_phys = pmap;
1891 * Allocate some segment registers for this pmap.
1893 hash = moea64_get_unique_vsid();
1895 for (i = 0; i < 16; i++)
1896 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1898 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1903 * Initialize the pmap associated with process 0.
1906 moea64_pinit0(mmu_t mmu, pmap_t pm)
1910 moea64_pinit(mmu, pm);
1911 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1915 * Set the physical protection on the specified range of this map as requested.
1918 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1924 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1927 * Grab the PTE pointer before we diddle with the cached PTE
1930 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1933 * Change the protection of the page.
1935 oldlo = pvo->pvo_pte.lpte.pte_lo;
1936 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1937 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1938 if ((prot & VM_PROT_EXECUTE) == 0)
1939 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1940 if (prot & VM_PROT_WRITE)
1941 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
1943 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1945 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1948 * If the PVO is in the page table, update that pte as well.
1951 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1953 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
1954 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1955 if ((pg->oflags & VPO_UNMANAGED) == 0)
1956 vm_page_aflag_set(pg, PGA_EXECUTABLE);
1957 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
1958 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
1962 * Update vm about the REF/CHG bits if the page is managed and we have
1963 * removed write access.
1965 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
1966 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) {
1968 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
1970 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
1971 vm_page_aflag_set(pg, PGA_REFERENCED);
1977 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1980 struct pvo_entry *pvo, *tpvo, key;
1982 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
1985 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1986 ("moea64_protect: non current pmap"));
1988 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1989 moea64_remove(mmu, pm, sva, eva);
1995 key.pvo_vaddr = sva;
1996 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1997 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1998 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1999 moea64_pvo_protect(mmu, pm, pvo, prot);
2006 * Map a list of wired pages into kernel virtual address space. This is
2007 * intended for temporary mappings which do not need page modification or
2008 * references recorded. Existing mappings in the region are overwritten.
2011 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2013 while (count-- > 0) {
2014 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2021 * Remove page mappings from kernel virtual address space. Intended for
2022 * temporary mappings entered by moea64_qenter.
2025 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2027 while (count-- > 0) {
2028 moea64_kremove(mmu, va);
2034 moea64_release_vsid(uint64_t vsid)
2038 mtx_lock(&moea64_slb_mutex);
2039 idx = vsid & (NVSIDS-1);
2040 mask = 1 << (idx % VSID_NBPW);
2042 KASSERT(moea64_vsid_bitmap[idx] & mask,
2043 ("Freeing unallocated VSID %#jx", vsid));
2044 moea64_vsid_bitmap[idx] &= ~mask;
2045 mtx_unlock(&moea64_slb_mutex);
2050 moea64_release(mmu_t mmu, pmap_t pmap)
2054 * Free segment registers' VSIDs
2056 #ifdef __powerpc64__
2057 slb_free_tree(pmap);
2058 slb_free_user_cache(pmap->pm_slb);
2060 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2062 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2067 * Remove all pages mapped by the specified pmap
2070 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2072 struct pvo_entry *pvo, *tpvo;
2076 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2077 if (!(pvo->pvo_vaddr & PVO_WIRED))
2078 moea64_pvo_remove(mmu, pvo);
2085 * Remove the given range of addresses from the specified map.
2088 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2090 struct pvo_entry *pvo, *tpvo, key;
2093 * Perform an unsynchronized read. This is, however, safe.
2095 if (pm->pm_stats.resident_count == 0)
2100 key.pvo_vaddr = sva;
2101 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2102 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2103 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2104 moea64_pvo_remove(mmu, pvo);
2111 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2112 * will reflect changes in pte's back to the vm_page.
2115 moea64_remove_all(mmu_t mmu, vm_page_t m)
2117 struct pvo_entry *pvo, *next_pvo;
2121 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2122 pmap = pvo->pvo_pmap;
2124 moea64_pvo_remove(mmu, pvo);
2128 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2130 vm_page_aflag_clear(m, PGA_WRITEABLE);
2131 vm_page_aflag_clear(m, PGA_EXECUTABLE);
2135 * Allocate a physical page of memory directly from the phys_avail map.
2136 * Can only be called from moea64_bootstrap before avail start and end are
2140 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2145 size = round_page(size);
2146 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2148 s = (phys_avail[i] + align - 1) & ~(align - 1);
2153 if (s < phys_avail[i] || e > phys_avail[i + 1])
2156 if (s + size > platform_real_maxaddr())
2159 if (s == phys_avail[i]) {
2160 phys_avail[i] += size;
2161 } else if (e == phys_avail[i + 1]) {
2162 phys_avail[i + 1] -= size;
2164 for (j = phys_avail_count * 2; j > i; j -= 2) {
2165 phys_avail[j] = phys_avail[j - 2];
2166 phys_avail[j + 1] = phys_avail[j - 1];
2169 phys_avail[i + 3] = phys_avail[i + 1];
2170 phys_avail[i + 1] = s;
2171 phys_avail[i + 2] = e;
2177 panic("moea64_bootstrap_alloc: could not allocate memory");
2181 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2182 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2183 uint64_t pte_lo, int flags)
2185 struct pvo_entry *pvo;
2193 * One nasty thing that can happen here is that the UMA calls to
2194 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2195 * which calls UMA...
2197 * We break the loop by detecting recursion and allocating out of
2198 * the bootstrap pool.
2202 bootstrap = (flags & PVO_BOOTSTRAP);
2204 if (!moea64_initialized)
2207 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2208 rw_assert(&moea64_table_lock, RA_WLOCKED);
2211 * Compute the PTE Group index.
2214 vsid = va_to_vsid(pm, va);
2215 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2218 * Remove any existing mapping for this page. Reuse the pvo entry if
2219 * there is a mapping.
2221 moea64_pvo_enter_calls++;
2223 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2224 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2225 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2226 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2227 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2228 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2229 /* Re-insert if spilled */
2230 i = MOEA64_PTE_INSERT(mmu, ptegidx,
2231 &pvo->pvo_pte.lpte);
2233 PVO_PTEGIDX_SET(pvo, i);
2234 moea64_pte_overflow--;
2238 moea64_pvo_remove(mmu, pvo);
2244 * If we aren't overwriting a mapping, try to allocate.
2247 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2248 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2249 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2250 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2252 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2253 moea64_bpvo_pool_index++;
2256 pvo = uma_zalloc(zone, M_NOWAIT);
2262 moea64_pvo_entries++;
2263 pvo->pvo_vaddr = va;
2264 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2267 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2268 pvo->pvo_vaddr &= ~ADDR_POFF;
2270 if (flags & PVO_WIRED)
2271 pvo->pvo_vaddr |= PVO_WIRED;
2272 if (pvo_head != NULL)
2273 pvo->pvo_vaddr |= PVO_MANAGED;
2275 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2276 if (flags & PVO_LARGE)
2277 pvo->pvo_vaddr |= PVO_LARGE;
2279 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2280 (uint64_t)(pa) | pte_lo, flags);
2285 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2288 * Remember if the list was empty and therefore will be the first
2291 if (pvo_head != NULL) {
2292 if (LIST_FIRST(pvo_head) == NULL)
2294 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2297 if (pvo->pvo_vaddr & PVO_WIRED) {
2298 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2299 pm->pm_stats.wired_count++;
2301 pm->pm_stats.resident_count++;
2304 * We hope this succeeds but it isn't required.
2306 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2308 PVO_PTEGIDX_SET(pvo, i);
2310 panic("moea64_pvo_enter: overflow");
2311 moea64_pte_overflow++;
2314 if (pm == kernel_pmap)
2317 #ifdef __powerpc64__
2319 * Make sure all our bootstrap mappings are in the SLB as soon
2320 * as virtual memory is switched on.
2322 if (!pmap_bootstrapped)
2323 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2326 return (first ? ENOENT : 0);
2330 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2335 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2336 rw_assert(&moea64_table_lock, RA_WLOCKED);
2339 * If there is an active pte entry, we need to deactivate it (and
2340 * save the ref & cfg bits).
2342 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2344 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2345 PVO_PTEGIDX_CLR(pvo);
2347 moea64_pte_overflow--;
2351 * Update our statistics.
2353 pvo->pvo_pmap->pm_stats.resident_count--;
2354 if (pvo->pvo_vaddr & PVO_WIRED)
2355 pvo->pvo_pmap->pm_stats.wired_count--;
2358 * Remove this PVO from the pmap list.
2360 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2363 * Remove this from the overflow list and return it to the pool
2364 * if we aren't going to reuse it.
2366 LIST_REMOVE(pvo, pvo_olink);
2369 * Update vm about the REF/CHG bits if the page is managed.
2371 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2373 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2374 LIST_REMOVE(pvo, pvo_vlink);
2375 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2376 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2378 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2379 vm_page_aflag_set(pg, PGA_REFERENCED);
2380 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2381 vm_page_aflag_clear(pg, PGA_WRITEABLE);
2383 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2384 vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2387 moea64_pvo_entries--;
2388 moea64_pvo_remove_calls++;
2390 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2391 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2392 moea64_upvo_zone, pvo);
2395 static struct pvo_entry *
2396 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2398 struct pvo_entry key;
2400 key.pvo_vaddr = va & ~ADDR_POFF;
2401 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2405 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2407 struct pvo_entry *pvo;
2411 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2413 * See if we saved the bit off. If so, return success.
2415 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2422 * No luck, now go through the hard part of looking at the PTEs
2423 * themselves. Sync so that any pending REF/CHG bits are flushed to
2427 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2430 * See if this pvo has a valid PTE. if so, fetch the
2431 * REF/CHG bits from the valid PTE. If the appropriate
2432 * ptebit is set, return success.
2434 PMAP_LOCK(pvo->pvo_pmap);
2435 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2437 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2438 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2439 PMAP_UNLOCK(pvo->pvo_pmap);
2444 PMAP_UNLOCK(pvo->pvo_pmap);
2452 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2455 struct pvo_entry *pvo;
2459 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2460 * we can reset the right ones). note that since the pvo entries and
2461 * list heads are accessed via BAT0 and are never placed in the page
2462 * table, we don't have to worry about further accesses setting the
2468 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2469 * valid pte clear the ptebit from the valid pte.
2473 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2474 PMAP_LOCK(pvo->pvo_pmap);
2475 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2477 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2478 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2480 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2481 pvo->pvo_vpn, ptebit);
2484 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2485 PMAP_UNLOCK(pvo->pvo_pmap);
2493 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2495 struct pvo_entry *pvo, key;
2499 PMAP_LOCK(kernel_pmap);
2500 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2501 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2502 ppa < pa + size; ppa += PAGE_SIZE,
2503 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2505 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2510 PMAP_UNLOCK(kernel_pmap);
2516 * Map a set of physical memory pages into the kernel virtual
2517 * address space. Return a pointer to where it is mapped. This
2518 * routine is intended to be used for mapping device memory,
2522 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2524 vm_offset_t va, tmpva, ppa, offset;
2526 ppa = trunc_page(pa);
2527 offset = pa & PAGE_MASK;
2528 size = roundup2(offset + size, PAGE_SIZE);
2530 va = kva_alloc(size);
2533 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2535 for (tmpva = va; size > 0;) {
2536 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2542 return ((void *)(va + offset));
2546 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2549 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2553 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2555 vm_offset_t base, offset;
2557 base = trunc_page(va);
2558 offset = va & PAGE_MASK;
2559 size = roundup2(offset + size, PAGE_SIZE);
2561 kva_free(base, size);
2565 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2567 struct pvo_entry *pvo;
2574 lim = round_page(va);
2575 len = MIN(lim - va, sz);
2576 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2577 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2578 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2580 moea64_syncicache(mmu, pm, va, pa, len);