2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008-2015 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Manages physical address maps.
35 * Since the information managed by this module is also stored by the
36 * logical address mapping module, this module may throw away valid virtual
37 * to physical mappings at almost any time. However, invalidations of
38 * mappings must be done as requested.
40 * In order to cope with hardware architectures which make virtual to
41 * physical map invalidates expensive, this module may delay invalidate
42 * reduced protection operations until such time as they are actually
43 * necessary. This module is given full information as to which processors
44 * are currently using which maps, and to when physical maps must be made
48 #include "opt_kstack_pages.h"
50 #include <sys/param.h>
51 #include <sys/kernel.h>
53 #include <sys/queue.h>
54 #include <sys/cpuset.h>
55 #include <sys/kerneldump.h>
58 #include <sys/msgbuf.h>
59 #include <sys/malloc.h>
60 #include <sys/mutex.h>
62 #include <sys/rwlock.h>
63 #include <sys/sched.h>
64 #include <sys/sysctl.h>
65 #include <sys/systm.h>
66 #include <sys/vmmeter.h>
71 #include <dev/ofw/openfirm.h>
74 #include <vm/vm_param.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_page.h>
77 #include <vm/vm_phys.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_object.h>
80 #include <vm/vm_extern.h>
81 #include <vm/vm_pageout.h>
84 #include <machine/_inttypes.h>
85 #include <machine/cpu.h>
86 #include <machine/platform.h>
87 #include <machine/frame.h>
88 #include <machine/md_var.h>
89 #include <machine/psl.h>
90 #include <machine/bat.h>
91 #include <machine/hid.h>
92 #include <machine/pte.h>
93 #include <machine/sr.h>
94 #include <machine/trap.h>
95 #include <machine/mmuvar.h>
97 #include "mmu_oea64.h"
99 #include "moea64_if.h"
101 void moea64_release_vsid(uint64_t vsid);
102 uintptr_t moea64_get_unique_vsid(void);
104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
105 #define ENABLE_TRANS(msr) mtmsr(msr)
107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
109 #define VSID_HASH_MASK 0x0000007fffffffffULL
114 * There are two locks of interest: the page locks and the pmap locks, which
115 * protect their individual PVO lists and are locked in that order. The contents
116 * of all PVO entries are protected by the locks of their respective pmaps.
117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
122 #define PV_LOCK_PER_DOM (PA_LOCK_COUNT * 3)
123 #define PV_LOCK_COUNT (PV_LOCK_PER_DOM * MAXMEMDOM)
124 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
127 * Cheap NUMA-izing of the pv locks, to reduce contention across domains.
128 * NUMA domains on POWER9 appear to be indexed as sparse memory spaces, with the
129 * index at (N << 45).
132 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_PER_DOM + \
133 (((pa) >> 45) % MAXMEMDOM) * PV_LOCK_PER_DOM)
135 #define PV_LOCK_IDX(pa) (pa_index(pa) % PV_LOCK_COUNT)
137 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[PV_LOCK_IDX(pa)]))
138 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa))
139 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa))
140 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
141 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m))
142 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m))
143 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
152 extern unsigned char _etext[];
153 extern unsigned char _end[];
155 extern void *slbtrap, *slbtrapend;
158 * Map of physical memory regions.
160 static struct mem_region *regions;
161 static struct mem_region *pregions;
162 static struct numa_mem_region *numa_pregions;
163 static u_int phys_avail_count;
164 static int regions_sz, pregions_sz, numapregions_sz;
166 extern void bs_remap_earlyboot(void);
169 * Lock for the SLB tables.
171 struct mtx moea64_slb_mutex;
176 u_long moea64_pteg_count;
177 u_long moea64_pteg_mask;
183 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */
185 static struct pvo_entry *moea64_bpvo_pool;
186 static int moea64_bpvo_pool_index = 0;
187 static int moea64_bpvo_pool_size = 327680;
188 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
189 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
190 &moea64_bpvo_pool_index, 0, "");
192 #define VSID_NBPW (sizeof(u_int32_t) * 8)
194 #define NVSIDS (NPMAPS * 16)
195 #define VSID_HASHMASK 0xffffffffUL
197 #define NVSIDS NPMAPS
198 #define VSID_HASHMASK 0xfffffUL
200 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
202 static boolean_t moea64_initialized = FALSE;
208 u_int moea64_pte_valid = 0;
209 u_int moea64_pte_overflow = 0;
210 u_int moea64_pvo_entries = 0;
211 u_int moea64_pvo_enter_calls = 0;
212 u_int moea64_pvo_remove_calls = 0;
213 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
214 &moea64_pte_valid, 0, "");
215 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
216 &moea64_pte_overflow, 0, "");
217 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
218 &moea64_pvo_entries, 0, "");
219 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
220 &moea64_pvo_enter_calls, 0, "");
221 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
222 &moea64_pvo_remove_calls, 0, "");
225 vm_offset_t moea64_scratchpage_va[2];
226 struct pvo_entry *moea64_scratchpage_pvo[2];
227 struct mtx moea64_scratchpage_mtx;
229 uint64_t moea64_large_page_mask = 0;
230 uint64_t moea64_large_page_size = 0;
231 int moea64_large_page_shift = 0;
236 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo,
237 struct pvo_head *pvo_head, struct pvo_entry **oldpvo);
238 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo);
239 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo);
240 static void moea64_pvo_remove_from_page_locked(mmu_t mmu,
241 struct pvo_entry *pvo, vm_page_t m);
242 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
247 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t);
248 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t);
249 static void moea64_kremove(mmu_t, vm_offset_t);
250 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
251 vm_paddr_t pa, vm_size_t sz);
252 static void moea64_pmap_init_qpages(void);
255 * Kernel MMU interface
257 void moea64_clear_modify(mmu_t, vm_page_t);
258 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
259 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
260 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
261 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
262 u_int flags, int8_t psind);
263 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
265 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
266 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
267 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
268 void moea64_init(mmu_t);
269 boolean_t moea64_is_modified(mmu_t, vm_page_t);
270 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
271 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
272 int moea64_ts_referenced(mmu_t, vm_page_t);
273 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
274 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
275 void moea64_page_init(mmu_t, vm_page_t);
276 int moea64_page_wired_mappings(mmu_t, vm_page_t);
277 void moea64_pinit(mmu_t, pmap_t);
278 void moea64_pinit0(mmu_t, pmap_t);
279 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
280 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
281 void moea64_qremove(mmu_t, vm_offset_t, int);
282 void moea64_release(mmu_t, pmap_t);
283 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
284 void moea64_remove_pages(mmu_t, pmap_t);
285 void moea64_remove_all(mmu_t, vm_page_t);
286 void moea64_remove_write(mmu_t, vm_page_t);
287 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
288 void moea64_zero_page(mmu_t, vm_page_t);
289 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
290 void moea64_activate(mmu_t, struct thread *);
291 void moea64_deactivate(mmu_t, struct thread *);
292 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
293 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
294 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
295 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
296 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
297 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma);
298 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
299 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
300 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
301 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz,
303 void moea64_scan_init(mmu_t mmu);
304 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m);
305 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr);
306 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm,
307 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
308 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
309 int *is_user, vm_offset_t *decoded_addr);
310 static size_t moea64_scan_pmap(mmu_t mmu);
311 static void *moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs);
314 static mmu_method_t moea64_methods[] = {
315 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
316 MMUMETHOD(mmu_copy_page, moea64_copy_page),
317 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
318 MMUMETHOD(mmu_enter, moea64_enter),
319 MMUMETHOD(mmu_enter_object, moea64_enter_object),
320 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
321 MMUMETHOD(mmu_extract, moea64_extract),
322 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
323 MMUMETHOD(mmu_init, moea64_init),
324 MMUMETHOD(mmu_is_modified, moea64_is_modified),
325 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
326 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
327 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
328 MMUMETHOD(mmu_map, moea64_map),
329 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
330 MMUMETHOD(mmu_page_init, moea64_page_init),
331 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
332 MMUMETHOD(mmu_pinit, moea64_pinit),
333 MMUMETHOD(mmu_pinit0, moea64_pinit0),
334 MMUMETHOD(mmu_protect, moea64_protect),
335 MMUMETHOD(mmu_qenter, moea64_qenter),
336 MMUMETHOD(mmu_qremove, moea64_qremove),
337 MMUMETHOD(mmu_release, moea64_release),
338 MMUMETHOD(mmu_remove, moea64_remove),
339 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
340 MMUMETHOD(mmu_remove_all, moea64_remove_all),
341 MMUMETHOD(mmu_remove_write, moea64_remove_write),
342 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
343 MMUMETHOD(mmu_unwire, moea64_unwire),
344 MMUMETHOD(mmu_zero_page, moea64_zero_page),
345 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
346 MMUMETHOD(mmu_activate, moea64_activate),
347 MMUMETHOD(mmu_deactivate, moea64_deactivate),
348 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
349 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page),
350 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page),
352 /* Internal interfaces */
353 MMUMETHOD(mmu_mapdev, moea64_mapdev),
354 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
355 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
356 MMUMETHOD(mmu_kextract, moea64_kextract),
357 MMUMETHOD(mmu_kenter, moea64_kenter),
358 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
359 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
360 MMUMETHOD(mmu_scan_init, moea64_scan_init),
361 MMUMETHOD(mmu_scan_pmap, moea64_scan_pmap),
362 MMUMETHOD(mmu_dump_pmap_init, moea64_dump_pmap_init),
363 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
364 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr),
365 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr),
370 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
372 static struct pvo_head *
373 vm_page_to_pvoh(vm_page_t m)
376 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
377 return (&m->md.mdpg_pvoh);
380 static struct pvo_entry *
381 alloc_pvo_entry(int bootstrap)
383 struct pvo_entry *pvo;
385 if (!moea64_initialized || bootstrap) {
386 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
387 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
388 moea64_bpvo_pool_index, moea64_bpvo_pool_size,
389 moea64_bpvo_pool_size * sizeof(struct pvo_entry));
391 pvo = &moea64_bpvo_pool[
392 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
393 bzero(pvo, sizeof(*pvo));
394 pvo->pvo_vaddr = PVO_BOOTSTRAP;
396 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT | M_ZERO);
403 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
409 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
411 pvo->pvo_pmap = pmap;
413 pvo->pvo_vaddr |= va;
414 vsid = va_to_vsid(pmap, va);
415 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
418 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift :
420 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
421 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
425 free_pvo_entry(struct pvo_entry *pvo)
428 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
429 uma_zfree(moea64_pvo_zone, pvo);
433 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
436 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) &
438 lpte->pte_hi |= LPTE_VALID;
440 if (pvo->pvo_vaddr & PVO_LARGE)
441 lpte->pte_hi |= LPTE_BIG;
442 if (pvo->pvo_vaddr & PVO_WIRED)
443 lpte->pte_hi |= LPTE_WIRED;
444 if (pvo->pvo_vaddr & PVO_HID)
445 lpte->pte_hi |= LPTE_HID;
447 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
448 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
449 lpte->pte_lo |= LPTE_BW;
451 lpte->pte_lo |= LPTE_BR;
453 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
454 lpte->pte_lo |= LPTE_NOEXEC;
457 static __inline uint64_t
458 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
463 if (ma != VM_MEMATTR_DEFAULT) {
465 case VM_MEMATTR_UNCACHEABLE:
466 return (LPTE_I | LPTE_G);
467 case VM_MEMATTR_CACHEABLE:
469 case VM_MEMATTR_WRITE_COMBINING:
470 case VM_MEMATTR_WRITE_BACK:
471 case VM_MEMATTR_PREFETCHABLE:
473 case VM_MEMATTR_WRITE_THROUGH:
474 return (LPTE_W | LPTE_M);
479 * Assume the page is cache inhibited and access is guarded unless
480 * it's in our available memory array.
482 pte_lo = LPTE_I | LPTE_G;
483 for (i = 0; i < pregions_sz; i++) {
484 if ((pa >= pregions[i].mr_start) &&
485 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
486 pte_lo &= ~(LPTE_I | LPTE_G);
496 * Quick sort callout for comparing memory regions.
498 static int om_cmp(const void *a, const void *b);
501 om_cmp(const void *a, const void *b)
503 const struct ofw_map *mapa;
504 const struct ofw_map *mapb;
508 if (mapa->om_pa < mapb->om_pa)
510 else if (mapa->om_pa > mapb->om_pa)
517 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
519 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
520 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
521 struct pvo_entry *pvo;
527 bzero(translations, sz);
528 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
530 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
531 panic("moea64_bootstrap: can't get ofw translations");
533 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
534 sz /= sizeof(cell_t);
535 for (i = 0, j = 0; i < sz; j++) {
536 translations[j].om_va = trans_cells[i++];
537 translations[j].om_len = trans_cells[i++];
538 translations[j].om_pa = trans_cells[i++];
540 translations[j].om_pa <<= 32;
541 translations[j].om_pa |= trans_cells[i++];
543 translations[j].om_mode = trans_cells[i++];
545 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
549 qsort(translations, sz, sizeof (*translations), om_cmp);
551 for (i = 0; i < sz; i++) {
552 pa_base = translations[i].om_pa;
553 #ifndef __powerpc64__
554 if ((translations[i].om_pa >> 32) != 0)
555 panic("OFW translations above 32-bit boundary!");
558 if (pa_base % PAGE_SIZE)
559 panic("OFW translation not page-aligned (phys)!");
560 if (translations[i].om_va % PAGE_SIZE)
561 panic("OFW translation not page-aligned (virt)!");
563 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
564 pa_base, translations[i].om_va, translations[i].om_len);
566 /* Now enter the pages for this mapping */
569 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
570 /* If this address is direct-mapped, skip remapping */
572 translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
573 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT)
577 PMAP_LOCK(kernel_pmap);
578 pvo = moea64_pvo_find_va(kernel_pmap,
579 translations[i].om_va + off);
580 PMAP_UNLOCK(kernel_pmap);
584 moea64_kenter(mmup, translations[i].om_va + off,
593 moea64_probe_large_page(void)
595 uint16_t pvr = mfpvr() >> 16;
601 powerpc_sync(); isync();
602 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
603 powerpc_sync(); isync();
607 if (moea64_large_page_size == 0) {
608 moea64_large_page_size = 0x1000000; /* 16 MB */
609 moea64_large_page_shift = 24;
613 moea64_large_page_mask = moea64_large_page_size - 1;
617 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
624 cache = PCPU_GET(aim.slb);
625 esid = va >> ADDR_SR_SHFT;
626 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
628 for (i = 0; i < 64; i++) {
629 if (cache[i].slbe == (slbe | i))
634 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
636 entry.slbv |= SLBV_L;
638 slb_insert_kernel(entry.slbe, entry.slbv);
643 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
644 vm_offset_t kernelend)
646 struct pvo_entry *pvo;
648 vm_paddr_t pa, pkernelstart, pkernelend;
649 vm_offset_t size, off;
653 if (moea64_large_page_size == 0)
658 PMAP_LOCK(kernel_pmap);
659 for (i = 0; i < pregions_sz; i++) {
660 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
661 pregions[i].mr_size; pa += moea64_large_page_size) {
664 pvo = alloc_pvo_entry(1 /* bootstrap */);
665 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
666 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa));
669 * Set memory access as guarded if prefetch within
670 * the page could exit the available physmem area.
672 if (pa & moea64_large_page_mask) {
673 pa &= moea64_large_page_mask;
676 if (pa + moea64_large_page_size >
677 pregions[i].mr_start + pregions[i].mr_size)
680 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
682 pvo->pvo_pte.pa = pa | pte_lo;
683 moea64_pvo_enter(mmup, pvo, NULL, NULL);
686 PMAP_UNLOCK(kernel_pmap);
690 * Make sure the kernel and BPVO pool stay mapped on systems either
691 * without a direct map or on which the kernel is not already executing
692 * out of the direct-mapped region.
694 if (kernelstart < DMAP_BASE_ADDRESS) {
696 * For pre-dmap execution, we need to use identity mapping
697 * because we will be operating with the mmu on but in the
698 * wrong address configuration until we __restartkernel().
700 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
702 moea64_kenter(mmup, pa, pa);
703 } else if (!hw_direct_map) {
704 pkernelstart = kernelstart & ~DMAP_BASE_ADDRESS;
705 pkernelend = kernelend & ~DMAP_BASE_ADDRESS;
706 for (pa = pkernelstart & ~PAGE_MASK; pa < pkernelend;
708 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa);
711 if (!hw_direct_map) {
712 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
713 off = (vm_offset_t)(moea64_bpvo_pool);
714 for (pa = off; pa < off + size; pa += PAGE_SIZE)
715 moea64_kenter(mmup, pa, pa);
717 /* Map exception vectors */
718 for (pa = EXC_RSVD; pa < EXC_LAST; pa += PAGE_SIZE)
719 moea64_kenter(mmup, pa | DMAP_BASE_ADDRESS, pa);
724 * Allow user to override unmapped_buf_allowed for testing.
725 * XXXKIB Only direct map implementation was tested.
727 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
728 &unmapped_buf_allowed))
729 unmapped_buf_allowed = hw_direct_map;
732 /* Quick sort callout for comparing physical addresses. */
734 pa_cmp(const void *a, const void *b)
736 const vm_paddr_t *pa = a, *pb = b;
747 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
750 vm_size_t physsz, hwphyssz;
751 vm_paddr_t kernelphysstart, kernelphysend;
754 #ifndef __powerpc64__
755 /* We don't have a direct map since there is no BAT */
758 /* Make sure battable is zero, since we have no BAT */
759 for (i = 0; i < 16; i++) {
760 battable[i].batu = 0;
761 battable[i].batl = 0;
764 moea64_probe_large_page();
766 /* Use a direct map if we have large page support */
767 if (moea64_large_page_size > 0)
772 /* Install trap handlers for SLBs */
773 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
774 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
775 __syncicache((void *)EXC_DSE, 0x80);
776 __syncicache((void *)EXC_ISE, 0x80);
779 kernelphysstart = kernelstart & ~DMAP_BASE_ADDRESS;
780 kernelphysend = kernelend & ~DMAP_BASE_ADDRESS;
782 /* Get physical memory regions from firmware */
783 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
784 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
786 if (PHYS_AVAIL_ENTRIES < regions_sz)
787 panic("moea64_bootstrap: phys_avail too small");
789 phys_avail_count = 0;
792 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
793 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
794 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
795 regions[i].mr_start, regions[i].mr_start +
796 regions[i].mr_size, regions[i].mr_size);
798 (physsz + regions[i].mr_size) >= hwphyssz) {
799 if (physsz < hwphyssz) {
800 phys_avail[j] = regions[i].mr_start;
801 phys_avail[j + 1] = regions[i].mr_start +
805 dump_avail[j] = phys_avail[j];
806 dump_avail[j + 1] = phys_avail[j + 1];
810 phys_avail[j] = regions[i].mr_start;
811 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
813 physsz += regions[i].mr_size;
814 dump_avail[j] = phys_avail[j];
815 dump_avail[j + 1] = phys_avail[j + 1];
818 /* Check for overlap with the kernel and exception vectors */
820 for (j = 0; j < 2*phys_avail_count; j+=2) {
821 if (phys_avail[j] < EXC_LAST)
822 phys_avail[j] += EXC_LAST;
824 if (phys_avail[j] >= kernelphysstart &&
825 phys_avail[j+1] <= kernelphysend) {
826 phys_avail[j] = phys_avail[j+1] = ~0;
831 if (kernelphysstart >= phys_avail[j] &&
832 kernelphysstart < phys_avail[j+1]) {
833 if (kernelphysend < phys_avail[j+1]) {
834 phys_avail[2*phys_avail_count] =
835 (kernelphysend & ~PAGE_MASK) + PAGE_SIZE;
836 phys_avail[2*phys_avail_count + 1] =
841 phys_avail[j+1] = kernelphysstart & ~PAGE_MASK;
844 if (kernelphysend >= phys_avail[j] &&
845 kernelphysend < phys_avail[j+1]) {
846 if (kernelphysstart > phys_avail[j]) {
847 phys_avail[2*phys_avail_count] = phys_avail[j];
848 phys_avail[2*phys_avail_count + 1] =
849 kernelphysstart & ~PAGE_MASK;
853 phys_avail[j] = (kernelphysend & ~PAGE_MASK) +
858 /* Remove physical available regions marked for removal (~0) */
860 qsort(phys_avail, 2*phys_avail_count, sizeof(phys_avail[0]),
862 phys_avail_count -= rm_pavail;
863 for (i = 2*phys_avail_count;
864 i < 2*(phys_avail_count + rm_pavail); i+=2)
865 phys_avail[i] = phys_avail[i+1] = 0;
868 physmem = btoc(physsz);
871 moea64_pteg_count = PTEGCOUNT;
873 moea64_pteg_count = 0x1000;
875 while (moea64_pteg_count < physmem)
876 moea64_pteg_count <<= 1;
878 moea64_pteg_count >>= 1;
879 #endif /* PTEGCOUNT */
883 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
890 moea64_pteg_mask = moea64_pteg_count - 1;
893 * Initialize SLB table lock and page locks
895 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
896 for (i = 0; i < PV_LOCK_COUNT; i++)
897 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
900 * Initialise the bootstrap pvo pool.
902 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
903 moea64_bpvo_pool_size*sizeof(struct pvo_entry), PAGE_SIZE);
904 moea64_bpvo_pool_index = 0;
906 /* Place at address usable through the direct map */
908 moea64_bpvo_pool = (struct pvo_entry *)
909 PHYS_TO_DMAP((uintptr_t)moea64_bpvo_pool);
912 * Make sure kernel vsid is allocated as well as VSID 0.
914 #ifndef __powerpc64__
915 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
916 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
917 moea64_vsid_bitmap[0] |= 1;
921 * Initialize the kernel pmap (which is statically allocated).
924 for (i = 0; i < 64; i++) {
925 pcpup->pc_aim.slb[i].slbv = 0;
926 pcpup->pc_aim.slb[i].slbe = 0;
929 for (i = 0; i < 16; i++)
930 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
933 kernel_pmap->pmap_phys = kernel_pmap;
934 CPU_FILL(&kernel_pmap->pm_active);
935 RB_INIT(&kernel_pmap->pmap_pvo);
937 PMAP_LOCK_INIT(kernel_pmap);
940 * Now map in all the other buffers we allocated earlier
943 moea64_setup_direct_map(mmup, kernelstart, kernelend);
947 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
958 * Set up the Open Firmware pmap and add its mappings if not in real
962 chosen = OF_finddevice("/chosen");
963 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
964 mmu = OF_instance_to_package(mmui);
966 (sz = OF_getproplen(mmu, "translations")) == -1)
968 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
969 panic("moea64_bootstrap: too many ofw translations");
972 moea64_add_ofw_mappings(mmup, mmu, sz);
976 * Calculate the last available physical address.
979 for (i = 0; phys_avail[i + 2] != 0; i += 2)
980 Maxmem = MAX(Maxmem, powerpc_btop(phys_avail[i + 1]));
985 MMU_CPU_BOOTSTRAP(mmup,0);
986 mtmsr(mfmsr() | PSL_DR | PSL_IR);
990 * Set the start and end of kva.
992 virtual_avail = VM_MIN_KERNEL_ADDRESS;
993 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
996 * Map the entire KVA range into the SLB. We must not fault there.
999 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
1000 moea64_bootstrap_slb_prefault(va, 0);
1004 * Remap any early IO mappings (console framebuffer, etc.)
1006 bs_remap_earlyboot();
1009 * Figure out how far we can extend virtual_end into segment 16
1010 * without running into existing mappings. Segment 16 is guaranteed
1011 * to contain neither RAM nor devices (at least on Apple hardware),
1012 * but will generally contain some OFW mappings we should not
1016 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
1017 PMAP_LOCK(kernel_pmap);
1018 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
1019 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
1020 virtual_end += PAGE_SIZE;
1021 PMAP_UNLOCK(kernel_pmap);
1025 * Allocate a kernel stack with a guard page for thread0 and map it
1026 * into the kernel page map.
1028 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
1029 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1030 virtual_avail = va + kstack_pages * PAGE_SIZE;
1031 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
1032 thread0.td_kstack = va;
1033 thread0.td_kstack_pages = kstack_pages;
1034 for (i = 0; i < kstack_pages; i++) {
1035 moea64_kenter(mmup, va, pa);
1041 * Allocate virtual address space for the message buffer.
1043 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
1044 msgbufp = (struct msgbuf *)virtual_avail;
1046 virtual_avail += round_page(msgbufsize);
1047 while (va < virtual_avail) {
1048 moea64_kenter(mmup, va, pa);
1054 * Allocate virtual address space for the dynamic percpu area.
1056 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
1057 dpcpu = (void *)virtual_avail;
1059 virtual_avail += DPCPU_SIZE;
1060 while (va < virtual_avail) {
1061 moea64_kenter(mmup, va, pa);
1065 dpcpu_init(dpcpu, curcpu);
1067 crashdumpmap = (caddr_t)virtual_avail;
1068 virtual_avail += MAXDUMPPGS * PAGE_SIZE;
1071 * Allocate some things for page zeroing. We put this directly
1072 * in the page table and use MOEA64_PTE_REPLACE to avoid any
1073 * of the PVO book-keeping or other parts of the VM system
1074 * from even knowing that this hack exists.
1077 if (!hw_direct_map) {
1078 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
1080 for (i = 0; i < 2; i++) {
1081 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
1082 virtual_end -= PAGE_SIZE;
1084 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
1086 PMAP_LOCK(kernel_pmap);
1087 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
1088 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
1089 PMAP_UNLOCK(kernel_pmap);
1093 numa_mem_regions(&numa_pregions, &numapregions_sz);
1097 moea64_pmap_init_qpages(void)
1107 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1108 if (pc->pc_qmap_addr == 0)
1109 panic("pmap_init_qpages: unable to allocate KVA");
1110 PMAP_LOCK(kernel_pmap);
1111 pc->pc_aim.qmap_pvo =
1112 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1113 PMAP_UNLOCK(kernel_pmap);
1114 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF);
1118 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1121 * Activate a user pmap. This mostly involves setting some non-CPU
1125 moea64_activate(mmu_t mmu, struct thread *td)
1129 pm = &td->td_proc->p_vmspace->vm_pmap;
1130 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1132 #ifdef __powerpc64__
1133 PCPU_SET(aim.userslb, pm->pm_slb);
1134 __asm __volatile("slbmte %0, %1; isync" ::
1135 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1137 PCPU_SET(curpmap, pm->pmap_phys);
1138 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1143 moea64_deactivate(mmu_t mmu, struct thread *td)
1147 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1149 pm = &td->td_proc->p_vmspace->vm_pmap;
1150 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1151 #ifdef __powerpc64__
1152 PCPU_SET(aim.userslb, NULL);
1154 PCPU_SET(curpmap, NULL);
1159 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1161 struct pvo_entry key, *pvo;
1165 key.pvo_vaddr = sva;
1167 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1168 pvo != NULL && PVO_VADDR(pvo) < eva;
1169 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1170 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1171 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1173 pvo->pvo_vaddr &= ~PVO_WIRED;
1174 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */);
1175 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1176 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1179 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1181 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1182 if (refchg & LPTE_CHG)
1184 if (refchg & LPTE_REF)
1185 vm_page_aflag_set(m, PGA_REFERENCED);
1187 pm->pm_stats.wired_count--;
1193 * This goes through and sets the physical address of our
1194 * special scratch PTE to the PA we want to zero or copy. Because
1195 * of locking issues (this can get called in pvo_enter() by
1196 * the UMA allocator), we can't use most other utility functions here
1200 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa)
1202 struct pvo_entry *pvo;
1204 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1205 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1207 pvo = moea64_scratchpage_pvo[which];
1208 PMAP_LOCK(pvo->pvo_pmap);
1210 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1211 MOEA64_PTE_REPLACE(mmup, pvo, MOEA64_PTE_INVALIDATE);
1212 PMAP_UNLOCK(pvo->pvo_pmap);
1217 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1222 dst = VM_PAGE_TO_PHYS(mdst);
1223 src = VM_PAGE_TO_PHYS(msrc);
1225 if (hw_direct_map) {
1226 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1229 mtx_lock(&moea64_scratchpage_mtx);
1231 moea64_set_scratchpage_pa(mmu, 0, src);
1232 moea64_set_scratchpage_pa(mmu, 1, dst);
1234 bcopy((void *)moea64_scratchpage_va[0],
1235 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1237 mtx_unlock(&moea64_scratchpage_mtx);
1242 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1243 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1246 vm_offset_t a_pg_offset, b_pg_offset;
1249 while (xfersize > 0) {
1250 a_pg_offset = a_offset & PAGE_MASK;
1251 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1252 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1253 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1255 b_pg_offset = b_offset & PAGE_MASK;
1256 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1257 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1258 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1260 bcopy(a_cp, b_cp, cnt);
1268 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1269 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1272 vm_offset_t a_pg_offset, b_pg_offset;
1275 mtx_lock(&moea64_scratchpage_mtx);
1276 while (xfersize > 0) {
1277 a_pg_offset = a_offset & PAGE_MASK;
1278 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1279 moea64_set_scratchpage_pa(mmu, 0,
1280 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1281 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1282 b_pg_offset = b_offset & PAGE_MASK;
1283 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1284 moea64_set_scratchpage_pa(mmu, 1,
1285 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1286 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1287 bcopy(a_cp, b_cp, cnt);
1292 mtx_unlock(&moea64_scratchpage_mtx);
1296 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1297 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1300 if (hw_direct_map) {
1301 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1304 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1310 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1312 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1314 if (size + off > PAGE_SIZE)
1315 panic("moea64_zero_page: size + off > PAGE_SIZE");
1317 if (hw_direct_map) {
1318 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size);
1320 mtx_lock(&moea64_scratchpage_mtx);
1321 moea64_set_scratchpage_pa(mmu, 0, pa);
1322 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1323 mtx_unlock(&moea64_scratchpage_mtx);
1328 * Zero a page of physical memory by temporarily mapping it
1331 moea64_zero_page(mmu_t mmu, vm_page_t m)
1333 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1334 vm_offset_t va, off;
1336 if (!hw_direct_map) {
1337 mtx_lock(&moea64_scratchpage_mtx);
1339 moea64_set_scratchpage_pa(mmu, 0, pa);
1340 va = moea64_scratchpage_va[0];
1342 va = PHYS_TO_DMAP(pa);
1345 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1346 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1349 mtx_unlock(&moea64_scratchpage_mtx);
1353 moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
1355 struct pvo_entry *pvo;
1356 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1359 return (PHYS_TO_DMAP(pa));
1362 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1363 * a critical section and access the PCPU data like on i386.
1364 * Instead, pin the thread and grab the PCPU lock to prevent
1365 * a preempting thread from using the same PCPU data.
1369 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED);
1370 pvo = PCPU_GET(aim.qmap_pvo);
1372 mtx_lock(PCPU_PTR(aim.qmap_lock));
1373 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1375 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
1378 return (PCPU_GET(qmap_addr));
1382 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1387 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED);
1388 KASSERT(PCPU_GET(qmap_addr) == addr,
1389 ("moea64_quick_remove_page: invalid address"));
1390 mtx_unlock(PCPU_PTR(aim.qmap_lock));
1395 * Map the given physical page at the specified virtual address in the
1396 * target pmap with the protection requested. If specified the page
1397 * will be wired down.
1401 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1402 vm_prot_t prot, u_int flags, int8_t psind)
1404 struct pvo_entry *pvo, *oldpvo;
1405 struct pvo_head *pvo_head;
1409 if ((m->oflags & VPO_UNMANAGED) == 0) {
1410 if ((flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1411 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1413 VM_OBJECT_ASSERT_LOCKED(m->object);
1416 pvo = alloc_pvo_entry(0);
1418 return (KERN_RESOURCE_SHORTAGE);
1419 pvo->pvo_pmap = NULL; /* to be filled in later */
1420 pvo->pvo_pte.prot = prot;
1422 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1423 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo;
1425 if ((flags & PMAP_ENTER_WIRED) != 0)
1426 pvo->pvo_vaddr |= PVO_WIRED;
1428 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1431 pvo_head = &m->md.mdpg_pvoh;
1432 pvo->pvo_vaddr |= PVO_MANAGED;
1437 if (pvo->pvo_pmap == NULL)
1438 init_pvo_entry(pvo, pmap, va);
1439 if (prot & VM_PROT_WRITE)
1440 if (pmap_bootstrapped &&
1441 (m->oflags & VPO_UNMANAGED) == 0)
1442 vm_page_aflag_set(m, PGA_WRITEABLE);
1444 error = moea64_pvo_enter(mmu, pvo, pvo_head, &oldpvo);
1445 if (error == EEXIST) {
1446 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1447 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1448 oldpvo->pvo_pte.prot == prot) {
1449 /* Identical mapping already exists */
1452 /* If not in page table, reinsert it */
1453 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) {
1454 STAT_MOEA64(moea64_pte_overflow--);
1455 MOEA64_PTE_INSERT(mmu, oldpvo);
1458 /* Then just clean up and go home */
1461 free_pvo_entry(pvo);
1464 /* Otherwise, need to kill it first */
1465 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1466 "mapping does not match new mapping"));
1467 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1468 moea64_pvo_enter(mmu, pvo, pvo_head, NULL);
1474 /* Free any dead pages */
1475 if (error == EEXIST) {
1476 moea64_pvo_remove_from_page(mmu, oldpvo);
1477 free_pvo_entry(oldpvo);
1482 * Flush the page from the instruction cache if this page is
1483 * mapped executable and cacheable.
1485 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1486 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1487 vm_page_aflag_set(m, PGA_EXECUTABLE);
1488 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1490 return (KERN_SUCCESS);
1494 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1499 * This is much trickier than on older systems because
1500 * we can't sync the icache on physical addresses directly
1501 * without a direct map. Instead we check a couple of cases
1502 * where the memory is already mapped in and, failing that,
1503 * use the same trick we use for page zeroing to create
1504 * a temporary mapping for this physical address.
1507 if (!pmap_bootstrapped) {
1509 * If PMAP is not bootstrapped, we are likely to be
1512 __syncicache((void *)(uintptr_t)pa, sz);
1513 } else if (pmap == kernel_pmap) {
1514 __syncicache((void *)va, sz);
1515 } else if (hw_direct_map) {
1516 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz);
1518 /* Use the scratch page to set up a temp mapping */
1520 mtx_lock(&moea64_scratchpage_mtx);
1522 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1523 __syncicache((void *)(moea64_scratchpage_va[1] +
1524 (va & ADDR_POFF)), sz);
1526 mtx_unlock(&moea64_scratchpage_mtx);
1531 * Maps a sequence of resident pages belonging to the same object.
1532 * The sequence begins with the given page m_start. This page is
1533 * mapped at the given virtual address start. Each subsequent page is
1534 * mapped at a virtual address that is offset from start by the same
1535 * amount as the page is offset from m_start within the object. The
1536 * last page in the sequence is the page with the largest offset from
1537 * m_start that can be mapped at a virtual address less than the given
1538 * virtual address end. Not every virtual page between start and end
1539 * is mapped; only those for which a resident page exists with the
1540 * corresponding offset from m_start are mapped.
1543 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1544 vm_page_t m_start, vm_prot_t prot)
1547 vm_pindex_t diff, psize;
1549 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1551 psize = atop(end - start);
1553 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1554 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1555 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1556 PMAP_ENTER_QUICK_LOCKED, 0);
1557 m = TAILQ_NEXT(m, listq);
1562 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1566 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1567 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1571 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1573 struct pvo_entry *pvo;
1577 pvo = moea64_pvo_find_va(pm, va);
1581 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1588 * Atomically extract and hold the physical page with the given
1589 * pmap and virtual address pair if that mapping permits the given
1593 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1595 struct pvo_entry *pvo;
1600 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1601 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1602 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1603 if (!vm_page_wire_mapped(m))
1610 static mmu_t installed_mmu;
1613 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1614 uint8_t *flags, int wait)
1616 struct pvo_entry *pvo;
1622 * This entire routine is a horrible hack to avoid bothering kmem
1623 * for new KVA addresses. Because this can get called from inside
1624 * kmem allocation routines, calling kmem for a new address here
1625 * can lead to multiply locking non-recursive mutexes.
1628 *flags = UMA_SLAB_PRIV;
1629 needed_lock = !PMAP_LOCKED(kernel_pmap);
1631 m = vm_page_alloc_domain(NULL, 0, domain,
1632 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ);
1636 va = VM_PAGE_TO_PHYS(m);
1638 pvo = alloc_pvo_entry(1 /* bootstrap */);
1640 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1641 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1644 PMAP_LOCK(kernel_pmap);
1646 init_pvo_entry(pvo, kernel_pmap, va);
1647 pvo->pvo_vaddr |= PVO_WIRED;
1649 moea64_pvo_enter(installed_mmu, pvo, NULL, NULL);
1652 PMAP_UNLOCK(kernel_pmap);
1654 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1655 bzero((void *)va, PAGE_SIZE);
1660 extern int elf32_nxstack;
1663 moea64_init(mmu_t mmu)
1666 CTR0(KTR_PMAP, "moea64_init");
1668 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1669 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1670 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1672 if (!hw_direct_map) {
1673 installed_mmu = mmu;
1674 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1677 #ifdef COMPAT_FREEBSD32
1681 moea64_initialized = TRUE;
1685 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1688 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1689 ("moea64_is_referenced: page %p is not managed", m));
1691 return (moea64_query_bit(mmu, m, LPTE_REF));
1695 moea64_is_modified(mmu_t mmu, vm_page_t m)
1698 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1699 ("moea64_is_modified: page %p is not managed", m));
1702 * If the page is not busied then this check is racy.
1704 if (!pmap_page_is_write_mapped(m))
1707 return (moea64_query_bit(mmu, m, LPTE_CHG));
1711 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1713 struct pvo_entry *pvo;
1714 boolean_t rv = TRUE;
1717 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1725 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1728 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1729 ("moea64_clear_modify: page %p is not managed", m));
1730 vm_page_assert_busied(m);
1732 if (!pmap_page_is_write_mapped(m))
1734 moea64_clear_bit(mmu, m, LPTE_CHG);
1738 * Clear the write and modified bits in each of the given page's mappings.
1741 moea64_remove_write(mmu_t mmu, vm_page_t m)
1743 struct pvo_entry *pvo;
1744 int64_t refchg, ret;
1747 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1748 ("moea64_remove_write: page %p is not managed", m));
1749 vm_page_assert_busied(m);
1751 if (!pmap_page_is_write_mapped(m))
1757 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1758 pmap = pvo->pvo_pmap;
1760 if (!(pvo->pvo_vaddr & PVO_DEAD) &&
1761 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1762 pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
1763 ret = MOEA64_PTE_REPLACE(mmu, pvo,
1764 MOEA64_PTE_PROT_UPDATE);
1768 if (pvo->pvo_pmap == kernel_pmap)
1773 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
1775 vm_page_aflag_clear(m, PGA_WRITEABLE);
1780 * moea64_ts_referenced:
1782 * Return a count of reference bits for a page, clearing those bits.
1783 * It is not necessary for every reference bit to be cleared, but it
1784 * is necessary that 0 only be returned when there are truly no
1785 * reference bits set.
1787 * XXX: The exact number of bits to check and clear is a matter that
1788 * should be tested and standardized at some point in the future for
1789 * optimal aging of shared pages.
1792 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1795 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1796 ("moea64_ts_referenced: page %p is not managed", m));
1797 return (moea64_clear_bit(mmu, m, LPTE_REF));
1801 * Modify the WIMG settings of all mappings for a page.
1804 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1806 struct pvo_entry *pvo;
1811 if ((m->oflags & VPO_UNMANAGED) != 0) {
1812 m->md.mdpg_cache_attrs = ma;
1816 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1819 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1820 pmap = pvo->pvo_pmap;
1822 if (!(pvo->pvo_vaddr & PVO_DEAD)) {
1823 pvo->pvo_pte.pa &= ~LPTE_WIMG;
1824 pvo->pvo_pte.pa |= lo;
1825 refchg = MOEA64_PTE_REPLACE(mmu, pvo,
1826 MOEA64_PTE_INVALIDATE);
1828 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
1830 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1831 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1833 atomic_readandclear_32(&m->md.mdpg_attrs);
1834 if (refchg & LPTE_CHG)
1836 if (refchg & LPTE_REF)
1837 vm_page_aflag_set(m, PGA_REFERENCED);
1839 if (pvo->pvo_pmap == kernel_pmap)
1844 m->md.mdpg_cache_attrs = ma;
1849 * Map a wired page into kernel virtual address space.
1852 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1855 struct pvo_entry *pvo, *oldpvo;
1858 pvo = alloc_pvo_entry(0);
1861 } while (pvo == NULL);
1862 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
1863 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
1864 pvo->pvo_vaddr |= PVO_WIRED;
1866 PMAP_LOCK(kernel_pmap);
1867 oldpvo = moea64_pvo_find_va(kernel_pmap, va);
1869 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1870 init_pvo_entry(pvo, kernel_pmap, va);
1871 error = moea64_pvo_enter(mmu, pvo, NULL, NULL);
1872 PMAP_UNLOCK(kernel_pmap);
1874 /* Free any dead pages */
1875 if (oldpvo != NULL) {
1876 moea64_pvo_remove_from_page(mmu, oldpvo);
1877 free_pvo_entry(oldpvo);
1880 if (error != 0 && error != ENOENT)
1881 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va,
1882 (uintmax_t)pa, error);
1886 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1889 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1893 * Extract the physical page address associated with the given kernel virtual
1897 moea64_kextract(mmu_t mmu, vm_offset_t va)
1899 struct pvo_entry *pvo;
1903 * Shortcut the direct-mapped case when applicable. We never put
1904 * anything but 1:1 (or 62-bit aliased) mappings below
1905 * VM_MIN_KERNEL_ADDRESS.
1907 if (va < VM_MIN_KERNEL_ADDRESS)
1908 return (va & ~DMAP_BASE_ADDRESS);
1910 PMAP_LOCK(kernel_pmap);
1911 pvo = moea64_pvo_find_va(kernel_pmap, va);
1912 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1914 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1915 PMAP_UNLOCK(kernel_pmap);
1920 * Remove a wired page from kernel virtual address space.
1923 moea64_kremove(mmu_t mmu, vm_offset_t va)
1925 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1929 * Provide a kernel pointer corresponding to a given userland pointer.
1930 * The returned pointer is valid until the next time this function is
1931 * called in this thread. This is used internally in copyin/copyout.
1934 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1935 void **kaddr, size_t ulen, size_t *klen)
1938 #ifdef __powerpc64__
1943 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1944 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1952 #ifdef __powerpc64__
1953 /* Try lockless look-up first */
1954 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
1957 /* If it isn't there, we need to pre-fault the VSID */
1959 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
1965 /* Mark segment no-execute */
1968 slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
1970 /* Mark segment no-execute */
1974 /* If we have already set this VSID, we can just return */
1975 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
1978 __asm __volatile("isync");
1979 curthread->td_pcb->pcb_cpu.aim.usr_segm =
1980 (uintptr_t)uaddr >> ADDR_SR_SHFT;
1981 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
1982 #ifdef __powerpc64__
1983 __asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
1984 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
1986 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
1993 * Figure out where a given kernel pointer (usually in a fault) points
1994 * to from the VM's perspective, potentially remapping into userland's
1998 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
1999 vm_offset_t *decoded_addr)
2001 vm_offset_t user_sr;
2003 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
2004 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm;
2005 addr &= ADDR_PIDX | ADDR_POFF;
2006 addr |= user_sr << ADDR_SR_SHFT;
2007 *decoded_addr = addr;
2010 *decoded_addr = addr;
2018 * Map a range of physical addresses into kernel virtual address space.
2020 * The value passed in *virt is a suggested virtual address for the mapping.
2021 * Architectures which can support a direct-mapped physical to virtual region
2022 * can return the appropriate address within that region, leaving '*virt'
2023 * unchanged. Other architectures should map the pages starting at '*virt' and
2024 * update '*virt' with the first usable address after the mapped region.
2027 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2028 vm_paddr_t pa_end, int prot)
2030 vm_offset_t sva, va;
2032 if (hw_direct_map) {
2034 * Check if every page in the region is covered by the direct
2035 * map. The direct map covers all of physical memory. Use
2036 * moea64_calc_wimg() as a shortcut to see if the page is in
2037 * physical memory as a way to see if the direct map covers it.
2039 for (va = pa_start; va < pa_end; va += PAGE_SIZE)
2040 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
2043 return (PHYS_TO_DMAP(pa_start));
2047 /* XXX respect prot argument */
2048 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
2049 moea64_kenter(mmu, va, pa_start);
2056 * Returns true if the pmap's pv is one of the first
2057 * 16 pvs linked to from this page. This count may
2058 * be changed upwards or downwards in the future; it
2059 * is only necessary that true be returned for a small
2060 * subset of pmaps for proper page aging.
2063 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2066 struct pvo_entry *pvo;
2069 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2070 ("moea64_page_exists_quick: page %p is not managed", m));
2074 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2075 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
2087 moea64_page_init(mmu_t mmu __unused, vm_page_t m)
2090 m->md.mdpg_attrs = 0;
2091 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
2092 LIST_INIT(&m->md.mdpg_pvoh);
2096 * Return the number of managed mappings to the given physical page
2100 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
2102 struct pvo_entry *pvo;
2106 if ((m->oflags & VPO_UNMANAGED) != 0)
2109 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
2110 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2116 static uintptr_t moea64_vsidcontext;
2119 moea64_get_unique_vsid(void) {
2126 __asm __volatile("mftb %0" : "=r"(entropy));
2128 mtx_lock(&moea64_slb_mutex);
2129 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2133 * Create a new value by mutiplying by a prime and adding in
2134 * entropy from the timebase register. This is to make the
2135 * VSID more random so that the PT hash function collides
2136 * less often. (Note that the prime casues gcc to do shifts
2137 * instead of a multiply.)
2139 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2140 hash = moea64_vsidcontext & (NVSIDS - 1);
2141 if (hash == 0) /* 0 is special, avoid it */
2144 mask = 1 << (hash & (VSID_NBPW - 1));
2145 hash = (moea64_vsidcontext & VSID_HASHMASK);
2146 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
2147 /* anything free in this bucket? */
2148 if (moea64_vsid_bitmap[n] == 0xffffffff) {
2149 entropy = (moea64_vsidcontext >> 20);
2152 i = ffs(~moea64_vsid_bitmap[n]) - 1;
2154 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2157 if (hash == VSID_VRMA) /* also special, avoid this too */
2159 KASSERT(!(moea64_vsid_bitmap[n] & mask),
2160 ("Allocating in-use VSID %#zx\n", hash));
2161 moea64_vsid_bitmap[n] |= mask;
2162 mtx_unlock(&moea64_slb_mutex);
2166 mtx_unlock(&moea64_slb_mutex);
2167 panic("%s: out of segments",__func__);
2170 #ifdef __powerpc64__
2172 moea64_pinit(mmu_t mmu, pmap_t pmap)
2175 RB_INIT(&pmap->pmap_pvo);
2177 pmap->pm_slb_tree_root = slb_alloc_tree();
2178 pmap->pm_slb = slb_alloc_user_cache();
2179 pmap->pm_slb_len = 0;
2183 moea64_pinit(mmu_t mmu, pmap_t pmap)
2188 RB_INIT(&pmap->pmap_pvo);
2190 if (pmap_bootstrapped)
2191 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
2194 pmap->pmap_phys = pmap;
2197 * Allocate some segment registers for this pmap.
2199 hash = moea64_get_unique_vsid();
2201 for (i = 0; i < 16; i++)
2202 pmap->pm_sr[i] = VSID_MAKE(i, hash);
2204 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2209 * Initialize the pmap associated with process 0.
2212 moea64_pinit0(mmu_t mmu, pmap_t pm)
2216 moea64_pinit(mmu, pm);
2217 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2221 * Set the physical protection on the specified range of this map as requested.
2224 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2230 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2233 * Change the protection of the page.
2235 oldprot = pvo->pvo_pte.prot;
2236 pvo->pvo_pte.prot = prot;
2237 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2240 * If the PVO is in the page table, update mapping
2242 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE);
2244 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2246 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2247 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2248 if ((pg->oflags & VPO_UNMANAGED) == 0)
2249 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2250 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2251 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE);
2255 * Update vm about the REF/CHG bits if the page is managed and we have
2256 * removed write access.
2258 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2259 (oldprot & VM_PROT_WRITE)) {
2260 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2261 if (refchg & LPTE_CHG)
2263 if (refchg & LPTE_REF)
2264 vm_page_aflag_set(pg, PGA_REFERENCED);
2269 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2272 struct pvo_entry *pvo, *tpvo, key;
2274 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2277 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2278 ("moea64_protect: non current pmap"));
2280 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2281 moea64_remove(mmu, pm, sva, eva);
2286 key.pvo_vaddr = sva;
2287 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2288 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2289 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2290 moea64_pvo_protect(mmu, pm, pvo, prot);
2296 * Map a list of wired pages into kernel virtual address space. This is
2297 * intended for temporary mappings which do not need page modification or
2298 * references recorded. Existing mappings in the region are overwritten.
2301 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2303 while (count-- > 0) {
2304 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2311 * Remove page mappings from kernel virtual address space. Intended for
2312 * temporary mappings entered by moea64_qenter.
2315 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2317 while (count-- > 0) {
2318 moea64_kremove(mmu, va);
2324 moea64_release_vsid(uint64_t vsid)
2328 mtx_lock(&moea64_slb_mutex);
2329 idx = vsid & (NVSIDS-1);
2330 mask = 1 << (idx % VSID_NBPW);
2332 KASSERT(moea64_vsid_bitmap[idx] & mask,
2333 ("Freeing unallocated VSID %#jx", vsid));
2334 moea64_vsid_bitmap[idx] &= ~mask;
2335 mtx_unlock(&moea64_slb_mutex);
2340 moea64_release(mmu_t mmu, pmap_t pmap)
2344 * Free segment registers' VSIDs
2346 #ifdef __powerpc64__
2347 slb_free_tree(pmap);
2348 slb_free_user_cache(pmap->pm_slb);
2350 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2352 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2357 * Remove all pages mapped by the specified pmap
2360 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2362 struct pvo_entry *pvo, *tpvo;
2363 struct pvo_dlist tofree;
2365 SLIST_INIT(&tofree);
2368 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2369 if (pvo->pvo_vaddr & PVO_WIRED)
2373 * For locking reasons, remove this from the page table and
2374 * pmap, but save delinking from the vm_page for a second
2377 moea64_pvo_remove_from_pmap(mmu, pvo);
2378 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink);
2382 while (!SLIST_EMPTY(&tofree)) {
2383 pvo = SLIST_FIRST(&tofree);
2384 SLIST_REMOVE_HEAD(&tofree, pvo_dlink);
2385 moea64_pvo_remove_from_page(mmu, pvo);
2386 free_pvo_entry(pvo);
2391 * Remove the given range of addresses from the specified map.
2394 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2396 struct pvo_entry *pvo, *tpvo, key;
2397 struct pvo_dlist tofree;
2400 * Perform an unsynchronized read. This is, however, safe.
2402 if (pm->pm_stats.resident_count == 0)
2405 key.pvo_vaddr = sva;
2407 SLIST_INIT(&tofree);
2410 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2411 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2412 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2415 * For locking reasons, remove this from the page table and
2416 * pmap, but save delinking from the vm_page for a second
2419 moea64_pvo_remove_from_pmap(mmu, pvo);
2420 SLIST_INSERT_HEAD(&tofree, pvo, pvo_dlink);
2424 while (!SLIST_EMPTY(&tofree)) {
2425 pvo = SLIST_FIRST(&tofree);
2426 SLIST_REMOVE_HEAD(&tofree, pvo_dlink);
2427 moea64_pvo_remove_from_page(mmu, pvo);
2428 free_pvo_entry(pvo);
2433 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2434 * will reflect changes in pte's back to the vm_page.
2437 moea64_remove_all(mmu_t mmu, vm_page_t m)
2439 struct pvo_entry *pvo, *next_pvo;
2440 struct pvo_head freequeue;
2444 LIST_INIT(&freequeue);
2447 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2448 pmap = pvo->pvo_pmap;
2450 wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2452 moea64_pvo_remove_from_pmap(mmu, pvo);
2453 moea64_pvo_remove_from_page_locked(mmu, pvo, m);
2455 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2459 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2460 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable"));
2463 /* Clean up UMA allocations */
2464 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2465 free_pvo_entry(pvo);
2469 * Allocate a physical page of memory directly from the phys_avail map.
2470 * Can only be called from moea64_bootstrap before avail start and end are
2474 moea64_bootstrap_alloc(vm_size_t size, vm_size_t align)
2479 size = round_page(size);
2480 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2482 s = roundup2(phys_avail[i], align);
2487 if (s < phys_avail[i] || e > phys_avail[i + 1])
2490 if (s + size > platform_real_maxaddr())
2493 if (s == phys_avail[i]) {
2494 phys_avail[i] += size;
2495 } else if (e == phys_avail[i + 1]) {
2496 phys_avail[i + 1] -= size;
2498 for (j = phys_avail_count * 2; j > i; j -= 2) {
2499 phys_avail[j] = phys_avail[j - 2];
2500 phys_avail[j + 1] = phys_avail[j - 1];
2503 phys_avail[i + 3] = phys_avail[i + 1];
2504 phys_avail[i + 1] = s;
2505 phys_avail[i + 2] = e;
2511 panic("moea64_bootstrap_alloc: could not allocate memory");
2515 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head,
2516 struct pvo_entry **oldpvop)
2519 struct pvo_entry *old_pvo;
2521 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2523 STAT_MOEA64(moea64_pvo_enter_calls++);
2528 old_pvo = RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2530 if (old_pvo != NULL) {
2531 if (oldpvop != NULL)
2537 * Remember if the list was empty and therefore will be the first
2540 if (pvo_head != NULL) {
2541 if (LIST_FIRST(pvo_head) == NULL)
2543 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2546 if (pvo->pvo_vaddr & PVO_WIRED)
2547 pvo->pvo_pmap->pm_stats.wired_count++;
2548 pvo->pvo_pmap->pm_stats.resident_count++;
2551 * Insert it into the hardware page table
2553 err = MOEA64_PTE_INSERT(mmu, pvo);
2555 panic("moea64_pvo_enter: overflow");
2558 STAT_MOEA64(moea64_pvo_entries++);
2560 if (pvo->pvo_pmap == kernel_pmap)
2563 #ifdef __powerpc64__
2565 * Make sure all our bootstrap mappings are in the SLB as soon
2566 * as virtual memory is switched on.
2568 if (!pmap_bootstrapped)
2569 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2570 pvo->pvo_vaddr & PVO_LARGE);
2573 return (first ? ENOENT : 0);
2577 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo)
2582 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2583 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2584 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2587 * If there is an active pte entry, we need to deactivate it
2589 refchg = MOEA64_PTE_UNSET(mmu, pvo);
2592 * If it was evicted from the page table, be pessimistic and
2595 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2602 * Update our statistics.
2604 pvo->pvo_pmap->pm_stats.resident_count--;
2605 if (pvo->pvo_vaddr & PVO_WIRED)
2606 pvo->pvo_pmap->pm_stats.wired_count--;
2609 * Remove this PVO from the pmap list.
2611 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2614 * Mark this for the next sweep
2616 pvo->pvo_vaddr |= PVO_DEAD;
2618 /* Send RC bits to VM */
2619 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2620 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2621 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2623 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2624 if (refchg & LPTE_CHG)
2626 if (refchg & LPTE_REF)
2627 vm_page_aflag_set(pg, PGA_REFERENCED);
2633 moea64_pvo_remove_from_page_locked(mmu_t mmu, struct pvo_entry *pvo,
2637 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
2639 /* Use NULL pmaps as a sentinel for races in page deletion */
2640 if (pvo->pvo_pmap == NULL)
2642 pvo->pvo_pmap = NULL;
2645 * Update vm about page writeability/executability if managed
2647 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN);
2648 if (pvo->pvo_vaddr & PVO_MANAGED) {
2650 LIST_REMOVE(pvo, pvo_vlink);
2651 if (LIST_EMPTY(vm_page_to_pvoh(m)))
2652 vm_page_aflag_clear(m,
2653 PGA_WRITEABLE | PGA_EXECUTABLE);
2657 STAT_MOEA64(moea64_pvo_entries--);
2658 STAT_MOEA64(moea64_pvo_remove_calls++);
2662 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo)
2664 vm_page_t pg = NULL;
2666 if (pvo->pvo_vaddr & PVO_MANAGED)
2667 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2669 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2670 moea64_pvo_remove_from_page_locked(mmu, pvo, pg);
2671 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2674 static struct pvo_entry *
2675 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2677 struct pvo_entry key;
2679 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2681 key.pvo_vaddr = va & ~ADDR_POFF;
2682 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2686 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit)
2688 struct pvo_entry *pvo;
2693 * See if this bit is stored in the page already.
2695 if (m->md.mdpg_attrs & ptebit)
2699 * Examine each PTE. Sync so that any pending REF/CHG bits are
2700 * flushed to the PTEs.
2705 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2709 * See if this pvo has a valid PTE. if so, fetch the
2710 * REF/CHG bits from the valid PTE. If the appropriate
2711 * ptebit is set, return success.
2713 PMAP_LOCK(pvo->pvo_pmap);
2714 if (!(pvo->pvo_vaddr & PVO_DEAD))
2715 ret = MOEA64_PTE_SYNCH(mmu, pvo);
2716 PMAP_UNLOCK(pvo->pvo_pmap);
2719 atomic_set_32(&m->md.mdpg_attrs,
2720 ret & (LPTE_CHG | LPTE_REF));
2733 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2736 struct pvo_entry *pvo;
2740 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2741 * we can reset the right ones).
2746 * For each pvo entry, clear the pte's ptebit.
2750 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2753 PMAP_LOCK(pvo->pvo_pmap);
2754 if (!(pvo->pvo_vaddr & PVO_DEAD))
2755 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit);
2756 PMAP_UNLOCK(pvo->pvo_pmap);
2758 if (ret > 0 && (ret & ptebit))
2761 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
2768 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2770 struct pvo_entry *pvo, key;
2774 if (hw_direct_map && mem_valid(pa, size) == 0)
2777 PMAP_LOCK(kernel_pmap);
2778 ppa = pa & ~ADDR_POFF;
2779 key.pvo_vaddr = DMAP_BASE_ADDRESS + ppa;
2780 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2781 ppa < pa + size; ppa += PAGE_SIZE,
2782 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2783 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) {
2788 PMAP_UNLOCK(kernel_pmap);
2794 * Map a set of physical memory pages into the kernel virtual
2795 * address space. Return a pointer to where it is mapped. This
2796 * routine is intended to be used for mapping device memory,
2800 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2802 vm_offset_t va, tmpva, ppa, offset;
2804 ppa = trunc_page(pa);
2805 offset = pa & PAGE_MASK;
2806 size = roundup2(offset + size, PAGE_SIZE);
2808 va = kva_alloc(size);
2811 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2813 for (tmpva = va; size > 0;) {
2814 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2820 return ((void *)(va + offset));
2824 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2827 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2831 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2833 vm_offset_t base, offset;
2835 base = trunc_page(va);
2836 offset = va & PAGE_MASK;
2837 size = roundup2(offset + size, PAGE_SIZE);
2839 kva_free(base, size);
2843 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2845 struct pvo_entry *pvo;
2850 if (__predict_false(pm == NULL))
2851 pm = &curthread->td_proc->p_vmspace->vm_pmap;
2855 lim = round_page(va+1);
2856 len = MIN(lim - va, sz);
2857 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2858 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
2859 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF);
2860 moea64_syncicache(mmu, pm, va, pa, len);
2869 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2872 *va = (void *)(uintptr_t)pa;
2875 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2878 moea64_scan_init(mmu_t mmu)
2880 struct pvo_entry *pvo;
2885 /* Initialize phys. segments for dumpsys(). */
2886 memset(&dump_map, 0, sizeof(dump_map));
2887 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2888 for (i = 0; i < pregions_sz; i++) {
2889 dump_map[i].pa_start = pregions[i].mr_start;
2890 dump_map[i].pa_size = pregions[i].mr_size;
2895 /* Virtual segments for minidumps: */
2896 memset(&dump_map, 0, sizeof(dump_map));
2898 /* 1st: kernel .data and .bss. */
2899 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2900 dump_map[0].pa_size = round_page((uintptr_t)_end) -
2901 dump_map[0].pa_start;
2903 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2904 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr;
2905 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2907 /* 3rd: kernel VM. */
2908 va = dump_map[1].pa_start + dump_map[1].pa_size;
2909 /* Find start of next chunk (from va). */
2910 while (va < virtual_end) {
2911 /* Don't dump the buffer cache. */
2912 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2913 va = kmi.buffer_eva;
2916 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2917 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2921 if (va < virtual_end) {
2922 dump_map[2].pa_start = va;
2924 /* Find last page in chunk. */
2925 while (va < virtual_end) {
2926 /* Don't run into the buffer cache. */
2927 if (va == kmi.buffer_sva)
2929 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2930 if (pvo == NULL || (pvo->pvo_vaddr & PVO_DEAD))
2934 dump_map[2].pa_size = va - dump_map[2].pa_start;
2938 #ifdef __powerpc64__
2941 moea64_scan_pmap(mmu_t mmu)
2943 struct pvo_entry *pvo;
2944 vm_paddr_t pa, pa_end;
2945 vm_offset_t va, pgva, kstart, kend, kstart_lp, kend_lp;
2948 lpsize = moea64_large_page_size;
2949 kstart = trunc_page((vm_offset_t)_etext);
2950 kend = round_page((vm_offset_t)_end);
2951 kstart_lp = kstart & ~moea64_large_page_mask;
2952 kend_lp = (kend + moea64_large_page_mask) & ~moea64_large_page_mask;
2954 CTR4(KTR_PMAP, "moea64_scan_pmap: kstart=0x%016lx, kend=0x%016lx, "
2955 "kstart_lp=0x%016lx, kend_lp=0x%016lx",
2956 kstart, kend, kstart_lp, kend_lp);
2958 PMAP_LOCK(kernel_pmap);
2959 RB_FOREACH(pvo, pvo_tree, &kernel_pmap->pmap_pvo) {
2960 va = pvo->pvo_vaddr;
2965 /* Skip DMAP (except kernel area) */
2966 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS) {
2967 if (va & PVO_LARGE) {
2968 pgva = va & ~moea64_large_page_mask;
2969 if (pgva < kstart_lp || pgva >= kend_lp)
2972 pgva = trunc_page(va);
2973 if (pgva < kstart || pgva >= kend)
2978 pa = pvo->pvo_pte.pa & LPTE_RPGN;
2980 if (va & PVO_LARGE) {
2981 pa_end = pa + lpsize;
2982 for (; pa < pa_end; pa += PAGE_SIZE) {
2983 if (is_dumpable(pa))
2987 if (is_dumpable(pa))
2991 PMAP_UNLOCK(kernel_pmap);
2993 return (sizeof(struct lpte) * moea64_pteg_count * 8);
2996 static struct dump_context dump_ctx;
2999 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs)
3002 dump_ctx.ptex_end = moea64_pteg_count * 8;
3003 dump_ctx.blksz = blkpgs * PAGE_SIZE;
3010 moea64_scan_pmap(mmu_t mmu)
3016 moea64_dump_pmap_init(mmu_t mmu, unsigned blkpgs)