2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008-2015 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Manages physical address maps.
35 * Since the information managed by this module is also stored by the
36 * logical address mapping module, this module may throw away valid virtual
37 * to physical mappings at almost any time. However, invalidations of
38 * mappings must be done as requested.
40 * In order to cope with hardware architectures which make virtual to
41 * physical map invalidates expensive, this module may delay invalidate
42 * reduced protection operations until such time as they are actually
43 * necessary. This module is given full information as to which processors
44 * are currently using which maps, and to when physical maps must be made
48 #include "opt_compat.h"
49 #include "opt_kstack_pages.h"
51 #include <sys/param.h>
52 #include <sys/kernel.h>
54 #include <sys/queue.h>
55 #include <sys/cpuset.h>
56 #include <sys/kerneldump.h>
59 #include <sys/msgbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/mutex.h>
63 #include <sys/rwlock.h>
64 #include <sys/sched.h>
65 #include <sys/sysctl.h>
66 #include <sys/systm.h>
67 #include <sys/vmmeter.h>
72 #include <dev/ofw/openfirm.h>
75 #include <vm/vm_param.h>
76 #include <vm/vm_kern.h>
77 #include <vm/vm_page.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_object.h>
80 #include <vm/vm_extern.h>
81 #include <vm/vm_pageout.h>
84 #include <machine/_inttypes.h>
85 #include <machine/cpu.h>
86 #include <machine/platform.h>
87 #include <machine/frame.h>
88 #include <machine/md_var.h>
89 #include <machine/psl.h>
90 #include <machine/bat.h>
91 #include <machine/hid.h>
92 #include <machine/pte.h>
93 #include <machine/sr.h>
94 #include <machine/trap.h>
95 #include <machine/mmuvar.h>
97 #include "mmu_oea64.h"
99 #include "moea64_if.h"
101 void moea64_release_vsid(uint64_t vsid);
102 uintptr_t moea64_get_unique_vsid(void);
104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
105 #define ENABLE_TRANS(msr) mtmsr(msr)
107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
109 #define VSID_HASH_MASK 0x0000007fffffffffULL
114 * There are two locks of interest: the page locks and the pmap locks, which
115 * protect their individual PVO lists and are locked in that order. The contents
116 * of all PVO entries are protected by the locks of their respective pmaps.
117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
122 #define PV_LOCK_COUNT PA_LOCK_COUNT*3
123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
125 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT]))
126 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa))
127 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa))
128 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
129 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m))
130 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m))
131 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
140 extern unsigned char _etext[];
141 extern unsigned char _end[];
144 * Map of physical memory regions.
146 static struct mem_region *regions;
147 static struct mem_region *pregions;
148 static u_int phys_avail_count;
149 static int regions_sz, pregions_sz;
151 extern void bs_remap_earlyboot(void);
154 * Lock for the SLB tables.
156 struct mtx moea64_slb_mutex;
161 u_int moea64_pteg_count;
162 u_int moea64_pteg_mask;
168 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */
170 static struct pvo_entry *moea64_bpvo_pool;
171 static int moea64_bpvo_pool_index = 0;
172 static int moea64_bpvo_pool_size = 327680;
173 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
174 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
175 &moea64_bpvo_pool_index, 0, "");
177 #define VSID_NBPW (sizeof(u_int32_t) * 8)
179 #define NVSIDS (NPMAPS * 16)
180 #define VSID_HASHMASK 0xffffffffUL
182 #define NVSIDS NPMAPS
183 #define VSID_HASHMASK 0xfffffUL
185 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
187 static boolean_t moea64_initialized = FALSE;
192 u_int moea64_pte_valid = 0;
193 u_int moea64_pte_overflow = 0;
194 u_int moea64_pvo_entries = 0;
195 u_int moea64_pvo_enter_calls = 0;
196 u_int moea64_pvo_remove_calls = 0;
197 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
198 &moea64_pte_valid, 0, "");
199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
200 &moea64_pte_overflow, 0, "");
201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
202 &moea64_pvo_entries, 0, "");
203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
204 &moea64_pvo_enter_calls, 0, "");
205 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
206 &moea64_pvo_remove_calls, 0, "");
208 vm_offset_t moea64_scratchpage_va[2];
209 struct pvo_entry *moea64_scratchpage_pvo[2];
210 struct mtx moea64_scratchpage_mtx;
212 uint64_t moea64_large_page_mask = 0;
213 uint64_t moea64_large_page_size = 0;
214 int moea64_large_page_shift = 0;
219 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo,
220 struct pvo_head *pvo_head);
221 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo);
222 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo);
223 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
228 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t);
229 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t);
230 static void moea64_kremove(mmu_t, vm_offset_t);
231 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
232 vm_paddr_t pa, vm_size_t sz);
233 static void moea64_pmap_init_qpages(void);
236 * Kernel MMU interface
238 void moea64_clear_modify(mmu_t, vm_page_t);
239 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
240 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
241 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
242 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
243 u_int flags, int8_t psind);
244 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
246 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
247 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
248 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
249 void moea64_init(mmu_t);
250 boolean_t moea64_is_modified(mmu_t, vm_page_t);
251 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
252 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
253 int moea64_ts_referenced(mmu_t, vm_page_t);
254 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
255 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
256 void moea64_page_init(mmu_t, vm_page_t);
257 int moea64_page_wired_mappings(mmu_t, vm_page_t);
258 void moea64_pinit(mmu_t, pmap_t);
259 void moea64_pinit0(mmu_t, pmap_t);
260 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
261 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
262 void moea64_qremove(mmu_t, vm_offset_t, int);
263 void moea64_release(mmu_t, pmap_t);
264 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
265 void moea64_remove_pages(mmu_t, pmap_t);
266 void moea64_remove_all(mmu_t, vm_page_t);
267 void moea64_remove_write(mmu_t, vm_page_t);
268 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
269 void moea64_zero_page(mmu_t, vm_page_t);
270 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
271 void moea64_activate(mmu_t, struct thread *);
272 void moea64_deactivate(mmu_t, struct thread *);
273 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
274 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
275 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
276 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
277 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
278 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma);
279 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
280 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
281 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
282 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz,
284 void moea64_scan_init(mmu_t mmu);
285 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m);
286 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr);
287 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm,
288 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
291 static mmu_method_t moea64_methods[] = {
292 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
293 MMUMETHOD(mmu_copy_page, moea64_copy_page),
294 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
295 MMUMETHOD(mmu_enter, moea64_enter),
296 MMUMETHOD(mmu_enter_object, moea64_enter_object),
297 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
298 MMUMETHOD(mmu_extract, moea64_extract),
299 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
300 MMUMETHOD(mmu_init, moea64_init),
301 MMUMETHOD(mmu_is_modified, moea64_is_modified),
302 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
303 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
304 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
305 MMUMETHOD(mmu_map, moea64_map),
306 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
307 MMUMETHOD(mmu_page_init, moea64_page_init),
308 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
309 MMUMETHOD(mmu_pinit, moea64_pinit),
310 MMUMETHOD(mmu_pinit0, moea64_pinit0),
311 MMUMETHOD(mmu_protect, moea64_protect),
312 MMUMETHOD(mmu_qenter, moea64_qenter),
313 MMUMETHOD(mmu_qremove, moea64_qremove),
314 MMUMETHOD(mmu_release, moea64_release),
315 MMUMETHOD(mmu_remove, moea64_remove),
316 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
317 MMUMETHOD(mmu_remove_all, moea64_remove_all),
318 MMUMETHOD(mmu_remove_write, moea64_remove_write),
319 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
320 MMUMETHOD(mmu_unwire, moea64_unwire),
321 MMUMETHOD(mmu_zero_page, moea64_zero_page),
322 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
323 MMUMETHOD(mmu_activate, moea64_activate),
324 MMUMETHOD(mmu_deactivate, moea64_deactivate),
325 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
326 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page),
327 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page),
329 /* Internal interfaces */
330 MMUMETHOD(mmu_mapdev, moea64_mapdev),
331 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
332 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
333 MMUMETHOD(mmu_kextract, moea64_kextract),
334 MMUMETHOD(mmu_kenter, moea64_kenter),
335 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
336 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
337 MMUMETHOD(mmu_scan_init, moea64_scan_init),
338 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
339 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr),
344 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
346 static struct pvo_head *
347 vm_page_to_pvoh(vm_page_t m)
350 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
351 return (&m->md.mdpg_pvoh);
354 static struct pvo_entry *
355 alloc_pvo_entry(int bootstrap)
357 struct pvo_entry *pvo;
359 if (!moea64_initialized || bootstrap) {
360 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
361 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
362 moea64_bpvo_pool_index, moea64_bpvo_pool_size,
363 moea64_bpvo_pool_size * sizeof(struct pvo_entry));
365 pvo = &moea64_bpvo_pool[
366 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
367 bzero(pvo, sizeof(*pvo));
368 pvo->pvo_vaddr = PVO_BOOTSTRAP;
370 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT);
371 bzero(pvo, sizeof(*pvo));
379 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
385 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
387 pvo->pvo_pmap = pmap;
389 pvo->pvo_vaddr |= va;
390 vsid = va_to_vsid(pmap, va);
391 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
394 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift :
396 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
397 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
401 free_pvo_entry(struct pvo_entry *pvo)
404 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
405 uma_zfree(moea64_pvo_zone, pvo);
409 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
412 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) &
414 lpte->pte_hi |= LPTE_VALID;
416 if (pvo->pvo_vaddr & PVO_LARGE)
417 lpte->pte_hi |= LPTE_BIG;
418 if (pvo->pvo_vaddr & PVO_WIRED)
419 lpte->pte_hi |= LPTE_WIRED;
420 if (pvo->pvo_vaddr & PVO_HID)
421 lpte->pte_hi |= LPTE_HID;
423 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
424 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
425 lpte->pte_lo |= LPTE_BW;
427 lpte->pte_lo |= LPTE_BR;
429 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
430 lpte->pte_lo |= LPTE_NOEXEC;
433 static __inline uint64_t
434 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
439 if (ma != VM_MEMATTR_DEFAULT) {
441 case VM_MEMATTR_UNCACHEABLE:
442 return (LPTE_I | LPTE_G);
443 case VM_MEMATTR_CACHEABLE:
445 case VM_MEMATTR_WRITE_COMBINING:
446 case VM_MEMATTR_WRITE_BACK:
447 case VM_MEMATTR_PREFETCHABLE:
449 case VM_MEMATTR_WRITE_THROUGH:
450 return (LPTE_W | LPTE_M);
455 * Assume the page is cache inhibited and access is guarded unless
456 * it's in our available memory array.
458 pte_lo = LPTE_I | LPTE_G;
459 for (i = 0; i < pregions_sz; i++) {
460 if ((pa >= pregions[i].mr_start) &&
461 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
462 pte_lo &= ~(LPTE_I | LPTE_G);
472 * Quick sort callout for comparing memory regions.
474 static int om_cmp(const void *a, const void *b);
477 om_cmp(const void *a, const void *b)
479 const struct ofw_map *mapa;
480 const struct ofw_map *mapb;
484 if (mapa->om_pa < mapb->om_pa)
486 else if (mapa->om_pa > mapb->om_pa)
493 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
495 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
496 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
497 struct pvo_entry *pvo;
503 bzero(translations, sz);
504 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
506 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
507 panic("moea64_bootstrap: can't get ofw translations");
509 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
510 sz /= sizeof(cell_t);
511 for (i = 0, j = 0; i < sz; j++) {
512 translations[j].om_va = trans_cells[i++];
513 translations[j].om_len = trans_cells[i++];
514 translations[j].om_pa = trans_cells[i++];
516 translations[j].om_pa <<= 32;
517 translations[j].om_pa |= trans_cells[i++];
519 translations[j].om_mode = trans_cells[i++];
521 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
525 qsort(translations, sz, sizeof (*translations), om_cmp);
527 for (i = 0; i < sz; i++) {
528 pa_base = translations[i].om_pa;
529 #ifndef __powerpc64__
530 if ((translations[i].om_pa >> 32) != 0)
531 panic("OFW translations above 32-bit boundary!");
534 if (pa_base % PAGE_SIZE)
535 panic("OFW translation not page-aligned (phys)!");
536 if (translations[i].om_va % PAGE_SIZE)
537 panic("OFW translation not page-aligned (virt)!");
539 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
540 pa_base, translations[i].om_va, translations[i].om_len);
542 /* Now enter the pages for this mapping */
545 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
546 /* If this address is direct-mapped, skip remapping */
548 translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
549 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M)
552 PMAP_LOCK(kernel_pmap);
553 pvo = moea64_pvo_find_va(kernel_pmap,
554 translations[i].om_va + off);
555 PMAP_UNLOCK(kernel_pmap);
559 moea64_kenter(mmup, translations[i].om_va + off,
568 moea64_probe_large_page(void)
570 uint16_t pvr = mfpvr() >> 16;
576 powerpc_sync(); isync();
577 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
578 powerpc_sync(); isync();
582 if (moea64_large_page_size == 0) {
583 moea64_large_page_size = 0x1000000; /* 16 MB */
584 moea64_large_page_shift = 24;
588 moea64_large_page_mask = moea64_large_page_size - 1;
592 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
599 cache = PCPU_GET(slb);
600 esid = va >> ADDR_SR_SHFT;
601 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
603 for (i = 0; i < 64; i++) {
604 if (cache[i].slbe == (slbe | i))
609 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
611 entry.slbv |= SLBV_L;
613 slb_insert_kernel(entry.slbe, entry.slbv);
618 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
619 vm_offset_t kernelend)
621 struct pvo_entry *pvo;
624 vm_offset_t size, off;
628 if (moea64_large_page_size == 0)
633 PMAP_LOCK(kernel_pmap);
634 for (i = 0; i < pregions_sz; i++) {
635 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
636 pregions[i].mr_size; pa += moea64_large_page_size) {
639 pvo = alloc_pvo_entry(1 /* bootstrap */);
640 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
641 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa));
644 * Set memory access as guarded if prefetch within
645 * the page could exit the available physmem area.
647 if (pa & moea64_large_page_mask) {
648 pa &= moea64_large_page_mask;
651 if (pa + moea64_large_page_size >
652 pregions[i].mr_start + pregions[i].mr_size)
655 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
657 pvo->pvo_pte.pa = pa | pte_lo;
658 moea64_pvo_enter(mmup, pvo, NULL);
661 PMAP_UNLOCK(kernel_pmap);
663 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
664 off = (vm_offset_t)(moea64_bpvo_pool);
665 for (pa = off; pa < off + size; pa += PAGE_SIZE)
666 moea64_kenter(mmup, pa, pa);
669 * Map certain important things, like ourselves.
671 * NOTE: We do not map the exception vector space. That code is
672 * used only in real mode, and leaving it unmapped allows us to
673 * catch NULL pointer deferences, instead of making NULL a valid
677 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
679 moea64_kenter(mmup, pa, pa);
684 * Allow user to override unmapped_buf_allowed for testing.
685 * XXXKIB Only direct map implementation was tested.
687 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
688 &unmapped_buf_allowed))
689 unmapped_buf_allowed = hw_direct_map;
693 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
696 vm_size_t physsz, hwphyssz;
698 #ifndef __powerpc64__
699 /* We don't have a direct map since there is no BAT */
702 /* Make sure battable is zero, since we have no BAT */
703 for (i = 0; i < 16; i++) {
704 battable[i].batu = 0;
705 battable[i].batl = 0;
708 moea64_probe_large_page();
710 /* Use a direct map if we have large page support */
711 if (moea64_large_page_size > 0)
717 /* Get physical memory regions from firmware */
718 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
719 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
721 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
722 panic("moea64_bootstrap: phys_avail too small");
724 phys_avail_count = 0;
727 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
728 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
729 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
730 regions[i].mr_start, regions[i].mr_start +
731 regions[i].mr_size, regions[i].mr_size);
733 (physsz + regions[i].mr_size) >= hwphyssz) {
734 if (physsz < hwphyssz) {
735 phys_avail[j] = regions[i].mr_start;
736 phys_avail[j + 1] = regions[i].mr_start +
743 phys_avail[j] = regions[i].mr_start;
744 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
746 physsz += regions[i].mr_size;
749 /* Check for overlap with the kernel and exception vectors */
750 for (j = 0; j < 2*phys_avail_count; j+=2) {
751 if (phys_avail[j] < EXC_LAST)
752 phys_avail[j] += EXC_LAST;
754 if (kernelstart >= phys_avail[j] &&
755 kernelstart < phys_avail[j+1]) {
756 if (kernelend < phys_avail[j+1]) {
757 phys_avail[2*phys_avail_count] =
758 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
759 phys_avail[2*phys_avail_count + 1] =
764 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
767 if (kernelend >= phys_avail[j] &&
768 kernelend < phys_avail[j+1]) {
769 if (kernelstart > phys_avail[j]) {
770 phys_avail[2*phys_avail_count] = phys_avail[j];
771 phys_avail[2*phys_avail_count + 1] =
772 kernelstart & ~PAGE_MASK;
776 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
780 physmem = btoc(physsz);
783 moea64_pteg_count = PTEGCOUNT;
785 moea64_pteg_count = 0x1000;
787 while (moea64_pteg_count < physmem)
788 moea64_pteg_count <<= 1;
790 moea64_pteg_count >>= 1;
791 #endif /* PTEGCOUNT */
795 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
802 moea64_pteg_mask = moea64_pteg_count - 1;
805 * Initialize SLB table lock and page locks
807 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
808 for (i = 0; i < PV_LOCK_COUNT; i++)
809 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
812 * Initialise the bootstrap pvo pool.
814 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
815 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0);
816 moea64_bpvo_pool_index = 0;
819 * Make sure kernel vsid is allocated as well as VSID 0.
821 #ifndef __powerpc64__
822 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
823 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
824 moea64_vsid_bitmap[0] |= 1;
828 * Initialize the kernel pmap (which is statically allocated).
831 for (i = 0; i < 64; i++) {
832 pcpup->pc_slb[i].slbv = 0;
833 pcpup->pc_slb[i].slbe = 0;
836 for (i = 0; i < 16; i++)
837 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
840 kernel_pmap->pmap_phys = kernel_pmap;
841 CPU_FILL(&kernel_pmap->pm_active);
842 RB_INIT(&kernel_pmap->pmap_pvo);
844 PMAP_LOCK_INIT(kernel_pmap);
847 * Now map in all the other buffers we allocated earlier
850 moea64_setup_direct_map(mmup, kernelstart, kernelend);
854 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
865 * Set up the Open Firmware pmap and add its mappings if not in real
869 chosen = OF_finddevice("/chosen");
870 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
871 mmu = OF_instance_to_package(mmui);
873 (sz = OF_getproplen(mmu, "translations")) == -1)
875 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
876 panic("moea64_bootstrap: too many ofw translations");
879 moea64_add_ofw_mappings(mmup, mmu, sz);
883 * Calculate the last available physical address.
886 for (i = 0; phys_avail[i + 2] != 0; i += 2)
887 Maxmem = max(Maxmem, powerpc_btop(phys_avail[i + 1]));
890 * Initialize MMU and remap early physical mappings
892 MMU_CPU_BOOTSTRAP(mmup,0);
893 mtmsr(mfmsr() | PSL_DR | PSL_IR);
895 bs_remap_earlyboot();
898 * Set the start and end of kva.
900 virtual_avail = VM_MIN_KERNEL_ADDRESS;
901 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
904 * Map the entire KVA range into the SLB. We must not fault there.
907 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
908 moea64_bootstrap_slb_prefault(va, 0);
912 * Figure out how far we can extend virtual_end into segment 16
913 * without running into existing mappings. Segment 16 is guaranteed
914 * to contain neither RAM nor devices (at least on Apple hardware),
915 * but will generally contain some OFW mappings we should not
919 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
920 PMAP_LOCK(kernel_pmap);
921 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
922 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
923 virtual_end += PAGE_SIZE;
924 PMAP_UNLOCK(kernel_pmap);
928 * Allocate a kernel stack with a guard page for thread0 and map it
929 * into the kernel page map.
931 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
932 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
933 virtual_avail = va + kstack_pages * PAGE_SIZE;
934 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
935 thread0.td_kstack = va;
936 thread0.td_kstack_pages = kstack_pages;
937 for (i = 0; i < kstack_pages; i++) {
938 moea64_kenter(mmup, va, pa);
944 * Allocate virtual address space for the message buffer.
946 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
947 msgbufp = (struct msgbuf *)virtual_avail;
949 virtual_avail += round_page(msgbufsize);
950 while (va < virtual_avail) {
951 moea64_kenter(mmup, va, pa);
957 * Allocate virtual address space for the dynamic percpu area.
959 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
960 dpcpu = (void *)virtual_avail;
962 virtual_avail += DPCPU_SIZE;
963 while (va < virtual_avail) {
964 moea64_kenter(mmup, va, pa);
968 dpcpu_init(dpcpu, curcpu);
971 * Allocate some things for page zeroing. We put this directly
972 * in the page table and use MOEA64_PTE_REPLACE to avoid any
973 * of the PVO book-keeping or other parts of the VM system
974 * from even knowing that this hack exists.
977 if (!hw_direct_map) {
978 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
980 for (i = 0; i < 2; i++) {
981 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
982 virtual_end -= PAGE_SIZE;
984 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
986 PMAP_LOCK(kernel_pmap);
987 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
988 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
989 PMAP_UNLOCK(kernel_pmap);
995 moea64_pmap_init_qpages(void)
1005 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1006 if (pc->pc_qmap_addr == 0)
1007 panic("pmap_init_qpages: unable to allocate KVA");
1008 PMAP_LOCK(kernel_pmap);
1009 pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1010 PMAP_UNLOCK(kernel_pmap);
1011 mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF);
1015 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1018 * Activate a user pmap. This mostly involves setting some non-CPU
1022 moea64_activate(mmu_t mmu, struct thread *td)
1026 pm = &td->td_proc->p_vmspace->vm_pmap;
1027 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1029 #ifdef __powerpc64__
1030 PCPU_SET(userslb, pm->pm_slb);
1031 __asm __volatile("slbmte %0, %1; isync" ::
1032 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1034 PCPU_SET(curpmap, pm->pmap_phys);
1035 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1040 moea64_deactivate(mmu_t mmu, struct thread *td)
1044 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1046 pm = &td->td_proc->p_vmspace->vm_pmap;
1047 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1048 #ifdef __powerpc64__
1049 PCPU_SET(userslb, NULL);
1051 PCPU_SET(curpmap, NULL);
1056 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1058 struct pvo_entry key, *pvo;
1062 key.pvo_vaddr = sva;
1064 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1065 pvo != NULL && PVO_VADDR(pvo) < eva;
1066 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1067 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1068 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1070 pvo->pvo_vaddr &= ~PVO_WIRED;
1071 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */);
1072 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1073 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1076 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1078 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1079 if (refchg & LPTE_CHG)
1081 if (refchg & LPTE_REF)
1082 vm_page_aflag_set(m, PGA_REFERENCED);
1084 pm->pm_stats.wired_count--;
1090 * This goes through and sets the physical address of our
1091 * special scratch PTE to the PA we want to zero or copy. Because
1092 * of locking issues (this can get called in pvo_enter() by
1093 * the UMA allocator), we can't use most other utility functions here
1097 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) {
1099 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1100 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1102 moea64_scratchpage_pvo[which]->pvo_pte.pa =
1103 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1104 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which],
1105 MOEA64_PTE_INVALIDATE);
1110 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1115 dst = VM_PAGE_TO_PHYS(mdst);
1116 src = VM_PAGE_TO_PHYS(msrc);
1118 if (hw_direct_map) {
1119 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1122 mtx_lock(&moea64_scratchpage_mtx);
1124 moea64_set_scratchpage_pa(mmu, 0, src);
1125 moea64_set_scratchpage_pa(mmu, 1, dst);
1127 bcopy((void *)moea64_scratchpage_va[0],
1128 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1130 mtx_unlock(&moea64_scratchpage_mtx);
1135 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1136 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1139 vm_offset_t a_pg_offset, b_pg_offset;
1142 while (xfersize > 0) {
1143 a_pg_offset = a_offset & PAGE_MASK;
1144 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1145 a_cp = (char *)PHYS_TO_DMAP(
1146 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1148 b_pg_offset = b_offset & PAGE_MASK;
1149 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1150 b_cp = (char *)PHYS_TO_DMAP(
1151 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1153 bcopy(a_cp, b_cp, cnt);
1161 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1162 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1165 vm_offset_t a_pg_offset, b_pg_offset;
1168 mtx_lock(&moea64_scratchpage_mtx);
1169 while (xfersize > 0) {
1170 a_pg_offset = a_offset & PAGE_MASK;
1171 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1172 moea64_set_scratchpage_pa(mmu, 0,
1173 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1174 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1175 b_pg_offset = b_offset & PAGE_MASK;
1176 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1177 moea64_set_scratchpage_pa(mmu, 1,
1178 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1179 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1180 bcopy(a_cp, b_cp, cnt);
1185 mtx_unlock(&moea64_scratchpage_mtx);
1189 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1190 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1193 if (hw_direct_map) {
1194 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1197 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1203 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1205 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1207 if (size + off > PAGE_SIZE)
1208 panic("moea64_zero_page: size + off > PAGE_SIZE");
1210 if (hw_direct_map) {
1211 bzero((caddr_t)PHYS_TO_DMAP(pa) + off, size);
1213 mtx_lock(&moea64_scratchpage_mtx);
1214 moea64_set_scratchpage_pa(mmu, 0, pa);
1215 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1216 mtx_unlock(&moea64_scratchpage_mtx);
1221 * Zero a page of physical memory by temporarily mapping it
1224 moea64_zero_page(mmu_t mmu, vm_page_t m)
1226 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1227 vm_offset_t va, off;
1229 if (!hw_direct_map) {
1230 mtx_lock(&moea64_scratchpage_mtx);
1232 moea64_set_scratchpage_pa(mmu, 0, pa);
1233 va = moea64_scratchpage_va[0];
1235 va = PHYS_TO_DMAP(pa);
1238 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1239 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1242 mtx_unlock(&moea64_scratchpage_mtx);
1246 moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
1248 struct pvo_entry *pvo;
1249 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1252 return (PHYS_TO_DMAP(pa));
1255 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1256 * a critical section and access the PCPU data like on i386.
1257 * Instead, pin the thread and grab the PCPU lock to prevent
1258 * a preempting thread from using the same PCPU data.
1262 mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED);
1263 pvo = PCPU_GET(qmap_pvo);
1265 mtx_lock(PCPU_PTR(qmap_lock));
1266 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1268 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
1271 return (PCPU_GET(qmap_addr));
1275 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1280 mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED);
1281 KASSERT(PCPU_GET(qmap_addr) == addr,
1282 ("moea64_quick_remove_page: invalid address"));
1283 mtx_unlock(PCPU_PTR(qmap_lock));
1288 * Map the given physical page at the specified virtual address in the
1289 * target pmap with the protection requested. If specified the page
1290 * will be wired down.
1294 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1295 vm_prot_t prot, u_int flags, int8_t psind)
1297 struct pvo_entry *pvo, *oldpvo;
1298 struct pvo_head *pvo_head;
1302 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1303 VM_OBJECT_ASSERT_LOCKED(m->object);
1305 pvo = alloc_pvo_entry(0);
1306 pvo->pvo_pmap = NULL; /* to be filled in later */
1307 pvo->pvo_pte.prot = prot;
1309 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1310 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo;
1312 if ((flags & PMAP_ENTER_WIRED) != 0)
1313 pvo->pvo_vaddr |= PVO_WIRED;
1315 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1318 pvo_head = &m->md.mdpg_pvoh;
1319 pvo->pvo_vaddr |= PVO_MANAGED;
1325 if (pvo->pvo_pmap == NULL)
1326 init_pvo_entry(pvo, pmap, va);
1327 if (prot & VM_PROT_WRITE)
1328 if (pmap_bootstrapped &&
1329 (m->oflags & VPO_UNMANAGED) == 0)
1330 vm_page_aflag_set(m, PGA_WRITEABLE);
1332 oldpvo = moea64_pvo_find_va(pmap, va);
1333 if (oldpvo != NULL) {
1334 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1335 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1336 oldpvo->pvo_pte.prot == prot) {
1337 /* Identical mapping already exists */
1340 /* If not in page table, reinsert it */
1341 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) {
1342 moea64_pte_overflow--;
1343 MOEA64_PTE_INSERT(mmu, oldpvo);
1346 /* Then just clean up and go home */
1349 free_pvo_entry(pvo);
1353 /* Otherwise, need to kill it first */
1354 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1355 "mapping does not match new mapping"));
1356 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1358 error = moea64_pvo_enter(mmu, pvo, pvo_head);
1362 /* Free any dead pages */
1363 if (oldpvo != NULL) {
1364 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1365 moea64_pvo_remove_from_page(mmu, oldpvo);
1366 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1367 free_pvo_entry(oldpvo);
1370 if (error != ENOMEM)
1372 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1373 return (KERN_RESOURCE_SHORTAGE);
1374 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1379 * Flush the page from the instruction cache if this page is
1380 * mapped executable and cacheable.
1382 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1383 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1384 vm_page_aflag_set(m, PGA_EXECUTABLE);
1385 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1387 return (KERN_SUCCESS);
1391 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1396 * This is much trickier than on older systems because
1397 * we can't sync the icache on physical addresses directly
1398 * without a direct map. Instead we check a couple of cases
1399 * where the memory is already mapped in and, failing that,
1400 * use the same trick we use for page zeroing to create
1401 * a temporary mapping for this physical address.
1404 if (!pmap_bootstrapped) {
1406 * If PMAP is not bootstrapped, we are likely to be
1409 __syncicache((void *)pa, sz);
1410 } else if (pmap == kernel_pmap) {
1411 __syncicache((void *)va, sz);
1412 } else if (hw_direct_map) {
1413 __syncicache((void *)PHYS_TO_DMAP(pa), sz);
1415 /* Use the scratch page to set up a temp mapping */
1417 mtx_lock(&moea64_scratchpage_mtx);
1419 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1420 __syncicache((void *)(moea64_scratchpage_va[1] +
1421 (va & ADDR_POFF)), sz);
1423 mtx_unlock(&moea64_scratchpage_mtx);
1428 * Maps a sequence of resident pages belonging to the same object.
1429 * The sequence begins with the given page m_start. This page is
1430 * mapped at the given virtual address start. Each subsequent page is
1431 * mapped at a virtual address that is offset from start by the same
1432 * amount as the page is offset from m_start within the object. The
1433 * last page in the sequence is the page with the largest offset from
1434 * m_start that can be mapped at a virtual address less than the given
1435 * virtual address end. Not every virtual page between start and end
1436 * is mapped; only those for which a resident page exists with the
1437 * corresponding offset from m_start are mapped.
1440 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1441 vm_page_t m_start, vm_prot_t prot)
1444 vm_pindex_t diff, psize;
1446 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1448 psize = atop(end - start);
1450 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1451 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1452 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0);
1453 m = TAILQ_NEXT(m, listq);
1458 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1462 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1463 PMAP_ENTER_NOSLEEP, 0);
1467 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1469 struct pvo_entry *pvo;
1473 pvo = moea64_pvo_find_va(pm, va);
1477 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1484 * Atomically extract and hold the physical page with the given
1485 * pmap and virtual address pair if that mapping permits the given
1489 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1491 struct pvo_entry *pvo;
1499 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1500 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1501 if (vm_page_pa_tryrelock(pmap,
1502 pvo->pvo_pte.pa & LPTE_RPGN, &pa))
1504 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1512 static mmu_t installed_mmu;
1515 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1516 uint8_t *flags, int wait)
1518 struct pvo_entry *pvo;
1524 * This entire routine is a horrible hack to avoid bothering kmem
1525 * for new KVA addresses. Because this can get called from inside
1526 * kmem allocation routines, calling kmem for a new address here
1527 * can lead to multiply locking non-recursive mutexes.
1530 *flags = UMA_SLAB_PRIV;
1531 needed_lock = !PMAP_LOCKED(kernel_pmap);
1533 m = vm_page_alloc_domain(NULL, 0, domain,
1534 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ);
1538 va = VM_PAGE_TO_PHYS(m);
1540 pvo = alloc_pvo_entry(1 /* bootstrap */);
1542 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1543 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1546 PMAP_LOCK(kernel_pmap);
1548 init_pvo_entry(pvo, kernel_pmap, va);
1549 pvo->pvo_vaddr |= PVO_WIRED;
1551 moea64_pvo_enter(installed_mmu, pvo, NULL);
1554 PMAP_UNLOCK(kernel_pmap);
1556 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1557 bzero((void *)va, PAGE_SIZE);
1562 extern int elf32_nxstack;
1565 moea64_init(mmu_t mmu)
1568 CTR0(KTR_PMAP, "moea64_init");
1570 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1571 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1572 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1574 if (!hw_direct_map) {
1575 installed_mmu = mmu;
1576 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1579 #ifdef COMPAT_FREEBSD32
1583 moea64_initialized = TRUE;
1587 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1590 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1591 ("moea64_is_referenced: page %p is not managed", m));
1593 return (moea64_query_bit(mmu, m, LPTE_REF));
1597 moea64_is_modified(mmu_t mmu, vm_page_t m)
1600 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1601 ("moea64_is_modified: page %p is not managed", m));
1604 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1605 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1606 * is clear, no PTEs can have LPTE_CHG set.
1608 VM_OBJECT_ASSERT_LOCKED(m->object);
1609 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1611 return (moea64_query_bit(mmu, m, LPTE_CHG));
1615 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1617 struct pvo_entry *pvo;
1618 boolean_t rv = TRUE;
1621 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1629 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1632 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1633 ("moea64_clear_modify: page %p is not managed", m));
1634 VM_OBJECT_ASSERT_WLOCKED(m->object);
1635 KASSERT(!vm_page_xbusied(m),
1636 ("moea64_clear_modify: page %p is exclusive busied", m));
1639 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1640 * set. If the object containing the page is locked and the page is
1641 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1643 if ((m->aflags & PGA_WRITEABLE) == 0)
1645 moea64_clear_bit(mmu, m, LPTE_CHG);
1649 * Clear the write and modified bits in each of the given page's mappings.
1652 moea64_remove_write(mmu_t mmu, vm_page_t m)
1654 struct pvo_entry *pvo;
1655 int64_t refchg, ret;
1658 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1659 ("moea64_remove_write: page %p is not managed", m));
1662 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1663 * set by another thread while the object is locked. Thus,
1664 * if PGA_WRITEABLE is clear, no page table entries need updating.
1666 VM_OBJECT_ASSERT_WLOCKED(m->object);
1667 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1672 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1673 pmap = pvo->pvo_pmap;
1675 if (!(pvo->pvo_vaddr & PVO_DEAD) &&
1676 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1677 pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
1678 ret = MOEA64_PTE_REPLACE(mmu, pvo,
1679 MOEA64_PTE_PROT_UPDATE);
1683 if (pvo->pvo_pmap == kernel_pmap)
1688 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
1690 vm_page_aflag_clear(m, PGA_WRITEABLE);
1695 * moea64_ts_referenced:
1697 * Return a count of reference bits for a page, clearing those bits.
1698 * It is not necessary for every reference bit to be cleared, but it
1699 * is necessary that 0 only be returned when there are truly no
1700 * reference bits set.
1702 * XXX: The exact number of bits to check and clear is a matter that
1703 * should be tested and standardized at some point in the future for
1704 * optimal aging of shared pages.
1707 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1710 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1711 ("moea64_ts_referenced: page %p is not managed", m));
1712 return (moea64_clear_bit(mmu, m, LPTE_REF));
1716 * Modify the WIMG settings of all mappings for a page.
1719 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1721 struct pvo_entry *pvo;
1726 if ((m->oflags & VPO_UNMANAGED) != 0) {
1727 m->md.mdpg_cache_attrs = ma;
1731 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1734 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1735 pmap = pvo->pvo_pmap;
1737 if (!(pvo->pvo_vaddr & PVO_DEAD)) {
1738 pvo->pvo_pte.pa &= ~LPTE_WIMG;
1739 pvo->pvo_pte.pa |= lo;
1740 refchg = MOEA64_PTE_REPLACE(mmu, pvo,
1741 MOEA64_PTE_INVALIDATE);
1743 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
1745 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1746 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1748 atomic_readandclear_32(&m->md.mdpg_attrs);
1749 if (refchg & LPTE_CHG)
1751 if (refchg & LPTE_REF)
1752 vm_page_aflag_set(m, PGA_REFERENCED);
1754 if (pvo->pvo_pmap == kernel_pmap)
1759 m->md.mdpg_cache_attrs = ma;
1764 * Map a wired page into kernel virtual address space.
1767 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1770 struct pvo_entry *pvo, *oldpvo;
1772 pvo = alloc_pvo_entry(0);
1773 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
1774 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
1775 pvo->pvo_vaddr |= PVO_WIRED;
1777 PMAP_LOCK(kernel_pmap);
1778 oldpvo = moea64_pvo_find_va(kernel_pmap, va);
1780 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1781 init_pvo_entry(pvo, kernel_pmap, va);
1782 error = moea64_pvo_enter(mmu, pvo, NULL);
1783 PMAP_UNLOCK(kernel_pmap);
1785 /* Free any dead pages */
1786 if (oldpvo != NULL) {
1787 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1788 moea64_pvo_remove_from_page(mmu, oldpvo);
1789 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1790 free_pvo_entry(oldpvo);
1793 if (error != 0 && error != ENOENT)
1794 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1799 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1802 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1806 * Extract the physical page address associated with the given kernel virtual
1810 moea64_kextract(mmu_t mmu, vm_offset_t va)
1812 struct pvo_entry *pvo;
1816 * Shortcut the direct-mapped case when applicable. We never put
1817 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1819 if (va < VM_MIN_KERNEL_ADDRESS)
1822 PMAP_LOCK(kernel_pmap);
1823 pvo = moea64_pvo_find_va(kernel_pmap, va);
1824 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1826 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1827 PMAP_UNLOCK(kernel_pmap);
1832 * Remove a wired page from kernel virtual address space.
1835 moea64_kremove(mmu_t mmu, vm_offset_t va)
1837 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1841 * Provide a kernel pointer corresponding to a given userland pointer.
1842 * The returned pointer is valid until the next time this function is
1843 * called in this thread. This is used internally in copyin/copyout.
1846 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1847 void **kaddr, size_t ulen, size_t *klen)
1850 #ifdef __powerpc64__
1855 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1856 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1864 #ifdef __powerpc64__
1865 /* Try lockless look-up first */
1866 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
1869 /* If it isn't there, we need to pre-fault the VSID */
1871 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
1877 /* Mark segment no-execute */
1880 slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
1882 /* Mark segment no-execute */
1886 /* If we have already set this VSID, we can just return */
1887 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
1890 __asm __volatile("isync");
1891 curthread->td_pcb->pcb_cpu.aim.usr_segm =
1892 (uintptr_t)uaddr >> ADDR_SR_SHFT;
1893 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
1894 #ifdef __powerpc64__
1895 __asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
1896 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
1898 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
1905 * Map a range of physical addresses into kernel virtual address space.
1907 * The value passed in *virt is a suggested virtual address for the mapping.
1908 * Architectures which can support a direct-mapped physical to virtual region
1909 * can return the appropriate address within that region, leaving '*virt'
1910 * unchanged. Other architectures should map the pages starting at '*virt' and
1911 * update '*virt' with the first usable address after the mapped region.
1914 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1915 vm_paddr_t pa_end, int prot)
1917 vm_offset_t sva, va;
1919 if (hw_direct_map) {
1921 * Check if every page in the region is covered by the direct
1922 * map. The direct map covers all of physical memory. Use
1923 * moea64_calc_wimg() as a shortcut to see if the page is in
1924 * physical memory as a way to see if the direct map covers it.
1926 for (va = pa_start; va < pa_end; va += PAGE_SIZE)
1927 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
1930 return (PHYS_TO_DMAP(pa_start));
1934 /* XXX respect prot argument */
1935 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1936 moea64_kenter(mmu, va, pa_start);
1943 * Returns true if the pmap's pv is one of the first
1944 * 16 pvs linked to from this page. This count may
1945 * be changed upwards or downwards in the future; it
1946 * is only necessary that true be returned for a small
1947 * subset of pmaps for proper page aging.
1950 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1953 struct pvo_entry *pvo;
1956 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1957 ("moea64_page_exists_quick: page %p is not managed", m));
1961 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1962 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
1974 moea64_page_init(mmu_t mmu __unused, vm_page_t m)
1977 m->md.mdpg_attrs = 0;
1978 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
1979 LIST_INIT(&m->md.mdpg_pvoh);
1983 * Return the number of managed mappings to the given physical page
1987 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1989 struct pvo_entry *pvo;
1993 if ((m->oflags & VPO_UNMANAGED) != 0)
1996 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1997 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2003 static uintptr_t moea64_vsidcontext;
2006 moea64_get_unique_vsid(void) {
2013 __asm __volatile("mftb %0" : "=r"(entropy));
2015 mtx_lock(&moea64_slb_mutex);
2016 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2020 * Create a new value by mutiplying by a prime and adding in
2021 * entropy from the timebase register. This is to make the
2022 * VSID more random so that the PT hash function collides
2023 * less often. (Note that the prime casues gcc to do shifts
2024 * instead of a multiply.)
2026 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2027 hash = moea64_vsidcontext & (NVSIDS - 1);
2028 if (hash == 0) /* 0 is special, avoid it */
2031 mask = 1 << (hash & (VSID_NBPW - 1));
2032 hash = (moea64_vsidcontext & VSID_HASHMASK);
2033 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
2034 /* anything free in this bucket? */
2035 if (moea64_vsid_bitmap[n] == 0xffffffff) {
2036 entropy = (moea64_vsidcontext >> 20);
2039 i = ffs(~moea64_vsid_bitmap[n]) - 1;
2041 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2044 if (hash == VSID_VRMA) /* also special, avoid this too */
2046 KASSERT(!(moea64_vsid_bitmap[n] & mask),
2047 ("Allocating in-use VSID %#zx\n", hash));
2048 moea64_vsid_bitmap[n] |= mask;
2049 mtx_unlock(&moea64_slb_mutex);
2053 mtx_unlock(&moea64_slb_mutex);
2054 panic("%s: out of segments",__func__);
2057 #ifdef __powerpc64__
2059 moea64_pinit(mmu_t mmu, pmap_t pmap)
2062 RB_INIT(&pmap->pmap_pvo);
2064 pmap->pm_slb_tree_root = slb_alloc_tree();
2065 pmap->pm_slb = slb_alloc_user_cache();
2066 pmap->pm_slb_len = 0;
2070 moea64_pinit(mmu_t mmu, pmap_t pmap)
2075 RB_INIT(&pmap->pmap_pvo);
2077 if (pmap_bootstrapped)
2078 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
2081 pmap->pmap_phys = pmap;
2084 * Allocate some segment registers for this pmap.
2086 hash = moea64_get_unique_vsid();
2088 for (i = 0; i < 16; i++)
2089 pmap->pm_sr[i] = VSID_MAKE(i, hash);
2091 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2096 * Initialize the pmap associated with process 0.
2099 moea64_pinit0(mmu_t mmu, pmap_t pm)
2103 moea64_pinit(mmu, pm);
2104 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2108 * Set the physical protection on the specified range of this map as requested.
2111 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2117 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2120 * Change the protection of the page.
2122 oldprot = pvo->pvo_pte.prot;
2123 pvo->pvo_pte.prot = prot;
2124 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2127 * If the PVO is in the page table, update mapping
2129 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE);
2131 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2133 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2134 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2135 if ((pg->oflags & VPO_UNMANAGED) == 0)
2136 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2137 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2138 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE);
2142 * Update vm about the REF/CHG bits if the page is managed and we have
2143 * removed write access.
2145 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2146 (oldprot & VM_PROT_WRITE)) {
2147 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2148 if (refchg & LPTE_CHG)
2150 if (refchg & LPTE_REF)
2151 vm_page_aflag_set(pg, PGA_REFERENCED);
2156 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2159 struct pvo_entry *pvo, *tpvo, key;
2161 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2164 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2165 ("moea64_protect: non current pmap"));
2167 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2168 moea64_remove(mmu, pm, sva, eva);
2173 key.pvo_vaddr = sva;
2174 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2175 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2176 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2177 moea64_pvo_protect(mmu, pm, pvo, prot);
2183 * Map a list of wired pages into kernel virtual address space. This is
2184 * intended for temporary mappings which do not need page modification or
2185 * references recorded. Existing mappings in the region are overwritten.
2188 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2190 while (count-- > 0) {
2191 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2198 * Remove page mappings from kernel virtual address space. Intended for
2199 * temporary mappings entered by moea64_qenter.
2202 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2204 while (count-- > 0) {
2205 moea64_kremove(mmu, va);
2211 moea64_release_vsid(uint64_t vsid)
2215 mtx_lock(&moea64_slb_mutex);
2216 idx = vsid & (NVSIDS-1);
2217 mask = 1 << (idx % VSID_NBPW);
2219 KASSERT(moea64_vsid_bitmap[idx] & mask,
2220 ("Freeing unallocated VSID %#jx", vsid));
2221 moea64_vsid_bitmap[idx] &= ~mask;
2222 mtx_unlock(&moea64_slb_mutex);
2227 moea64_release(mmu_t mmu, pmap_t pmap)
2231 * Free segment registers' VSIDs
2233 #ifdef __powerpc64__
2234 slb_free_tree(pmap);
2235 slb_free_user_cache(pmap->pm_slb);
2237 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2239 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2244 * Remove all pages mapped by the specified pmap
2247 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2249 struct pvo_entry *pvo, *tpvo;
2250 struct pvo_tree tofree;
2255 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2256 if (pvo->pvo_vaddr & PVO_WIRED)
2260 * For locking reasons, remove this from the page table and
2261 * pmap, but save delinking from the vm_page for a second
2264 moea64_pvo_remove_from_pmap(mmu, pvo);
2265 RB_INSERT(pvo_tree, &tofree, pvo);
2269 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2270 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2271 moea64_pvo_remove_from_page(mmu, pvo);
2272 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2273 RB_REMOVE(pvo_tree, &tofree, pvo);
2274 free_pvo_entry(pvo);
2279 * Remove the given range of addresses from the specified map.
2282 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2284 struct pvo_entry *pvo, *tpvo, key;
2285 struct pvo_tree tofree;
2288 * Perform an unsynchronized read. This is, however, safe.
2290 if (pm->pm_stats.resident_count == 0)
2293 key.pvo_vaddr = sva;
2298 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2299 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2300 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2303 * For locking reasons, remove this from the page table and
2304 * pmap, but save delinking from the vm_page for a second
2307 moea64_pvo_remove_from_pmap(mmu, pvo);
2308 RB_INSERT(pvo_tree, &tofree, pvo);
2312 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2313 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2314 moea64_pvo_remove_from_page(mmu, pvo);
2315 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2316 RB_REMOVE(pvo_tree, &tofree, pvo);
2317 free_pvo_entry(pvo);
2322 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2323 * will reflect changes in pte's back to the vm_page.
2326 moea64_remove_all(mmu_t mmu, vm_page_t m)
2328 struct pvo_entry *pvo, *next_pvo;
2329 struct pvo_head freequeue;
2333 LIST_INIT(&freequeue);
2336 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2337 pmap = pvo->pvo_pmap;
2339 wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2341 moea64_pvo_remove_from_pmap(mmu, pvo);
2342 moea64_pvo_remove_from_page(mmu, pvo);
2344 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2348 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2349 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable"));
2352 /* Clean up UMA allocations */
2353 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2354 free_pvo_entry(pvo);
2358 * Allocate a physical page of memory directly from the phys_avail map.
2359 * Can only be called from moea64_bootstrap before avail start and end are
2363 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2368 size = round_page(size);
2369 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2371 s = roundup2(phys_avail[i], align);
2376 if (s < phys_avail[i] || e > phys_avail[i + 1])
2379 if (s + size > platform_real_maxaddr())
2382 if (s == phys_avail[i]) {
2383 phys_avail[i] += size;
2384 } else if (e == phys_avail[i + 1]) {
2385 phys_avail[i + 1] -= size;
2387 for (j = phys_avail_count * 2; j > i; j -= 2) {
2388 phys_avail[j] = phys_avail[j - 2];
2389 phys_avail[j + 1] = phys_avail[j - 1];
2392 phys_avail[i + 3] = phys_avail[i + 1];
2393 phys_avail[i + 1] = s;
2394 phys_avail[i + 2] = e;
2400 panic("moea64_bootstrap_alloc: could not allocate memory");
2404 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head)
2408 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2409 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL,
2410 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo)));
2412 moea64_pvo_enter_calls++;
2417 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2420 * Remember if the list was empty and therefore will be the first
2423 if (pvo_head != NULL) {
2424 if (LIST_FIRST(pvo_head) == NULL)
2426 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2429 if (pvo->pvo_vaddr & PVO_WIRED)
2430 pvo->pvo_pmap->pm_stats.wired_count++;
2431 pvo->pvo_pmap->pm_stats.resident_count++;
2434 * Insert it into the hardware page table
2436 err = MOEA64_PTE_INSERT(mmu, pvo);
2438 panic("moea64_pvo_enter: overflow");
2441 moea64_pvo_entries++;
2443 if (pvo->pvo_pmap == kernel_pmap)
2446 #ifdef __powerpc64__
2448 * Make sure all our bootstrap mappings are in the SLB as soon
2449 * as virtual memory is switched on.
2451 if (!pmap_bootstrapped)
2452 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2453 pvo->pvo_vaddr & PVO_LARGE);
2456 return (first ? ENOENT : 0);
2460 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo)
2465 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2466 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2467 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2470 * If there is an active pte entry, we need to deactivate it
2472 refchg = MOEA64_PTE_UNSET(mmu, pvo);
2475 * If it was evicted from the page table, be pessimistic and
2478 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2485 * Update our statistics.
2487 pvo->pvo_pmap->pm_stats.resident_count--;
2488 if (pvo->pvo_vaddr & PVO_WIRED)
2489 pvo->pvo_pmap->pm_stats.wired_count--;
2492 * Remove this PVO from the pmap list.
2494 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2497 * Mark this for the next sweep
2499 pvo->pvo_vaddr |= PVO_DEAD;
2501 /* Send RC bits to VM */
2502 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2503 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2504 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2506 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2507 if (refchg & LPTE_CHG)
2509 if (refchg & LPTE_REF)
2510 vm_page_aflag_set(pg, PGA_REFERENCED);
2516 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo)
2520 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
2522 /* Use NULL pmaps as a sentinel for races in page deletion */
2523 if (pvo->pvo_pmap == NULL)
2525 pvo->pvo_pmap = NULL;
2528 * Update vm about page writeability/executability if managed
2530 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN);
2531 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2533 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) {
2534 LIST_REMOVE(pvo, pvo_vlink);
2535 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2536 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE);
2539 moea64_pvo_entries--;
2540 moea64_pvo_remove_calls++;
2543 static struct pvo_entry *
2544 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2546 struct pvo_entry key;
2548 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2550 key.pvo_vaddr = va & ~ADDR_POFF;
2551 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2555 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit)
2557 struct pvo_entry *pvo;
2562 * See if this bit is stored in the page already.
2564 if (m->md.mdpg_attrs & ptebit)
2568 * Examine each PTE. Sync so that any pending REF/CHG bits are
2569 * flushed to the PTEs.
2574 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2578 * See if this pvo has a valid PTE. if so, fetch the
2579 * REF/CHG bits from the valid PTE. If the appropriate
2580 * ptebit is set, return success.
2582 PMAP_LOCK(pvo->pvo_pmap);
2583 if (!(pvo->pvo_vaddr & PVO_DEAD))
2584 ret = MOEA64_PTE_SYNCH(mmu, pvo);
2585 PMAP_UNLOCK(pvo->pvo_pmap);
2588 atomic_set_32(&m->md.mdpg_attrs,
2589 ret & (LPTE_CHG | LPTE_REF));
2602 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2605 struct pvo_entry *pvo;
2609 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2610 * we can reset the right ones).
2615 * For each pvo entry, clear the pte's ptebit.
2619 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2622 PMAP_LOCK(pvo->pvo_pmap);
2623 if (!(pvo->pvo_vaddr & PVO_DEAD))
2624 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit);
2625 PMAP_UNLOCK(pvo->pvo_pmap);
2627 if (ret > 0 && (ret & ptebit))
2630 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
2637 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2639 struct pvo_entry *pvo, key;
2643 PMAP_LOCK(kernel_pmap);
2644 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2645 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2646 ppa < pa + size; ppa += PAGE_SIZE,
2647 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2648 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) {
2653 PMAP_UNLOCK(kernel_pmap);
2659 * Map a set of physical memory pages into the kernel virtual
2660 * address space. Return a pointer to where it is mapped. This
2661 * routine is intended to be used for mapping device memory,
2665 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2667 vm_offset_t va, tmpva, ppa, offset;
2669 ppa = trunc_page(pa);
2670 offset = pa & PAGE_MASK;
2671 size = roundup2(offset + size, PAGE_SIZE);
2673 va = kva_alloc(size);
2676 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2678 for (tmpva = va; size > 0;) {
2679 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2685 return ((void *)(va + offset));
2689 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2692 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2696 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2698 vm_offset_t base, offset;
2700 base = trunc_page(va);
2701 offset = va & PAGE_MASK;
2702 size = roundup2(offset + size, PAGE_SIZE);
2704 kva_free(base, size);
2708 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2710 struct pvo_entry *pvo;
2717 lim = round_page(va);
2718 len = MIN(lim - va, sz);
2719 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2720 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
2721 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF);
2722 moea64_syncicache(mmu, pm, va, pa, len);
2731 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2737 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2740 moea64_scan_init(mmu_t mmu)
2742 struct pvo_entry *pvo;
2747 /* Initialize phys. segments for dumpsys(). */
2748 memset(&dump_map, 0, sizeof(dump_map));
2749 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2750 for (i = 0; i < pregions_sz; i++) {
2751 dump_map[i].pa_start = pregions[i].mr_start;
2752 dump_map[i].pa_size = pregions[i].mr_size;
2757 /* Virtual segments for minidumps: */
2758 memset(&dump_map, 0, sizeof(dump_map));
2760 /* 1st: kernel .data and .bss. */
2761 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2762 dump_map[0].pa_size = round_page((uintptr_t)_end) -
2763 dump_map[0].pa_start;
2765 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2766 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
2767 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2769 /* 3rd: kernel VM. */
2770 va = dump_map[1].pa_start + dump_map[1].pa_size;
2771 /* Find start of next chunk (from va). */
2772 while (va < virtual_end) {
2773 /* Don't dump the buffer cache. */
2774 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2775 va = kmi.buffer_eva;
2778 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2779 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2783 if (va < virtual_end) {
2784 dump_map[2].pa_start = va;
2786 /* Find last page in chunk. */
2787 while (va < virtual_end) {
2788 /* Don't run into the buffer cache. */
2789 if (va == kmi.buffer_sva)
2791 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2792 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2796 dump_map[2].pa_size = va - dump_map[2].pa_start;