2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
31 * Copyright (C) 1995, 1996 TooLs GmbH.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by TooLs GmbH.
45 * 4. The name of TooLs GmbH may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62 * Copyright (C) 2001 Benno Rice.
63 * All rights reserved.
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is also stored by the
93 * logical address mapping module, this module may throw away valid virtual
94 * to physical mappings at almost any time. However, invalidations of
95 * mappings must be done as requested.
97 * In order to cope with hardware architectures which make virtual to
98 * physical map invalidates expensive, this module may delay invalidate
99 * reduced protection operations until such time as they are actually
100 * necessary. This module is given full information as to which processors
101 * are currently using which maps, and to when physical maps must be made
105 #include "opt_compat.h"
106 #include "opt_kstack_pages.h"
108 #include <sys/param.h>
109 #include <sys/kernel.h>
110 #include <sys/queue.h>
111 #include <sys/cpuset.h>
113 #include <sys/lock.h>
114 #include <sys/msgbuf.h>
115 #include <sys/malloc.h>
116 #include <sys/mutex.h>
117 #include <sys/proc.h>
118 #include <sys/rwlock.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/systm.h>
122 #include <sys/vmmeter.h>
126 #include <dev/ofw/openfirm.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
138 #include <machine/_inttypes.h>
139 #include <machine/cpu.h>
140 #include <machine/platform.h>
141 #include <machine/frame.h>
142 #include <machine/md_var.h>
143 #include <machine/psl.h>
144 #include <machine/bat.h>
145 #include <machine/hid.h>
146 #include <machine/pte.h>
147 #include <machine/sr.h>
148 #include <machine/trap.h>
149 #include <machine/mmuvar.h>
151 #include "mmu_oea64.h"
153 #include "moea64_if.h"
155 void moea64_release_vsid(uint64_t vsid);
156 uintptr_t moea64_get_unique_vsid(void);
158 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
159 #define ENABLE_TRANS(msr) mtmsr(msr)
161 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
162 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
163 #define VSID_HASH_MASK 0x0000007fffffffffULL
167 * -- Read lock: if no modifications are being made to either the PVO lists
168 * or page table or if any modifications being made result in internal
169 * changes (e.g. wiring, protection) such that the existence of the PVOs
170 * is unchanged and they remain associated with the same pmap (in which
171 * case the changes should be protected by the pmap lock)
172 * -- Write lock: required if PTEs/PVOs are being inserted or removed.
175 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
176 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
177 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
178 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
187 extern unsigned char _etext[];
188 extern unsigned char _end[];
190 extern int dumpsys_minidump;
193 * Map of physical memory regions.
195 static struct mem_region *regions;
196 static struct mem_region *pregions;
197 static u_int phys_avail_count;
198 static int regions_sz, pregions_sz;
200 extern void bs_remap_earlyboot(void);
203 * Lock for the pteg and pvo tables.
205 struct rwlock moea64_table_lock;
206 struct mtx moea64_slb_mutex;
211 u_int moea64_pteg_count;
212 u_int moea64_pteg_mask;
217 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
219 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
220 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
222 #define BPVO_POOL_SIZE 327680
223 static struct pvo_entry *moea64_bpvo_pool;
224 static int moea64_bpvo_pool_index = 0;
226 #define VSID_NBPW (sizeof(u_int32_t) * 8)
228 #define NVSIDS (NPMAPS * 16)
229 #define VSID_HASHMASK 0xffffffffUL
231 #define NVSIDS NPMAPS
232 #define VSID_HASHMASK 0xfffffUL
234 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
236 static boolean_t moea64_initialized = FALSE;
241 u_int moea64_pte_valid = 0;
242 u_int moea64_pte_overflow = 0;
243 u_int moea64_pvo_entries = 0;
244 u_int moea64_pvo_enter_calls = 0;
245 u_int moea64_pvo_remove_calls = 0;
246 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
247 &moea64_pte_valid, 0, "");
248 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
249 &moea64_pte_overflow, 0, "");
250 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
251 &moea64_pvo_entries, 0, "");
252 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
253 &moea64_pvo_enter_calls, 0, "");
254 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
255 &moea64_pvo_remove_calls, 0, "");
257 vm_offset_t moea64_scratchpage_va[2];
258 struct pvo_entry *moea64_scratchpage_pvo[2];
259 uintptr_t moea64_scratchpage_pte[2];
260 struct mtx moea64_scratchpage_mtx;
262 uint64_t moea64_large_page_mask = 0;
263 uint64_t moea64_large_page_size = 0;
264 int moea64_large_page_shift = 0;
269 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
270 vm_offset_t, vm_offset_t, uint64_t, int);
271 static void moea64_pvo_remove(mmu_t, struct pvo_entry *);
272 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
277 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
278 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
279 static void moea64_kremove(mmu_t, vm_offset_t);
280 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
281 vm_offset_t pa, vm_size_t sz);
284 * Kernel MMU interface
286 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
287 void moea64_clear_modify(mmu_t, vm_page_t);
288 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
289 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
290 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
291 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
292 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
294 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
295 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
296 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
297 void moea64_init(mmu_t);
298 boolean_t moea64_is_modified(mmu_t, vm_page_t);
299 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
300 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
301 int moea64_ts_referenced(mmu_t, vm_page_t);
302 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
303 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
304 int moea64_page_wired_mappings(mmu_t, vm_page_t);
305 void moea64_pinit(mmu_t, pmap_t);
306 void moea64_pinit0(mmu_t, pmap_t);
307 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
308 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
309 void moea64_qremove(mmu_t, vm_offset_t, int);
310 void moea64_release(mmu_t, pmap_t);
311 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
312 void moea64_remove_pages(mmu_t, pmap_t);
313 void moea64_remove_all(mmu_t, vm_page_t);
314 void moea64_remove_write(mmu_t, vm_page_t);
315 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
316 void moea64_zero_page(mmu_t, vm_page_t);
317 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
318 void moea64_zero_page_idle(mmu_t, vm_page_t);
319 void moea64_activate(mmu_t, struct thread *);
320 void moea64_deactivate(mmu_t, struct thread *);
321 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
322 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
323 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
324 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
325 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
326 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
327 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
328 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
329 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
330 vm_offset_t moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
332 struct pmap_md * moea64_scan_md(mmu_t mmu, struct pmap_md *prev);
334 static mmu_method_t moea64_methods[] = {
335 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
336 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
337 MMUMETHOD(mmu_copy_page, moea64_copy_page),
338 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
339 MMUMETHOD(mmu_enter, moea64_enter),
340 MMUMETHOD(mmu_enter_object, moea64_enter_object),
341 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
342 MMUMETHOD(mmu_extract, moea64_extract),
343 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
344 MMUMETHOD(mmu_init, moea64_init),
345 MMUMETHOD(mmu_is_modified, moea64_is_modified),
346 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
347 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
348 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
349 MMUMETHOD(mmu_map, moea64_map),
350 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
351 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
352 MMUMETHOD(mmu_pinit, moea64_pinit),
353 MMUMETHOD(mmu_pinit0, moea64_pinit0),
354 MMUMETHOD(mmu_protect, moea64_protect),
355 MMUMETHOD(mmu_qenter, moea64_qenter),
356 MMUMETHOD(mmu_qremove, moea64_qremove),
357 MMUMETHOD(mmu_release, moea64_release),
358 MMUMETHOD(mmu_remove, moea64_remove),
359 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
360 MMUMETHOD(mmu_remove_all, moea64_remove_all),
361 MMUMETHOD(mmu_remove_write, moea64_remove_write),
362 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
363 MMUMETHOD(mmu_unwire, moea64_unwire),
364 MMUMETHOD(mmu_zero_page, moea64_zero_page),
365 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
366 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
367 MMUMETHOD(mmu_activate, moea64_activate),
368 MMUMETHOD(mmu_deactivate, moea64_deactivate),
369 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
371 /* Internal interfaces */
372 MMUMETHOD(mmu_mapdev, moea64_mapdev),
373 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
374 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
375 MMUMETHOD(mmu_kextract, moea64_kextract),
376 MMUMETHOD(mmu_kenter, moea64_kenter),
377 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
378 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
379 MMUMETHOD(mmu_scan_md, moea64_scan_md),
380 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
385 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
387 static __inline u_int
388 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
393 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
394 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
396 return (hash & moea64_pteg_mask);
399 static __inline struct pvo_head *
400 vm_page_to_pvoh(vm_page_t m)
403 return (&m->md.mdpg_pvoh);
407 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
408 uint64_t pte_lo, int flags)
412 * Construct a PTE. Default to IMB initially. Valid bit only gets
413 * set when the real pte is set in memory.
415 * Note: Don't set the valid bit for correct operation of tlb update.
417 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
418 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
420 if (flags & PVO_LARGE)
421 pt->pte_hi |= LPTE_BIG;
426 static __inline uint64_t
427 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
432 if (ma != VM_MEMATTR_DEFAULT) {
434 case VM_MEMATTR_UNCACHEABLE:
435 return (LPTE_I | LPTE_G);
436 case VM_MEMATTR_WRITE_COMBINING:
437 case VM_MEMATTR_WRITE_BACK:
438 case VM_MEMATTR_PREFETCHABLE:
440 case VM_MEMATTR_WRITE_THROUGH:
441 return (LPTE_W | LPTE_M);
446 * Assume the page is cache inhibited and access is guarded unless
447 * it's in our available memory array.
449 pte_lo = LPTE_I | LPTE_G;
450 for (i = 0; i < pregions_sz; i++) {
451 if ((pa >= pregions[i].mr_start) &&
452 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
453 pte_lo &= ~(LPTE_I | LPTE_G);
463 * Quick sort callout for comparing memory regions.
465 static int om_cmp(const void *a, const void *b);
468 om_cmp(const void *a, const void *b)
470 const struct ofw_map *mapa;
471 const struct ofw_map *mapb;
475 if (mapa->om_pa < mapb->om_pa)
477 else if (mapa->om_pa > mapb->om_pa)
484 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
486 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
487 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
493 bzero(translations, sz);
494 OF_getprop(OF_finddevice("/"), "#address-cells", &acells,
496 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1)
497 panic("moea64_bootstrap: can't get ofw translations");
499 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
500 sz /= sizeof(cell_t);
501 for (i = 0, j = 0; i < sz; j++) {
502 translations[j].om_va = trans_cells[i++];
503 translations[j].om_len = trans_cells[i++];
504 translations[j].om_pa = trans_cells[i++];
506 translations[j].om_pa <<= 32;
507 translations[j].om_pa |= trans_cells[i++];
509 translations[j].om_mode = trans_cells[i++];
511 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
515 qsort(translations, sz, sizeof (*translations), om_cmp);
517 for (i = 0; i < sz; i++) {
518 pa_base = translations[i].om_pa;
519 #ifndef __powerpc64__
520 if ((translations[i].om_pa >> 32) != 0)
521 panic("OFW translations above 32-bit boundary!");
524 if (pa_base % PAGE_SIZE)
525 panic("OFW translation not page-aligned (phys)!");
526 if (translations[i].om_va % PAGE_SIZE)
527 panic("OFW translation not page-aligned (virt)!");
529 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
530 pa_base, translations[i].om_va, translations[i].om_len);
532 /* Now enter the pages for this mapping */
535 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
536 if (moea64_pvo_find_va(kernel_pmap,
537 translations[i].om_va + off) != NULL)
540 moea64_kenter(mmup, translations[i].om_va + off,
549 moea64_probe_large_page(void)
551 uint16_t pvr = mfpvr() >> 16;
557 powerpc_sync(); isync();
558 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
559 powerpc_sync(); isync();
563 moea64_large_page_size = 0x1000000; /* 16 MB */
564 moea64_large_page_shift = 24;
567 moea64_large_page_mask = moea64_large_page_size - 1;
571 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
578 cache = PCPU_GET(slb);
579 esid = va >> ADDR_SR_SHFT;
580 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
582 for (i = 0; i < 64; i++) {
583 if (cache[i].slbe == (slbe | i))
588 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
590 entry.slbv |= SLBV_L;
592 slb_insert_kernel(entry.slbe, entry.slbv);
597 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
598 vm_offset_t kernelend)
602 vm_offset_t size, off;
606 if (moea64_large_page_size == 0)
612 PMAP_LOCK(kernel_pmap);
613 for (i = 0; i < pregions_sz; i++) {
614 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
615 pregions[i].mr_size; pa += moea64_large_page_size) {
619 * Set memory access as guarded if prefetch within
620 * the page could exit the available physmem area.
622 if (pa & moea64_large_page_mask) {
623 pa &= moea64_large_page_mask;
626 if (pa + moea64_large_page_size >
627 pregions[i].mr_start + pregions[i].mr_size)
630 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
631 NULL, pa, pa, pte_lo,
632 PVO_WIRED | PVO_LARGE);
635 PMAP_UNLOCK(kernel_pmap);
638 size = sizeof(struct pvo_head) * moea64_pteg_count;
639 off = (vm_offset_t)(moea64_pvo_table);
640 for (pa = off; pa < off + size; pa += PAGE_SIZE)
641 moea64_kenter(mmup, pa, pa);
642 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
643 off = (vm_offset_t)(moea64_bpvo_pool);
644 for (pa = off; pa < off + size; pa += PAGE_SIZE)
645 moea64_kenter(mmup, pa, pa);
648 * Map certain important things, like ourselves.
650 * NOTE: We do not map the exception vector space. That code is
651 * used only in real mode, and leaving it unmapped allows us to
652 * catch NULL pointer deferences, instead of making NULL a valid
656 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
658 moea64_kenter(mmup, pa, pa);
663 * Allow user to override unmapped_buf_allowed for testing.
664 * XXXKIB Only direct map implementation was tested.
666 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
667 &unmapped_buf_allowed))
668 unmapped_buf_allowed = hw_direct_map;
672 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
675 vm_size_t physsz, hwphyssz;
677 #ifndef __powerpc64__
678 /* We don't have a direct map since there is no BAT */
681 /* Make sure battable is zero, since we have no BAT */
682 for (i = 0; i < 16; i++) {
683 battable[i].batu = 0;
684 battable[i].batl = 0;
687 moea64_probe_large_page();
689 /* Use a direct map if we have large page support */
690 if (moea64_large_page_size > 0)
696 /* Get physical memory regions from firmware */
697 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
698 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
700 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
701 panic("moea64_bootstrap: phys_avail too small");
703 phys_avail_count = 0;
706 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
707 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
708 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
709 regions[i].mr_start, regions[i].mr_start +
710 regions[i].mr_size, regions[i].mr_size);
712 (physsz + regions[i].mr_size) >= hwphyssz) {
713 if (physsz < hwphyssz) {
714 phys_avail[j] = regions[i].mr_start;
715 phys_avail[j + 1] = regions[i].mr_start +
722 phys_avail[j] = regions[i].mr_start;
723 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
725 physsz += regions[i].mr_size;
728 /* Check for overlap with the kernel and exception vectors */
729 for (j = 0; j < 2*phys_avail_count; j+=2) {
730 if (phys_avail[j] < EXC_LAST)
731 phys_avail[j] += EXC_LAST;
733 if (kernelstart >= phys_avail[j] &&
734 kernelstart < phys_avail[j+1]) {
735 if (kernelend < phys_avail[j+1]) {
736 phys_avail[2*phys_avail_count] =
737 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
738 phys_avail[2*phys_avail_count + 1] =
743 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
746 if (kernelend >= phys_avail[j] &&
747 kernelend < phys_avail[j+1]) {
748 if (kernelstart > phys_avail[j]) {
749 phys_avail[2*phys_avail_count] = phys_avail[j];
750 phys_avail[2*phys_avail_count + 1] =
751 kernelstart & ~PAGE_MASK;
755 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
759 physmem = btoc(physsz);
762 moea64_pteg_count = PTEGCOUNT;
764 moea64_pteg_count = 0x1000;
766 while (moea64_pteg_count < physmem)
767 moea64_pteg_count <<= 1;
769 moea64_pteg_count >>= 1;
770 #endif /* PTEGCOUNT */
774 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
783 moea64_pteg_mask = moea64_pteg_count - 1;
786 * Allocate pv/overflow lists.
788 size = sizeof(struct pvo_head) * moea64_pteg_count;
790 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
792 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
795 for (i = 0; i < moea64_pteg_count; i++)
796 LIST_INIT(&moea64_pvo_table[i]);
800 * Initialize the lock that synchronizes access to the pteg and pvo
803 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
804 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
807 * Initialise the unmanaged pvo pool.
809 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
810 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
811 moea64_bpvo_pool_index = 0;
814 * Make sure kernel vsid is allocated as well as VSID 0.
816 #ifndef __powerpc64__
817 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
818 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
819 moea64_vsid_bitmap[0] |= 1;
823 * Initialize the kernel pmap (which is statically allocated).
826 for (i = 0; i < 64; i++) {
827 pcpup->pc_slb[i].slbv = 0;
828 pcpup->pc_slb[i].slbe = 0;
831 for (i = 0; i < 16; i++)
832 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
835 kernel_pmap->pmap_phys = kernel_pmap;
836 CPU_FILL(&kernel_pmap->pm_active);
837 RB_INIT(&kernel_pmap->pmap_pvo);
839 PMAP_LOCK_INIT(kernel_pmap);
842 * Now map in all the other buffers we allocated earlier
845 moea64_setup_direct_map(mmup, kernelstart, kernelend);
849 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
860 * Set up the Open Firmware pmap and add its mappings if not in real
864 chosen = OF_finddevice("/chosen");
865 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
866 mmu = OF_instance_to_package(mmui);
867 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
869 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
870 panic("moea64_bootstrap: too many ofw translations");
873 moea64_add_ofw_mappings(mmup, mmu, sz);
877 * Calculate the last available physical address.
879 for (i = 0; phys_avail[i + 2] != 0; i += 2)
881 Maxmem = powerpc_btop(phys_avail[i + 1]);
884 * Initialize MMU and remap early physical mappings
886 MMU_CPU_BOOTSTRAP(mmup,0);
887 mtmsr(mfmsr() | PSL_DR | PSL_IR);
889 bs_remap_earlyboot();
892 * Set the start and end of kva.
894 virtual_avail = VM_MIN_KERNEL_ADDRESS;
895 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
898 * Map the entire KVA range into the SLB. We must not fault there.
901 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
902 moea64_bootstrap_slb_prefault(va, 0);
906 * Figure out how far we can extend virtual_end into segment 16
907 * without running into existing mappings. Segment 16 is guaranteed
908 * to contain neither RAM nor devices (at least on Apple hardware),
909 * but will generally contain some OFW mappings we should not
913 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
914 PMAP_LOCK(kernel_pmap);
915 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
916 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
917 virtual_end += PAGE_SIZE;
918 PMAP_UNLOCK(kernel_pmap);
922 * Allocate a kernel stack with a guard page for thread0 and map it
923 * into the kernel page map.
925 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
926 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
927 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
928 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
929 thread0.td_kstack = va;
930 thread0.td_kstack_pages = KSTACK_PAGES;
931 for (i = 0; i < KSTACK_PAGES; i++) {
932 moea64_kenter(mmup, va, pa);
938 * Allocate virtual address space for the message buffer.
940 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
941 msgbufp = (struct msgbuf *)virtual_avail;
943 virtual_avail += round_page(msgbufsize);
944 while (va < virtual_avail) {
945 moea64_kenter(mmup, va, pa);
951 * Allocate virtual address space for the dynamic percpu area.
953 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
954 dpcpu = (void *)virtual_avail;
956 virtual_avail += DPCPU_SIZE;
957 while (va < virtual_avail) {
958 moea64_kenter(mmup, va, pa);
962 dpcpu_init(dpcpu, 0);
965 * Allocate some things for page zeroing. We put this directly
966 * in the page table, marked with LPTE_LOCKED, to avoid any
967 * of the PVO book-keeping or other parts of the VM system
968 * from even knowing that this hack exists.
971 if (!hw_direct_map) {
972 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
974 for (i = 0; i < 2; i++) {
975 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
976 virtual_end -= PAGE_SIZE;
978 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
980 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
981 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
983 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
984 mmup, moea64_scratchpage_pvo[i]);
985 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
987 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
988 &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
989 moea64_scratchpage_pvo[i]->pvo_vpn);
996 * Activate a user pmap. The pmap must be activated before its address
997 * space can be accessed in any way.
1000 moea64_activate(mmu_t mmu, struct thread *td)
1004 pm = &td->td_proc->p_vmspace->vm_pmap;
1005 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1007 #ifdef __powerpc64__
1008 PCPU_SET(userslb, pm->pm_slb);
1010 PCPU_SET(curpmap, pm->pmap_phys);
1015 moea64_deactivate(mmu_t mmu, struct thread *td)
1019 pm = &td->td_proc->p_vmspace->vm_pmap;
1020 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1021 #ifdef __powerpc64__
1022 PCPU_SET(userslb, NULL);
1024 PCPU_SET(curpmap, NULL);
1029 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1031 struct pvo_entry *pvo;
1038 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1041 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1044 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1045 pm->pm_stats.wired_count++;
1046 pvo->pvo_vaddr |= PVO_WIRED;
1047 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1049 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1050 pm->pm_stats.wired_count--;
1051 pvo->pvo_vaddr &= ~PVO_WIRED;
1052 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1056 /* Update wiring flag in page table. */
1057 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1061 * If we are wiring the page, and it wasn't in the
1062 * page table before, add it.
1064 vsid = PVO_VSID(pvo);
1065 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1066 pvo->pvo_vaddr & PVO_LARGE);
1068 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1071 PVO_PTEGIDX_CLR(pvo);
1072 PVO_PTEGIDX_SET(pvo, i);
1082 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1084 struct pvo_entry key, *pvo;
1089 key.pvo_vaddr = sva;
1090 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1091 pvo != NULL && PVO_VADDR(pvo) < eva;
1092 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1093 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1094 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1095 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1097 pvo->pvo_vaddr &= ~PVO_WIRED;
1098 if ((pvo->pvo_pte.lpte.pte_hi & LPTE_WIRED) == 0)
1099 panic("moea64_unwire: pte %p is missing LPTE_WIRED",
1100 &pvo->pvo_pte.lpte);
1101 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1104 * The PTE's wired attribute is not a hardware
1105 * feature, so there is no need to invalidate any TLB
1108 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1111 pm->pm_stats.wired_count--;
1118 * This goes through and sets the physical address of our
1119 * special scratch PTE to the PA we want to zero or copy. Because
1120 * of locking issues (this can get called in pvo_enter() by
1121 * the UMA allocator), we can't use most other utility functions here
1125 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1127 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1128 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1130 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1131 ~(LPTE_WIMG | LPTE_RPGN);
1132 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1133 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1134 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1135 &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1136 moea64_scratchpage_pvo[which]->pvo_vpn);
1141 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1146 dst = VM_PAGE_TO_PHYS(mdst);
1147 src = VM_PAGE_TO_PHYS(msrc);
1149 if (hw_direct_map) {
1150 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1152 mtx_lock(&moea64_scratchpage_mtx);
1154 moea64_set_scratchpage_pa(mmu, 0, src);
1155 moea64_set_scratchpage_pa(mmu, 1, dst);
1157 bcopy((void *)moea64_scratchpage_va[0],
1158 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1160 mtx_unlock(&moea64_scratchpage_mtx);
1165 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1166 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1169 vm_offset_t a_pg_offset, b_pg_offset;
1172 while (xfersize > 0) {
1173 a_pg_offset = a_offset & PAGE_MASK;
1174 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1175 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1177 b_pg_offset = b_offset & PAGE_MASK;
1178 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1179 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1181 bcopy(a_cp, b_cp, cnt);
1189 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1190 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1193 vm_offset_t a_pg_offset, b_pg_offset;
1196 mtx_lock(&moea64_scratchpage_mtx);
1197 while (xfersize > 0) {
1198 a_pg_offset = a_offset & PAGE_MASK;
1199 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1200 moea64_set_scratchpage_pa(mmu, 0,
1201 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1202 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1203 b_pg_offset = b_offset & PAGE_MASK;
1204 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1205 moea64_set_scratchpage_pa(mmu, 1,
1206 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1207 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1208 bcopy(a_cp, b_cp, cnt);
1213 mtx_unlock(&moea64_scratchpage_mtx);
1217 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1218 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1221 if (hw_direct_map) {
1222 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1225 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1231 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1233 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1235 if (size + off > PAGE_SIZE)
1236 panic("moea64_zero_page: size + off > PAGE_SIZE");
1238 if (hw_direct_map) {
1239 bzero((caddr_t)pa + off, size);
1241 mtx_lock(&moea64_scratchpage_mtx);
1242 moea64_set_scratchpage_pa(mmu, 0, pa);
1243 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1244 mtx_unlock(&moea64_scratchpage_mtx);
1249 * Zero a page of physical memory by temporarily mapping it
1252 moea64_zero_page(mmu_t mmu, vm_page_t m)
1254 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1255 vm_offset_t va, off;
1257 if (!hw_direct_map) {
1258 mtx_lock(&moea64_scratchpage_mtx);
1260 moea64_set_scratchpage_pa(mmu, 0, pa);
1261 va = moea64_scratchpage_va[0];
1266 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1267 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1270 mtx_unlock(&moea64_scratchpage_mtx);
1274 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1277 moea64_zero_page(mmu, m);
1281 * Map the given physical page at the specified virtual address in the
1282 * target pmap with the protection requested. If specified the page
1283 * will be wired down.
1287 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1288 vm_prot_t prot, boolean_t wired)
1290 struct pvo_head *pvo_head;
1297 if (!moea64_initialized) {
1300 zone = moea64_upvo_zone;
1303 pvo_head = vm_page_to_pvoh(m);
1305 zone = moea64_mpvo_zone;
1306 pvo_flags = PVO_MANAGED;
1309 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1310 VM_OBJECT_ASSERT_LOCKED(m->object);
1312 /* XXX change the pvo head for fake pages */
1313 if ((m->oflags & VPO_UNMANAGED) != 0) {
1314 pvo_flags &= ~PVO_MANAGED;
1316 zone = moea64_upvo_zone;
1319 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1321 if (prot & VM_PROT_WRITE) {
1323 if (pmap_bootstrapped &&
1324 (m->oflags & VPO_UNMANAGED) == 0)
1325 vm_page_aflag_set(m, PGA_WRITEABLE);
1329 if ((prot & VM_PROT_EXECUTE) == 0)
1330 pte_lo |= LPTE_NOEXEC;
1333 pvo_flags |= PVO_WIRED;
1337 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1338 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1343 * Flush the page from the instruction cache if this page is
1344 * mapped executable and cacheable.
1346 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1347 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1348 vm_page_aflag_set(m, PGA_EXECUTABLE);
1349 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1354 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1359 * This is much trickier than on older systems because
1360 * we can't sync the icache on physical addresses directly
1361 * without a direct map. Instead we check a couple of cases
1362 * where the memory is already mapped in and, failing that,
1363 * use the same trick we use for page zeroing to create
1364 * a temporary mapping for this physical address.
1367 if (!pmap_bootstrapped) {
1369 * If PMAP is not bootstrapped, we are likely to be
1372 __syncicache((void *)pa, sz);
1373 } else if (pmap == kernel_pmap) {
1374 __syncicache((void *)va, sz);
1375 } else if (hw_direct_map) {
1376 __syncicache((void *)pa, sz);
1378 /* Use the scratch page to set up a temp mapping */
1380 mtx_lock(&moea64_scratchpage_mtx);
1382 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1383 __syncicache((void *)(moea64_scratchpage_va[1] +
1384 (va & ADDR_POFF)), sz);
1386 mtx_unlock(&moea64_scratchpage_mtx);
1391 * Maps a sequence of resident pages belonging to the same object.
1392 * The sequence begins with the given page m_start. This page is
1393 * mapped at the given virtual address start. Each subsequent page is
1394 * mapped at a virtual address that is offset from start by the same
1395 * amount as the page is offset from m_start within the object. The
1396 * last page in the sequence is the page with the largest offset from
1397 * m_start that can be mapped at a virtual address less than the given
1398 * virtual address end. Not every virtual page between start and end
1399 * is mapped; only those for which a resident page exists with the
1400 * corresponding offset from m_start are mapped.
1403 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1404 vm_page_t m_start, vm_prot_t prot)
1407 vm_pindex_t diff, psize;
1409 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1411 psize = atop(end - start);
1413 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1414 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1415 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1416 m = TAILQ_NEXT(m, listq);
1421 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1425 moea64_enter(mmu, pm, va, m,
1426 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1430 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1432 struct pvo_entry *pvo;
1436 pvo = moea64_pvo_find_va(pm, va);
1440 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1441 (va - PVO_VADDR(pvo));
1447 * Atomically extract and hold the physical page with the given
1448 * pmap and virtual address pair if that mapping permits the given
1452 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1454 struct pvo_entry *pvo;
1462 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1463 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1464 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1465 (prot & VM_PROT_WRITE) == 0)) {
1466 if (vm_page_pa_tryrelock(pmap,
1467 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1469 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1477 static mmu_t installed_mmu;
1480 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1483 * This entire routine is a horrible hack to avoid bothering kmem
1484 * for new KVA addresses. Because this can get called from inside
1485 * kmem allocation routines, calling kmem for a new address here
1486 * can lead to multiply locking non-recursive mutexes.
1491 int pflags, needed_lock;
1493 *flags = UMA_SLAB_PRIV;
1494 needed_lock = !PMAP_LOCKED(kernel_pmap);
1495 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
1498 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
1500 if (wait & M_NOWAIT)
1507 va = VM_PAGE_TO_PHYS(m);
1511 PMAP_LOCK(kernel_pmap);
1513 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1514 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP);
1517 PMAP_UNLOCK(kernel_pmap);
1520 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1521 bzero((void *)va, PAGE_SIZE);
1526 extern int elf32_nxstack;
1529 moea64_init(mmu_t mmu)
1532 CTR0(KTR_PMAP, "moea64_init");
1534 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1535 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1536 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1537 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1538 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1539 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1541 if (!hw_direct_map) {
1542 installed_mmu = mmu;
1543 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1544 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1547 #ifdef COMPAT_FREEBSD32
1551 moea64_initialized = TRUE;
1555 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1558 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1559 ("moea64_is_referenced: page %p is not managed", m));
1560 return (moea64_query_bit(mmu, m, PTE_REF));
1564 moea64_is_modified(mmu_t mmu, vm_page_t m)
1567 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1568 ("moea64_is_modified: page %p is not managed", m));
1571 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1572 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1573 * is clear, no PTEs can have LPTE_CHG set.
1575 VM_OBJECT_ASSERT_LOCKED(m->object);
1576 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1578 return (moea64_query_bit(mmu, m, LPTE_CHG));
1582 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1584 struct pvo_entry *pvo;
1588 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1589 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1595 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1598 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1599 ("moea64_clear_modify: page %p is not managed", m));
1600 VM_OBJECT_ASSERT_WLOCKED(m->object);
1601 KASSERT(!vm_page_xbusied(m),
1602 ("moea64_clear_modify: page %p is exclusive busied", m));
1605 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1606 * set. If the object containing the page is locked and the page is
1607 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1609 if ((m->aflags & PGA_WRITEABLE) == 0)
1611 moea64_clear_bit(mmu, m, LPTE_CHG);
1615 * Clear the write and modified bits in each of the given page's mappings.
1618 moea64_remove_write(mmu_t mmu, vm_page_t m)
1620 struct pvo_entry *pvo;
1625 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1626 ("moea64_remove_write: page %p is not managed", m));
1629 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1630 * set by another thread while the object is locked. Thus,
1631 * if PGA_WRITEABLE is clear, no page table entries need updating.
1633 VM_OBJECT_ASSERT_WLOCKED(m->object);
1634 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1638 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1639 pmap = pvo->pvo_pmap;
1641 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1642 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1643 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1644 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1646 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1647 lo |= pvo->pvo_pte.lpte.pte_lo;
1648 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1649 MOEA64_PTE_CHANGE(mmu, pt,
1650 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1651 if (pvo->pvo_pmap == kernel_pmap)
1655 if ((lo & LPTE_CHG) != 0)
1660 vm_page_aflag_clear(m, PGA_WRITEABLE);
1664 * moea64_ts_referenced:
1666 * Return a count of reference bits for a page, clearing those bits.
1667 * It is not necessary for every reference bit to be cleared, but it
1668 * is necessary that 0 only be returned when there are truly no
1669 * reference bits set.
1671 * XXX: The exact number of bits to check and clear is a matter that
1672 * should be tested and standardized at some point in the future for
1673 * optimal aging of shared pages.
1676 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1679 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1680 ("moea64_ts_referenced: page %p is not managed", m));
1681 return (moea64_clear_bit(mmu, m, LPTE_REF));
1685 * Modify the WIMG settings of all mappings for a page.
1688 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1690 struct pvo_entry *pvo;
1691 struct pvo_head *pvo_head;
1696 if ((m->oflags & VPO_UNMANAGED) != 0) {
1697 m->md.mdpg_cache_attrs = ma;
1701 pvo_head = vm_page_to_pvoh(m);
1702 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1704 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1705 pmap = pvo->pvo_pmap;
1707 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1708 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1709 pvo->pvo_pte.lpte.pte_lo |= lo;
1711 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1713 if (pvo->pvo_pmap == kernel_pmap)
1719 m->md.mdpg_cache_attrs = ma;
1723 * Map a wired page into kernel virtual address space.
1726 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1731 pte_lo = moea64_calc_wimg(pa, ma);
1734 PMAP_LOCK(kernel_pmap);
1735 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1736 NULL, va, pa, pte_lo, PVO_WIRED);
1737 PMAP_UNLOCK(kernel_pmap);
1740 if (error != 0 && error != ENOENT)
1741 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1746 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1749 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1753 * Extract the physical page address associated with the given kernel virtual
1757 moea64_kextract(mmu_t mmu, vm_offset_t va)
1759 struct pvo_entry *pvo;
1763 * Shortcut the direct-mapped case when applicable. We never put
1764 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1766 if (va < VM_MIN_KERNEL_ADDRESS)
1769 PMAP_LOCK(kernel_pmap);
1770 pvo = moea64_pvo_find_va(kernel_pmap, va);
1771 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1773 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1774 PMAP_UNLOCK(kernel_pmap);
1779 * Remove a wired page from kernel virtual address space.
1782 moea64_kremove(mmu_t mmu, vm_offset_t va)
1784 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1788 * Map a range of physical addresses into kernel virtual address space.
1790 * The value passed in *virt is a suggested virtual address for the mapping.
1791 * Architectures which can support a direct-mapped physical to virtual region
1792 * can return the appropriate address within that region, leaving '*virt'
1793 * unchanged. We cannot and therefore do not; *virt is updated with the
1794 * first usable address after the mapped region.
1797 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1798 vm_paddr_t pa_end, int prot)
1800 vm_offset_t sva, va;
1804 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1805 moea64_kenter(mmu, va, pa_start);
1812 * Returns true if the pmap's pv is one of the first
1813 * 16 pvs linked to from this page. This count may
1814 * be changed upwards or downwards in the future; it
1815 * is only necessary that true be returned for a small
1816 * subset of pmaps for proper page aging.
1819 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1822 struct pvo_entry *pvo;
1825 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1826 ("moea64_page_exists_quick: page %p is not managed", m));
1830 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1831 if (pvo->pvo_pmap == pmap) {
1843 * Return the number of managed mappings to the given physical page
1847 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1849 struct pvo_entry *pvo;
1853 if ((m->oflags & VPO_UNMANAGED) != 0)
1856 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1857 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1863 static uintptr_t moea64_vsidcontext;
1866 moea64_get_unique_vsid(void) {
1873 __asm __volatile("mftb %0" : "=r"(entropy));
1875 mtx_lock(&moea64_slb_mutex);
1876 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1880 * Create a new value by mutiplying by a prime and adding in
1881 * entropy from the timebase register. This is to make the
1882 * VSID more random so that the PT hash function collides
1883 * less often. (Note that the prime casues gcc to do shifts
1884 * instead of a multiply.)
1886 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1887 hash = moea64_vsidcontext & (NVSIDS - 1);
1888 if (hash == 0) /* 0 is special, avoid it */
1891 mask = 1 << (hash & (VSID_NBPW - 1));
1892 hash = (moea64_vsidcontext & VSID_HASHMASK);
1893 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1894 /* anything free in this bucket? */
1895 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1896 entropy = (moea64_vsidcontext >> 20);
1899 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1901 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1904 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1905 ("Allocating in-use VSID %#zx\n", hash));
1906 moea64_vsid_bitmap[n] |= mask;
1907 mtx_unlock(&moea64_slb_mutex);
1911 mtx_unlock(&moea64_slb_mutex);
1912 panic("%s: out of segments",__func__);
1915 #ifdef __powerpc64__
1917 moea64_pinit(mmu_t mmu, pmap_t pmap)
1920 RB_INIT(&pmap->pmap_pvo);
1922 pmap->pm_slb_tree_root = slb_alloc_tree();
1923 pmap->pm_slb = slb_alloc_user_cache();
1924 pmap->pm_slb_len = 0;
1928 moea64_pinit(mmu_t mmu, pmap_t pmap)
1933 RB_INIT(&pmap->pmap_pvo);
1935 if (pmap_bootstrapped)
1936 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1939 pmap->pmap_phys = pmap;
1942 * Allocate some segment registers for this pmap.
1944 hash = moea64_get_unique_vsid();
1946 for (i = 0; i < 16; i++)
1947 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1949 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1954 * Initialize the pmap associated with process 0.
1957 moea64_pinit0(mmu_t mmu, pmap_t pm)
1961 moea64_pinit(mmu, pm);
1962 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1966 * Set the physical protection on the specified range of this map as requested.
1969 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1975 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1978 * Grab the PTE pointer before we diddle with the cached PTE
1981 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1984 * Change the protection of the page.
1986 oldlo = pvo->pvo_pte.lpte.pte_lo;
1987 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1988 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1989 if ((prot & VM_PROT_EXECUTE) == 0)
1990 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1991 if (prot & VM_PROT_WRITE)
1992 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
1994 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1996 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1999 * If the PVO is in the page table, update that pte as well.
2002 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
2004 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2005 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2006 if ((pg->oflags & VPO_UNMANAGED) == 0)
2007 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2008 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2009 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
2013 * Update vm about the REF/CHG bits if the page is managed and we have
2014 * removed write access.
2016 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
2017 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) {
2019 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2021 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2022 vm_page_aflag_set(pg, PGA_REFERENCED);
2028 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2031 struct pvo_entry *pvo, *tpvo, key;
2033 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2036 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2037 ("moea64_protect: non current pmap"));
2039 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2040 moea64_remove(mmu, pm, sva, eva);
2046 key.pvo_vaddr = sva;
2047 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2048 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2049 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2050 moea64_pvo_protect(mmu, pm, pvo, prot);
2057 * Map a list of wired pages into kernel virtual address space. This is
2058 * intended for temporary mappings which do not need page modification or
2059 * references recorded. Existing mappings in the region are overwritten.
2062 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2064 while (count-- > 0) {
2065 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2072 * Remove page mappings from kernel virtual address space. Intended for
2073 * temporary mappings entered by moea64_qenter.
2076 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2078 while (count-- > 0) {
2079 moea64_kremove(mmu, va);
2085 moea64_release_vsid(uint64_t vsid)
2089 mtx_lock(&moea64_slb_mutex);
2090 idx = vsid & (NVSIDS-1);
2091 mask = 1 << (idx % VSID_NBPW);
2093 KASSERT(moea64_vsid_bitmap[idx] & mask,
2094 ("Freeing unallocated VSID %#jx", vsid));
2095 moea64_vsid_bitmap[idx] &= ~mask;
2096 mtx_unlock(&moea64_slb_mutex);
2101 moea64_release(mmu_t mmu, pmap_t pmap)
2105 * Free segment registers' VSIDs
2107 #ifdef __powerpc64__
2108 slb_free_tree(pmap);
2109 slb_free_user_cache(pmap->pm_slb);
2111 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2113 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2118 * Remove all pages mapped by the specified pmap
2121 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2123 struct pvo_entry *pvo, *tpvo;
2127 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2128 if (!(pvo->pvo_vaddr & PVO_WIRED))
2129 moea64_pvo_remove(mmu, pvo);
2136 * Remove the given range of addresses from the specified map.
2139 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2141 struct pvo_entry *pvo, *tpvo, key;
2144 * Perform an unsynchronized read. This is, however, safe.
2146 if (pm->pm_stats.resident_count == 0)
2151 key.pvo_vaddr = sva;
2152 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2153 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2154 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2155 moea64_pvo_remove(mmu, pvo);
2162 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2163 * will reflect changes in pte's back to the vm_page.
2166 moea64_remove_all(mmu_t mmu, vm_page_t m)
2168 struct pvo_entry *pvo, *next_pvo;
2172 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2173 pmap = pvo->pvo_pmap;
2175 moea64_pvo_remove(mmu, pvo);
2179 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2181 vm_page_aflag_clear(m, PGA_WRITEABLE);
2182 vm_page_aflag_clear(m, PGA_EXECUTABLE);
2186 * Allocate a physical page of memory directly from the phys_avail map.
2187 * Can only be called from moea64_bootstrap before avail start and end are
2191 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2196 size = round_page(size);
2197 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2199 s = (phys_avail[i] + align - 1) & ~(align - 1);
2204 if (s < phys_avail[i] || e > phys_avail[i + 1])
2207 if (s + size > platform_real_maxaddr())
2210 if (s == phys_avail[i]) {
2211 phys_avail[i] += size;
2212 } else if (e == phys_avail[i + 1]) {
2213 phys_avail[i + 1] -= size;
2215 for (j = phys_avail_count * 2; j > i; j -= 2) {
2216 phys_avail[j] = phys_avail[j - 2];
2217 phys_avail[j + 1] = phys_avail[j - 1];
2220 phys_avail[i + 3] = phys_avail[i + 1];
2221 phys_avail[i + 1] = s;
2222 phys_avail[i + 2] = e;
2228 panic("moea64_bootstrap_alloc: could not allocate memory");
2232 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2233 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2234 uint64_t pte_lo, int flags)
2236 struct pvo_entry *pvo;
2245 * One nasty thing that can happen here is that the UMA calls to
2246 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2247 * which calls UMA...
2249 * We break the loop by detecting recursion and allocating out of
2250 * the bootstrap pool.
2254 bootstrap = (flags & PVO_BOOTSTRAP);
2256 if (!moea64_initialized)
2259 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2260 rw_assert(&moea64_table_lock, RA_WLOCKED);
2263 * Compute the PTE Group index.
2266 vsid = va_to_vsid(pm, va);
2267 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2270 * Remove any existing mapping for this page. Reuse the pvo entry if
2271 * there is a mapping.
2273 moea64_pvo_enter_calls++;
2275 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2276 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2277 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2278 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2279 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2281 * The physical page and protection are not
2282 * changing. Instead, this may be a request
2283 * to change the mapping's wired attribute.
2286 if ((flags & PVO_WIRED) != 0 &&
2287 (pvo->pvo_vaddr & PVO_WIRED) == 0) {
2288 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2289 pvo->pvo_vaddr |= PVO_WIRED;
2290 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2291 pm->pm_stats.wired_count++;
2292 } else if ((flags & PVO_WIRED) == 0 &&
2293 (pvo->pvo_vaddr & PVO_WIRED) != 0) {
2294 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2295 pvo->pvo_vaddr &= ~PVO_WIRED;
2296 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
2297 pm->pm_stats.wired_count--;
2299 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2301 ("moea64_pvo_enter: valid pt"));
2302 /* Re-insert if spilled */
2303 i = MOEA64_PTE_INSERT(mmu, ptegidx,
2304 &pvo->pvo_pte.lpte);
2306 PVO_PTEGIDX_SET(pvo, i);
2307 moea64_pte_overflow--;
2308 } else if (pt != -1) {
2310 * The PTE's wired attribute is not a
2311 * hardware feature, so there is no
2312 * need to invalidate any TLB entries.
2314 MOEA64_PTE_CHANGE(mmu, pt,
2315 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2319 moea64_pvo_remove(mmu, pvo);
2325 * If we aren't overwriting a mapping, try to allocate.
2328 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2329 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2330 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2331 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2333 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2334 moea64_bpvo_pool_index++;
2337 pvo = uma_zalloc(zone, M_NOWAIT);
2343 moea64_pvo_entries++;
2344 pvo->pvo_vaddr = va;
2345 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2348 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2349 pvo->pvo_vaddr &= ~ADDR_POFF;
2351 if (flags & PVO_WIRED)
2352 pvo->pvo_vaddr |= PVO_WIRED;
2353 if (pvo_head != NULL)
2354 pvo->pvo_vaddr |= PVO_MANAGED;
2356 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2357 if (flags & PVO_LARGE)
2358 pvo->pvo_vaddr |= PVO_LARGE;
2360 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2361 (uint64_t)(pa) | pte_lo, flags);
2366 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2369 * Remember if the list was empty and therefore will be the first
2372 if (pvo_head != NULL) {
2373 if (LIST_FIRST(pvo_head) == NULL)
2375 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2378 if (pvo->pvo_vaddr & PVO_WIRED) {
2379 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2380 pm->pm_stats.wired_count++;
2382 pm->pm_stats.resident_count++;
2385 * We hope this succeeds but it isn't required.
2387 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2389 PVO_PTEGIDX_SET(pvo, i);
2391 panic("moea64_pvo_enter: overflow");
2392 moea64_pte_overflow++;
2395 if (pm == kernel_pmap)
2398 #ifdef __powerpc64__
2400 * Make sure all our bootstrap mappings are in the SLB as soon
2401 * as virtual memory is switched on.
2403 if (!pmap_bootstrapped)
2404 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2407 return (first ? ENOENT : 0);
2411 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2416 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2417 rw_assert(&moea64_table_lock, RA_WLOCKED);
2420 * If there is an active pte entry, we need to deactivate it (and
2421 * save the ref & cfg bits).
2423 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2425 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2426 PVO_PTEGIDX_CLR(pvo);
2428 moea64_pte_overflow--;
2432 * Update our statistics.
2434 pvo->pvo_pmap->pm_stats.resident_count--;
2435 if (pvo->pvo_vaddr & PVO_WIRED)
2436 pvo->pvo_pmap->pm_stats.wired_count--;
2439 * Remove this PVO from the pmap list.
2441 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2444 * Remove this from the overflow list and return it to the pool
2445 * if we aren't going to reuse it.
2447 LIST_REMOVE(pvo, pvo_olink);
2450 * Update vm about the REF/CHG bits if the page is managed.
2452 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2454 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2455 LIST_REMOVE(pvo, pvo_vlink);
2456 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2457 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2459 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2460 vm_page_aflag_set(pg, PGA_REFERENCED);
2461 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2462 vm_page_aflag_clear(pg, PGA_WRITEABLE);
2464 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2465 vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2468 moea64_pvo_entries--;
2469 moea64_pvo_remove_calls++;
2471 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2472 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2473 moea64_upvo_zone, pvo);
2476 static struct pvo_entry *
2477 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2479 struct pvo_entry key;
2481 key.pvo_vaddr = va & ~ADDR_POFF;
2482 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2486 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2488 struct pvo_entry *pvo;
2492 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2494 * See if we saved the bit off. If so, return success.
2496 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2503 * No luck, now go through the hard part of looking at the PTEs
2504 * themselves. Sync so that any pending REF/CHG bits are flushed to
2508 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2511 * See if this pvo has a valid PTE. if so, fetch the
2512 * REF/CHG bits from the valid PTE. If the appropriate
2513 * ptebit is set, return success.
2515 PMAP_LOCK(pvo->pvo_pmap);
2516 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2518 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2519 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2520 PMAP_UNLOCK(pvo->pvo_pmap);
2525 PMAP_UNLOCK(pvo->pvo_pmap);
2533 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2536 struct pvo_entry *pvo;
2540 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2541 * we can reset the right ones). note that since the pvo entries and
2542 * list heads are accessed via BAT0 and are never placed in the page
2543 * table, we don't have to worry about further accesses setting the
2549 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2550 * valid pte clear the ptebit from the valid pte.
2554 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2555 PMAP_LOCK(pvo->pvo_pmap);
2556 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2558 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2559 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2561 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2562 pvo->pvo_vpn, ptebit);
2565 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2566 PMAP_UNLOCK(pvo->pvo_pmap);
2574 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2576 struct pvo_entry *pvo, key;
2580 PMAP_LOCK(kernel_pmap);
2581 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2582 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2583 ppa < pa + size; ppa += PAGE_SIZE,
2584 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2586 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2591 PMAP_UNLOCK(kernel_pmap);
2597 * Map a set of physical memory pages into the kernel virtual
2598 * address space. Return a pointer to where it is mapped. This
2599 * routine is intended to be used for mapping device memory,
2603 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2605 vm_offset_t va, tmpva, ppa, offset;
2607 ppa = trunc_page(pa);
2608 offset = pa & PAGE_MASK;
2609 size = roundup2(offset + size, PAGE_SIZE);
2611 va = kva_alloc(size);
2614 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2616 for (tmpva = va; size > 0;) {
2617 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2623 return ((void *)(va + offset));
2627 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2630 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2634 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2636 vm_offset_t base, offset;
2638 base = trunc_page(va);
2639 offset = va & PAGE_MASK;
2640 size = roundup2(offset + size, PAGE_SIZE);
2642 kva_free(base, size);
2646 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2648 struct pvo_entry *pvo;
2655 lim = round_page(va);
2656 len = MIN(lim - va, sz);
2657 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2658 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2659 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2661 moea64_syncicache(mmu, pm, va, pa, len);
2670 moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2673 if (md->md_vaddr == ~0UL)
2674 return (md->md_paddr + ofs);
2676 return (md->md_vaddr + ofs);
2680 moea64_scan_md(mmu_t mmu, struct pmap_md *prev)
2682 static struct pmap_md md;
2683 struct pvo_entry *pvo;
2686 if (dumpsys_minidump) {
2687 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2689 /* 1st: kernel .data and .bss. */
2691 md.md_vaddr = trunc_page((uintptr_t)_etext);
2692 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2695 switch (prev->md_index) {
2697 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2699 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2700 md.md_size = round_page(msgbufp->msg_size);
2703 /* 3rd: kernel VM. */
2704 va = prev->md_vaddr + prev->md_size;
2705 /* Find start of next chunk (from va). */
2706 while (va < virtual_end) {
2707 /* Don't dump the buffer cache. */
2708 if (va >= kmi.buffer_sva &&
2709 va < kmi.buffer_eva) {
2710 va = kmi.buffer_eva;
2713 pvo = moea64_pvo_find_va(kernel_pmap,
2716 (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID))
2720 if (va < virtual_end) {
2723 /* Find last page in chunk. */
2724 while (va < virtual_end) {
2725 /* Don't run into the buffer cache. */
2726 if (va == kmi.buffer_sva)
2728 pvo = moea64_pvo_find_va(kernel_pmap,
2731 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID))
2735 md.md_size = va - md.md_vaddr;
2743 } else { /* minidumps */
2745 /* first physical chunk. */
2746 md.md_paddr = pregions[0].mr_start;
2747 md.md_size = pregions[0].mr_size;
2750 } else if (md.md_index < pregions_sz) {
2751 md.md_paddr = pregions[md.md_index].mr_start;
2752 md.md_size = pregions[md.md_index].mr_size;
2756 /* There's no next physical chunk. */