2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_compat.h"
113 #include "opt_kstack_pages.h"
115 #include <sys/param.h>
116 #include <sys/kernel.h>
117 #include <sys/queue.h>
118 #include <sys/cpuset.h>
120 #include <sys/lock.h>
121 #include <sys/msgbuf.h>
122 #include <sys/malloc.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rwlock.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/systm.h>
129 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
145 #include <machine/_inttypes.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/frame.h>
149 #include <machine/md_var.h>
150 #include <machine/psl.h>
151 #include <machine/bat.h>
152 #include <machine/hid.h>
153 #include <machine/pte.h>
154 #include <machine/sr.h>
155 #include <machine/trap.h>
156 #include <machine/mmuvar.h>
158 #include "mmu_oea64.h"
160 #include "moea64_if.h"
162 void moea64_release_vsid(uint64_t vsid);
163 uintptr_t moea64_get_unique_vsid(void);
165 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
166 #define ENABLE_TRANS(msr) mtmsr(msr)
168 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
169 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
170 #define VSID_HASH_MASK 0x0000007fffffffffULL
174 * -- Read lock: if no modifications are being made to either the PVO lists
175 * or page table or if any modifications being made result in internal
176 * changes (e.g. wiring, protection) such that the existence of the PVOs
177 * is unchanged and they remain associated with the same pmap (in which
178 * case the changes should be protected by the pmap lock)
179 * -- Write lock: required if PTEs/PVOs are being inserted or removed.
182 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
183 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
184 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
185 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
194 extern unsigned char _etext[];
195 extern unsigned char _end[];
197 extern int dumpsys_minidump;
200 * Map of physical memory regions.
202 static struct mem_region *regions;
203 static struct mem_region *pregions;
204 static u_int phys_avail_count;
205 static int regions_sz, pregions_sz;
207 extern void bs_remap_earlyboot(void);
210 * Lock for the pteg and pvo tables.
212 struct rwlock moea64_table_lock;
213 struct mtx moea64_slb_mutex;
218 u_int moea64_pteg_count;
219 u_int moea64_pteg_mask;
224 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
226 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
227 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
229 #define BPVO_POOL_SIZE 327680
230 static struct pvo_entry *moea64_bpvo_pool;
231 static int moea64_bpvo_pool_index = 0;
233 #define VSID_NBPW (sizeof(u_int32_t) * 8)
235 #define NVSIDS (NPMAPS * 16)
236 #define VSID_HASHMASK 0xffffffffUL
238 #define NVSIDS NPMAPS
239 #define VSID_HASHMASK 0xfffffUL
241 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
243 static boolean_t moea64_initialized = FALSE;
248 u_int moea64_pte_valid = 0;
249 u_int moea64_pte_overflow = 0;
250 u_int moea64_pvo_entries = 0;
251 u_int moea64_pvo_enter_calls = 0;
252 u_int moea64_pvo_remove_calls = 0;
253 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
254 &moea64_pte_valid, 0, "");
255 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
256 &moea64_pte_overflow, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
258 &moea64_pvo_entries, 0, "");
259 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
260 &moea64_pvo_enter_calls, 0, "");
261 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
262 &moea64_pvo_remove_calls, 0, "");
264 vm_offset_t moea64_scratchpage_va[2];
265 struct pvo_entry *moea64_scratchpage_pvo[2];
266 uintptr_t moea64_scratchpage_pte[2];
267 struct mtx moea64_scratchpage_mtx;
269 uint64_t moea64_large_page_mask = 0;
270 uint64_t moea64_large_page_size = 0;
271 int moea64_large_page_shift = 0;
276 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
277 vm_offset_t, vm_offset_t, uint64_t, int);
278 static void moea64_pvo_remove(mmu_t, struct pvo_entry *);
279 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
284 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
285 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
286 static void moea64_kremove(mmu_t, vm_offset_t);
287 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
288 vm_offset_t pa, vm_size_t sz);
291 * Kernel MMU interface
293 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
294 void moea64_clear_modify(mmu_t, vm_page_t);
295 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
296 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
297 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
298 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
299 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
301 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
302 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
303 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
304 void moea64_init(mmu_t);
305 boolean_t moea64_is_modified(mmu_t, vm_page_t);
306 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
307 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
308 int moea64_ts_referenced(mmu_t, vm_page_t);
309 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
310 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
311 int moea64_page_wired_mappings(mmu_t, vm_page_t);
312 void moea64_pinit(mmu_t, pmap_t);
313 void moea64_pinit0(mmu_t, pmap_t);
314 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
315 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
316 void moea64_qremove(mmu_t, vm_offset_t, int);
317 void moea64_release(mmu_t, pmap_t);
318 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
319 void moea64_remove_pages(mmu_t, pmap_t);
320 void moea64_remove_all(mmu_t, vm_page_t);
321 void moea64_remove_write(mmu_t, vm_page_t);
322 void moea64_zero_page(mmu_t, vm_page_t);
323 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
324 void moea64_zero_page_idle(mmu_t, vm_page_t);
325 void moea64_activate(mmu_t, struct thread *);
326 void moea64_deactivate(mmu_t, struct thread *);
327 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
328 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
329 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
330 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
331 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
332 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
333 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
334 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
335 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
336 vm_offset_t moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
338 struct pmap_md * moea64_scan_md(mmu_t mmu, struct pmap_md *prev);
340 static mmu_method_t moea64_methods[] = {
341 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
342 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
343 MMUMETHOD(mmu_copy_page, moea64_copy_page),
344 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
345 MMUMETHOD(mmu_enter, moea64_enter),
346 MMUMETHOD(mmu_enter_object, moea64_enter_object),
347 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
348 MMUMETHOD(mmu_extract, moea64_extract),
349 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
350 MMUMETHOD(mmu_init, moea64_init),
351 MMUMETHOD(mmu_is_modified, moea64_is_modified),
352 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
353 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
354 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
355 MMUMETHOD(mmu_map, moea64_map),
356 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
357 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
358 MMUMETHOD(mmu_pinit, moea64_pinit),
359 MMUMETHOD(mmu_pinit0, moea64_pinit0),
360 MMUMETHOD(mmu_protect, moea64_protect),
361 MMUMETHOD(mmu_qenter, moea64_qenter),
362 MMUMETHOD(mmu_qremove, moea64_qremove),
363 MMUMETHOD(mmu_release, moea64_release),
364 MMUMETHOD(mmu_remove, moea64_remove),
365 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
366 MMUMETHOD(mmu_remove_all, moea64_remove_all),
367 MMUMETHOD(mmu_remove_write, moea64_remove_write),
368 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
369 MMUMETHOD(mmu_zero_page, moea64_zero_page),
370 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
371 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
372 MMUMETHOD(mmu_activate, moea64_activate),
373 MMUMETHOD(mmu_deactivate, moea64_deactivate),
374 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
376 /* Internal interfaces */
377 MMUMETHOD(mmu_mapdev, moea64_mapdev),
378 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
379 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
380 MMUMETHOD(mmu_kextract, moea64_kextract),
381 MMUMETHOD(mmu_kenter, moea64_kenter),
382 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
383 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
384 MMUMETHOD(mmu_scan_md, moea64_scan_md),
385 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
390 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
392 static __inline u_int
393 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
398 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
399 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
401 return (hash & moea64_pteg_mask);
404 static __inline struct pvo_head *
405 vm_page_to_pvoh(vm_page_t m)
408 return (&m->md.mdpg_pvoh);
412 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
413 uint64_t pte_lo, int flags)
417 * Construct a PTE. Default to IMB initially. Valid bit only gets
418 * set when the real pte is set in memory.
420 * Note: Don't set the valid bit for correct operation of tlb update.
422 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
423 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
425 if (flags & PVO_LARGE)
426 pt->pte_hi |= LPTE_BIG;
431 static __inline uint64_t
432 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
437 if (ma != VM_MEMATTR_DEFAULT) {
439 case VM_MEMATTR_UNCACHEABLE:
440 return (LPTE_I | LPTE_G);
441 case VM_MEMATTR_WRITE_COMBINING:
442 case VM_MEMATTR_WRITE_BACK:
443 case VM_MEMATTR_PREFETCHABLE:
445 case VM_MEMATTR_WRITE_THROUGH:
446 return (LPTE_W | LPTE_M);
451 * Assume the page is cache inhibited and access is guarded unless
452 * it's in our available memory array.
454 pte_lo = LPTE_I | LPTE_G;
455 for (i = 0; i < pregions_sz; i++) {
456 if ((pa >= pregions[i].mr_start) &&
457 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
458 pte_lo &= ~(LPTE_I | LPTE_G);
468 * Quick sort callout for comparing memory regions.
470 static int om_cmp(const void *a, const void *b);
473 om_cmp(const void *a, const void *b)
475 const struct ofw_map *mapa;
476 const struct ofw_map *mapb;
480 if (mapa->om_pa < mapb->om_pa)
482 else if (mapa->om_pa > mapb->om_pa)
489 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
491 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
492 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
498 bzero(translations, sz);
499 OF_getprop(OF_finddevice("/"), "#address-cells", &acells,
501 if (OF_getprop(mmu, "translations", trans_cells, sz) == -1)
502 panic("moea64_bootstrap: can't get ofw translations");
504 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
505 sz /= sizeof(cell_t);
506 for (i = 0, j = 0; i < sz; j++) {
507 translations[j].om_va = trans_cells[i++];
508 translations[j].om_len = trans_cells[i++];
509 translations[j].om_pa = trans_cells[i++];
511 translations[j].om_pa <<= 32;
512 translations[j].om_pa |= trans_cells[i++];
514 translations[j].om_mode = trans_cells[i++];
516 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
520 qsort(translations, sz, sizeof (*translations), om_cmp);
522 for (i = 0; i < sz; i++) {
523 pa_base = translations[i].om_pa;
524 #ifndef __powerpc64__
525 if ((translations[i].om_pa >> 32) != 0)
526 panic("OFW translations above 32-bit boundary!");
529 if (pa_base % PAGE_SIZE)
530 panic("OFW translation not page-aligned (phys)!");
531 if (translations[i].om_va % PAGE_SIZE)
532 panic("OFW translation not page-aligned (virt)!");
534 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
535 pa_base, translations[i].om_va, translations[i].om_len);
537 /* Now enter the pages for this mapping */
540 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
541 if (moea64_pvo_find_va(kernel_pmap,
542 translations[i].om_va + off) != NULL)
545 moea64_kenter(mmup, translations[i].om_va + off,
554 moea64_probe_large_page(void)
556 uint16_t pvr = mfpvr() >> 16;
562 powerpc_sync(); isync();
563 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
564 powerpc_sync(); isync();
568 moea64_large_page_size = 0x1000000; /* 16 MB */
569 moea64_large_page_shift = 24;
572 moea64_large_page_mask = moea64_large_page_size - 1;
576 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
583 cache = PCPU_GET(slb);
584 esid = va >> ADDR_SR_SHFT;
585 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
587 for (i = 0; i < 64; i++) {
588 if (cache[i].slbe == (slbe | i))
593 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
595 entry.slbv |= SLBV_L;
597 slb_insert_kernel(entry.slbe, entry.slbv);
602 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
603 vm_offset_t kernelend)
607 vm_offset_t size, off;
611 if (moea64_large_page_size == 0)
617 PMAP_LOCK(kernel_pmap);
618 for (i = 0; i < pregions_sz; i++) {
619 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
620 pregions[i].mr_size; pa += moea64_large_page_size) {
624 * Set memory access as guarded if prefetch within
625 * the page could exit the available physmem area.
627 if (pa & moea64_large_page_mask) {
628 pa &= moea64_large_page_mask;
631 if (pa + moea64_large_page_size >
632 pregions[i].mr_start + pregions[i].mr_size)
635 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
636 NULL, pa, pa, pte_lo,
637 PVO_WIRED | PVO_LARGE);
640 PMAP_UNLOCK(kernel_pmap);
643 size = sizeof(struct pvo_head) * moea64_pteg_count;
644 off = (vm_offset_t)(moea64_pvo_table);
645 for (pa = off; pa < off + size; pa += PAGE_SIZE)
646 moea64_kenter(mmup, pa, pa);
647 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
648 off = (vm_offset_t)(moea64_bpvo_pool);
649 for (pa = off; pa < off + size; pa += PAGE_SIZE)
650 moea64_kenter(mmup, pa, pa);
653 * Map certain important things, like ourselves.
655 * NOTE: We do not map the exception vector space. That code is
656 * used only in real mode, and leaving it unmapped allows us to
657 * catch NULL pointer deferences, instead of making NULL a valid
661 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
663 moea64_kenter(mmup, pa, pa);
668 * Allow user to override unmapped_buf_allowed for testing.
669 * XXXKIB Only direct map implementation was tested.
671 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
672 &unmapped_buf_allowed))
673 unmapped_buf_allowed = hw_direct_map;
677 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
680 vm_size_t physsz, hwphyssz;
682 #ifndef __powerpc64__
683 /* We don't have a direct map since there is no BAT */
686 /* Make sure battable is zero, since we have no BAT */
687 for (i = 0; i < 16; i++) {
688 battable[i].batu = 0;
689 battable[i].batl = 0;
692 moea64_probe_large_page();
694 /* Use a direct map if we have large page support */
695 if (moea64_large_page_size > 0)
701 /* Get physical memory regions from firmware */
702 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
703 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
705 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
706 panic("moea64_bootstrap: phys_avail too small");
708 phys_avail_count = 0;
711 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
712 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
713 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
714 regions[i].mr_start, regions[i].mr_start +
715 regions[i].mr_size, regions[i].mr_size);
717 (physsz + regions[i].mr_size) >= hwphyssz) {
718 if (physsz < hwphyssz) {
719 phys_avail[j] = regions[i].mr_start;
720 phys_avail[j + 1] = regions[i].mr_start +
727 phys_avail[j] = regions[i].mr_start;
728 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
730 physsz += regions[i].mr_size;
733 /* Check for overlap with the kernel and exception vectors */
734 for (j = 0; j < 2*phys_avail_count; j+=2) {
735 if (phys_avail[j] < EXC_LAST)
736 phys_avail[j] += EXC_LAST;
738 if (kernelstart >= phys_avail[j] &&
739 kernelstart < phys_avail[j+1]) {
740 if (kernelend < phys_avail[j+1]) {
741 phys_avail[2*phys_avail_count] =
742 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
743 phys_avail[2*phys_avail_count + 1] =
748 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
751 if (kernelend >= phys_avail[j] &&
752 kernelend < phys_avail[j+1]) {
753 if (kernelstart > phys_avail[j]) {
754 phys_avail[2*phys_avail_count] = phys_avail[j];
755 phys_avail[2*phys_avail_count + 1] =
756 kernelstart & ~PAGE_MASK;
760 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
764 physmem = btoc(physsz);
767 moea64_pteg_count = PTEGCOUNT;
769 moea64_pteg_count = 0x1000;
771 while (moea64_pteg_count < physmem)
772 moea64_pteg_count <<= 1;
774 moea64_pteg_count >>= 1;
775 #endif /* PTEGCOUNT */
779 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
788 moea64_pteg_mask = moea64_pteg_count - 1;
791 * Allocate pv/overflow lists.
793 size = sizeof(struct pvo_head) * moea64_pteg_count;
795 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
797 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
800 for (i = 0; i < moea64_pteg_count; i++)
801 LIST_INIT(&moea64_pvo_table[i]);
805 * Initialize the lock that synchronizes access to the pteg and pvo
808 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
809 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
812 * Initialise the unmanaged pvo pool.
814 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
815 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
816 moea64_bpvo_pool_index = 0;
819 * Make sure kernel vsid is allocated as well as VSID 0.
821 #ifndef __powerpc64__
822 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
823 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
824 moea64_vsid_bitmap[0] |= 1;
828 * Initialize the kernel pmap (which is statically allocated).
831 for (i = 0; i < 64; i++) {
832 pcpup->pc_slb[i].slbv = 0;
833 pcpup->pc_slb[i].slbe = 0;
836 for (i = 0; i < 16; i++)
837 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
840 kernel_pmap->pmap_phys = kernel_pmap;
841 CPU_FILL(&kernel_pmap->pm_active);
842 RB_INIT(&kernel_pmap->pmap_pvo);
844 PMAP_LOCK_INIT(kernel_pmap);
847 * Now map in all the other buffers we allocated earlier
850 moea64_setup_direct_map(mmup, kernelstart, kernelend);
854 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
865 * Set up the Open Firmware pmap and add its mappings if not in real
869 chosen = OF_finddevice("/chosen");
870 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
871 mmu = OF_instance_to_package(mmui);
872 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
874 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
875 panic("moea64_bootstrap: too many ofw translations");
878 moea64_add_ofw_mappings(mmup, mmu, sz);
882 * Calculate the last available physical address.
884 for (i = 0; phys_avail[i + 2] != 0; i += 2)
886 Maxmem = powerpc_btop(phys_avail[i + 1]);
889 * Initialize MMU and remap early physical mappings
891 MMU_CPU_BOOTSTRAP(mmup,0);
892 mtmsr(mfmsr() | PSL_DR | PSL_IR);
894 bs_remap_earlyboot();
897 * Set the start and end of kva.
899 virtual_avail = VM_MIN_KERNEL_ADDRESS;
900 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
903 * Map the entire KVA range into the SLB. We must not fault there.
906 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
907 moea64_bootstrap_slb_prefault(va, 0);
911 * Figure out how far we can extend virtual_end into segment 16
912 * without running into existing mappings. Segment 16 is guaranteed
913 * to contain neither RAM nor devices (at least on Apple hardware),
914 * but will generally contain some OFW mappings we should not
918 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
919 PMAP_LOCK(kernel_pmap);
920 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
921 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
922 virtual_end += PAGE_SIZE;
923 PMAP_UNLOCK(kernel_pmap);
927 * Allocate a kernel stack with a guard page for thread0 and map it
928 * into the kernel page map.
930 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
931 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
932 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
933 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
934 thread0.td_kstack = va;
935 thread0.td_kstack_pages = KSTACK_PAGES;
936 for (i = 0; i < KSTACK_PAGES; i++) {
937 moea64_kenter(mmup, va, pa);
943 * Allocate virtual address space for the message buffer.
945 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
946 msgbufp = (struct msgbuf *)virtual_avail;
948 virtual_avail += round_page(msgbufsize);
949 while (va < virtual_avail) {
950 moea64_kenter(mmup, va, pa);
956 * Allocate virtual address space for the dynamic percpu area.
958 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
959 dpcpu = (void *)virtual_avail;
961 virtual_avail += DPCPU_SIZE;
962 while (va < virtual_avail) {
963 moea64_kenter(mmup, va, pa);
967 dpcpu_init(dpcpu, 0);
970 * Allocate some things for page zeroing. We put this directly
971 * in the page table, marked with LPTE_LOCKED, to avoid any
972 * of the PVO book-keeping or other parts of the VM system
973 * from even knowing that this hack exists.
976 if (!hw_direct_map) {
977 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
979 for (i = 0; i < 2; i++) {
980 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
981 virtual_end -= PAGE_SIZE;
983 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
985 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
986 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
988 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
989 mmup, moea64_scratchpage_pvo[i]);
990 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
992 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
993 &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
994 moea64_scratchpage_pvo[i]->pvo_vpn);
1001 * Activate a user pmap. The pmap must be activated before its address
1002 * space can be accessed in any way.
1005 moea64_activate(mmu_t mmu, struct thread *td)
1009 pm = &td->td_proc->p_vmspace->vm_pmap;
1010 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1012 #ifdef __powerpc64__
1013 PCPU_SET(userslb, pm->pm_slb);
1015 PCPU_SET(curpmap, pm->pmap_phys);
1020 moea64_deactivate(mmu_t mmu, struct thread *td)
1024 pm = &td->td_proc->p_vmspace->vm_pmap;
1025 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1026 #ifdef __powerpc64__
1027 PCPU_SET(userslb, NULL);
1029 PCPU_SET(curpmap, NULL);
1034 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1036 struct pvo_entry *pvo;
1043 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1046 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1049 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1050 pm->pm_stats.wired_count++;
1051 pvo->pvo_vaddr |= PVO_WIRED;
1052 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1054 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1055 pm->pm_stats.wired_count--;
1056 pvo->pvo_vaddr &= ~PVO_WIRED;
1057 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1061 /* Update wiring flag in page table. */
1062 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1066 * If we are wiring the page, and it wasn't in the
1067 * page table before, add it.
1069 vsid = PVO_VSID(pvo);
1070 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1071 pvo->pvo_vaddr & PVO_LARGE);
1073 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1076 PVO_PTEGIDX_CLR(pvo);
1077 PVO_PTEGIDX_SET(pvo, i);
1087 * This goes through and sets the physical address of our
1088 * special scratch PTE to the PA we want to zero or copy. Because
1089 * of locking issues (this can get called in pvo_enter() by
1090 * the UMA allocator), we can't use most other utility functions here
1094 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1096 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1097 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1099 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1100 ~(LPTE_WIMG | LPTE_RPGN);
1101 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1102 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1103 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1104 &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1105 moea64_scratchpage_pvo[which]->pvo_vpn);
1110 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1115 dst = VM_PAGE_TO_PHYS(mdst);
1116 src = VM_PAGE_TO_PHYS(msrc);
1118 if (hw_direct_map) {
1119 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1121 mtx_lock(&moea64_scratchpage_mtx);
1123 moea64_set_scratchpage_pa(mmu, 0, src);
1124 moea64_set_scratchpage_pa(mmu, 1, dst);
1126 bcopy((void *)moea64_scratchpage_va[0],
1127 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1129 mtx_unlock(&moea64_scratchpage_mtx);
1134 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1135 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1138 vm_offset_t a_pg_offset, b_pg_offset;
1141 while (xfersize > 0) {
1142 a_pg_offset = a_offset & PAGE_MASK;
1143 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1144 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1146 b_pg_offset = b_offset & PAGE_MASK;
1147 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1148 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1150 bcopy(a_cp, b_cp, cnt);
1158 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1159 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1162 vm_offset_t a_pg_offset, b_pg_offset;
1165 mtx_lock(&moea64_scratchpage_mtx);
1166 while (xfersize > 0) {
1167 a_pg_offset = a_offset & PAGE_MASK;
1168 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1169 moea64_set_scratchpage_pa(mmu, 0,
1170 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1171 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1172 b_pg_offset = b_offset & PAGE_MASK;
1173 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1174 moea64_set_scratchpage_pa(mmu, 1,
1175 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1176 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1177 bcopy(a_cp, b_cp, cnt);
1182 mtx_unlock(&moea64_scratchpage_mtx);
1186 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1187 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1190 if (hw_direct_map) {
1191 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1194 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1200 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1202 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1204 if (size + off > PAGE_SIZE)
1205 panic("moea64_zero_page: size + off > PAGE_SIZE");
1207 if (hw_direct_map) {
1208 bzero((caddr_t)pa + off, size);
1210 mtx_lock(&moea64_scratchpage_mtx);
1211 moea64_set_scratchpage_pa(mmu, 0, pa);
1212 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1213 mtx_unlock(&moea64_scratchpage_mtx);
1218 * Zero a page of physical memory by temporarily mapping it
1221 moea64_zero_page(mmu_t mmu, vm_page_t m)
1223 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1224 vm_offset_t va, off;
1226 if (!hw_direct_map) {
1227 mtx_lock(&moea64_scratchpage_mtx);
1229 moea64_set_scratchpage_pa(mmu, 0, pa);
1230 va = moea64_scratchpage_va[0];
1235 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1236 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1239 mtx_unlock(&moea64_scratchpage_mtx);
1243 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1246 moea64_zero_page(mmu, m);
1250 * Map the given physical page at the specified virtual address in the
1251 * target pmap with the protection requested. If specified the page
1252 * will be wired down.
1256 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1257 vm_prot_t prot, boolean_t wired)
1259 struct pvo_head *pvo_head;
1266 if (!moea64_initialized) {
1269 zone = moea64_upvo_zone;
1272 pvo_head = vm_page_to_pvoh(m);
1274 zone = moea64_mpvo_zone;
1275 pvo_flags = PVO_MANAGED;
1278 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1279 VM_OBJECT_ASSERT_LOCKED(m->object);
1281 /* XXX change the pvo head for fake pages */
1282 if ((m->oflags & VPO_UNMANAGED) != 0) {
1283 pvo_flags &= ~PVO_MANAGED;
1285 zone = moea64_upvo_zone;
1288 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1290 if (prot & VM_PROT_WRITE) {
1292 if (pmap_bootstrapped &&
1293 (m->oflags & VPO_UNMANAGED) == 0)
1294 vm_page_aflag_set(m, PGA_WRITEABLE);
1298 if ((prot & VM_PROT_EXECUTE) == 0)
1299 pte_lo |= LPTE_NOEXEC;
1302 pvo_flags |= PVO_WIRED;
1306 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1307 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1312 * Flush the page from the instruction cache if this page is
1313 * mapped executable and cacheable.
1315 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1316 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1317 vm_page_aflag_set(m, PGA_EXECUTABLE);
1318 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1323 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1328 * This is much trickier than on older systems because
1329 * we can't sync the icache on physical addresses directly
1330 * without a direct map. Instead we check a couple of cases
1331 * where the memory is already mapped in and, failing that,
1332 * use the same trick we use for page zeroing to create
1333 * a temporary mapping for this physical address.
1336 if (!pmap_bootstrapped) {
1338 * If PMAP is not bootstrapped, we are likely to be
1341 __syncicache((void *)pa, sz);
1342 } else if (pmap == kernel_pmap) {
1343 __syncicache((void *)va, sz);
1344 } else if (hw_direct_map) {
1345 __syncicache((void *)pa, sz);
1347 /* Use the scratch page to set up a temp mapping */
1349 mtx_lock(&moea64_scratchpage_mtx);
1351 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1352 __syncicache((void *)(moea64_scratchpage_va[1] +
1353 (va & ADDR_POFF)), sz);
1355 mtx_unlock(&moea64_scratchpage_mtx);
1360 * Maps a sequence of resident pages belonging to the same object.
1361 * The sequence begins with the given page m_start. This page is
1362 * mapped at the given virtual address start. Each subsequent page is
1363 * mapped at a virtual address that is offset from start by the same
1364 * amount as the page is offset from m_start within the object. The
1365 * last page in the sequence is the page with the largest offset from
1366 * m_start that can be mapped at a virtual address less than the given
1367 * virtual address end. Not every virtual page between start and end
1368 * is mapped; only those for which a resident page exists with the
1369 * corresponding offset from m_start are mapped.
1372 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1373 vm_page_t m_start, vm_prot_t prot)
1376 vm_pindex_t diff, psize;
1378 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1380 psize = atop(end - start);
1382 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1383 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1384 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1385 m = TAILQ_NEXT(m, listq);
1390 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1394 moea64_enter(mmu, pm, va, m,
1395 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1399 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1401 struct pvo_entry *pvo;
1405 pvo = moea64_pvo_find_va(pm, va);
1409 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1410 (va - PVO_VADDR(pvo));
1416 * Atomically extract and hold the physical page with the given
1417 * pmap and virtual address pair if that mapping permits the given
1421 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1423 struct pvo_entry *pvo;
1431 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1432 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1433 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1434 (prot & VM_PROT_WRITE) == 0)) {
1435 if (vm_page_pa_tryrelock(pmap,
1436 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1438 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1446 static mmu_t installed_mmu;
1449 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1452 * This entire routine is a horrible hack to avoid bothering kmem
1453 * for new KVA addresses. Because this can get called from inside
1454 * kmem allocation routines, calling kmem for a new address here
1455 * can lead to multiply locking non-recursive mutexes.
1460 int pflags, needed_lock;
1462 *flags = UMA_SLAB_PRIV;
1463 needed_lock = !PMAP_LOCKED(kernel_pmap);
1464 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
1467 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
1469 if (wait & M_NOWAIT)
1476 va = VM_PAGE_TO_PHYS(m);
1480 PMAP_LOCK(kernel_pmap);
1482 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1483 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP);
1486 PMAP_UNLOCK(kernel_pmap);
1489 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1490 bzero((void *)va, PAGE_SIZE);
1495 extern int elf32_nxstack;
1498 moea64_init(mmu_t mmu)
1501 CTR0(KTR_PMAP, "moea64_init");
1503 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1504 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1505 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1506 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1507 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1508 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1510 if (!hw_direct_map) {
1511 installed_mmu = mmu;
1512 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1513 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1516 #ifdef COMPAT_FREEBSD32
1520 moea64_initialized = TRUE;
1524 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1527 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1528 ("moea64_is_referenced: page %p is not managed", m));
1529 return (moea64_query_bit(mmu, m, PTE_REF));
1533 moea64_is_modified(mmu_t mmu, vm_page_t m)
1536 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1537 ("moea64_is_modified: page %p is not managed", m));
1540 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1541 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1542 * is clear, no PTEs can have LPTE_CHG set.
1544 VM_OBJECT_ASSERT_LOCKED(m->object);
1545 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1547 return (moea64_query_bit(mmu, m, LPTE_CHG));
1551 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1553 struct pvo_entry *pvo;
1557 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1558 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1564 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1567 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1568 ("moea64_clear_modify: page %p is not managed", m));
1569 VM_OBJECT_ASSERT_WLOCKED(m->object);
1570 KASSERT(!vm_page_xbusied(m),
1571 ("moea64_clear_modify: page %p is exclusive busied", m));
1574 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1575 * set. If the object containing the page is locked and the page is
1576 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1578 if ((m->aflags & PGA_WRITEABLE) == 0)
1580 moea64_clear_bit(mmu, m, LPTE_CHG);
1584 * Clear the write and modified bits in each of the given page's mappings.
1587 moea64_remove_write(mmu_t mmu, vm_page_t m)
1589 struct pvo_entry *pvo;
1594 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1595 ("moea64_remove_write: page %p is not managed", m));
1598 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1599 * set by another thread while the object is locked. Thus,
1600 * if PGA_WRITEABLE is clear, no page table entries need updating.
1602 VM_OBJECT_ASSERT_WLOCKED(m->object);
1603 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1607 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1608 pmap = pvo->pvo_pmap;
1610 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1611 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1612 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1613 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1615 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1616 lo |= pvo->pvo_pte.lpte.pte_lo;
1617 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1618 MOEA64_PTE_CHANGE(mmu, pt,
1619 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1620 if (pvo->pvo_pmap == kernel_pmap)
1624 if ((lo & LPTE_CHG) != 0)
1629 vm_page_aflag_clear(m, PGA_WRITEABLE);
1633 * moea64_ts_referenced:
1635 * Return a count of reference bits for a page, clearing those bits.
1636 * It is not necessary for every reference bit to be cleared, but it
1637 * is necessary that 0 only be returned when there are truly no
1638 * reference bits set.
1640 * XXX: The exact number of bits to check and clear is a matter that
1641 * should be tested and standardized at some point in the future for
1642 * optimal aging of shared pages.
1645 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1648 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1649 ("moea64_ts_referenced: page %p is not managed", m));
1650 return (moea64_clear_bit(mmu, m, LPTE_REF));
1654 * Modify the WIMG settings of all mappings for a page.
1657 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1659 struct pvo_entry *pvo;
1660 struct pvo_head *pvo_head;
1665 if ((m->oflags & VPO_UNMANAGED) != 0) {
1666 m->md.mdpg_cache_attrs = ma;
1670 pvo_head = vm_page_to_pvoh(m);
1671 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1673 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1674 pmap = pvo->pvo_pmap;
1676 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1677 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1678 pvo->pvo_pte.lpte.pte_lo |= lo;
1680 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1682 if (pvo->pvo_pmap == kernel_pmap)
1688 m->md.mdpg_cache_attrs = ma;
1692 * Map a wired page into kernel virtual address space.
1695 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1700 pte_lo = moea64_calc_wimg(pa, ma);
1703 PMAP_LOCK(kernel_pmap);
1704 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1705 NULL, va, pa, pte_lo, PVO_WIRED);
1706 PMAP_UNLOCK(kernel_pmap);
1709 if (error != 0 && error != ENOENT)
1710 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1715 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1718 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1722 * Extract the physical page address associated with the given kernel virtual
1726 moea64_kextract(mmu_t mmu, vm_offset_t va)
1728 struct pvo_entry *pvo;
1732 * Shortcut the direct-mapped case when applicable. We never put
1733 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1735 if (va < VM_MIN_KERNEL_ADDRESS)
1738 PMAP_LOCK(kernel_pmap);
1739 pvo = moea64_pvo_find_va(kernel_pmap, va);
1740 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1742 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1743 PMAP_UNLOCK(kernel_pmap);
1748 * Remove a wired page from kernel virtual address space.
1751 moea64_kremove(mmu_t mmu, vm_offset_t va)
1753 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1757 * Map a range of physical addresses into kernel virtual address space.
1759 * The value passed in *virt is a suggested virtual address for the mapping.
1760 * Architectures which can support a direct-mapped physical to virtual region
1761 * can return the appropriate address within that region, leaving '*virt'
1762 * unchanged. We cannot and therefore do not; *virt is updated with the
1763 * first usable address after the mapped region.
1766 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1767 vm_paddr_t pa_end, int prot)
1769 vm_offset_t sva, va;
1773 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1774 moea64_kenter(mmu, va, pa_start);
1781 * Returns true if the pmap's pv is one of the first
1782 * 16 pvs linked to from this page. This count may
1783 * be changed upwards or downwards in the future; it
1784 * is only necessary that true be returned for a small
1785 * subset of pmaps for proper page aging.
1788 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1791 struct pvo_entry *pvo;
1794 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1795 ("moea64_page_exists_quick: page %p is not managed", m));
1799 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1800 if (pvo->pvo_pmap == pmap) {
1812 * Return the number of managed mappings to the given physical page
1816 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1818 struct pvo_entry *pvo;
1822 if ((m->oflags & VPO_UNMANAGED) != 0)
1825 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1826 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1832 static uintptr_t moea64_vsidcontext;
1835 moea64_get_unique_vsid(void) {
1842 __asm __volatile("mftb %0" : "=r"(entropy));
1844 mtx_lock(&moea64_slb_mutex);
1845 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1849 * Create a new value by mutiplying by a prime and adding in
1850 * entropy from the timebase register. This is to make the
1851 * VSID more random so that the PT hash function collides
1852 * less often. (Note that the prime casues gcc to do shifts
1853 * instead of a multiply.)
1855 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1856 hash = moea64_vsidcontext & (NVSIDS - 1);
1857 if (hash == 0) /* 0 is special, avoid it */
1860 mask = 1 << (hash & (VSID_NBPW - 1));
1861 hash = (moea64_vsidcontext & VSID_HASHMASK);
1862 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1863 /* anything free in this bucket? */
1864 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1865 entropy = (moea64_vsidcontext >> 20);
1868 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1870 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1873 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1874 ("Allocating in-use VSID %#zx\n", hash));
1875 moea64_vsid_bitmap[n] |= mask;
1876 mtx_unlock(&moea64_slb_mutex);
1880 mtx_unlock(&moea64_slb_mutex);
1881 panic("%s: out of segments",__func__);
1884 #ifdef __powerpc64__
1886 moea64_pinit(mmu_t mmu, pmap_t pmap)
1889 RB_INIT(&pmap->pmap_pvo);
1891 pmap->pm_slb_tree_root = slb_alloc_tree();
1892 pmap->pm_slb = slb_alloc_user_cache();
1893 pmap->pm_slb_len = 0;
1897 moea64_pinit(mmu_t mmu, pmap_t pmap)
1902 RB_INIT(&pmap->pmap_pvo);
1904 if (pmap_bootstrapped)
1905 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1908 pmap->pmap_phys = pmap;
1911 * Allocate some segment registers for this pmap.
1913 hash = moea64_get_unique_vsid();
1915 for (i = 0; i < 16; i++)
1916 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1918 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1923 * Initialize the pmap associated with process 0.
1926 moea64_pinit0(mmu_t mmu, pmap_t pm)
1930 moea64_pinit(mmu, pm);
1931 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1935 * Set the physical protection on the specified range of this map as requested.
1938 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1944 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1947 * Grab the PTE pointer before we diddle with the cached PTE
1950 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1953 * Change the protection of the page.
1955 oldlo = pvo->pvo_pte.lpte.pte_lo;
1956 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1957 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1958 if ((prot & VM_PROT_EXECUTE) == 0)
1959 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1960 if (prot & VM_PROT_WRITE)
1961 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
1963 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1965 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1968 * If the PVO is in the page table, update that pte as well.
1971 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1973 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
1974 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1975 if ((pg->oflags & VPO_UNMANAGED) == 0)
1976 vm_page_aflag_set(pg, PGA_EXECUTABLE);
1977 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
1978 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
1982 * Update vm about the REF/CHG bits if the page is managed and we have
1983 * removed write access.
1985 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
1986 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) {
1988 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
1990 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
1991 vm_page_aflag_set(pg, PGA_REFERENCED);
1997 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2000 struct pvo_entry *pvo, *tpvo, key;
2002 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2005 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2006 ("moea64_protect: non current pmap"));
2008 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2009 moea64_remove(mmu, pm, sva, eva);
2015 key.pvo_vaddr = sva;
2016 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2017 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2018 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2019 moea64_pvo_protect(mmu, pm, pvo, prot);
2026 * Map a list of wired pages into kernel virtual address space. This is
2027 * intended for temporary mappings which do not need page modification or
2028 * references recorded. Existing mappings in the region are overwritten.
2031 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2033 while (count-- > 0) {
2034 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2041 * Remove page mappings from kernel virtual address space. Intended for
2042 * temporary mappings entered by moea64_qenter.
2045 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2047 while (count-- > 0) {
2048 moea64_kremove(mmu, va);
2054 moea64_release_vsid(uint64_t vsid)
2058 mtx_lock(&moea64_slb_mutex);
2059 idx = vsid & (NVSIDS-1);
2060 mask = 1 << (idx % VSID_NBPW);
2062 KASSERT(moea64_vsid_bitmap[idx] & mask,
2063 ("Freeing unallocated VSID %#jx", vsid));
2064 moea64_vsid_bitmap[idx] &= ~mask;
2065 mtx_unlock(&moea64_slb_mutex);
2070 moea64_release(mmu_t mmu, pmap_t pmap)
2074 * Free segment registers' VSIDs
2076 #ifdef __powerpc64__
2077 slb_free_tree(pmap);
2078 slb_free_user_cache(pmap->pm_slb);
2080 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2082 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2087 * Remove all pages mapped by the specified pmap
2090 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2092 struct pvo_entry *pvo, *tpvo;
2096 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2097 if (!(pvo->pvo_vaddr & PVO_WIRED))
2098 moea64_pvo_remove(mmu, pvo);
2105 * Remove the given range of addresses from the specified map.
2108 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2110 struct pvo_entry *pvo, *tpvo, key;
2113 * Perform an unsynchronized read. This is, however, safe.
2115 if (pm->pm_stats.resident_count == 0)
2120 key.pvo_vaddr = sva;
2121 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2122 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2123 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2124 moea64_pvo_remove(mmu, pvo);
2131 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2132 * will reflect changes in pte's back to the vm_page.
2135 moea64_remove_all(mmu_t mmu, vm_page_t m)
2137 struct pvo_entry *pvo, *next_pvo;
2141 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2142 pmap = pvo->pvo_pmap;
2144 moea64_pvo_remove(mmu, pvo);
2148 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2150 vm_page_aflag_clear(m, PGA_WRITEABLE);
2151 vm_page_aflag_clear(m, PGA_EXECUTABLE);
2155 * Allocate a physical page of memory directly from the phys_avail map.
2156 * Can only be called from moea64_bootstrap before avail start and end are
2160 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2165 size = round_page(size);
2166 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2168 s = (phys_avail[i] + align - 1) & ~(align - 1);
2173 if (s < phys_avail[i] || e > phys_avail[i + 1])
2176 if (s + size > platform_real_maxaddr())
2179 if (s == phys_avail[i]) {
2180 phys_avail[i] += size;
2181 } else if (e == phys_avail[i + 1]) {
2182 phys_avail[i + 1] -= size;
2184 for (j = phys_avail_count * 2; j > i; j -= 2) {
2185 phys_avail[j] = phys_avail[j - 2];
2186 phys_avail[j + 1] = phys_avail[j - 1];
2189 phys_avail[i + 3] = phys_avail[i + 1];
2190 phys_avail[i + 1] = s;
2191 phys_avail[i + 2] = e;
2197 panic("moea64_bootstrap_alloc: could not allocate memory");
2201 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2202 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2203 uint64_t pte_lo, int flags)
2205 struct pvo_entry *pvo;
2213 * One nasty thing that can happen here is that the UMA calls to
2214 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2215 * which calls UMA...
2217 * We break the loop by detecting recursion and allocating out of
2218 * the bootstrap pool.
2222 bootstrap = (flags & PVO_BOOTSTRAP);
2224 if (!moea64_initialized)
2227 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2228 rw_assert(&moea64_table_lock, RA_WLOCKED);
2231 * Compute the PTE Group index.
2234 vsid = va_to_vsid(pm, va);
2235 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2238 * Remove any existing mapping for this page. Reuse the pvo entry if
2239 * there is a mapping.
2241 moea64_pvo_enter_calls++;
2243 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2244 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2245 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2246 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2247 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2248 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2249 /* Re-insert if spilled */
2250 i = MOEA64_PTE_INSERT(mmu, ptegidx,
2251 &pvo->pvo_pte.lpte);
2253 PVO_PTEGIDX_SET(pvo, i);
2254 moea64_pte_overflow--;
2258 moea64_pvo_remove(mmu, pvo);
2264 * If we aren't overwriting a mapping, try to allocate.
2267 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2268 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2269 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2270 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2272 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2273 moea64_bpvo_pool_index++;
2276 pvo = uma_zalloc(zone, M_NOWAIT);
2282 moea64_pvo_entries++;
2283 pvo->pvo_vaddr = va;
2284 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2287 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2288 pvo->pvo_vaddr &= ~ADDR_POFF;
2290 if (flags & PVO_WIRED)
2291 pvo->pvo_vaddr |= PVO_WIRED;
2292 if (pvo_head != NULL)
2293 pvo->pvo_vaddr |= PVO_MANAGED;
2295 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2296 if (flags & PVO_LARGE)
2297 pvo->pvo_vaddr |= PVO_LARGE;
2299 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2300 (uint64_t)(pa) | pte_lo, flags);
2305 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2308 * Remember if the list was empty and therefore will be the first
2311 if (pvo_head != NULL) {
2312 if (LIST_FIRST(pvo_head) == NULL)
2314 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2317 if (pvo->pvo_vaddr & PVO_WIRED) {
2318 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2319 pm->pm_stats.wired_count++;
2321 pm->pm_stats.resident_count++;
2324 * We hope this succeeds but it isn't required.
2326 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2328 PVO_PTEGIDX_SET(pvo, i);
2330 panic("moea64_pvo_enter: overflow");
2331 moea64_pte_overflow++;
2334 if (pm == kernel_pmap)
2337 #ifdef __powerpc64__
2339 * Make sure all our bootstrap mappings are in the SLB as soon
2340 * as virtual memory is switched on.
2342 if (!pmap_bootstrapped)
2343 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2346 return (first ? ENOENT : 0);
2350 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2355 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2356 rw_assert(&moea64_table_lock, RA_WLOCKED);
2359 * If there is an active pte entry, we need to deactivate it (and
2360 * save the ref & cfg bits).
2362 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2364 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2365 PVO_PTEGIDX_CLR(pvo);
2367 moea64_pte_overflow--;
2371 * Update our statistics.
2373 pvo->pvo_pmap->pm_stats.resident_count--;
2374 if (pvo->pvo_vaddr & PVO_WIRED)
2375 pvo->pvo_pmap->pm_stats.wired_count--;
2378 * Remove this PVO from the pmap list.
2380 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2383 * Remove this from the overflow list and return it to the pool
2384 * if we aren't going to reuse it.
2386 LIST_REMOVE(pvo, pvo_olink);
2389 * Update vm about the REF/CHG bits if the page is managed.
2391 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2393 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2394 LIST_REMOVE(pvo, pvo_vlink);
2395 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2396 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2398 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2399 vm_page_aflag_set(pg, PGA_REFERENCED);
2400 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2401 vm_page_aflag_clear(pg, PGA_WRITEABLE);
2403 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2404 vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2407 moea64_pvo_entries--;
2408 moea64_pvo_remove_calls++;
2410 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2411 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2412 moea64_upvo_zone, pvo);
2415 static struct pvo_entry *
2416 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2418 struct pvo_entry key;
2420 key.pvo_vaddr = va & ~ADDR_POFF;
2421 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2425 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2427 struct pvo_entry *pvo;
2431 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2433 * See if we saved the bit off. If so, return success.
2435 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2442 * No luck, now go through the hard part of looking at the PTEs
2443 * themselves. Sync so that any pending REF/CHG bits are flushed to
2447 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2450 * See if this pvo has a valid PTE. if so, fetch the
2451 * REF/CHG bits from the valid PTE. If the appropriate
2452 * ptebit is set, return success.
2454 PMAP_LOCK(pvo->pvo_pmap);
2455 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2457 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2458 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2459 PMAP_UNLOCK(pvo->pvo_pmap);
2464 PMAP_UNLOCK(pvo->pvo_pmap);
2472 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2475 struct pvo_entry *pvo;
2479 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2480 * we can reset the right ones). note that since the pvo entries and
2481 * list heads are accessed via BAT0 and are never placed in the page
2482 * table, we don't have to worry about further accesses setting the
2488 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2489 * valid pte clear the ptebit from the valid pte.
2493 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2494 PMAP_LOCK(pvo->pvo_pmap);
2495 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2497 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2498 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2500 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2501 pvo->pvo_vpn, ptebit);
2504 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2505 PMAP_UNLOCK(pvo->pvo_pmap);
2513 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2515 struct pvo_entry *pvo, key;
2519 PMAP_LOCK(kernel_pmap);
2520 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2521 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2522 ppa < pa + size; ppa += PAGE_SIZE,
2523 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2525 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2530 PMAP_UNLOCK(kernel_pmap);
2536 * Map a set of physical memory pages into the kernel virtual
2537 * address space. Return a pointer to where it is mapped. This
2538 * routine is intended to be used for mapping device memory,
2542 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2544 vm_offset_t va, tmpva, ppa, offset;
2546 ppa = trunc_page(pa);
2547 offset = pa & PAGE_MASK;
2548 size = roundup2(offset + size, PAGE_SIZE);
2550 va = kva_alloc(size);
2553 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2555 for (tmpva = va; size > 0;) {
2556 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2562 return ((void *)(va + offset));
2566 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2569 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2573 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2575 vm_offset_t base, offset;
2577 base = trunc_page(va);
2578 offset = va & PAGE_MASK;
2579 size = roundup2(offset + size, PAGE_SIZE);
2581 kva_free(base, size);
2585 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2587 struct pvo_entry *pvo;
2594 lim = round_page(va);
2595 len = MIN(lim - va, sz);
2596 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2597 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2598 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2600 moea64_syncicache(mmu, pm, va, pa, len);
2609 moea64_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2612 if (md->md_vaddr == ~0UL)
2613 return (md->md_paddr + ofs);
2615 return (md->md_vaddr + ofs);
2619 moea64_scan_md(mmu_t mmu, struct pmap_md *prev)
2621 static struct pmap_md md;
2622 struct pvo_entry *pvo;
2625 if (dumpsys_minidump) {
2626 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2628 /* 1st: kernel .data and .bss. */
2630 md.md_vaddr = trunc_page((uintptr_t)_etext);
2631 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2634 switch (prev->md_index) {
2636 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2638 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2639 md.md_size = round_page(msgbufp->msg_size);
2642 /* 3rd: kernel VM. */
2643 va = prev->md_vaddr + prev->md_size;
2644 /* Find start of next chunk (from va). */
2645 while (va < virtual_end) {
2646 /* Don't dump the buffer cache. */
2647 if (va >= kmi.buffer_sva &&
2648 va < kmi.buffer_eva) {
2649 va = kmi.buffer_eva;
2652 pvo = moea64_pvo_find_va(kernel_pmap,
2655 (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID))
2659 if (va < virtual_end) {
2662 /* Find last page in chunk. */
2663 while (va < virtual_end) {
2664 /* Don't run into the buffer cache. */
2665 if (va == kmi.buffer_sva)
2667 pvo = moea64_pvo_find_va(kernel_pmap,
2670 !(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID))
2674 md.md_size = va - md.md_vaddr;
2682 } else { /* minidumps */
2684 /* first physical chunk. */
2685 md.md_paddr = pregions[0].mr_start;
2686 md.md_size = pregions[0].mr_size;
2689 } else if (md.md_index < pregions_sz) {
2690 md.md_paddr = pregions[md.md_index].mr_start;
2691 md.md_size = pregions[md.md_index].mr_size;
2695 /* There's no next physical chunk. */