2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008-2015 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Manages physical address maps.
35 * Since the information managed by this module is also stored by the
36 * logical address mapping module, this module may throw away valid virtual
37 * to physical mappings at almost any time. However, invalidations of
38 * mappings must be done as requested.
40 * In order to cope with hardware architectures which make virtual to
41 * physical map invalidates expensive, this module may delay invalidate
42 * reduced protection operations until such time as they are actually
43 * necessary. This module is given full information as to which processors
44 * are currently using which maps, and to when physical maps must be made
48 #include "opt_compat.h"
49 #include "opt_kstack_pages.h"
51 #include <sys/param.h>
52 #include <sys/kernel.h>
54 #include <sys/queue.h>
55 #include <sys/cpuset.h>
56 #include <sys/kerneldump.h>
59 #include <sys/msgbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/mutex.h>
63 #include <sys/rwlock.h>
64 #include <sys/sched.h>
65 #include <sys/sysctl.h>
66 #include <sys/systm.h>
67 #include <sys/vmmeter.h>
72 #include <dev/ofw/openfirm.h>
75 #include <vm/vm_param.h>
76 #include <vm/vm_kern.h>
77 #include <vm/vm_page.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_object.h>
80 #include <vm/vm_extern.h>
81 #include <vm/vm_pageout.h>
84 #include <machine/_inttypes.h>
85 #include <machine/cpu.h>
86 #include <machine/platform.h>
87 #include <machine/frame.h>
88 #include <machine/md_var.h>
89 #include <machine/psl.h>
90 #include <machine/bat.h>
91 #include <machine/hid.h>
92 #include <machine/pte.h>
93 #include <machine/sr.h>
94 #include <machine/trap.h>
95 #include <machine/mmuvar.h>
97 #include "mmu_oea64.h"
99 #include "moea64_if.h"
101 void moea64_release_vsid(uint64_t vsid);
102 uintptr_t moea64_get_unique_vsid(void);
104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
105 #define ENABLE_TRANS(msr) mtmsr(msr)
107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
109 #define VSID_HASH_MASK 0x0000007fffffffffULL
114 * There are two locks of interest: the page locks and the pmap locks, which
115 * protect their individual PVO lists and are locked in that order. The contents
116 * of all PVO entries are protected by the locks of their respective pmaps.
117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
122 #define PV_LOCK_COUNT PA_LOCK_COUNT*3
123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
125 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT]))
126 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa))
127 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa))
128 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
129 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m))
130 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m))
131 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
140 extern unsigned char _etext[];
141 extern unsigned char _end[];
143 extern void *slbtrap, *slbtrapend;
146 * Map of physical memory regions.
148 static struct mem_region *regions;
149 static struct mem_region *pregions;
150 static u_int phys_avail_count;
151 static int regions_sz, pregions_sz;
153 extern void bs_remap_earlyboot(void);
156 * Lock for the SLB tables.
158 struct mtx moea64_slb_mutex;
163 u_int moea64_pteg_count;
164 u_int moea64_pteg_mask;
170 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */
172 static struct pvo_entry *moea64_bpvo_pool;
173 static int moea64_bpvo_pool_index = 0;
174 static int moea64_bpvo_pool_size = 327680;
175 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
176 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
177 &moea64_bpvo_pool_index, 0, "");
179 #define VSID_NBPW (sizeof(u_int32_t) * 8)
181 #define NVSIDS (NPMAPS * 16)
182 #define VSID_HASHMASK 0xffffffffUL
184 #define NVSIDS NPMAPS
185 #define VSID_HASHMASK 0xfffffUL
187 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
189 static boolean_t moea64_initialized = FALSE;
194 u_int moea64_pte_valid = 0;
195 u_int moea64_pte_overflow = 0;
196 u_int moea64_pvo_entries = 0;
197 u_int moea64_pvo_enter_calls = 0;
198 u_int moea64_pvo_remove_calls = 0;
199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
200 &moea64_pte_valid, 0, "");
201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
202 &moea64_pte_overflow, 0, "");
203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
204 &moea64_pvo_entries, 0, "");
205 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
206 &moea64_pvo_enter_calls, 0, "");
207 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
208 &moea64_pvo_remove_calls, 0, "");
210 vm_offset_t moea64_scratchpage_va[2];
211 struct pvo_entry *moea64_scratchpage_pvo[2];
212 struct mtx moea64_scratchpage_mtx;
214 uint64_t moea64_large_page_mask = 0;
215 uint64_t moea64_large_page_size = 0;
216 int moea64_large_page_shift = 0;
221 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo,
222 struct pvo_head *pvo_head);
223 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo);
224 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo);
225 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
230 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t);
231 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t);
232 static void moea64_kremove(mmu_t, vm_offset_t);
233 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
234 vm_paddr_t pa, vm_size_t sz);
235 static void moea64_pmap_init_qpages(void);
238 * Kernel MMU interface
240 void moea64_clear_modify(mmu_t, vm_page_t);
241 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
242 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
243 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
244 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
245 u_int flags, int8_t psind);
246 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
248 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
249 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
250 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
251 void moea64_init(mmu_t);
252 boolean_t moea64_is_modified(mmu_t, vm_page_t);
253 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
254 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
255 int moea64_ts_referenced(mmu_t, vm_page_t);
256 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
257 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
258 void moea64_page_init(mmu_t, vm_page_t);
259 int moea64_page_wired_mappings(mmu_t, vm_page_t);
260 void moea64_pinit(mmu_t, pmap_t);
261 void moea64_pinit0(mmu_t, pmap_t);
262 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
263 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
264 void moea64_qremove(mmu_t, vm_offset_t, int);
265 void moea64_release(mmu_t, pmap_t);
266 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
267 void moea64_remove_pages(mmu_t, pmap_t);
268 void moea64_remove_all(mmu_t, vm_page_t);
269 void moea64_remove_write(mmu_t, vm_page_t);
270 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
271 void moea64_zero_page(mmu_t, vm_page_t);
272 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
273 void moea64_activate(mmu_t, struct thread *);
274 void moea64_deactivate(mmu_t, struct thread *);
275 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
276 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
277 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
278 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
279 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
280 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma);
281 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
282 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
283 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
284 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz,
286 void moea64_scan_init(mmu_t mmu);
287 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m);
288 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr);
289 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm,
290 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
293 static mmu_method_t moea64_methods[] = {
294 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
295 MMUMETHOD(mmu_copy_page, moea64_copy_page),
296 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
297 MMUMETHOD(mmu_enter, moea64_enter),
298 MMUMETHOD(mmu_enter_object, moea64_enter_object),
299 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
300 MMUMETHOD(mmu_extract, moea64_extract),
301 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
302 MMUMETHOD(mmu_init, moea64_init),
303 MMUMETHOD(mmu_is_modified, moea64_is_modified),
304 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
305 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
306 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
307 MMUMETHOD(mmu_map, moea64_map),
308 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
309 MMUMETHOD(mmu_page_init, moea64_page_init),
310 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
311 MMUMETHOD(mmu_pinit, moea64_pinit),
312 MMUMETHOD(mmu_pinit0, moea64_pinit0),
313 MMUMETHOD(mmu_protect, moea64_protect),
314 MMUMETHOD(mmu_qenter, moea64_qenter),
315 MMUMETHOD(mmu_qremove, moea64_qremove),
316 MMUMETHOD(mmu_release, moea64_release),
317 MMUMETHOD(mmu_remove, moea64_remove),
318 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
319 MMUMETHOD(mmu_remove_all, moea64_remove_all),
320 MMUMETHOD(mmu_remove_write, moea64_remove_write),
321 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
322 MMUMETHOD(mmu_unwire, moea64_unwire),
323 MMUMETHOD(mmu_zero_page, moea64_zero_page),
324 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
325 MMUMETHOD(mmu_activate, moea64_activate),
326 MMUMETHOD(mmu_deactivate, moea64_deactivate),
327 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
328 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page),
329 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page),
331 /* Internal interfaces */
332 MMUMETHOD(mmu_mapdev, moea64_mapdev),
333 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
334 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
335 MMUMETHOD(mmu_kextract, moea64_kextract),
336 MMUMETHOD(mmu_kenter, moea64_kenter),
337 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
338 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
339 MMUMETHOD(mmu_scan_init, moea64_scan_init),
340 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
341 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr),
346 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
348 static struct pvo_head *
349 vm_page_to_pvoh(vm_page_t m)
352 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
353 return (&m->md.mdpg_pvoh);
356 static struct pvo_entry *
357 alloc_pvo_entry(int bootstrap)
359 struct pvo_entry *pvo;
361 if (!moea64_initialized || bootstrap) {
362 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
363 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
364 moea64_bpvo_pool_index, moea64_bpvo_pool_size,
365 moea64_bpvo_pool_size * sizeof(struct pvo_entry));
367 pvo = &moea64_bpvo_pool[
368 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
369 bzero(pvo, sizeof(*pvo));
370 pvo->pvo_vaddr = PVO_BOOTSTRAP;
372 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT);
373 bzero(pvo, sizeof(*pvo));
381 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
387 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
389 pvo->pvo_pmap = pmap;
391 pvo->pvo_vaddr |= va;
392 vsid = va_to_vsid(pmap, va);
393 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
396 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift :
398 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
399 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
403 free_pvo_entry(struct pvo_entry *pvo)
406 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
407 uma_zfree(moea64_pvo_zone, pvo);
411 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
414 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) &
416 lpte->pte_hi |= LPTE_VALID;
418 if (pvo->pvo_vaddr & PVO_LARGE)
419 lpte->pte_hi |= LPTE_BIG;
420 if (pvo->pvo_vaddr & PVO_WIRED)
421 lpte->pte_hi |= LPTE_WIRED;
422 if (pvo->pvo_vaddr & PVO_HID)
423 lpte->pte_hi |= LPTE_HID;
425 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
426 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
427 lpte->pte_lo |= LPTE_BW;
429 lpte->pte_lo |= LPTE_BR;
431 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
432 lpte->pte_lo |= LPTE_NOEXEC;
435 static __inline uint64_t
436 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
441 if (ma != VM_MEMATTR_DEFAULT) {
443 case VM_MEMATTR_UNCACHEABLE:
444 return (LPTE_I | LPTE_G);
445 case VM_MEMATTR_CACHEABLE:
447 case VM_MEMATTR_WRITE_COMBINING:
448 case VM_MEMATTR_WRITE_BACK:
449 case VM_MEMATTR_PREFETCHABLE:
451 case VM_MEMATTR_WRITE_THROUGH:
452 return (LPTE_W | LPTE_M);
457 * Assume the page is cache inhibited and access is guarded unless
458 * it's in our available memory array.
460 pte_lo = LPTE_I | LPTE_G;
461 for (i = 0; i < pregions_sz; i++) {
462 if ((pa >= pregions[i].mr_start) &&
463 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
464 pte_lo &= ~(LPTE_I | LPTE_G);
474 * Quick sort callout for comparing memory regions.
476 static int om_cmp(const void *a, const void *b);
479 om_cmp(const void *a, const void *b)
481 const struct ofw_map *mapa;
482 const struct ofw_map *mapb;
486 if (mapa->om_pa < mapb->om_pa)
488 else if (mapa->om_pa > mapb->om_pa)
495 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
497 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
498 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
499 struct pvo_entry *pvo;
505 bzero(translations, sz);
506 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
508 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
509 panic("moea64_bootstrap: can't get ofw translations");
511 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
512 sz /= sizeof(cell_t);
513 for (i = 0, j = 0; i < sz; j++) {
514 translations[j].om_va = trans_cells[i++];
515 translations[j].om_len = trans_cells[i++];
516 translations[j].om_pa = trans_cells[i++];
518 translations[j].om_pa <<= 32;
519 translations[j].om_pa |= trans_cells[i++];
521 translations[j].om_mode = trans_cells[i++];
523 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
527 qsort(translations, sz, sizeof (*translations), om_cmp);
529 for (i = 0; i < sz; i++) {
530 pa_base = translations[i].om_pa;
531 #ifndef __powerpc64__
532 if ((translations[i].om_pa >> 32) != 0)
533 panic("OFW translations above 32-bit boundary!");
536 if (pa_base % PAGE_SIZE)
537 panic("OFW translation not page-aligned (phys)!");
538 if (translations[i].om_va % PAGE_SIZE)
539 panic("OFW translation not page-aligned (virt)!");
541 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
542 pa_base, translations[i].om_va, translations[i].om_len);
544 /* Now enter the pages for this mapping */
547 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
548 /* If this address is direct-mapped, skip remapping */
550 translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
551 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M)
554 PMAP_LOCK(kernel_pmap);
555 pvo = moea64_pvo_find_va(kernel_pmap,
556 translations[i].om_va + off);
557 PMAP_UNLOCK(kernel_pmap);
561 moea64_kenter(mmup, translations[i].om_va + off,
570 moea64_probe_large_page(void)
572 uint16_t pvr = mfpvr() >> 16;
578 powerpc_sync(); isync();
579 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
580 powerpc_sync(); isync();
584 if (moea64_large_page_size == 0) {
585 moea64_large_page_size = 0x1000000; /* 16 MB */
586 moea64_large_page_shift = 24;
590 moea64_large_page_mask = moea64_large_page_size - 1;
594 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
601 cache = PCPU_GET(slb);
602 esid = va >> ADDR_SR_SHFT;
603 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
605 for (i = 0; i < 64; i++) {
606 if (cache[i].slbe == (slbe | i))
611 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
613 entry.slbv |= SLBV_L;
615 slb_insert_kernel(entry.slbe, entry.slbv);
620 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
621 vm_offset_t kernelend)
623 struct pvo_entry *pvo;
626 vm_offset_t size, off;
630 if (moea64_large_page_size == 0)
635 PMAP_LOCK(kernel_pmap);
636 for (i = 0; i < pregions_sz; i++) {
637 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
638 pregions[i].mr_size; pa += moea64_large_page_size) {
641 pvo = alloc_pvo_entry(1 /* bootstrap */);
642 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
643 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa));
646 * Set memory access as guarded if prefetch within
647 * the page could exit the available physmem area.
649 if (pa & moea64_large_page_mask) {
650 pa &= moea64_large_page_mask;
653 if (pa + moea64_large_page_size >
654 pregions[i].mr_start + pregions[i].mr_size)
657 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
659 pvo->pvo_pte.pa = pa | pte_lo;
660 moea64_pvo_enter(mmup, pvo, NULL);
663 PMAP_UNLOCK(kernel_pmap);
665 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
666 off = (vm_offset_t)(moea64_bpvo_pool);
667 for (pa = off; pa < off + size; pa += PAGE_SIZE)
668 moea64_kenter(mmup, pa, pa);
671 * Map certain important things, like ourselves.
673 * NOTE: We do not map the exception vector space. That code is
674 * used only in real mode, and leaving it unmapped allows us to
675 * catch NULL pointer deferences, instead of making NULL a valid
679 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
681 moea64_kenter(mmup, pa, pa);
686 * Allow user to override unmapped_buf_allowed for testing.
687 * XXXKIB Only direct map implementation was tested.
689 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
690 &unmapped_buf_allowed))
691 unmapped_buf_allowed = hw_direct_map;
695 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
698 vm_size_t physsz, hwphyssz;
700 #ifndef __powerpc64__
701 /* We don't have a direct map since there is no BAT */
704 /* Make sure battable is zero, since we have no BAT */
705 for (i = 0; i < 16; i++) {
706 battable[i].batu = 0;
707 battable[i].batl = 0;
710 moea64_probe_large_page();
712 /* Use a direct map if we have large page support */
713 if (moea64_large_page_size > 0)
718 /* Install trap handlers for SLBs */
719 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
720 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
721 __syncicache((void *)EXC_DSE, 0x80);
722 __syncicache((void *)EXC_ISE, 0x80);
725 /* Get physical memory regions from firmware */
726 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
727 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
729 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
730 panic("moea64_bootstrap: phys_avail too small");
732 phys_avail_count = 0;
735 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
736 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
737 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
738 regions[i].mr_start, regions[i].mr_start +
739 regions[i].mr_size, regions[i].mr_size);
741 (physsz + regions[i].mr_size) >= hwphyssz) {
742 if (physsz < hwphyssz) {
743 phys_avail[j] = regions[i].mr_start;
744 phys_avail[j + 1] = regions[i].mr_start +
751 phys_avail[j] = regions[i].mr_start;
752 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
754 physsz += regions[i].mr_size;
757 /* Check for overlap with the kernel and exception vectors */
758 for (j = 0; j < 2*phys_avail_count; j+=2) {
759 if (phys_avail[j] < EXC_LAST)
760 phys_avail[j] += EXC_LAST;
762 if (kernelstart >= phys_avail[j] &&
763 kernelstart < phys_avail[j+1]) {
764 if (kernelend < phys_avail[j+1]) {
765 phys_avail[2*phys_avail_count] =
766 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
767 phys_avail[2*phys_avail_count + 1] =
772 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
775 if (kernelend >= phys_avail[j] &&
776 kernelend < phys_avail[j+1]) {
777 if (kernelstart > phys_avail[j]) {
778 phys_avail[2*phys_avail_count] = phys_avail[j];
779 phys_avail[2*phys_avail_count + 1] =
780 kernelstart & ~PAGE_MASK;
784 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
788 physmem = btoc(physsz);
791 moea64_pteg_count = PTEGCOUNT;
793 moea64_pteg_count = 0x1000;
795 while (moea64_pteg_count < physmem)
796 moea64_pteg_count <<= 1;
798 moea64_pteg_count >>= 1;
799 #endif /* PTEGCOUNT */
803 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
810 moea64_pteg_mask = moea64_pteg_count - 1;
813 * Initialize SLB table lock and page locks
815 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
816 for (i = 0; i < PV_LOCK_COUNT; i++)
817 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
820 * Initialise the bootstrap pvo pool.
822 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
823 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0);
824 moea64_bpvo_pool_index = 0;
827 * Make sure kernel vsid is allocated as well as VSID 0.
829 #ifndef __powerpc64__
830 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
831 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
832 moea64_vsid_bitmap[0] |= 1;
836 * Initialize the kernel pmap (which is statically allocated).
839 for (i = 0; i < 64; i++) {
840 pcpup->pc_slb[i].slbv = 0;
841 pcpup->pc_slb[i].slbe = 0;
844 for (i = 0; i < 16; i++)
845 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
848 kernel_pmap->pmap_phys = kernel_pmap;
849 CPU_FILL(&kernel_pmap->pm_active);
850 RB_INIT(&kernel_pmap->pmap_pvo);
852 PMAP_LOCK_INIT(kernel_pmap);
855 * Now map in all the other buffers we allocated earlier
858 moea64_setup_direct_map(mmup, kernelstart, kernelend);
862 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
873 * Set up the Open Firmware pmap and add its mappings if not in real
877 chosen = OF_finddevice("/chosen");
878 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
879 mmu = OF_instance_to_package(mmui);
881 (sz = OF_getproplen(mmu, "translations")) == -1)
883 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
884 panic("moea64_bootstrap: too many ofw translations");
887 moea64_add_ofw_mappings(mmup, mmu, sz);
891 * Calculate the last available physical address.
894 for (i = 0; phys_avail[i + 2] != 0; i += 2)
895 Maxmem = max(Maxmem, powerpc_btop(phys_avail[i + 1]));
898 * Initialize MMU and remap early physical mappings
900 MMU_CPU_BOOTSTRAP(mmup,0);
901 mtmsr(mfmsr() | PSL_DR | PSL_IR);
903 bs_remap_earlyboot();
906 * Set the start and end of kva.
908 virtual_avail = VM_MIN_KERNEL_ADDRESS;
909 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
912 * Map the entire KVA range into the SLB. We must not fault there.
915 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
916 moea64_bootstrap_slb_prefault(va, 0);
920 * Figure out how far we can extend virtual_end into segment 16
921 * without running into existing mappings. Segment 16 is guaranteed
922 * to contain neither RAM nor devices (at least on Apple hardware),
923 * but will generally contain some OFW mappings we should not
927 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
928 PMAP_LOCK(kernel_pmap);
929 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
930 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
931 virtual_end += PAGE_SIZE;
932 PMAP_UNLOCK(kernel_pmap);
936 * Allocate a kernel stack with a guard page for thread0 and map it
937 * into the kernel page map.
939 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
940 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
941 virtual_avail = va + kstack_pages * PAGE_SIZE;
942 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
943 thread0.td_kstack = va;
944 thread0.td_kstack_pages = kstack_pages;
945 for (i = 0; i < kstack_pages; i++) {
946 moea64_kenter(mmup, va, pa);
952 * Allocate virtual address space for the message buffer.
954 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
955 msgbufp = (struct msgbuf *)virtual_avail;
957 virtual_avail += round_page(msgbufsize);
958 while (va < virtual_avail) {
959 moea64_kenter(mmup, va, pa);
965 * Allocate virtual address space for the dynamic percpu area.
967 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
968 dpcpu = (void *)virtual_avail;
970 virtual_avail += DPCPU_SIZE;
971 while (va < virtual_avail) {
972 moea64_kenter(mmup, va, pa);
976 dpcpu_init(dpcpu, curcpu);
979 * Allocate some things for page zeroing. We put this directly
980 * in the page table and use MOEA64_PTE_REPLACE to avoid any
981 * of the PVO book-keeping or other parts of the VM system
982 * from even knowing that this hack exists.
985 if (!hw_direct_map) {
986 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
988 for (i = 0; i < 2; i++) {
989 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
990 virtual_end -= PAGE_SIZE;
992 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
994 PMAP_LOCK(kernel_pmap);
995 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
996 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
997 PMAP_UNLOCK(kernel_pmap);
1003 moea64_pmap_init_qpages(void)
1013 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1014 if (pc->pc_qmap_addr == 0)
1015 panic("pmap_init_qpages: unable to allocate KVA");
1016 PMAP_LOCK(kernel_pmap);
1017 pc->pc_qmap_pvo = moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1018 PMAP_UNLOCK(kernel_pmap);
1019 mtx_init(&pc->pc_qmap_lock, "qmap lock", NULL, MTX_DEF);
1023 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1026 * Activate a user pmap. This mostly involves setting some non-CPU
1030 moea64_activate(mmu_t mmu, struct thread *td)
1034 pm = &td->td_proc->p_vmspace->vm_pmap;
1035 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1037 #ifdef __powerpc64__
1038 PCPU_SET(userslb, pm->pm_slb);
1039 __asm __volatile("slbmte %0, %1; isync" ::
1040 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1042 PCPU_SET(curpmap, pm->pmap_phys);
1043 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1048 moea64_deactivate(mmu_t mmu, struct thread *td)
1052 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1054 pm = &td->td_proc->p_vmspace->vm_pmap;
1055 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1056 #ifdef __powerpc64__
1057 PCPU_SET(userslb, NULL);
1059 PCPU_SET(curpmap, NULL);
1064 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1066 struct pvo_entry key, *pvo;
1070 key.pvo_vaddr = sva;
1072 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1073 pvo != NULL && PVO_VADDR(pvo) < eva;
1074 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1075 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1076 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1078 pvo->pvo_vaddr &= ~PVO_WIRED;
1079 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */);
1080 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1081 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1084 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1086 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1087 if (refchg & LPTE_CHG)
1089 if (refchg & LPTE_REF)
1090 vm_page_aflag_set(m, PGA_REFERENCED);
1092 pm->pm_stats.wired_count--;
1098 * This goes through and sets the physical address of our
1099 * special scratch PTE to the PA we want to zero or copy. Because
1100 * of locking issues (this can get called in pvo_enter() by
1101 * the UMA allocator), we can't use most other utility functions here
1105 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) {
1107 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1108 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1110 moea64_scratchpage_pvo[which]->pvo_pte.pa =
1111 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1112 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which],
1113 MOEA64_PTE_INVALIDATE);
1118 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1123 dst = VM_PAGE_TO_PHYS(mdst);
1124 src = VM_PAGE_TO_PHYS(msrc);
1126 if (hw_direct_map) {
1127 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1130 mtx_lock(&moea64_scratchpage_mtx);
1132 moea64_set_scratchpage_pa(mmu, 0, src);
1133 moea64_set_scratchpage_pa(mmu, 1, dst);
1135 bcopy((void *)moea64_scratchpage_va[0],
1136 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1138 mtx_unlock(&moea64_scratchpage_mtx);
1143 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1144 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1147 vm_offset_t a_pg_offset, b_pg_offset;
1150 while (xfersize > 0) {
1151 a_pg_offset = a_offset & PAGE_MASK;
1152 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1153 a_cp = (char *)PHYS_TO_DMAP(
1154 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1156 b_pg_offset = b_offset & PAGE_MASK;
1157 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1158 b_cp = (char *)PHYS_TO_DMAP(
1159 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1161 bcopy(a_cp, b_cp, cnt);
1169 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1170 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1173 vm_offset_t a_pg_offset, b_pg_offset;
1176 mtx_lock(&moea64_scratchpage_mtx);
1177 while (xfersize > 0) {
1178 a_pg_offset = a_offset & PAGE_MASK;
1179 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1180 moea64_set_scratchpage_pa(mmu, 0,
1181 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1182 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1183 b_pg_offset = b_offset & PAGE_MASK;
1184 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1185 moea64_set_scratchpage_pa(mmu, 1,
1186 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1187 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1188 bcopy(a_cp, b_cp, cnt);
1193 mtx_unlock(&moea64_scratchpage_mtx);
1197 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1198 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1201 if (hw_direct_map) {
1202 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1205 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1211 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1213 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1215 if (size + off > PAGE_SIZE)
1216 panic("moea64_zero_page: size + off > PAGE_SIZE");
1218 if (hw_direct_map) {
1219 bzero((caddr_t)PHYS_TO_DMAP(pa) + off, size);
1221 mtx_lock(&moea64_scratchpage_mtx);
1222 moea64_set_scratchpage_pa(mmu, 0, pa);
1223 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1224 mtx_unlock(&moea64_scratchpage_mtx);
1229 * Zero a page of physical memory by temporarily mapping it
1232 moea64_zero_page(mmu_t mmu, vm_page_t m)
1234 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1235 vm_offset_t va, off;
1237 if (!hw_direct_map) {
1238 mtx_lock(&moea64_scratchpage_mtx);
1240 moea64_set_scratchpage_pa(mmu, 0, pa);
1241 va = moea64_scratchpage_va[0];
1243 va = PHYS_TO_DMAP(pa);
1246 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1247 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1250 mtx_unlock(&moea64_scratchpage_mtx);
1254 moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
1256 struct pvo_entry *pvo;
1257 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1260 return (PHYS_TO_DMAP(pa));
1263 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1264 * a critical section and access the PCPU data like on i386.
1265 * Instead, pin the thread and grab the PCPU lock to prevent
1266 * a preempting thread from using the same PCPU data.
1270 mtx_assert(PCPU_PTR(qmap_lock), MA_NOTOWNED);
1271 pvo = PCPU_GET(qmap_pvo);
1273 mtx_lock(PCPU_PTR(qmap_lock));
1274 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1276 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
1279 return (PCPU_GET(qmap_addr));
1283 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1288 mtx_assert(PCPU_PTR(qmap_lock), MA_OWNED);
1289 KASSERT(PCPU_GET(qmap_addr) == addr,
1290 ("moea64_quick_remove_page: invalid address"));
1291 mtx_unlock(PCPU_PTR(qmap_lock));
1296 * Map the given physical page at the specified virtual address in the
1297 * target pmap with the protection requested. If specified the page
1298 * will be wired down.
1302 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1303 vm_prot_t prot, u_int flags, int8_t psind)
1305 struct pvo_entry *pvo, *oldpvo;
1306 struct pvo_head *pvo_head;
1310 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1311 VM_OBJECT_ASSERT_LOCKED(m->object);
1313 pvo = alloc_pvo_entry(0);
1314 pvo->pvo_pmap = NULL; /* to be filled in later */
1315 pvo->pvo_pte.prot = prot;
1317 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1318 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo;
1320 if ((flags & PMAP_ENTER_WIRED) != 0)
1321 pvo->pvo_vaddr |= PVO_WIRED;
1323 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1326 pvo_head = &m->md.mdpg_pvoh;
1327 pvo->pvo_vaddr |= PVO_MANAGED;
1333 if (pvo->pvo_pmap == NULL)
1334 init_pvo_entry(pvo, pmap, va);
1335 if (prot & VM_PROT_WRITE)
1336 if (pmap_bootstrapped &&
1337 (m->oflags & VPO_UNMANAGED) == 0)
1338 vm_page_aflag_set(m, PGA_WRITEABLE);
1340 oldpvo = moea64_pvo_find_va(pmap, va);
1341 if (oldpvo != NULL) {
1342 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1343 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1344 oldpvo->pvo_pte.prot == prot) {
1345 /* Identical mapping already exists */
1348 /* If not in page table, reinsert it */
1349 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) {
1350 moea64_pte_overflow--;
1351 MOEA64_PTE_INSERT(mmu, oldpvo);
1354 /* Then just clean up and go home */
1357 free_pvo_entry(pvo);
1361 /* Otherwise, need to kill it first */
1362 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1363 "mapping does not match new mapping"));
1364 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1366 error = moea64_pvo_enter(mmu, pvo, pvo_head);
1370 /* Free any dead pages */
1371 if (oldpvo != NULL) {
1372 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1373 moea64_pvo_remove_from_page(mmu, oldpvo);
1374 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1375 free_pvo_entry(oldpvo);
1378 if (error != ENOMEM)
1380 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1381 return (KERN_RESOURCE_SHORTAGE);
1382 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1387 * Flush the page from the instruction cache if this page is
1388 * mapped executable and cacheable.
1390 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1391 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1392 vm_page_aflag_set(m, PGA_EXECUTABLE);
1393 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1395 return (KERN_SUCCESS);
1399 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1404 * This is much trickier than on older systems because
1405 * we can't sync the icache on physical addresses directly
1406 * without a direct map. Instead we check a couple of cases
1407 * where the memory is already mapped in and, failing that,
1408 * use the same trick we use for page zeroing to create
1409 * a temporary mapping for this physical address.
1412 if (!pmap_bootstrapped) {
1414 * If PMAP is not bootstrapped, we are likely to be
1417 __syncicache((void *)pa, sz);
1418 } else if (pmap == kernel_pmap) {
1419 __syncicache((void *)va, sz);
1420 } else if (hw_direct_map) {
1421 __syncicache((void *)PHYS_TO_DMAP(pa), sz);
1423 /* Use the scratch page to set up a temp mapping */
1425 mtx_lock(&moea64_scratchpage_mtx);
1427 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1428 __syncicache((void *)(moea64_scratchpage_va[1] +
1429 (va & ADDR_POFF)), sz);
1431 mtx_unlock(&moea64_scratchpage_mtx);
1436 * Maps a sequence of resident pages belonging to the same object.
1437 * The sequence begins with the given page m_start. This page is
1438 * mapped at the given virtual address start. Each subsequent page is
1439 * mapped at a virtual address that is offset from start by the same
1440 * amount as the page is offset from m_start within the object. The
1441 * last page in the sequence is the page with the largest offset from
1442 * m_start that can be mapped at a virtual address less than the given
1443 * virtual address end. Not every virtual page between start and end
1444 * is mapped; only those for which a resident page exists with the
1445 * corresponding offset from m_start are mapped.
1448 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1449 vm_page_t m_start, vm_prot_t prot)
1452 vm_pindex_t diff, psize;
1454 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1456 psize = atop(end - start);
1458 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1459 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1460 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0);
1461 m = TAILQ_NEXT(m, listq);
1466 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1470 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1471 PMAP_ENTER_NOSLEEP, 0);
1475 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1477 struct pvo_entry *pvo;
1481 pvo = moea64_pvo_find_va(pm, va);
1485 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1492 * Atomically extract and hold the physical page with the given
1493 * pmap and virtual address pair if that mapping permits the given
1497 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1499 struct pvo_entry *pvo;
1507 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1508 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1509 if (vm_page_pa_tryrelock(pmap,
1510 pvo->pvo_pte.pa & LPTE_RPGN, &pa))
1512 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1520 static mmu_t installed_mmu;
1523 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1524 uint8_t *flags, int wait)
1526 struct pvo_entry *pvo;
1532 * This entire routine is a horrible hack to avoid bothering kmem
1533 * for new KVA addresses. Because this can get called from inside
1534 * kmem allocation routines, calling kmem for a new address here
1535 * can lead to multiply locking non-recursive mutexes.
1538 *flags = UMA_SLAB_PRIV;
1539 needed_lock = !PMAP_LOCKED(kernel_pmap);
1541 m = vm_page_alloc_domain(NULL, 0, domain,
1542 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ);
1546 va = VM_PAGE_TO_PHYS(m);
1548 pvo = alloc_pvo_entry(1 /* bootstrap */);
1550 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1551 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1554 PMAP_LOCK(kernel_pmap);
1556 init_pvo_entry(pvo, kernel_pmap, va);
1557 pvo->pvo_vaddr |= PVO_WIRED;
1559 moea64_pvo_enter(installed_mmu, pvo, NULL);
1562 PMAP_UNLOCK(kernel_pmap);
1564 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1565 bzero((void *)va, PAGE_SIZE);
1570 extern int elf32_nxstack;
1573 moea64_init(mmu_t mmu)
1576 CTR0(KTR_PMAP, "moea64_init");
1578 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1579 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1580 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1582 if (!hw_direct_map) {
1583 installed_mmu = mmu;
1584 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1587 #ifdef COMPAT_FREEBSD32
1591 moea64_initialized = TRUE;
1595 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1598 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1599 ("moea64_is_referenced: page %p is not managed", m));
1601 return (moea64_query_bit(mmu, m, LPTE_REF));
1605 moea64_is_modified(mmu_t mmu, vm_page_t m)
1608 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1609 ("moea64_is_modified: page %p is not managed", m));
1612 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1613 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1614 * is clear, no PTEs can have LPTE_CHG set.
1616 VM_OBJECT_ASSERT_LOCKED(m->object);
1617 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1619 return (moea64_query_bit(mmu, m, LPTE_CHG));
1623 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1625 struct pvo_entry *pvo;
1626 boolean_t rv = TRUE;
1629 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1637 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1640 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1641 ("moea64_clear_modify: page %p is not managed", m));
1642 VM_OBJECT_ASSERT_WLOCKED(m->object);
1643 KASSERT(!vm_page_xbusied(m),
1644 ("moea64_clear_modify: page %p is exclusive busied", m));
1647 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1648 * set. If the object containing the page is locked and the page is
1649 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1651 if ((m->aflags & PGA_WRITEABLE) == 0)
1653 moea64_clear_bit(mmu, m, LPTE_CHG);
1657 * Clear the write and modified bits in each of the given page's mappings.
1660 moea64_remove_write(mmu_t mmu, vm_page_t m)
1662 struct pvo_entry *pvo;
1663 int64_t refchg, ret;
1666 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1667 ("moea64_remove_write: page %p is not managed", m));
1670 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1671 * set by another thread while the object is locked. Thus,
1672 * if PGA_WRITEABLE is clear, no page table entries need updating.
1674 VM_OBJECT_ASSERT_WLOCKED(m->object);
1675 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1680 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1681 pmap = pvo->pvo_pmap;
1683 if (!(pvo->pvo_vaddr & PVO_DEAD) &&
1684 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1685 pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
1686 ret = MOEA64_PTE_REPLACE(mmu, pvo,
1687 MOEA64_PTE_PROT_UPDATE);
1691 if (pvo->pvo_pmap == kernel_pmap)
1696 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
1698 vm_page_aflag_clear(m, PGA_WRITEABLE);
1703 * moea64_ts_referenced:
1705 * Return a count of reference bits for a page, clearing those bits.
1706 * It is not necessary for every reference bit to be cleared, but it
1707 * is necessary that 0 only be returned when there are truly no
1708 * reference bits set.
1710 * XXX: The exact number of bits to check and clear is a matter that
1711 * should be tested and standardized at some point in the future for
1712 * optimal aging of shared pages.
1715 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1718 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1719 ("moea64_ts_referenced: page %p is not managed", m));
1720 return (moea64_clear_bit(mmu, m, LPTE_REF));
1724 * Modify the WIMG settings of all mappings for a page.
1727 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1729 struct pvo_entry *pvo;
1734 if ((m->oflags & VPO_UNMANAGED) != 0) {
1735 m->md.mdpg_cache_attrs = ma;
1739 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1742 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1743 pmap = pvo->pvo_pmap;
1745 if (!(pvo->pvo_vaddr & PVO_DEAD)) {
1746 pvo->pvo_pte.pa &= ~LPTE_WIMG;
1747 pvo->pvo_pte.pa |= lo;
1748 refchg = MOEA64_PTE_REPLACE(mmu, pvo,
1749 MOEA64_PTE_INVALIDATE);
1751 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
1753 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1754 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1756 atomic_readandclear_32(&m->md.mdpg_attrs);
1757 if (refchg & LPTE_CHG)
1759 if (refchg & LPTE_REF)
1760 vm_page_aflag_set(m, PGA_REFERENCED);
1762 if (pvo->pvo_pmap == kernel_pmap)
1767 m->md.mdpg_cache_attrs = ma;
1772 * Map a wired page into kernel virtual address space.
1775 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1778 struct pvo_entry *pvo, *oldpvo;
1780 pvo = alloc_pvo_entry(0);
1781 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
1782 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
1783 pvo->pvo_vaddr |= PVO_WIRED;
1785 PMAP_LOCK(kernel_pmap);
1786 oldpvo = moea64_pvo_find_va(kernel_pmap, va);
1788 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1789 init_pvo_entry(pvo, kernel_pmap, va);
1790 error = moea64_pvo_enter(mmu, pvo, NULL);
1791 PMAP_UNLOCK(kernel_pmap);
1793 /* Free any dead pages */
1794 if (oldpvo != NULL) {
1795 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1796 moea64_pvo_remove_from_page(mmu, oldpvo);
1797 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1798 free_pvo_entry(oldpvo);
1801 if (error != 0 && error != ENOENT)
1802 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1807 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1810 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1814 * Extract the physical page address associated with the given kernel virtual
1818 moea64_kextract(mmu_t mmu, vm_offset_t va)
1820 struct pvo_entry *pvo;
1824 * Shortcut the direct-mapped case when applicable. We never put
1825 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1827 if (va < VM_MIN_KERNEL_ADDRESS)
1830 PMAP_LOCK(kernel_pmap);
1831 pvo = moea64_pvo_find_va(kernel_pmap, va);
1832 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1834 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1835 PMAP_UNLOCK(kernel_pmap);
1840 * Remove a wired page from kernel virtual address space.
1843 moea64_kremove(mmu_t mmu, vm_offset_t va)
1845 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1849 * Provide a kernel pointer corresponding to a given userland pointer.
1850 * The returned pointer is valid until the next time this function is
1851 * called in this thread. This is used internally in copyin/copyout.
1854 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1855 void **kaddr, size_t ulen, size_t *klen)
1858 #ifdef __powerpc64__
1863 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1864 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1872 #ifdef __powerpc64__
1873 /* Try lockless look-up first */
1874 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
1877 /* If it isn't there, we need to pre-fault the VSID */
1879 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
1885 /* Mark segment no-execute */
1888 slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
1890 /* Mark segment no-execute */
1894 /* If we have already set this VSID, we can just return */
1895 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
1898 __asm __volatile("isync");
1899 curthread->td_pcb->pcb_cpu.aim.usr_segm =
1900 (uintptr_t)uaddr >> ADDR_SR_SHFT;
1901 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
1902 #ifdef __powerpc64__
1903 __asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
1904 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
1906 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
1913 * Map a range of physical addresses into kernel virtual address space.
1915 * The value passed in *virt is a suggested virtual address for the mapping.
1916 * Architectures which can support a direct-mapped physical to virtual region
1917 * can return the appropriate address within that region, leaving '*virt'
1918 * unchanged. Other architectures should map the pages starting at '*virt' and
1919 * update '*virt' with the first usable address after the mapped region.
1922 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1923 vm_paddr_t pa_end, int prot)
1925 vm_offset_t sva, va;
1927 if (hw_direct_map) {
1929 * Check if every page in the region is covered by the direct
1930 * map. The direct map covers all of physical memory. Use
1931 * moea64_calc_wimg() as a shortcut to see if the page is in
1932 * physical memory as a way to see if the direct map covers it.
1934 for (va = pa_start; va < pa_end; va += PAGE_SIZE)
1935 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
1938 return (PHYS_TO_DMAP(pa_start));
1942 /* XXX respect prot argument */
1943 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1944 moea64_kenter(mmu, va, pa_start);
1951 * Returns true if the pmap's pv is one of the first
1952 * 16 pvs linked to from this page. This count may
1953 * be changed upwards or downwards in the future; it
1954 * is only necessary that true be returned for a small
1955 * subset of pmaps for proper page aging.
1958 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1961 struct pvo_entry *pvo;
1964 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1965 ("moea64_page_exists_quick: page %p is not managed", m));
1969 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1970 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
1982 moea64_page_init(mmu_t mmu __unused, vm_page_t m)
1985 m->md.mdpg_attrs = 0;
1986 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
1987 LIST_INIT(&m->md.mdpg_pvoh);
1991 * Return the number of managed mappings to the given physical page
1995 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1997 struct pvo_entry *pvo;
2001 if ((m->oflags & VPO_UNMANAGED) != 0)
2004 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
2005 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2011 static uintptr_t moea64_vsidcontext;
2014 moea64_get_unique_vsid(void) {
2021 __asm __volatile("mftb %0" : "=r"(entropy));
2023 mtx_lock(&moea64_slb_mutex);
2024 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2028 * Create a new value by mutiplying by a prime and adding in
2029 * entropy from the timebase register. This is to make the
2030 * VSID more random so that the PT hash function collides
2031 * less often. (Note that the prime casues gcc to do shifts
2032 * instead of a multiply.)
2034 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2035 hash = moea64_vsidcontext & (NVSIDS - 1);
2036 if (hash == 0) /* 0 is special, avoid it */
2039 mask = 1 << (hash & (VSID_NBPW - 1));
2040 hash = (moea64_vsidcontext & VSID_HASHMASK);
2041 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
2042 /* anything free in this bucket? */
2043 if (moea64_vsid_bitmap[n] == 0xffffffff) {
2044 entropy = (moea64_vsidcontext >> 20);
2047 i = ffs(~moea64_vsid_bitmap[n]) - 1;
2049 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2052 if (hash == VSID_VRMA) /* also special, avoid this too */
2054 KASSERT(!(moea64_vsid_bitmap[n] & mask),
2055 ("Allocating in-use VSID %#zx\n", hash));
2056 moea64_vsid_bitmap[n] |= mask;
2057 mtx_unlock(&moea64_slb_mutex);
2061 mtx_unlock(&moea64_slb_mutex);
2062 panic("%s: out of segments",__func__);
2065 #ifdef __powerpc64__
2067 moea64_pinit(mmu_t mmu, pmap_t pmap)
2070 RB_INIT(&pmap->pmap_pvo);
2072 pmap->pm_slb_tree_root = slb_alloc_tree();
2073 pmap->pm_slb = slb_alloc_user_cache();
2074 pmap->pm_slb_len = 0;
2078 moea64_pinit(mmu_t mmu, pmap_t pmap)
2083 RB_INIT(&pmap->pmap_pvo);
2085 if (pmap_bootstrapped)
2086 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
2089 pmap->pmap_phys = pmap;
2092 * Allocate some segment registers for this pmap.
2094 hash = moea64_get_unique_vsid();
2096 for (i = 0; i < 16; i++)
2097 pmap->pm_sr[i] = VSID_MAKE(i, hash);
2099 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2104 * Initialize the pmap associated with process 0.
2107 moea64_pinit0(mmu_t mmu, pmap_t pm)
2111 moea64_pinit(mmu, pm);
2112 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2116 * Set the physical protection on the specified range of this map as requested.
2119 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2125 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2128 * Change the protection of the page.
2130 oldprot = pvo->pvo_pte.prot;
2131 pvo->pvo_pte.prot = prot;
2132 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2135 * If the PVO is in the page table, update mapping
2137 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE);
2139 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2141 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2142 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2143 if ((pg->oflags & VPO_UNMANAGED) == 0)
2144 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2145 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2146 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE);
2150 * Update vm about the REF/CHG bits if the page is managed and we have
2151 * removed write access.
2153 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2154 (oldprot & VM_PROT_WRITE)) {
2155 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2156 if (refchg & LPTE_CHG)
2158 if (refchg & LPTE_REF)
2159 vm_page_aflag_set(pg, PGA_REFERENCED);
2164 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2167 struct pvo_entry *pvo, *tpvo, key;
2169 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2172 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2173 ("moea64_protect: non current pmap"));
2175 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2176 moea64_remove(mmu, pm, sva, eva);
2181 key.pvo_vaddr = sva;
2182 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2183 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2184 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2185 moea64_pvo_protect(mmu, pm, pvo, prot);
2191 * Map a list of wired pages into kernel virtual address space. This is
2192 * intended for temporary mappings which do not need page modification or
2193 * references recorded. Existing mappings in the region are overwritten.
2196 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2198 while (count-- > 0) {
2199 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2206 * Remove page mappings from kernel virtual address space. Intended for
2207 * temporary mappings entered by moea64_qenter.
2210 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2212 while (count-- > 0) {
2213 moea64_kremove(mmu, va);
2219 moea64_release_vsid(uint64_t vsid)
2223 mtx_lock(&moea64_slb_mutex);
2224 idx = vsid & (NVSIDS-1);
2225 mask = 1 << (idx % VSID_NBPW);
2227 KASSERT(moea64_vsid_bitmap[idx] & mask,
2228 ("Freeing unallocated VSID %#jx", vsid));
2229 moea64_vsid_bitmap[idx] &= ~mask;
2230 mtx_unlock(&moea64_slb_mutex);
2235 moea64_release(mmu_t mmu, pmap_t pmap)
2239 * Free segment registers' VSIDs
2241 #ifdef __powerpc64__
2242 slb_free_tree(pmap);
2243 slb_free_user_cache(pmap->pm_slb);
2245 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2247 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2252 * Remove all pages mapped by the specified pmap
2255 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2257 struct pvo_entry *pvo, *tpvo;
2258 struct pvo_tree tofree;
2263 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2264 if (pvo->pvo_vaddr & PVO_WIRED)
2268 * For locking reasons, remove this from the page table and
2269 * pmap, but save delinking from the vm_page for a second
2272 moea64_pvo_remove_from_pmap(mmu, pvo);
2273 RB_INSERT(pvo_tree, &tofree, pvo);
2277 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2278 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2279 moea64_pvo_remove_from_page(mmu, pvo);
2280 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2281 RB_REMOVE(pvo_tree, &tofree, pvo);
2282 free_pvo_entry(pvo);
2287 * Remove the given range of addresses from the specified map.
2290 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2292 struct pvo_entry *pvo, *tpvo, key;
2293 struct pvo_tree tofree;
2296 * Perform an unsynchronized read. This is, however, safe.
2298 if (pm->pm_stats.resident_count == 0)
2301 key.pvo_vaddr = sva;
2306 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2307 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2308 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2311 * For locking reasons, remove this from the page table and
2312 * pmap, but save delinking from the vm_page for a second
2315 moea64_pvo_remove_from_pmap(mmu, pvo);
2316 RB_INSERT(pvo_tree, &tofree, pvo);
2320 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2321 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2322 moea64_pvo_remove_from_page(mmu, pvo);
2323 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2324 RB_REMOVE(pvo_tree, &tofree, pvo);
2325 free_pvo_entry(pvo);
2330 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2331 * will reflect changes in pte's back to the vm_page.
2334 moea64_remove_all(mmu_t mmu, vm_page_t m)
2336 struct pvo_entry *pvo, *next_pvo;
2337 struct pvo_head freequeue;
2341 LIST_INIT(&freequeue);
2344 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2345 pmap = pvo->pvo_pmap;
2347 wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2349 moea64_pvo_remove_from_pmap(mmu, pvo);
2350 moea64_pvo_remove_from_page(mmu, pvo);
2352 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2356 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2357 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable"));
2360 /* Clean up UMA allocations */
2361 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2362 free_pvo_entry(pvo);
2366 * Allocate a physical page of memory directly from the phys_avail map.
2367 * Can only be called from moea64_bootstrap before avail start and end are
2371 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2376 size = round_page(size);
2377 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2379 s = roundup2(phys_avail[i], align);
2384 if (s < phys_avail[i] || e > phys_avail[i + 1])
2387 if (s + size > platform_real_maxaddr())
2390 if (s == phys_avail[i]) {
2391 phys_avail[i] += size;
2392 } else if (e == phys_avail[i + 1]) {
2393 phys_avail[i + 1] -= size;
2395 for (j = phys_avail_count * 2; j > i; j -= 2) {
2396 phys_avail[j] = phys_avail[j - 2];
2397 phys_avail[j + 1] = phys_avail[j - 1];
2400 phys_avail[i + 3] = phys_avail[i + 1];
2401 phys_avail[i + 1] = s;
2402 phys_avail[i + 2] = e;
2408 panic("moea64_bootstrap_alloc: could not allocate memory");
2412 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head)
2416 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2417 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL,
2418 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo)));
2420 moea64_pvo_enter_calls++;
2425 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2428 * Remember if the list was empty and therefore will be the first
2431 if (pvo_head != NULL) {
2432 if (LIST_FIRST(pvo_head) == NULL)
2434 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2437 if (pvo->pvo_vaddr & PVO_WIRED)
2438 pvo->pvo_pmap->pm_stats.wired_count++;
2439 pvo->pvo_pmap->pm_stats.resident_count++;
2442 * Insert it into the hardware page table
2444 err = MOEA64_PTE_INSERT(mmu, pvo);
2446 panic("moea64_pvo_enter: overflow");
2449 moea64_pvo_entries++;
2451 if (pvo->pvo_pmap == kernel_pmap)
2454 #ifdef __powerpc64__
2456 * Make sure all our bootstrap mappings are in the SLB as soon
2457 * as virtual memory is switched on.
2459 if (!pmap_bootstrapped)
2460 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2461 pvo->pvo_vaddr & PVO_LARGE);
2464 return (first ? ENOENT : 0);
2468 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo)
2473 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2474 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2475 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2478 * If there is an active pte entry, we need to deactivate it
2480 refchg = MOEA64_PTE_UNSET(mmu, pvo);
2483 * If it was evicted from the page table, be pessimistic and
2486 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2493 * Update our statistics.
2495 pvo->pvo_pmap->pm_stats.resident_count--;
2496 if (pvo->pvo_vaddr & PVO_WIRED)
2497 pvo->pvo_pmap->pm_stats.wired_count--;
2500 * Remove this PVO from the pmap list.
2502 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2505 * Mark this for the next sweep
2507 pvo->pvo_vaddr |= PVO_DEAD;
2509 /* Send RC bits to VM */
2510 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2511 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2512 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2514 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2515 if (refchg & LPTE_CHG)
2517 if (refchg & LPTE_REF)
2518 vm_page_aflag_set(pg, PGA_REFERENCED);
2524 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo)
2528 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
2530 /* Use NULL pmaps as a sentinel for races in page deletion */
2531 if (pvo->pvo_pmap == NULL)
2533 pvo->pvo_pmap = NULL;
2536 * Update vm about page writeability/executability if managed
2538 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN);
2539 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2541 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) {
2542 LIST_REMOVE(pvo, pvo_vlink);
2543 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2544 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE);
2547 moea64_pvo_entries--;
2548 moea64_pvo_remove_calls++;
2551 static struct pvo_entry *
2552 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2554 struct pvo_entry key;
2556 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2558 key.pvo_vaddr = va & ~ADDR_POFF;
2559 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2563 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit)
2565 struct pvo_entry *pvo;
2570 * See if this bit is stored in the page already.
2572 if (m->md.mdpg_attrs & ptebit)
2576 * Examine each PTE. Sync so that any pending REF/CHG bits are
2577 * flushed to the PTEs.
2582 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2586 * See if this pvo has a valid PTE. if so, fetch the
2587 * REF/CHG bits from the valid PTE. If the appropriate
2588 * ptebit is set, return success.
2590 PMAP_LOCK(pvo->pvo_pmap);
2591 if (!(pvo->pvo_vaddr & PVO_DEAD))
2592 ret = MOEA64_PTE_SYNCH(mmu, pvo);
2593 PMAP_UNLOCK(pvo->pvo_pmap);
2596 atomic_set_32(&m->md.mdpg_attrs,
2597 ret & (LPTE_CHG | LPTE_REF));
2610 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2613 struct pvo_entry *pvo;
2617 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2618 * we can reset the right ones).
2623 * For each pvo entry, clear the pte's ptebit.
2627 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2630 PMAP_LOCK(pvo->pvo_pmap);
2631 if (!(pvo->pvo_vaddr & PVO_DEAD))
2632 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit);
2633 PMAP_UNLOCK(pvo->pvo_pmap);
2635 if (ret > 0 && (ret & ptebit))
2638 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
2645 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2647 struct pvo_entry *pvo, key;
2651 PMAP_LOCK(kernel_pmap);
2652 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2653 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2654 ppa < pa + size; ppa += PAGE_SIZE,
2655 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2656 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) {
2661 PMAP_UNLOCK(kernel_pmap);
2667 * Map a set of physical memory pages into the kernel virtual
2668 * address space. Return a pointer to where it is mapped. This
2669 * routine is intended to be used for mapping device memory,
2673 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2675 vm_offset_t va, tmpva, ppa, offset;
2677 ppa = trunc_page(pa);
2678 offset = pa & PAGE_MASK;
2679 size = roundup2(offset + size, PAGE_SIZE);
2681 va = kva_alloc(size);
2684 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2686 for (tmpva = va; size > 0;) {
2687 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2693 return ((void *)(va + offset));
2697 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2700 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2704 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2706 vm_offset_t base, offset;
2708 base = trunc_page(va);
2709 offset = va & PAGE_MASK;
2710 size = roundup2(offset + size, PAGE_SIZE);
2712 kva_free(base, size);
2716 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2718 struct pvo_entry *pvo;
2725 lim = round_page(va);
2726 len = MIN(lim - va, sz);
2727 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2728 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
2729 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF);
2730 moea64_syncicache(mmu, pm, va, pa, len);
2739 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2745 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2748 moea64_scan_init(mmu_t mmu)
2750 struct pvo_entry *pvo;
2755 /* Initialize phys. segments for dumpsys(). */
2756 memset(&dump_map, 0, sizeof(dump_map));
2757 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2758 for (i = 0; i < pregions_sz; i++) {
2759 dump_map[i].pa_start = pregions[i].mr_start;
2760 dump_map[i].pa_size = pregions[i].mr_size;
2765 /* Virtual segments for minidumps: */
2766 memset(&dump_map, 0, sizeof(dump_map));
2768 /* 1st: kernel .data and .bss. */
2769 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2770 dump_map[0].pa_size = round_page((uintptr_t)_end) -
2771 dump_map[0].pa_start;
2773 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2774 dump_map[1].pa_start = (vm_paddr_t)msgbufp->msg_ptr;
2775 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2777 /* 3rd: kernel VM. */
2778 va = dump_map[1].pa_start + dump_map[1].pa_size;
2779 /* Find start of next chunk (from va). */
2780 while (va < virtual_end) {
2781 /* Don't dump the buffer cache. */
2782 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2783 va = kmi.buffer_eva;
2786 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2787 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2791 if (va < virtual_end) {
2792 dump_map[2].pa_start = va;
2794 /* Find last page in chunk. */
2795 while (va < virtual_end) {
2796 /* Don't run into the buffer cache. */
2797 if (va == kmi.buffer_sva)
2799 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2800 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2804 dump_map[2].pa_size = va - dump_map[2].pa_start;