2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008-2015 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
33 * Manages physical address maps.
35 * Since the information managed by this module is also stored by the
36 * logical address mapping module, this module may throw away valid virtual
37 * to physical mappings at almost any time. However, invalidations of
38 * mappings must be done as requested.
40 * In order to cope with hardware architectures which make virtual to
41 * physical map invalidates expensive, this module may delay invalidate
42 * reduced protection operations until such time as they are actually
43 * necessary. This module is given full information as to which processors
44 * are currently using which maps, and to when physical maps must be made
48 #include "opt_compat.h"
49 #include "opt_kstack_pages.h"
51 #include <sys/param.h>
52 #include <sys/kernel.h>
54 #include <sys/queue.h>
55 #include <sys/cpuset.h>
56 #include <sys/kerneldump.h>
59 #include <sys/msgbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/mutex.h>
63 #include <sys/rwlock.h>
64 #include <sys/sched.h>
65 #include <sys/sysctl.h>
66 #include <sys/systm.h>
67 #include <sys/vmmeter.h>
72 #include <dev/ofw/openfirm.h>
75 #include <vm/vm_param.h>
76 #include <vm/vm_kern.h>
77 #include <vm/vm_page.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_object.h>
80 #include <vm/vm_extern.h>
81 #include <vm/vm_pageout.h>
84 #include <machine/_inttypes.h>
85 #include <machine/cpu.h>
86 #include <machine/platform.h>
87 #include <machine/frame.h>
88 #include <machine/md_var.h>
89 #include <machine/psl.h>
90 #include <machine/bat.h>
91 #include <machine/hid.h>
92 #include <machine/pte.h>
93 #include <machine/sr.h>
94 #include <machine/trap.h>
95 #include <machine/mmuvar.h>
97 #include "mmu_oea64.h"
99 #include "moea64_if.h"
101 void moea64_release_vsid(uint64_t vsid);
102 uintptr_t moea64_get_unique_vsid(void);
104 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
105 #define ENABLE_TRANS(msr) mtmsr(msr)
107 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
108 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
109 #define VSID_HASH_MASK 0x0000007fffffffffULL
114 * There are two locks of interest: the page locks and the pmap locks, which
115 * protect their individual PVO lists and are locked in that order. The contents
116 * of all PVO entries are protected by the locks of their respective pmaps.
117 * The pmap of any PVO is guaranteed not to change so long as the PVO is linked
122 #define PV_LOCK_COUNT PA_LOCK_COUNT*3
123 static struct mtx_padalign pv_lock[PV_LOCK_COUNT];
125 #define PV_LOCKPTR(pa) ((struct mtx *)(&pv_lock[pa_index(pa) % PV_LOCK_COUNT]))
126 #define PV_LOCK(pa) mtx_lock(PV_LOCKPTR(pa))
127 #define PV_UNLOCK(pa) mtx_unlock(PV_LOCKPTR(pa))
128 #define PV_LOCKASSERT(pa) mtx_assert(PV_LOCKPTR(pa), MA_OWNED)
129 #define PV_PAGE_LOCK(m) PV_LOCK(VM_PAGE_TO_PHYS(m))
130 #define PV_PAGE_UNLOCK(m) PV_UNLOCK(VM_PAGE_TO_PHYS(m))
131 #define PV_PAGE_LOCKASSERT(m) PV_LOCKASSERT(VM_PAGE_TO_PHYS(m))
140 extern unsigned char _etext[];
141 extern unsigned char _end[];
143 extern void *slbtrap, *slbtrapend;
146 * Map of physical memory regions.
148 static struct mem_region *regions;
149 static struct mem_region *pregions;
150 static u_int phys_avail_count;
151 static int regions_sz, pregions_sz;
153 extern void bs_remap_earlyboot(void);
156 * Lock for the SLB tables.
158 struct mtx moea64_slb_mutex;
163 u_int moea64_pteg_count;
164 u_int moea64_pteg_mask;
170 uma_zone_t moea64_pvo_zone; /* zone for pvo entries */
172 static struct pvo_entry *moea64_bpvo_pool;
173 static int moea64_bpvo_pool_index = 0;
174 static int moea64_bpvo_pool_size = 327680;
175 TUNABLE_INT("machdep.moea64_bpvo_pool_size", &moea64_bpvo_pool_size);
176 SYSCTL_INT(_machdep, OID_AUTO, moea64_allocated_bpvo_entries, CTLFLAG_RD,
177 &moea64_bpvo_pool_index, 0, "");
179 #define VSID_NBPW (sizeof(u_int32_t) * 8)
181 #define NVSIDS (NPMAPS * 16)
182 #define VSID_HASHMASK 0xffffffffUL
184 #define NVSIDS NPMAPS
185 #define VSID_HASHMASK 0xfffffUL
187 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
189 static boolean_t moea64_initialized = FALSE;
194 u_int moea64_pte_valid = 0;
195 u_int moea64_pte_overflow = 0;
196 u_int moea64_pvo_entries = 0;
197 u_int moea64_pvo_enter_calls = 0;
198 u_int moea64_pvo_remove_calls = 0;
199 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
200 &moea64_pte_valid, 0, "");
201 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
202 &moea64_pte_overflow, 0, "");
203 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
204 &moea64_pvo_entries, 0, "");
205 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
206 &moea64_pvo_enter_calls, 0, "");
207 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
208 &moea64_pvo_remove_calls, 0, "");
210 vm_offset_t moea64_scratchpage_va[2];
211 struct pvo_entry *moea64_scratchpage_pvo[2];
212 struct mtx moea64_scratchpage_mtx;
214 uint64_t moea64_large_page_mask = 0;
215 uint64_t moea64_large_page_size = 0;
216 int moea64_large_page_shift = 0;
221 static int moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo,
222 struct pvo_head *pvo_head);
223 static void moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo);
224 static void moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo);
225 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
230 static boolean_t moea64_query_bit(mmu_t, vm_page_t, uint64_t);
231 static u_int moea64_clear_bit(mmu_t, vm_page_t, uint64_t);
232 static void moea64_kremove(mmu_t, vm_offset_t);
233 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
234 vm_paddr_t pa, vm_size_t sz);
235 static void moea64_pmap_init_qpages(void);
238 * Kernel MMU interface
240 void moea64_clear_modify(mmu_t, vm_page_t);
241 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
242 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
243 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
244 int moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t,
245 u_int flags, int8_t psind);
246 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
248 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
249 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
250 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
251 void moea64_init(mmu_t);
252 boolean_t moea64_is_modified(mmu_t, vm_page_t);
253 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
254 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
255 int moea64_ts_referenced(mmu_t, vm_page_t);
256 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
257 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
258 void moea64_page_init(mmu_t, vm_page_t);
259 int moea64_page_wired_mappings(mmu_t, vm_page_t);
260 void moea64_pinit(mmu_t, pmap_t);
261 void moea64_pinit0(mmu_t, pmap_t);
262 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
263 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
264 void moea64_qremove(mmu_t, vm_offset_t, int);
265 void moea64_release(mmu_t, pmap_t);
266 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
267 void moea64_remove_pages(mmu_t, pmap_t);
268 void moea64_remove_all(mmu_t, vm_page_t);
269 void moea64_remove_write(mmu_t, vm_page_t);
270 void moea64_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
271 void moea64_zero_page(mmu_t, vm_page_t);
272 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
273 void moea64_activate(mmu_t, struct thread *);
274 void moea64_deactivate(mmu_t, struct thread *);
275 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
276 void *moea64_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
277 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
278 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
279 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
280 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t ma);
281 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
282 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
283 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
284 void moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz,
286 void moea64_scan_init(mmu_t mmu);
287 vm_offset_t moea64_quick_enter_page(mmu_t mmu, vm_page_t m);
288 void moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr);
289 static int moea64_map_user_ptr(mmu_t mmu, pmap_t pm,
290 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
291 static int moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
292 int *is_user, vm_offset_t *decoded_addr);
295 static mmu_method_t moea64_methods[] = {
296 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
297 MMUMETHOD(mmu_copy_page, moea64_copy_page),
298 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
299 MMUMETHOD(mmu_enter, moea64_enter),
300 MMUMETHOD(mmu_enter_object, moea64_enter_object),
301 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
302 MMUMETHOD(mmu_extract, moea64_extract),
303 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
304 MMUMETHOD(mmu_init, moea64_init),
305 MMUMETHOD(mmu_is_modified, moea64_is_modified),
306 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
307 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
308 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
309 MMUMETHOD(mmu_map, moea64_map),
310 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
311 MMUMETHOD(mmu_page_init, moea64_page_init),
312 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
313 MMUMETHOD(mmu_pinit, moea64_pinit),
314 MMUMETHOD(mmu_pinit0, moea64_pinit0),
315 MMUMETHOD(mmu_protect, moea64_protect),
316 MMUMETHOD(mmu_qenter, moea64_qenter),
317 MMUMETHOD(mmu_qremove, moea64_qremove),
318 MMUMETHOD(mmu_release, moea64_release),
319 MMUMETHOD(mmu_remove, moea64_remove),
320 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
321 MMUMETHOD(mmu_remove_all, moea64_remove_all),
322 MMUMETHOD(mmu_remove_write, moea64_remove_write),
323 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
324 MMUMETHOD(mmu_unwire, moea64_unwire),
325 MMUMETHOD(mmu_zero_page, moea64_zero_page),
326 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
327 MMUMETHOD(mmu_activate, moea64_activate),
328 MMUMETHOD(mmu_deactivate, moea64_deactivate),
329 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
330 MMUMETHOD(mmu_quick_enter_page, moea64_quick_enter_page),
331 MMUMETHOD(mmu_quick_remove_page, moea64_quick_remove_page),
333 /* Internal interfaces */
334 MMUMETHOD(mmu_mapdev, moea64_mapdev),
335 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
336 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
337 MMUMETHOD(mmu_kextract, moea64_kextract),
338 MMUMETHOD(mmu_kenter, moea64_kenter),
339 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
340 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
341 MMUMETHOD(mmu_scan_init, moea64_scan_init),
342 MMUMETHOD(mmu_dumpsys_map, moea64_dumpsys_map),
343 MMUMETHOD(mmu_map_user_ptr, moea64_map_user_ptr),
344 MMUMETHOD(mmu_decode_kernel_ptr, moea64_decode_kernel_ptr),
349 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
351 static struct pvo_head *
352 vm_page_to_pvoh(vm_page_t m)
355 mtx_assert(PV_LOCKPTR(VM_PAGE_TO_PHYS(m)), MA_OWNED);
356 return (&m->md.mdpg_pvoh);
359 static struct pvo_entry *
360 alloc_pvo_entry(int bootstrap)
362 struct pvo_entry *pvo;
364 if (!moea64_initialized || bootstrap) {
365 if (moea64_bpvo_pool_index >= moea64_bpvo_pool_size) {
366 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
367 moea64_bpvo_pool_index, moea64_bpvo_pool_size,
368 moea64_bpvo_pool_size * sizeof(struct pvo_entry));
370 pvo = &moea64_bpvo_pool[
371 atomic_fetchadd_int(&moea64_bpvo_pool_index, 1)];
372 bzero(pvo, sizeof(*pvo));
373 pvo->pvo_vaddr = PVO_BOOTSTRAP;
375 pvo = uma_zalloc(moea64_pvo_zone, M_NOWAIT);
376 bzero(pvo, sizeof(*pvo));
384 init_pvo_entry(struct pvo_entry *pvo, pmap_t pmap, vm_offset_t va)
390 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
392 pvo->pvo_pmap = pmap;
394 pvo->pvo_vaddr |= va;
395 vsid = va_to_vsid(pmap, va);
396 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
399 shift = (pvo->pvo_vaddr & PVO_LARGE) ? moea64_large_page_shift :
401 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)va & ADDR_PIDX) >> shift);
402 pvo->pvo_pte.slot = (hash & moea64_pteg_mask) << 3;
406 free_pvo_entry(struct pvo_entry *pvo)
409 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
410 uma_zfree(moea64_pvo_zone, pvo);
414 moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte)
417 lpte->pte_hi = (pvo->pvo_vpn >> (ADDR_API_SHFT64 - ADDR_PIDX_SHFT)) &
419 lpte->pte_hi |= LPTE_VALID;
421 if (pvo->pvo_vaddr & PVO_LARGE)
422 lpte->pte_hi |= LPTE_BIG;
423 if (pvo->pvo_vaddr & PVO_WIRED)
424 lpte->pte_hi |= LPTE_WIRED;
425 if (pvo->pvo_vaddr & PVO_HID)
426 lpte->pte_hi |= LPTE_HID;
428 lpte->pte_lo = pvo->pvo_pte.pa; /* Includes WIMG bits */
429 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
430 lpte->pte_lo |= LPTE_BW;
432 lpte->pte_lo |= LPTE_BR;
434 if (!(pvo->pvo_pte.prot & VM_PROT_EXECUTE))
435 lpte->pte_lo |= LPTE_NOEXEC;
438 static __inline uint64_t
439 moea64_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
444 if (ma != VM_MEMATTR_DEFAULT) {
446 case VM_MEMATTR_UNCACHEABLE:
447 return (LPTE_I | LPTE_G);
448 case VM_MEMATTR_CACHEABLE:
450 case VM_MEMATTR_WRITE_COMBINING:
451 case VM_MEMATTR_WRITE_BACK:
452 case VM_MEMATTR_PREFETCHABLE:
454 case VM_MEMATTR_WRITE_THROUGH:
455 return (LPTE_W | LPTE_M);
460 * Assume the page is cache inhibited and access is guarded unless
461 * it's in our available memory array.
463 pte_lo = LPTE_I | LPTE_G;
464 for (i = 0; i < pregions_sz; i++) {
465 if ((pa >= pregions[i].mr_start) &&
466 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
467 pte_lo &= ~(LPTE_I | LPTE_G);
477 * Quick sort callout for comparing memory regions.
479 static int om_cmp(const void *a, const void *b);
482 om_cmp(const void *a, const void *b)
484 const struct ofw_map *mapa;
485 const struct ofw_map *mapb;
489 if (mapa->om_pa < mapb->om_pa)
491 else if (mapa->om_pa > mapb->om_pa)
498 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
500 struct ofw_map translations[sz/(4*sizeof(cell_t))]; /*>= 4 cells per */
501 pcell_t acells, trans_cells[sz/sizeof(cell_t)];
502 struct pvo_entry *pvo;
508 bzero(translations, sz);
509 OF_getencprop(OF_finddevice("/"), "#address-cells", &acells,
511 if (OF_getencprop(mmu, "translations", trans_cells, sz) == -1)
512 panic("moea64_bootstrap: can't get ofw translations");
514 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
515 sz /= sizeof(cell_t);
516 for (i = 0, j = 0; i < sz; j++) {
517 translations[j].om_va = trans_cells[i++];
518 translations[j].om_len = trans_cells[i++];
519 translations[j].om_pa = trans_cells[i++];
521 translations[j].om_pa <<= 32;
522 translations[j].om_pa |= trans_cells[i++];
524 translations[j].om_mode = trans_cells[i++];
526 KASSERT(i == sz, ("Translations map has incorrect cell count (%d/%zd)",
530 qsort(translations, sz, sizeof (*translations), om_cmp);
532 for (i = 0; i < sz; i++) {
533 pa_base = translations[i].om_pa;
534 #ifndef __powerpc64__
535 if ((translations[i].om_pa >> 32) != 0)
536 panic("OFW translations above 32-bit boundary!");
539 if (pa_base % PAGE_SIZE)
540 panic("OFW translation not page-aligned (phys)!");
541 if (translations[i].om_va % PAGE_SIZE)
542 panic("OFW translation not page-aligned (virt)!");
544 CTR3(KTR_PMAP, "translation: pa=%#zx va=%#x len=%#x",
545 pa_base, translations[i].om_va, translations[i].om_len);
547 /* Now enter the pages for this mapping */
550 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
551 /* If this address is direct-mapped, skip remapping */
553 translations[i].om_va == PHYS_TO_DMAP(pa_base) &&
554 moea64_calc_wimg(pa_base + off, VM_MEMATTR_DEFAULT) == LPTE_M)
557 PMAP_LOCK(kernel_pmap);
558 pvo = moea64_pvo_find_va(kernel_pmap,
559 translations[i].om_va + off);
560 PMAP_UNLOCK(kernel_pmap);
564 moea64_kenter(mmup, translations[i].om_va + off,
573 moea64_probe_large_page(void)
575 uint16_t pvr = mfpvr() >> 16;
581 powerpc_sync(); isync();
582 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
583 powerpc_sync(); isync();
587 if (moea64_large_page_size == 0) {
588 moea64_large_page_size = 0x1000000; /* 16 MB */
589 moea64_large_page_shift = 24;
593 moea64_large_page_mask = moea64_large_page_size - 1;
597 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
604 cache = PCPU_GET(aim.slb);
605 esid = va >> ADDR_SR_SHFT;
606 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
608 for (i = 0; i < 64; i++) {
609 if (cache[i].slbe == (slbe | i))
614 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
616 entry.slbv |= SLBV_L;
618 slb_insert_kernel(entry.slbe, entry.slbv);
623 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
624 vm_offset_t kernelend)
626 struct pvo_entry *pvo;
629 vm_offset_t size, off;
633 if (moea64_large_page_size == 0)
638 PMAP_LOCK(kernel_pmap);
639 for (i = 0; i < pregions_sz; i++) {
640 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
641 pregions[i].mr_size; pa += moea64_large_page_size) {
644 pvo = alloc_pvo_entry(1 /* bootstrap */);
645 pvo->pvo_vaddr |= PVO_WIRED | PVO_LARGE;
646 init_pvo_entry(pvo, kernel_pmap, PHYS_TO_DMAP(pa));
649 * Set memory access as guarded if prefetch within
650 * the page could exit the available physmem area.
652 if (pa & moea64_large_page_mask) {
653 pa &= moea64_large_page_mask;
656 if (pa + moea64_large_page_size >
657 pregions[i].mr_start + pregions[i].mr_size)
660 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE |
662 pvo->pvo_pte.pa = pa | pte_lo;
663 moea64_pvo_enter(mmup, pvo, NULL);
666 PMAP_UNLOCK(kernel_pmap);
668 size = moea64_bpvo_pool_size*sizeof(struct pvo_entry);
669 off = (vm_offset_t)(moea64_bpvo_pool);
670 for (pa = off; pa < off + size; pa += PAGE_SIZE)
671 moea64_kenter(mmup, pa, pa);
674 * Map certain important things, like ourselves.
676 * NOTE: We do not map the exception vector space. That code is
677 * used only in real mode, and leaving it unmapped allows us to
678 * catch NULL pointer deferences, instead of making NULL a valid
682 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
684 moea64_kenter(mmup, pa, pa);
689 * Allow user to override unmapped_buf_allowed for testing.
690 * XXXKIB Only direct map implementation was tested.
692 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
693 &unmapped_buf_allowed))
694 unmapped_buf_allowed = hw_direct_map;
698 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
701 vm_size_t physsz, hwphyssz;
703 #ifndef __powerpc64__
704 /* We don't have a direct map since there is no BAT */
707 /* Make sure battable is zero, since we have no BAT */
708 for (i = 0; i < 16; i++) {
709 battable[i].batu = 0;
710 battable[i].batl = 0;
713 moea64_probe_large_page();
715 /* Use a direct map if we have large page support */
716 if (moea64_large_page_size > 0)
721 /* Install trap handlers for SLBs */
722 bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
723 bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
724 __syncicache((void *)EXC_DSE, 0x80);
725 __syncicache((void *)EXC_ISE, 0x80);
728 /* Get physical memory regions from firmware */
729 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
730 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
732 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
733 panic("moea64_bootstrap: phys_avail too small");
735 phys_avail_count = 0;
738 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
739 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
740 CTR3(KTR_PMAP, "region: %#zx - %#zx (%#zx)",
741 regions[i].mr_start, regions[i].mr_start +
742 regions[i].mr_size, regions[i].mr_size);
744 (physsz + regions[i].mr_size) >= hwphyssz) {
745 if (physsz < hwphyssz) {
746 phys_avail[j] = regions[i].mr_start;
747 phys_avail[j + 1] = regions[i].mr_start +
754 phys_avail[j] = regions[i].mr_start;
755 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
757 physsz += regions[i].mr_size;
760 /* Check for overlap with the kernel and exception vectors */
761 for (j = 0; j < 2*phys_avail_count; j+=2) {
762 if (phys_avail[j] < EXC_LAST)
763 phys_avail[j] += EXC_LAST;
765 if (kernelstart >= phys_avail[j] &&
766 kernelstart < phys_avail[j+1]) {
767 if (kernelend < phys_avail[j+1]) {
768 phys_avail[2*phys_avail_count] =
769 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
770 phys_avail[2*phys_avail_count + 1] =
775 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
778 if (kernelend >= phys_avail[j] &&
779 kernelend < phys_avail[j+1]) {
780 if (kernelstart > phys_avail[j]) {
781 phys_avail[2*phys_avail_count] = phys_avail[j];
782 phys_avail[2*phys_avail_count + 1] =
783 kernelstart & ~PAGE_MASK;
787 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
791 physmem = btoc(physsz);
794 moea64_pteg_count = PTEGCOUNT;
796 moea64_pteg_count = 0x1000;
798 while (moea64_pteg_count < physmem)
799 moea64_pteg_count <<= 1;
801 moea64_pteg_count >>= 1;
802 #endif /* PTEGCOUNT */
806 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
813 moea64_pteg_mask = moea64_pteg_count - 1;
816 * Initialize SLB table lock and page locks
818 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
819 for (i = 0; i < PV_LOCK_COUNT; i++)
820 mtx_init(&pv_lock[i], "page pv", NULL, MTX_DEF);
823 * Initialise the bootstrap pvo pool.
825 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
826 moea64_bpvo_pool_size*sizeof(struct pvo_entry), 0);
827 moea64_bpvo_pool_index = 0;
830 * Make sure kernel vsid is allocated as well as VSID 0.
832 #ifndef __powerpc64__
833 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
834 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
835 moea64_vsid_bitmap[0] |= 1;
839 * Initialize the kernel pmap (which is statically allocated).
842 for (i = 0; i < 64; i++) {
843 pcpup->pc_aim.slb[i].slbv = 0;
844 pcpup->pc_aim.slb[i].slbe = 0;
847 for (i = 0; i < 16; i++)
848 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
851 kernel_pmap->pmap_phys = kernel_pmap;
852 CPU_FILL(&kernel_pmap->pm_active);
853 RB_INIT(&kernel_pmap->pmap_pvo);
855 PMAP_LOCK_INIT(kernel_pmap);
858 * Now map in all the other buffers we allocated earlier
861 moea64_setup_direct_map(mmup, kernelstart, kernelend);
865 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
876 * Set up the Open Firmware pmap and add its mappings if not in real
880 chosen = OF_finddevice("/chosen");
881 if (chosen != -1 && OF_getencprop(chosen, "mmu", &mmui, 4) != -1) {
882 mmu = OF_instance_to_package(mmui);
884 (sz = OF_getproplen(mmu, "translations")) == -1)
886 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
887 panic("moea64_bootstrap: too many ofw translations");
890 moea64_add_ofw_mappings(mmup, mmu, sz);
894 * Calculate the last available physical address.
897 for (i = 0; phys_avail[i + 2] != 0; i += 2)
898 Maxmem = max(Maxmem, powerpc_btop(phys_avail[i + 1]));
901 * Initialize MMU and remap early physical mappings
903 MMU_CPU_BOOTSTRAP(mmup,0);
904 mtmsr(mfmsr() | PSL_DR | PSL_IR);
906 bs_remap_earlyboot();
909 * Set the start and end of kva.
911 virtual_avail = VM_MIN_KERNEL_ADDRESS;
912 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
915 * Map the entire KVA range into the SLB. We must not fault there.
918 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
919 moea64_bootstrap_slb_prefault(va, 0);
923 * Figure out how far we can extend virtual_end into segment 16
924 * without running into existing mappings. Segment 16 is guaranteed
925 * to contain neither RAM nor devices (at least on Apple hardware),
926 * but will generally contain some OFW mappings we should not
930 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
931 PMAP_LOCK(kernel_pmap);
932 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
933 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
934 virtual_end += PAGE_SIZE;
935 PMAP_UNLOCK(kernel_pmap);
939 * Allocate a kernel stack with a guard page for thread0 and map it
940 * into the kernel page map.
942 pa = moea64_bootstrap_alloc(kstack_pages * PAGE_SIZE, PAGE_SIZE);
943 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
944 virtual_avail = va + kstack_pages * PAGE_SIZE;
945 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
946 thread0.td_kstack = va;
947 thread0.td_kstack_pages = kstack_pages;
948 for (i = 0; i < kstack_pages; i++) {
949 moea64_kenter(mmup, va, pa);
955 * Allocate virtual address space for the message buffer.
957 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
958 msgbufp = (struct msgbuf *)virtual_avail;
960 virtual_avail += round_page(msgbufsize);
961 while (va < virtual_avail) {
962 moea64_kenter(mmup, va, pa);
968 * Allocate virtual address space for the dynamic percpu area.
970 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
971 dpcpu = (void *)virtual_avail;
973 virtual_avail += DPCPU_SIZE;
974 while (va < virtual_avail) {
975 moea64_kenter(mmup, va, pa);
979 dpcpu_init(dpcpu, curcpu);
982 * Allocate some things for page zeroing. We put this directly
983 * in the page table and use MOEA64_PTE_REPLACE to avoid any
984 * of the PVO book-keeping or other parts of the VM system
985 * from even knowing that this hack exists.
988 if (!hw_direct_map) {
989 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
991 for (i = 0; i < 2; i++) {
992 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
993 virtual_end -= PAGE_SIZE;
995 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
997 PMAP_LOCK(kernel_pmap);
998 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
999 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
1000 PMAP_UNLOCK(kernel_pmap);
1006 moea64_pmap_init_qpages(void)
1016 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1017 if (pc->pc_qmap_addr == 0)
1018 panic("pmap_init_qpages: unable to allocate KVA");
1019 PMAP_LOCK(kernel_pmap);
1020 pc->pc_aim.qmap_pvo =
1021 moea64_pvo_find_va(kernel_pmap, pc->pc_qmap_addr);
1022 PMAP_UNLOCK(kernel_pmap);
1023 mtx_init(&pc->pc_aim.qmap_lock, "qmap lock", NULL, MTX_DEF);
1027 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, moea64_pmap_init_qpages, NULL);
1030 * Activate a user pmap. This mostly involves setting some non-CPU
1034 moea64_activate(mmu_t mmu, struct thread *td)
1038 pm = &td->td_proc->p_vmspace->vm_pmap;
1039 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1041 #ifdef __powerpc64__
1042 PCPU_SET(aim.userslb, pm->pm_slb);
1043 __asm __volatile("slbmte %0, %1; isync" ::
1044 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
1046 PCPU_SET(curpmap, pm->pmap_phys);
1047 mtsrin(USER_SR << ADDR_SR_SHFT, td->td_pcb->pcb_cpu.aim.usr_vsid);
1052 moea64_deactivate(mmu_t mmu, struct thread *td)
1056 __asm __volatile("isync; slbie %0" :: "r"(USER_ADDR));
1058 pm = &td->td_proc->p_vmspace->vm_pmap;
1059 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1060 #ifdef __powerpc64__
1061 PCPU_SET(aim.userslb, NULL);
1063 PCPU_SET(curpmap, NULL);
1068 moea64_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1070 struct pvo_entry key, *pvo;
1074 key.pvo_vaddr = sva;
1076 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1077 pvo != NULL && PVO_VADDR(pvo) < eva;
1078 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1079 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1080 panic("moea64_unwire: pvo %p is missing PVO_WIRED",
1082 pvo->pvo_vaddr &= ~PVO_WIRED;
1083 refchg = MOEA64_PTE_REPLACE(mmu, pvo, 0 /* No invalidation */);
1084 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1085 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1088 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1090 refchg |= atomic_readandclear_32(&m->md.mdpg_attrs);
1091 if (refchg & LPTE_CHG)
1093 if (refchg & LPTE_REF)
1094 vm_page_aflag_set(m, PGA_REFERENCED);
1096 pm->pm_stats.wired_count--;
1102 * This goes through and sets the physical address of our
1103 * special scratch PTE to the PA we want to zero or copy. Because
1104 * of locking issues (this can get called in pvo_enter() by
1105 * the UMA allocator), we can't use most other utility functions here
1109 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_paddr_t pa) {
1111 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1112 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1114 moea64_scratchpage_pvo[which]->pvo_pte.pa =
1115 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1116 MOEA64_PTE_REPLACE(mmup, moea64_scratchpage_pvo[which],
1117 MOEA64_PTE_INVALIDATE);
1122 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1127 dst = VM_PAGE_TO_PHYS(mdst);
1128 src = VM_PAGE_TO_PHYS(msrc);
1130 if (hw_direct_map) {
1131 bcopy((void *)PHYS_TO_DMAP(src), (void *)PHYS_TO_DMAP(dst),
1134 mtx_lock(&moea64_scratchpage_mtx);
1136 moea64_set_scratchpage_pa(mmu, 0, src);
1137 moea64_set_scratchpage_pa(mmu, 1, dst);
1139 bcopy((void *)moea64_scratchpage_va[0],
1140 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1142 mtx_unlock(&moea64_scratchpage_mtx);
1147 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1148 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1151 vm_offset_t a_pg_offset, b_pg_offset;
1154 while (xfersize > 0) {
1155 a_pg_offset = a_offset & PAGE_MASK;
1156 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1157 a_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1158 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT])) +
1160 b_pg_offset = b_offset & PAGE_MASK;
1161 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1162 b_cp = (char *)(uintptr_t)PHYS_TO_DMAP(
1163 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT])) +
1165 bcopy(a_cp, b_cp, cnt);
1173 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1174 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1177 vm_offset_t a_pg_offset, b_pg_offset;
1180 mtx_lock(&moea64_scratchpage_mtx);
1181 while (xfersize > 0) {
1182 a_pg_offset = a_offset & PAGE_MASK;
1183 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1184 moea64_set_scratchpage_pa(mmu, 0,
1185 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1186 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1187 b_pg_offset = b_offset & PAGE_MASK;
1188 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1189 moea64_set_scratchpage_pa(mmu, 1,
1190 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1191 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1192 bcopy(a_cp, b_cp, cnt);
1197 mtx_unlock(&moea64_scratchpage_mtx);
1201 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1202 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1205 if (hw_direct_map) {
1206 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1209 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1215 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1217 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1219 if (size + off > PAGE_SIZE)
1220 panic("moea64_zero_page: size + off > PAGE_SIZE");
1222 if (hw_direct_map) {
1223 bzero((caddr_t)(uintptr_t)PHYS_TO_DMAP(pa) + off, size);
1225 mtx_lock(&moea64_scratchpage_mtx);
1226 moea64_set_scratchpage_pa(mmu, 0, pa);
1227 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1228 mtx_unlock(&moea64_scratchpage_mtx);
1233 * Zero a page of physical memory by temporarily mapping it
1236 moea64_zero_page(mmu_t mmu, vm_page_t m)
1238 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1239 vm_offset_t va, off;
1241 if (!hw_direct_map) {
1242 mtx_lock(&moea64_scratchpage_mtx);
1244 moea64_set_scratchpage_pa(mmu, 0, pa);
1245 va = moea64_scratchpage_va[0];
1247 va = PHYS_TO_DMAP(pa);
1250 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1251 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1254 mtx_unlock(&moea64_scratchpage_mtx);
1258 moea64_quick_enter_page(mmu_t mmu, vm_page_t m)
1260 struct pvo_entry *pvo;
1261 vm_paddr_t pa = VM_PAGE_TO_PHYS(m);
1264 return (PHYS_TO_DMAP(pa));
1267 * MOEA64_PTE_REPLACE does some locking, so we can't just grab
1268 * a critical section and access the PCPU data like on i386.
1269 * Instead, pin the thread and grab the PCPU lock to prevent
1270 * a preempting thread from using the same PCPU data.
1274 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_NOTOWNED);
1275 pvo = PCPU_GET(aim.qmap_pvo);
1277 mtx_lock(PCPU_PTR(aim.qmap_lock));
1278 pvo->pvo_pte.pa = moea64_calc_wimg(pa, pmap_page_get_memattr(m)) |
1280 MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_INVALIDATE);
1283 return (PCPU_GET(qmap_addr));
1287 moea64_quick_remove_page(mmu_t mmu, vm_offset_t addr)
1292 mtx_assert(PCPU_PTR(aim.qmap_lock), MA_OWNED);
1293 KASSERT(PCPU_GET(qmap_addr) == addr,
1294 ("moea64_quick_remove_page: invalid address"));
1295 mtx_unlock(PCPU_PTR(aim.qmap_lock));
1300 * Map the given physical page at the specified virtual address in the
1301 * target pmap with the protection requested. If specified the page
1302 * will be wired down.
1306 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1307 vm_prot_t prot, u_int flags, int8_t psind)
1309 struct pvo_entry *pvo, *oldpvo;
1310 struct pvo_head *pvo_head;
1314 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1315 VM_OBJECT_ASSERT_LOCKED(m->object);
1317 pvo = alloc_pvo_entry(0);
1318 pvo->pvo_pmap = NULL; /* to be filled in later */
1319 pvo->pvo_pte.prot = prot;
1321 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1322 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | pte_lo;
1324 if ((flags & PMAP_ENTER_WIRED) != 0)
1325 pvo->pvo_vaddr |= PVO_WIRED;
1327 if ((m->oflags & VPO_UNMANAGED) != 0 || !moea64_initialized) {
1330 pvo_head = &m->md.mdpg_pvoh;
1331 pvo->pvo_vaddr |= PVO_MANAGED;
1337 if (pvo->pvo_pmap == NULL)
1338 init_pvo_entry(pvo, pmap, va);
1339 if (prot & VM_PROT_WRITE)
1340 if (pmap_bootstrapped &&
1341 (m->oflags & VPO_UNMANAGED) == 0)
1342 vm_page_aflag_set(m, PGA_WRITEABLE);
1344 oldpvo = moea64_pvo_find_va(pmap, va);
1345 if (oldpvo != NULL) {
1346 if (oldpvo->pvo_vaddr == pvo->pvo_vaddr &&
1347 oldpvo->pvo_pte.pa == pvo->pvo_pte.pa &&
1348 oldpvo->pvo_pte.prot == prot) {
1349 /* Identical mapping already exists */
1352 /* If not in page table, reinsert it */
1353 if (MOEA64_PTE_SYNCH(mmu, oldpvo) < 0) {
1354 moea64_pte_overflow--;
1355 MOEA64_PTE_INSERT(mmu, oldpvo);
1358 /* Then just clean up and go home */
1361 free_pvo_entry(pvo);
1365 /* Otherwise, need to kill it first */
1366 KASSERT(oldpvo->pvo_pmap == pmap, ("pmap of old "
1367 "mapping does not match new mapping"));
1368 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1370 error = moea64_pvo_enter(mmu, pvo, pvo_head);
1374 /* Free any dead pages */
1375 if (oldpvo != NULL) {
1376 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1377 moea64_pvo_remove_from_page(mmu, oldpvo);
1378 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1379 free_pvo_entry(oldpvo);
1382 if (error != ENOMEM)
1384 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1385 return (KERN_RESOURCE_SHORTAGE);
1386 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1391 * Flush the page from the instruction cache if this page is
1392 * mapped executable and cacheable.
1394 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1395 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1396 vm_page_aflag_set(m, PGA_EXECUTABLE);
1397 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1399 return (KERN_SUCCESS);
1403 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1408 * This is much trickier than on older systems because
1409 * we can't sync the icache on physical addresses directly
1410 * without a direct map. Instead we check a couple of cases
1411 * where the memory is already mapped in and, failing that,
1412 * use the same trick we use for page zeroing to create
1413 * a temporary mapping for this physical address.
1416 if (!pmap_bootstrapped) {
1418 * If PMAP is not bootstrapped, we are likely to be
1421 __syncicache((void *)(uintptr_t)pa, sz);
1422 } else if (pmap == kernel_pmap) {
1423 __syncicache((void *)va, sz);
1424 } else if (hw_direct_map) {
1425 __syncicache((void *)(uintptr_t)PHYS_TO_DMAP(pa), sz);
1427 /* Use the scratch page to set up a temp mapping */
1429 mtx_lock(&moea64_scratchpage_mtx);
1431 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1432 __syncicache((void *)(moea64_scratchpage_va[1] +
1433 (va & ADDR_POFF)), sz);
1435 mtx_unlock(&moea64_scratchpage_mtx);
1440 * Maps a sequence of resident pages belonging to the same object.
1441 * The sequence begins with the given page m_start. This page is
1442 * mapped at the given virtual address start. Each subsequent page is
1443 * mapped at a virtual address that is offset from start by the same
1444 * amount as the page is offset from m_start within the object. The
1445 * last page in the sequence is the page with the largest offset from
1446 * m_start that can be mapped at a virtual address less than the given
1447 * virtual address end. Not every virtual page between start and end
1448 * is mapped; only those for which a resident page exists with the
1449 * corresponding offset from m_start are mapped.
1452 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1453 vm_page_t m_start, vm_prot_t prot)
1456 vm_pindex_t diff, psize;
1458 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1460 psize = atop(end - start);
1462 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1463 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1464 (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP, 0);
1465 m = TAILQ_NEXT(m, listq);
1470 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1474 moea64_enter(mmu, pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1475 PMAP_ENTER_NOSLEEP, 0);
1479 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1481 struct pvo_entry *pvo;
1485 pvo = moea64_pvo_find_va(pm, va);
1489 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1496 * Atomically extract and hold the physical page with the given
1497 * pmap and virtual address pair if that mapping permits the given
1501 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1503 struct pvo_entry *pvo;
1511 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1512 if (pvo != NULL && (pvo->pvo_pte.prot & prot) == prot) {
1513 if (vm_page_pa_tryrelock(pmap,
1514 pvo->pvo_pte.pa & LPTE_RPGN, &pa))
1516 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
1524 static mmu_t installed_mmu;
1527 moea64_uma_page_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
1528 uint8_t *flags, int wait)
1530 struct pvo_entry *pvo;
1536 * This entire routine is a horrible hack to avoid bothering kmem
1537 * for new KVA addresses. Because this can get called from inside
1538 * kmem allocation routines, calling kmem for a new address here
1539 * can lead to multiply locking non-recursive mutexes.
1542 *flags = UMA_SLAB_PRIV;
1543 needed_lock = !PMAP_LOCKED(kernel_pmap);
1545 m = vm_page_alloc_domain(NULL, 0, domain,
1546 malloc2vm_flags(wait) | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ);
1550 va = VM_PAGE_TO_PHYS(m);
1552 pvo = alloc_pvo_entry(1 /* bootstrap */);
1554 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE;
1555 pvo->pvo_pte.pa = VM_PAGE_TO_PHYS(m) | LPTE_M;
1558 PMAP_LOCK(kernel_pmap);
1560 init_pvo_entry(pvo, kernel_pmap, va);
1561 pvo->pvo_vaddr |= PVO_WIRED;
1563 moea64_pvo_enter(installed_mmu, pvo, NULL);
1566 PMAP_UNLOCK(kernel_pmap);
1568 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1569 bzero((void *)va, PAGE_SIZE);
1574 extern int elf32_nxstack;
1577 moea64_init(mmu_t mmu)
1580 CTR0(KTR_PMAP, "moea64_init");
1582 moea64_pvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1583 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1584 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1586 if (!hw_direct_map) {
1587 installed_mmu = mmu;
1588 uma_zone_set_allocf(moea64_pvo_zone, moea64_uma_page_alloc);
1591 #ifdef COMPAT_FREEBSD32
1595 moea64_initialized = TRUE;
1599 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1602 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1603 ("moea64_is_referenced: page %p is not managed", m));
1605 return (moea64_query_bit(mmu, m, LPTE_REF));
1609 moea64_is_modified(mmu_t mmu, vm_page_t m)
1612 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1613 ("moea64_is_modified: page %p is not managed", m));
1616 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1617 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1618 * is clear, no PTEs can have LPTE_CHG set.
1620 VM_OBJECT_ASSERT_LOCKED(m->object);
1621 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1623 return (moea64_query_bit(mmu, m, LPTE_CHG));
1627 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1629 struct pvo_entry *pvo;
1630 boolean_t rv = TRUE;
1633 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1641 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1644 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1645 ("moea64_clear_modify: page %p is not managed", m));
1646 VM_OBJECT_ASSERT_WLOCKED(m->object);
1647 KASSERT(!vm_page_xbusied(m),
1648 ("moea64_clear_modify: page %p is exclusive busied", m));
1651 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1652 * set. If the object containing the page is locked and the page is
1653 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1655 if ((m->aflags & PGA_WRITEABLE) == 0)
1657 moea64_clear_bit(mmu, m, LPTE_CHG);
1661 * Clear the write and modified bits in each of the given page's mappings.
1664 moea64_remove_write(mmu_t mmu, vm_page_t m)
1666 struct pvo_entry *pvo;
1667 int64_t refchg, ret;
1670 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1671 ("moea64_remove_write: page %p is not managed", m));
1674 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1675 * set by another thread while the object is locked. Thus,
1676 * if PGA_WRITEABLE is clear, no page table entries need updating.
1678 VM_OBJECT_ASSERT_WLOCKED(m->object);
1679 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1684 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1685 pmap = pvo->pvo_pmap;
1687 if (!(pvo->pvo_vaddr & PVO_DEAD) &&
1688 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1689 pvo->pvo_pte.prot &= ~VM_PROT_WRITE;
1690 ret = MOEA64_PTE_REPLACE(mmu, pvo,
1691 MOEA64_PTE_PROT_UPDATE);
1695 if (pvo->pvo_pmap == kernel_pmap)
1700 if ((refchg | atomic_readandclear_32(&m->md.mdpg_attrs)) & LPTE_CHG)
1702 vm_page_aflag_clear(m, PGA_WRITEABLE);
1707 * moea64_ts_referenced:
1709 * Return a count of reference bits for a page, clearing those bits.
1710 * It is not necessary for every reference bit to be cleared, but it
1711 * is necessary that 0 only be returned when there are truly no
1712 * reference bits set.
1714 * XXX: The exact number of bits to check and clear is a matter that
1715 * should be tested and standardized at some point in the future for
1716 * optimal aging of shared pages.
1719 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1722 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1723 ("moea64_ts_referenced: page %p is not managed", m));
1724 return (moea64_clear_bit(mmu, m, LPTE_REF));
1728 * Modify the WIMG settings of all mappings for a page.
1731 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1733 struct pvo_entry *pvo;
1738 if ((m->oflags & VPO_UNMANAGED) != 0) {
1739 m->md.mdpg_cache_attrs = ma;
1743 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1746 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1747 pmap = pvo->pvo_pmap;
1749 if (!(pvo->pvo_vaddr & PVO_DEAD)) {
1750 pvo->pvo_pte.pa &= ~LPTE_WIMG;
1751 pvo->pvo_pte.pa |= lo;
1752 refchg = MOEA64_PTE_REPLACE(mmu, pvo,
1753 MOEA64_PTE_INVALIDATE);
1755 refchg = (pvo->pvo_pte.prot & VM_PROT_WRITE) ?
1757 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
1758 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
1760 atomic_readandclear_32(&m->md.mdpg_attrs);
1761 if (refchg & LPTE_CHG)
1763 if (refchg & LPTE_REF)
1764 vm_page_aflag_set(m, PGA_REFERENCED);
1766 if (pvo->pvo_pmap == kernel_pmap)
1771 m->md.mdpg_cache_attrs = ma;
1776 * Map a wired page into kernel virtual address space.
1779 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1782 struct pvo_entry *pvo, *oldpvo;
1784 pvo = alloc_pvo_entry(0);
1785 pvo->pvo_pte.prot = VM_PROT_READ | VM_PROT_WRITE | VM_PROT_EXECUTE;
1786 pvo->pvo_pte.pa = (pa & ~ADDR_POFF) | moea64_calc_wimg(pa, ma);
1787 pvo->pvo_vaddr |= PVO_WIRED;
1789 PMAP_LOCK(kernel_pmap);
1790 oldpvo = moea64_pvo_find_va(kernel_pmap, va);
1792 moea64_pvo_remove_from_pmap(mmu, oldpvo);
1793 init_pvo_entry(pvo, kernel_pmap, va);
1794 error = moea64_pvo_enter(mmu, pvo, NULL);
1795 PMAP_UNLOCK(kernel_pmap);
1797 /* Free any dead pages */
1798 if (oldpvo != NULL) {
1799 PV_LOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1800 moea64_pvo_remove_from_page(mmu, oldpvo);
1801 PV_UNLOCK(oldpvo->pvo_pte.pa & LPTE_RPGN);
1802 free_pvo_entry(oldpvo);
1805 if (error != 0 && error != ENOENT)
1806 panic("moea64_kenter: failed to enter va %#zx pa %#jx: %d", va,
1807 (uintmax_t)pa, error);
1811 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1814 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1818 * Extract the physical page address associated with the given kernel virtual
1822 moea64_kextract(mmu_t mmu, vm_offset_t va)
1824 struct pvo_entry *pvo;
1828 * Shortcut the direct-mapped case when applicable. We never put
1829 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1831 if (va < VM_MIN_KERNEL_ADDRESS)
1834 PMAP_LOCK(kernel_pmap);
1835 pvo = moea64_pvo_find_va(kernel_pmap, va);
1836 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1838 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1839 PMAP_UNLOCK(kernel_pmap);
1844 * Remove a wired page from kernel virtual address space.
1847 moea64_kremove(mmu_t mmu, vm_offset_t va)
1849 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1853 * Provide a kernel pointer corresponding to a given userland pointer.
1854 * The returned pointer is valid until the next time this function is
1855 * called in this thread. This is used internally in copyin/copyout.
1858 moea64_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
1859 void **kaddr, size_t ulen, size_t *klen)
1862 #ifdef __powerpc64__
1867 *kaddr = (char *)USER_ADDR + ((uintptr_t)uaddr & ~SEGMENT_MASK);
1868 l = ((char *)USER_ADDR + SEGMENT_LENGTH) - (char *)(*kaddr);
1876 #ifdef __powerpc64__
1877 /* Try lockless look-up first */
1878 slb = user_va_to_slb_entry(pm, (vm_offset_t)uaddr);
1881 /* If it isn't there, we need to pre-fault the VSID */
1883 slbv = va_to_vsid(pm, (vm_offset_t)uaddr) << SLBV_VSID_SHIFT;
1889 /* Mark segment no-execute */
1892 slbv = va_to_vsid(pm, (vm_offset_t)uaddr);
1894 /* Mark segment no-execute */
1898 /* If we have already set this VSID, we can just return */
1899 if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == slbv)
1902 __asm __volatile("isync");
1903 curthread->td_pcb->pcb_cpu.aim.usr_segm =
1904 (uintptr_t)uaddr >> ADDR_SR_SHFT;
1905 curthread->td_pcb->pcb_cpu.aim.usr_vsid = slbv;
1906 #ifdef __powerpc64__
1907 __asm __volatile ("slbie %0; slbmte %1, %2; isync" ::
1908 "r"(USER_ADDR), "r"(slbv), "r"(USER_SLB_SLBE));
1910 __asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(slbv));
1917 * Figure out where a given kernel pointer (usually in a fault) points
1918 * to from the VM's perspective, potentially remapping into userland's
1922 moea64_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
1923 vm_offset_t *decoded_addr)
1925 vm_offset_t user_sr;
1927 if ((addr >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
1928 user_sr = curthread->td_pcb->pcb_cpu.aim.usr_segm;
1929 addr &= ADDR_PIDX | ADDR_POFF;
1930 addr |= user_sr << ADDR_SR_SHFT;
1931 *decoded_addr = addr;
1934 *decoded_addr = addr;
1942 * Map a range of physical addresses into kernel virtual address space.
1944 * The value passed in *virt is a suggested virtual address for the mapping.
1945 * Architectures which can support a direct-mapped physical to virtual region
1946 * can return the appropriate address within that region, leaving '*virt'
1947 * unchanged. Other architectures should map the pages starting at '*virt' and
1948 * update '*virt' with the first usable address after the mapped region.
1951 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1952 vm_paddr_t pa_end, int prot)
1954 vm_offset_t sva, va;
1956 if (hw_direct_map) {
1958 * Check if every page in the region is covered by the direct
1959 * map. The direct map covers all of physical memory. Use
1960 * moea64_calc_wimg() as a shortcut to see if the page is in
1961 * physical memory as a way to see if the direct map covers it.
1963 for (va = pa_start; va < pa_end; va += PAGE_SIZE)
1964 if (moea64_calc_wimg(va, VM_MEMATTR_DEFAULT) != LPTE_M)
1967 return (PHYS_TO_DMAP(pa_start));
1971 /* XXX respect prot argument */
1972 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1973 moea64_kenter(mmu, va, pa_start);
1980 * Returns true if the pmap's pv is one of the first
1981 * 16 pvs linked to from this page. This count may
1982 * be changed upwards or downwards in the future; it
1983 * is only necessary that true be returned for a small
1984 * subset of pmaps for proper page aging.
1987 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1990 struct pvo_entry *pvo;
1993 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1994 ("moea64_page_exists_quick: page %p is not managed", m));
1998 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1999 if (!(pvo->pvo_vaddr & PVO_DEAD) && pvo->pvo_pmap == pmap) {
2011 moea64_page_init(mmu_t mmu __unused, vm_page_t m)
2014 m->md.mdpg_attrs = 0;
2015 m->md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
2016 LIST_INIT(&m->md.mdpg_pvoh);
2020 * Return the number of managed mappings to the given physical page
2024 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
2026 struct pvo_entry *pvo;
2030 if ((m->oflags & VPO_UNMANAGED) != 0)
2033 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
2034 if ((pvo->pvo_vaddr & (PVO_DEAD | PVO_WIRED)) == PVO_WIRED)
2040 static uintptr_t moea64_vsidcontext;
2043 moea64_get_unique_vsid(void) {
2050 __asm __volatile("mftb %0" : "=r"(entropy));
2052 mtx_lock(&moea64_slb_mutex);
2053 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
2057 * Create a new value by mutiplying by a prime and adding in
2058 * entropy from the timebase register. This is to make the
2059 * VSID more random so that the PT hash function collides
2060 * less often. (Note that the prime casues gcc to do shifts
2061 * instead of a multiply.)
2063 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
2064 hash = moea64_vsidcontext & (NVSIDS - 1);
2065 if (hash == 0) /* 0 is special, avoid it */
2068 mask = 1 << (hash & (VSID_NBPW - 1));
2069 hash = (moea64_vsidcontext & VSID_HASHMASK);
2070 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
2071 /* anything free in this bucket? */
2072 if (moea64_vsid_bitmap[n] == 0xffffffff) {
2073 entropy = (moea64_vsidcontext >> 20);
2076 i = ffs(~moea64_vsid_bitmap[n]) - 1;
2078 hash &= rounddown2(VSID_HASHMASK, VSID_NBPW);
2081 if (hash == VSID_VRMA) /* also special, avoid this too */
2083 KASSERT(!(moea64_vsid_bitmap[n] & mask),
2084 ("Allocating in-use VSID %#zx\n", hash));
2085 moea64_vsid_bitmap[n] |= mask;
2086 mtx_unlock(&moea64_slb_mutex);
2090 mtx_unlock(&moea64_slb_mutex);
2091 panic("%s: out of segments",__func__);
2094 #ifdef __powerpc64__
2096 moea64_pinit(mmu_t mmu, pmap_t pmap)
2099 RB_INIT(&pmap->pmap_pvo);
2101 pmap->pm_slb_tree_root = slb_alloc_tree();
2102 pmap->pm_slb = slb_alloc_user_cache();
2103 pmap->pm_slb_len = 0;
2107 moea64_pinit(mmu_t mmu, pmap_t pmap)
2112 RB_INIT(&pmap->pmap_pvo);
2114 if (pmap_bootstrapped)
2115 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
2118 pmap->pmap_phys = pmap;
2121 * Allocate some segment registers for this pmap.
2123 hash = moea64_get_unique_vsid();
2125 for (i = 0; i < 16; i++)
2126 pmap->pm_sr[i] = VSID_MAKE(i, hash);
2128 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
2133 * Initialize the pmap associated with process 0.
2136 moea64_pinit0(mmu_t mmu, pmap_t pm)
2140 moea64_pinit(mmu, pm);
2141 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
2145 * Set the physical protection on the specified range of this map as requested.
2148 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
2154 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2157 * Change the protection of the page.
2159 oldprot = pvo->pvo_pte.prot;
2160 pvo->pvo_pte.prot = prot;
2161 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2164 * If the PVO is in the page table, update mapping
2166 refchg = MOEA64_PTE_REPLACE(mmu, pvo, MOEA64_PTE_PROT_UPDATE);
2168 refchg = (oldprot & VM_PROT_WRITE) ? LPTE_CHG : 0;
2170 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
2171 (pvo->pvo_pte.pa & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
2172 if ((pg->oflags & VPO_UNMANAGED) == 0)
2173 vm_page_aflag_set(pg, PGA_EXECUTABLE);
2174 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
2175 pvo->pvo_pte.pa & LPTE_RPGN, PAGE_SIZE);
2179 * Update vm about the REF/CHG bits if the page is managed and we have
2180 * removed write access.
2182 if (pg != NULL && (pvo->pvo_vaddr & PVO_MANAGED) &&
2183 (oldprot & VM_PROT_WRITE)) {
2184 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2185 if (refchg & LPTE_CHG)
2187 if (refchg & LPTE_REF)
2188 vm_page_aflag_set(pg, PGA_REFERENCED);
2193 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
2196 struct pvo_entry *pvo, *tpvo, key;
2198 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
2201 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2202 ("moea64_protect: non current pmap"));
2204 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2205 moea64_remove(mmu, pm, sva, eva);
2210 key.pvo_vaddr = sva;
2211 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2212 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2213 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2214 moea64_pvo_protect(mmu, pm, pvo, prot);
2220 * Map a list of wired pages into kernel virtual address space. This is
2221 * intended for temporary mappings which do not need page modification or
2222 * references recorded. Existing mappings in the region are overwritten.
2225 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2227 while (count-- > 0) {
2228 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2235 * Remove page mappings from kernel virtual address space. Intended for
2236 * temporary mappings entered by moea64_qenter.
2239 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2241 while (count-- > 0) {
2242 moea64_kremove(mmu, va);
2248 moea64_release_vsid(uint64_t vsid)
2252 mtx_lock(&moea64_slb_mutex);
2253 idx = vsid & (NVSIDS-1);
2254 mask = 1 << (idx % VSID_NBPW);
2256 KASSERT(moea64_vsid_bitmap[idx] & mask,
2257 ("Freeing unallocated VSID %#jx", vsid));
2258 moea64_vsid_bitmap[idx] &= ~mask;
2259 mtx_unlock(&moea64_slb_mutex);
2264 moea64_release(mmu_t mmu, pmap_t pmap)
2268 * Free segment registers' VSIDs
2270 #ifdef __powerpc64__
2271 slb_free_tree(pmap);
2272 slb_free_user_cache(pmap->pm_slb);
2274 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2276 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2281 * Remove all pages mapped by the specified pmap
2284 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2286 struct pvo_entry *pvo, *tpvo;
2287 struct pvo_tree tofree;
2292 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2293 if (pvo->pvo_vaddr & PVO_WIRED)
2297 * For locking reasons, remove this from the page table and
2298 * pmap, but save delinking from the vm_page for a second
2301 moea64_pvo_remove_from_pmap(mmu, pvo);
2302 RB_INSERT(pvo_tree, &tofree, pvo);
2306 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2307 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2308 moea64_pvo_remove_from_page(mmu, pvo);
2309 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2310 RB_REMOVE(pvo_tree, &tofree, pvo);
2311 free_pvo_entry(pvo);
2316 * Remove the given range of addresses from the specified map.
2319 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2321 struct pvo_entry *pvo, *tpvo, key;
2322 struct pvo_tree tofree;
2325 * Perform an unsynchronized read. This is, however, safe.
2327 if (pm->pm_stats.resident_count == 0)
2330 key.pvo_vaddr = sva;
2335 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2336 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2337 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2340 * For locking reasons, remove this from the page table and
2341 * pmap, but save delinking from the vm_page for a second
2344 moea64_pvo_remove_from_pmap(mmu, pvo);
2345 RB_INSERT(pvo_tree, &tofree, pvo);
2349 RB_FOREACH_SAFE(pvo, pvo_tree, &tofree, tpvo) {
2350 PV_LOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2351 moea64_pvo_remove_from_page(mmu, pvo);
2352 PV_UNLOCK(pvo->pvo_pte.pa & LPTE_RPGN);
2353 RB_REMOVE(pvo_tree, &tofree, pvo);
2354 free_pvo_entry(pvo);
2359 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2360 * will reflect changes in pte's back to the vm_page.
2363 moea64_remove_all(mmu_t mmu, vm_page_t m)
2365 struct pvo_entry *pvo, *next_pvo;
2366 struct pvo_head freequeue;
2370 LIST_INIT(&freequeue);
2373 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2374 pmap = pvo->pvo_pmap;
2376 wasdead = (pvo->pvo_vaddr & PVO_DEAD);
2378 moea64_pvo_remove_from_pmap(mmu, pvo);
2379 moea64_pvo_remove_from_page(mmu, pvo);
2381 LIST_INSERT_HEAD(&freequeue, pvo, pvo_vlink);
2385 KASSERT(!pmap_page_is_mapped(m), ("Page still has mappings"));
2386 KASSERT(!(m->aflags & PGA_WRITEABLE), ("Page still writable"));
2389 /* Clean up UMA allocations */
2390 LIST_FOREACH_SAFE(pvo, &freequeue, pvo_vlink, next_pvo)
2391 free_pvo_entry(pvo);
2395 * Allocate a physical page of memory directly from the phys_avail map.
2396 * Can only be called from moea64_bootstrap before avail start and end are
2400 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2405 size = round_page(size);
2406 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2408 s = roundup2(phys_avail[i], align);
2413 if (s < phys_avail[i] || e > phys_avail[i + 1])
2416 if (s + size > platform_real_maxaddr())
2419 if (s == phys_avail[i]) {
2420 phys_avail[i] += size;
2421 } else if (e == phys_avail[i + 1]) {
2422 phys_avail[i + 1] -= size;
2424 for (j = phys_avail_count * 2; j > i; j -= 2) {
2425 phys_avail[j] = phys_avail[j - 2];
2426 phys_avail[j + 1] = phys_avail[j - 1];
2429 phys_avail[i + 3] = phys_avail[i + 1];
2430 phys_avail[i + 1] = s;
2431 phys_avail[i + 2] = e;
2437 panic("moea64_bootstrap_alloc: could not allocate memory");
2441 moea64_pvo_enter(mmu_t mmu, struct pvo_entry *pvo, struct pvo_head *pvo_head)
2445 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2446 KASSERT(moea64_pvo_find_va(pvo->pvo_pmap, PVO_VADDR(pvo)) == NULL,
2447 ("Existing mapping for VA %#jx", (uintmax_t)PVO_VADDR(pvo)));
2449 moea64_pvo_enter_calls++;
2454 RB_INSERT(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2457 * Remember if the list was empty and therefore will be the first
2460 if (pvo_head != NULL) {
2461 if (LIST_FIRST(pvo_head) == NULL)
2463 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2466 if (pvo->pvo_vaddr & PVO_WIRED)
2467 pvo->pvo_pmap->pm_stats.wired_count++;
2468 pvo->pvo_pmap->pm_stats.resident_count++;
2471 * Insert it into the hardware page table
2473 err = MOEA64_PTE_INSERT(mmu, pvo);
2475 panic("moea64_pvo_enter: overflow");
2478 moea64_pvo_entries++;
2480 if (pvo->pvo_pmap == kernel_pmap)
2483 #ifdef __powerpc64__
2485 * Make sure all our bootstrap mappings are in the SLB as soon
2486 * as virtual memory is switched on.
2488 if (!pmap_bootstrapped)
2489 moea64_bootstrap_slb_prefault(PVO_VADDR(pvo),
2490 pvo->pvo_vaddr & PVO_LARGE);
2493 return (first ? ENOENT : 0);
2497 moea64_pvo_remove_from_pmap(mmu_t mmu, struct pvo_entry *pvo)
2502 KASSERT(pvo->pvo_pmap != NULL, ("Trying to remove PVO with no pmap"));
2503 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2504 KASSERT(!(pvo->pvo_vaddr & PVO_DEAD), ("Trying to remove dead PVO"));
2507 * If there is an active pte entry, we need to deactivate it
2509 refchg = MOEA64_PTE_UNSET(mmu, pvo);
2512 * If it was evicted from the page table, be pessimistic and
2515 if (pvo->pvo_pte.prot & VM_PROT_WRITE)
2522 * Update our statistics.
2524 pvo->pvo_pmap->pm_stats.resident_count--;
2525 if (pvo->pvo_vaddr & PVO_WIRED)
2526 pvo->pvo_pmap->pm_stats.wired_count--;
2529 * Remove this PVO from the pmap list.
2531 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2534 * Mark this for the next sweep
2536 pvo->pvo_vaddr |= PVO_DEAD;
2538 /* Send RC bits to VM */
2539 if ((pvo->pvo_vaddr & PVO_MANAGED) &&
2540 (pvo->pvo_pte.prot & VM_PROT_WRITE)) {
2541 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2543 refchg |= atomic_readandclear_32(&pg->md.mdpg_attrs);
2544 if (refchg & LPTE_CHG)
2546 if (refchg & LPTE_REF)
2547 vm_page_aflag_set(pg, PGA_REFERENCED);
2553 moea64_pvo_remove_from_page(mmu_t mmu, struct pvo_entry *pvo)
2557 KASSERT(pvo->pvo_vaddr & PVO_DEAD, ("Trying to delink live page"));
2559 /* Use NULL pmaps as a sentinel for races in page deletion */
2560 if (pvo->pvo_pmap == NULL)
2562 pvo->pvo_pmap = NULL;
2565 * Update vm about page writeability/executability if managed
2567 PV_LOCKASSERT(pvo->pvo_pte.pa & LPTE_RPGN);
2568 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pa & LPTE_RPGN);
2570 if ((pvo->pvo_vaddr & PVO_MANAGED) && pg != NULL) {
2571 LIST_REMOVE(pvo, pvo_vlink);
2572 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2573 vm_page_aflag_clear(pg, PGA_WRITEABLE | PGA_EXECUTABLE);
2576 moea64_pvo_entries--;
2577 moea64_pvo_remove_calls++;
2580 static struct pvo_entry *
2581 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2583 struct pvo_entry key;
2585 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2587 key.pvo_vaddr = va & ~ADDR_POFF;
2588 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2592 moea64_query_bit(mmu_t mmu, vm_page_t m, uint64_t ptebit)
2594 struct pvo_entry *pvo;
2599 * See if this bit is stored in the page already.
2601 if (m->md.mdpg_attrs & ptebit)
2605 * Examine each PTE. Sync so that any pending REF/CHG bits are
2606 * flushed to the PTEs.
2611 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2615 * See if this pvo has a valid PTE. if so, fetch the
2616 * REF/CHG bits from the valid PTE. If the appropriate
2617 * ptebit is set, return success.
2619 PMAP_LOCK(pvo->pvo_pmap);
2620 if (!(pvo->pvo_vaddr & PVO_DEAD))
2621 ret = MOEA64_PTE_SYNCH(mmu, pvo);
2622 PMAP_UNLOCK(pvo->pvo_pmap);
2625 atomic_set_32(&m->md.mdpg_attrs,
2626 ret & (LPTE_CHG | LPTE_REF));
2639 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2642 struct pvo_entry *pvo;
2646 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2647 * we can reset the right ones).
2652 * For each pvo entry, clear the pte's ptebit.
2656 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2659 PMAP_LOCK(pvo->pvo_pmap);
2660 if (!(pvo->pvo_vaddr & PVO_DEAD))
2661 ret = MOEA64_PTE_CLEAR(mmu, pvo, ptebit);
2662 PMAP_UNLOCK(pvo->pvo_pmap);
2664 if (ret > 0 && (ret & ptebit))
2667 atomic_clear_32(&m->md.mdpg_attrs, ptebit);
2674 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2676 struct pvo_entry *pvo, key;
2680 PMAP_LOCK(kernel_pmap);
2681 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2682 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2683 ppa < pa + size; ppa += PAGE_SIZE,
2684 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2685 if (pvo == NULL || (pvo->pvo_pte.pa & LPTE_RPGN) != ppa) {
2690 PMAP_UNLOCK(kernel_pmap);
2696 * Map a set of physical memory pages into the kernel virtual
2697 * address space. Return a pointer to where it is mapped. This
2698 * routine is intended to be used for mapping device memory,
2702 moea64_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2704 vm_offset_t va, tmpva, ppa, offset;
2706 ppa = trunc_page(pa);
2707 offset = pa & PAGE_MASK;
2708 size = roundup2(offset + size, PAGE_SIZE);
2710 va = kva_alloc(size);
2713 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2715 for (tmpva = va; size > 0;) {
2716 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2722 return ((void *)(va + offset));
2726 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2729 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2733 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2735 vm_offset_t base, offset;
2737 base = trunc_page(va);
2738 offset = va & PAGE_MASK;
2739 size = roundup2(offset + size, PAGE_SIZE);
2741 kva_free(base, size);
2745 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2747 struct pvo_entry *pvo;
2754 lim = round_page(va);
2755 len = MIN(lim - va, sz);
2756 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2757 if (pvo != NULL && !(pvo->pvo_pte.pa & LPTE_I)) {
2758 pa = (pvo->pvo_pte.pa & LPTE_RPGN) | (va & ADDR_POFF);
2759 moea64_syncicache(mmu, pm, va, pa, len);
2768 moea64_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2771 *va = (void *)(uintptr_t)pa;
2774 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2777 moea64_scan_init(mmu_t mmu)
2779 struct pvo_entry *pvo;
2784 /* Initialize phys. segments for dumpsys(). */
2785 memset(&dump_map, 0, sizeof(dump_map));
2786 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
2787 for (i = 0; i < pregions_sz; i++) {
2788 dump_map[i].pa_start = pregions[i].mr_start;
2789 dump_map[i].pa_size = pregions[i].mr_size;
2794 /* Virtual segments for minidumps: */
2795 memset(&dump_map, 0, sizeof(dump_map));
2797 /* 1st: kernel .data and .bss. */
2798 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2799 dump_map[0].pa_size = round_page((uintptr_t)_end) -
2800 dump_map[0].pa_start;
2802 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2803 dump_map[1].pa_start = (vm_paddr_t)(uintptr_t)msgbufp->msg_ptr;
2804 dump_map[1].pa_size = round_page(msgbufp->msg_size);
2806 /* 3rd: kernel VM. */
2807 va = dump_map[1].pa_start + dump_map[1].pa_size;
2808 /* Find start of next chunk (from va). */
2809 while (va < virtual_end) {
2810 /* Don't dump the buffer cache. */
2811 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2812 va = kmi.buffer_eva;
2815 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2816 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2820 if (va < virtual_end) {
2821 dump_map[2].pa_start = va;
2823 /* Find last page in chunk. */
2824 while (va < virtual_end) {
2825 /* Don't run into the buffer cache. */
2826 if (va == kmi.buffer_sva)
2828 pvo = moea64_pvo_find_va(kernel_pmap, va & ~ADDR_POFF);
2829 if (pvo != NULL && !(pvo->pvo_vaddr & PVO_DEAD))
2833 dump_map[2].pa_size = va - dump_map[2].pa_start;