2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_compat.h"
113 #include "opt_kstack_pages.h"
115 #include <sys/param.h>
116 #include <sys/kernel.h>
117 #include <sys/queue.h>
118 #include <sys/cpuset.h>
120 #include <sys/lock.h>
121 #include <sys/msgbuf.h>
122 #include <sys/malloc.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rwlock.h>
126 #include <sys/sched.h>
127 #include <sys/sysctl.h>
128 #include <sys/systm.h>
129 #include <sys/vmmeter.h>
133 #include <dev/ofw/openfirm.h>
136 #include <vm/vm_param.h>
137 #include <vm/vm_kern.h>
138 #include <vm/vm_page.h>
139 #include <vm/vm_map.h>
140 #include <vm/vm_object.h>
141 #include <vm/vm_extern.h>
142 #include <vm/vm_pageout.h>
145 #include <machine/_inttypes.h>
146 #include <machine/cpu.h>
147 #include <machine/platform.h>
148 #include <machine/frame.h>
149 #include <machine/md_var.h>
150 #include <machine/psl.h>
151 #include <machine/bat.h>
152 #include <machine/hid.h>
153 #include <machine/pte.h>
154 #include <machine/sr.h>
155 #include <machine/trap.h>
156 #include <machine/mmuvar.h>
158 #include "mmu_oea64.h"
160 #include "moea64_if.h"
162 void moea64_release_vsid(uint64_t vsid);
163 uintptr_t moea64_get_unique_vsid(void);
165 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
166 #define ENABLE_TRANS(msr) mtmsr(msr)
168 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
169 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
170 #define VSID_HASH_MASK 0x0000007fffffffffULL
174 * -- Read lock: if no modifications are being made to either the PVO lists
175 * or page table or if any modifications being made result in internal
176 * changes (e.g. wiring, protection) such that the existence of the PVOs
177 * is unchanged and they remain associated with the same pmap (in which
178 * case the changes should be protected by the pmap lock)
179 * -- Write lock: required if PTEs/PVOs are being inserted or removed.
182 #define LOCK_TABLE_RD() rw_rlock(&moea64_table_lock)
183 #define UNLOCK_TABLE_RD() rw_runlock(&moea64_table_lock)
184 #define LOCK_TABLE_WR() rw_wlock(&moea64_table_lock)
185 #define UNLOCK_TABLE_WR() rw_wunlock(&moea64_table_lock)
196 * Map of physical memory regions.
198 static struct mem_region *regions;
199 static struct mem_region *pregions;
200 static u_int phys_avail_count;
201 static int regions_sz, pregions_sz;
203 extern void bs_remap_earlyboot(void);
206 * Lock for the pteg and pvo tables.
208 struct rwlock moea64_table_lock;
209 struct mtx moea64_slb_mutex;
214 u_int moea64_pteg_count;
215 u_int moea64_pteg_mask;
220 struct pvo_head *moea64_pvo_table; /* pvo entries by pteg index */
222 uma_zone_t moea64_upvo_zone; /* zone for pvo entries for unmanaged pages */
223 uma_zone_t moea64_mpvo_zone; /* zone for pvo entries for managed pages */
225 #define BPVO_POOL_SIZE 327680
226 static struct pvo_entry *moea64_bpvo_pool;
227 static int moea64_bpvo_pool_index = 0;
229 #define VSID_NBPW (sizeof(u_int32_t) * 8)
231 #define NVSIDS (NPMAPS * 16)
232 #define VSID_HASHMASK 0xffffffffUL
234 #define NVSIDS NPMAPS
235 #define VSID_HASHMASK 0xfffffUL
237 static u_int moea64_vsid_bitmap[NVSIDS / VSID_NBPW];
239 static boolean_t moea64_initialized = FALSE;
244 u_int moea64_pte_valid = 0;
245 u_int moea64_pte_overflow = 0;
246 u_int moea64_pvo_entries = 0;
247 u_int moea64_pvo_enter_calls = 0;
248 u_int moea64_pvo_remove_calls = 0;
249 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_valid, CTLFLAG_RD,
250 &moea64_pte_valid, 0, "");
251 SYSCTL_INT(_machdep, OID_AUTO, moea64_pte_overflow, CTLFLAG_RD,
252 &moea64_pte_overflow, 0, "");
253 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_entries, CTLFLAG_RD,
254 &moea64_pvo_entries, 0, "");
255 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_enter_calls, CTLFLAG_RD,
256 &moea64_pvo_enter_calls, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea64_pvo_remove_calls, CTLFLAG_RD,
258 &moea64_pvo_remove_calls, 0, "");
260 vm_offset_t moea64_scratchpage_va[2];
261 struct pvo_entry *moea64_scratchpage_pvo[2];
262 uintptr_t moea64_scratchpage_pte[2];
263 struct mtx moea64_scratchpage_mtx;
265 uint64_t moea64_large_page_mask = 0;
266 int moea64_large_page_size = 0;
267 int moea64_large_page_shift = 0;
272 static int moea64_pvo_enter(mmu_t, pmap_t, uma_zone_t, struct pvo_head *,
273 vm_offset_t, vm_offset_t, uint64_t, int);
274 static void moea64_pvo_remove(mmu_t, struct pvo_entry *);
275 static struct pvo_entry *moea64_pvo_find_va(pmap_t, vm_offset_t);
280 static boolean_t moea64_query_bit(mmu_t, vm_page_t, u_int64_t);
281 static u_int moea64_clear_bit(mmu_t, vm_page_t, u_int64_t);
282 static void moea64_kremove(mmu_t, vm_offset_t);
283 static void moea64_syncicache(mmu_t, pmap_t pmap, vm_offset_t va,
284 vm_offset_t pa, vm_size_t sz);
287 * Kernel MMU interface
289 void moea64_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
290 void moea64_clear_modify(mmu_t, vm_page_t);
291 void moea64_clear_reference(mmu_t, vm_page_t);
292 void moea64_copy_page(mmu_t, vm_page_t, vm_page_t);
293 void moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
294 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
295 void moea64_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
296 void moea64_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
298 void moea64_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
299 vm_paddr_t moea64_extract(mmu_t, pmap_t, vm_offset_t);
300 vm_page_t moea64_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
301 void moea64_init(mmu_t);
302 boolean_t moea64_is_modified(mmu_t, vm_page_t);
303 boolean_t moea64_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
304 boolean_t moea64_is_referenced(mmu_t, vm_page_t);
305 int moea64_ts_referenced(mmu_t, vm_page_t);
306 vm_offset_t moea64_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
307 boolean_t moea64_page_exists_quick(mmu_t, pmap_t, vm_page_t);
308 int moea64_page_wired_mappings(mmu_t, vm_page_t);
309 void moea64_pinit(mmu_t, pmap_t);
310 void moea64_pinit0(mmu_t, pmap_t);
311 void moea64_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
312 void moea64_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
313 void moea64_qremove(mmu_t, vm_offset_t, int);
314 void moea64_release(mmu_t, pmap_t);
315 void moea64_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
316 void moea64_remove_pages(mmu_t, pmap_t);
317 void moea64_remove_all(mmu_t, vm_page_t);
318 void moea64_remove_write(mmu_t, vm_page_t);
319 void moea64_zero_page(mmu_t, vm_page_t);
320 void moea64_zero_page_area(mmu_t, vm_page_t, int, int);
321 void moea64_zero_page_idle(mmu_t, vm_page_t);
322 void moea64_activate(mmu_t, struct thread *);
323 void moea64_deactivate(mmu_t, struct thread *);
324 void *moea64_mapdev(mmu_t, vm_paddr_t, vm_size_t);
325 void *moea64_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
326 void moea64_unmapdev(mmu_t, vm_offset_t, vm_size_t);
327 vm_paddr_t moea64_kextract(mmu_t, vm_offset_t);
328 void moea64_page_set_memattr(mmu_t, vm_page_t m, vm_memattr_t ma);
329 void moea64_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t ma);
330 void moea64_kenter(mmu_t, vm_offset_t, vm_paddr_t);
331 boolean_t moea64_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
332 static void moea64_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
334 static mmu_method_t moea64_methods[] = {
335 MMUMETHOD(mmu_change_wiring, moea64_change_wiring),
336 MMUMETHOD(mmu_clear_modify, moea64_clear_modify),
337 MMUMETHOD(mmu_clear_reference, moea64_clear_reference),
338 MMUMETHOD(mmu_copy_page, moea64_copy_page),
339 MMUMETHOD(mmu_copy_pages, moea64_copy_pages),
340 MMUMETHOD(mmu_enter, moea64_enter),
341 MMUMETHOD(mmu_enter_object, moea64_enter_object),
342 MMUMETHOD(mmu_enter_quick, moea64_enter_quick),
343 MMUMETHOD(mmu_extract, moea64_extract),
344 MMUMETHOD(mmu_extract_and_hold, moea64_extract_and_hold),
345 MMUMETHOD(mmu_init, moea64_init),
346 MMUMETHOD(mmu_is_modified, moea64_is_modified),
347 MMUMETHOD(mmu_is_prefaultable, moea64_is_prefaultable),
348 MMUMETHOD(mmu_is_referenced, moea64_is_referenced),
349 MMUMETHOD(mmu_ts_referenced, moea64_ts_referenced),
350 MMUMETHOD(mmu_map, moea64_map),
351 MMUMETHOD(mmu_page_exists_quick,moea64_page_exists_quick),
352 MMUMETHOD(mmu_page_wired_mappings,moea64_page_wired_mappings),
353 MMUMETHOD(mmu_pinit, moea64_pinit),
354 MMUMETHOD(mmu_pinit0, moea64_pinit0),
355 MMUMETHOD(mmu_protect, moea64_protect),
356 MMUMETHOD(mmu_qenter, moea64_qenter),
357 MMUMETHOD(mmu_qremove, moea64_qremove),
358 MMUMETHOD(mmu_release, moea64_release),
359 MMUMETHOD(mmu_remove, moea64_remove),
360 MMUMETHOD(mmu_remove_pages, moea64_remove_pages),
361 MMUMETHOD(mmu_remove_all, moea64_remove_all),
362 MMUMETHOD(mmu_remove_write, moea64_remove_write),
363 MMUMETHOD(mmu_sync_icache, moea64_sync_icache),
364 MMUMETHOD(mmu_zero_page, moea64_zero_page),
365 MMUMETHOD(mmu_zero_page_area, moea64_zero_page_area),
366 MMUMETHOD(mmu_zero_page_idle, moea64_zero_page_idle),
367 MMUMETHOD(mmu_activate, moea64_activate),
368 MMUMETHOD(mmu_deactivate, moea64_deactivate),
369 MMUMETHOD(mmu_page_set_memattr, moea64_page_set_memattr),
371 /* Internal interfaces */
372 MMUMETHOD(mmu_mapdev, moea64_mapdev),
373 MMUMETHOD(mmu_mapdev_attr, moea64_mapdev_attr),
374 MMUMETHOD(mmu_unmapdev, moea64_unmapdev),
375 MMUMETHOD(mmu_kextract, moea64_kextract),
376 MMUMETHOD(mmu_kenter, moea64_kenter),
377 MMUMETHOD(mmu_kenter_attr, moea64_kenter_attr),
378 MMUMETHOD(mmu_dev_direct_mapped,moea64_dev_direct_mapped),
383 MMU_DEF(oea64_mmu, "mmu_oea64_base", moea64_methods, 0);
385 static __inline u_int
386 va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
391 shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
392 hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
394 return (hash & moea64_pteg_mask);
397 static __inline struct pvo_head *
398 vm_page_to_pvoh(vm_page_t m)
401 return (&m->md.mdpg_pvoh);
405 moea64_pte_create(struct lpte *pt, uint64_t vsid, vm_offset_t va,
406 uint64_t pte_lo, int flags)
410 * Construct a PTE. Default to IMB initially. Valid bit only gets
411 * set when the real pte is set in memory.
413 * Note: Don't set the valid bit for correct operation of tlb update.
415 pt->pte_hi = (vsid << LPTE_VSID_SHIFT) |
416 (((uint64_t)(va & ADDR_PIDX) >> ADDR_API_SHFT64) & LPTE_API);
418 if (flags & PVO_LARGE)
419 pt->pte_hi |= LPTE_BIG;
424 static __inline uint64_t
425 moea64_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
430 if (ma != VM_MEMATTR_DEFAULT) {
432 case VM_MEMATTR_UNCACHEABLE:
433 return (LPTE_I | LPTE_G);
434 case VM_MEMATTR_WRITE_COMBINING:
435 case VM_MEMATTR_WRITE_BACK:
436 case VM_MEMATTR_PREFETCHABLE:
438 case VM_MEMATTR_WRITE_THROUGH:
439 return (LPTE_W | LPTE_M);
444 * Assume the page is cache inhibited and access is guarded unless
445 * it's in our available memory array.
447 pte_lo = LPTE_I | LPTE_G;
448 for (i = 0; i < pregions_sz; i++) {
449 if ((pa >= pregions[i].mr_start) &&
450 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
451 pte_lo &= ~(LPTE_I | LPTE_G);
461 * Quick sort callout for comparing memory regions.
463 static int om_cmp(const void *a, const void *b);
466 om_cmp(const void *a, const void *b)
468 const struct ofw_map *mapa;
469 const struct ofw_map *mapb;
473 if (mapa->om_pa_hi < mapb->om_pa_hi)
475 else if (mapa->om_pa_hi > mapb->om_pa_hi)
477 else if (mapa->om_pa_lo < mapb->om_pa_lo)
479 else if (mapa->om_pa_lo > mapb->om_pa_lo)
486 moea64_add_ofw_mappings(mmu_t mmup, phandle_t mmu, size_t sz)
488 struct ofw_map translations[sz/sizeof(struct ofw_map)];
494 bzero(translations, sz);
495 if (OF_getprop(mmu, "translations", translations, sz) == -1)
496 panic("moea64_bootstrap: can't get ofw translations");
498 CTR0(KTR_PMAP, "moea64_add_ofw_mappings: translations");
499 sz /= sizeof(*translations);
500 qsort(translations, sz, sizeof (*translations), om_cmp);
502 for (i = 0; i < sz; i++) {
503 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
504 (uint32_t)(translations[i].om_pa_lo), translations[i].om_va,
505 translations[i].om_len);
507 if (translations[i].om_pa_lo % PAGE_SIZE)
508 panic("OFW translation not page-aligned!");
510 pa_base = translations[i].om_pa_lo;
513 pa_base += (vm_offset_t)translations[i].om_pa_hi << 32;
515 if (translations[i].om_pa_hi)
516 panic("OFW translations above 32-bit boundary!");
519 /* Now enter the pages for this mapping */
522 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
523 if (moea64_pvo_find_va(kernel_pmap,
524 translations[i].om_va + off) != NULL)
527 moea64_kenter(mmup, translations[i].om_va + off,
536 moea64_probe_large_page(void)
538 uint16_t pvr = mfpvr() >> 16;
544 powerpc_sync(); isync();
545 mtspr(SPR_HID4, mfspr(SPR_HID4) & ~HID4_970_DISABLE_LG_PG);
546 powerpc_sync(); isync();
550 moea64_large_page_size = 0x1000000; /* 16 MB */
551 moea64_large_page_shift = 24;
554 moea64_large_page_size = 0;
557 moea64_large_page_mask = moea64_large_page_size - 1;
561 moea64_bootstrap_slb_prefault(vm_offset_t va, int large)
568 cache = PCPU_GET(slb);
569 esid = va >> ADDR_SR_SHFT;
570 slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
572 for (i = 0; i < 64; i++) {
573 if (cache[i].slbe == (slbe | i))
578 entry.slbv = KERNEL_VSID(esid) << SLBV_VSID_SHIFT;
580 entry.slbv |= SLBV_L;
582 slb_insert_kernel(entry.slbe, entry.slbv);
587 moea64_setup_direct_map(mmu_t mmup, vm_offset_t kernelstart,
588 vm_offset_t kernelend)
592 vm_offset_t size, off;
596 if (moea64_large_page_size == 0)
602 PMAP_LOCK(kernel_pmap);
603 for (i = 0; i < pregions_sz; i++) {
604 for (pa = pregions[i].mr_start; pa < pregions[i].mr_start +
605 pregions[i].mr_size; pa += moea64_large_page_size) {
609 * Set memory access as guarded if prefetch within
610 * the page could exit the available physmem area.
612 if (pa & moea64_large_page_mask) {
613 pa &= moea64_large_page_mask;
616 if (pa + moea64_large_page_size >
617 pregions[i].mr_start + pregions[i].mr_size)
620 moea64_pvo_enter(mmup, kernel_pmap, moea64_upvo_zone,
621 NULL, pa, pa, pte_lo,
622 PVO_WIRED | PVO_LARGE);
625 PMAP_UNLOCK(kernel_pmap);
628 size = sizeof(struct pvo_head) * moea64_pteg_count;
629 off = (vm_offset_t)(moea64_pvo_table);
630 for (pa = off; pa < off + size; pa += PAGE_SIZE)
631 moea64_kenter(mmup, pa, pa);
632 size = BPVO_POOL_SIZE*sizeof(struct pvo_entry);
633 off = (vm_offset_t)(moea64_bpvo_pool);
634 for (pa = off; pa < off + size; pa += PAGE_SIZE)
635 moea64_kenter(mmup, pa, pa);
638 * Map certain important things, like ourselves.
640 * NOTE: We do not map the exception vector space. That code is
641 * used only in real mode, and leaving it unmapped allows us to
642 * catch NULL pointer deferences, instead of making NULL a valid
646 for (pa = kernelstart & ~PAGE_MASK; pa < kernelend;
648 moea64_kenter(mmup, pa, pa);
653 * Allow user to override unmapped_buf_allowed for testing.
654 * XXXKIB Only direct map implementation was tested.
656 if (!TUNABLE_INT_FETCH("vfs.unmapped_buf_allowed",
657 &unmapped_buf_allowed))
658 unmapped_buf_allowed = hw_direct_map;
662 moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
665 vm_size_t physsz, hwphyssz;
667 #ifndef __powerpc64__
668 /* We don't have a direct map since there is no BAT */
671 /* Make sure battable is zero, since we have no BAT */
672 for (i = 0; i < 16; i++) {
673 battable[i].batu = 0;
674 battable[i].batl = 0;
677 moea64_probe_large_page();
679 /* Use a direct map if we have large page support */
680 if (moea64_large_page_size > 0)
686 /* Get physical memory regions from firmware */
687 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
688 CTR0(KTR_PMAP, "moea64_bootstrap: physical memory");
690 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
691 panic("moea64_bootstrap: phys_avail too small");
693 phys_avail_count = 0;
696 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
697 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
698 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
699 regions[i].mr_start + regions[i].mr_size,
702 (physsz + regions[i].mr_size) >= hwphyssz) {
703 if (physsz < hwphyssz) {
704 phys_avail[j] = regions[i].mr_start;
705 phys_avail[j + 1] = regions[i].mr_start +
712 phys_avail[j] = regions[i].mr_start;
713 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
715 physsz += regions[i].mr_size;
718 /* Check for overlap with the kernel and exception vectors */
719 for (j = 0; j < 2*phys_avail_count; j+=2) {
720 if (phys_avail[j] < EXC_LAST)
721 phys_avail[j] += EXC_LAST;
723 if (kernelstart >= phys_avail[j] &&
724 kernelstart < phys_avail[j+1]) {
725 if (kernelend < phys_avail[j+1]) {
726 phys_avail[2*phys_avail_count] =
727 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
728 phys_avail[2*phys_avail_count + 1] =
733 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
736 if (kernelend >= phys_avail[j] &&
737 kernelend < phys_avail[j+1]) {
738 if (kernelstart > phys_avail[j]) {
739 phys_avail[2*phys_avail_count] = phys_avail[j];
740 phys_avail[2*phys_avail_count + 1] =
741 kernelstart & ~PAGE_MASK;
745 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
749 physmem = btoc(physsz);
752 moea64_pteg_count = PTEGCOUNT;
754 moea64_pteg_count = 0x1000;
756 while (moea64_pteg_count < physmem)
757 moea64_pteg_count <<= 1;
759 moea64_pteg_count >>= 1;
760 #endif /* PTEGCOUNT */
764 moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
773 moea64_pteg_mask = moea64_pteg_count - 1;
776 * Allocate pv/overflow lists.
778 size = sizeof(struct pvo_head) * moea64_pteg_count;
780 moea64_pvo_table = (struct pvo_head *)moea64_bootstrap_alloc(size,
782 CTR1(KTR_PMAP, "moea64_bootstrap: PVO table at %p", moea64_pvo_table);
785 for (i = 0; i < moea64_pteg_count; i++)
786 LIST_INIT(&moea64_pvo_table[i]);
790 * Initialize the lock that synchronizes access to the pteg and pvo
793 rw_init_flags(&moea64_table_lock, "pmap tables", RW_RECURSE);
794 mtx_init(&moea64_slb_mutex, "SLB table", NULL, MTX_DEF);
797 * Initialise the unmanaged pvo pool.
799 moea64_bpvo_pool = (struct pvo_entry *)moea64_bootstrap_alloc(
800 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
801 moea64_bpvo_pool_index = 0;
804 * Make sure kernel vsid is allocated as well as VSID 0.
806 #ifndef __powerpc64__
807 moea64_vsid_bitmap[(KERNEL_VSIDBITS & (NVSIDS - 1)) / VSID_NBPW]
808 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
809 moea64_vsid_bitmap[0] |= 1;
813 * Initialize the kernel pmap (which is statically allocated).
816 for (i = 0; i < 64; i++) {
817 pcpup->pc_slb[i].slbv = 0;
818 pcpup->pc_slb[i].slbe = 0;
821 for (i = 0; i < 16; i++)
822 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
825 kernel_pmap->pmap_phys = kernel_pmap;
826 CPU_FILL(&kernel_pmap->pm_active);
827 RB_INIT(&kernel_pmap->pmap_pvo);
829 PMAP_LOCK_INIT(kernel_pmap);
832 * Now map in all the other buffers we allocated earlier
835 moea64_setup_direct_map(mmup, kernelstart, kernelend);
839 moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
850 * Set up the Open Firmware pmap and add its mappings if not in real
854 chosen = OF_finddevice("/chosen");
855 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1) {
856 mmu = OF_instance_to_package(mmui);
857 if (mmu == -1 || (sz = OF_getproplen(mmu, "translations")) == -1)
859 if (sz > 6144 /* tmpstksz - 2 KB headroom */)
860 panic("moea64_bootstrap: too many ofw translations");
863 moea64_add_ofw_mappings(mmup, mmu, sz);
867 * Calculate the last available physical address.
869 for (i = 0; phys_avail[i + 2] != 0; i += 2)
871 Maxmem = powerpc_btop(phys_avail[i + 1]);
874 * Initialize MMU and remap early physical mappings
876 MMU_CPU_BOOTSTRAP(mmup,0);
877 mtmsr(mfmsr() | PSL_DR | PSL_IR);
879 bs_remap_earlyboot();
882 * Set the start and end of kva.
884 virtual_avail = VM_MIN_KERNEL_ADDRESS;
885 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
888 * Map the entire KVA range into the SLB. We must not fault there.
891 for (va = virtual_avail; va < virtual_end; va += SEGMENT_LENGTH)
892 moea64_bootstrap_slb_prefault(va, 0);
896 * Figure out how far we can extend virtual_end into segment 16
897 * without running into existing mappings. Segment 16 is guaranteed
898 * to contain neither RAM nor devices (at least on Apple hardware),
899 * but will generally contain some OFW mappings we should not
903 #ifndef __powerpc64__ /* KVA is in high memory on PPC64 */
904 PMAP_LOCK(kernel_pmap);
905 while (virtual_end < VM_MAX_KERNEL_ADDRESS &&
906 moea64_pvo_find_va(kernel_pmap, virtual_end+1) == NULL)
907 virtual_end += PAGE_SIZE;
908 PMAP_UNLOCK(kernel_pmap);
912 * Allocate a kernel stack with a guard page for thread0 and map it
913 * into the kernel page map.
915 pa = moea64_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
916 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
917 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
918 CTR2(KTR_PMAP, "moea64_bootstrap: kstack0 at %#x (%#x)", pa, va);
919 thread0.td_kstack = va;
920 thread0.td_kstack_pages = KSTACK_PAGES;
921 for (i = 0; i < KSTACK_PAGES; i++) {
922 moea64_kenter(mmup, va, pa);
928 * Allocate virtual address space for the message buffer.
930 pa = msgbuf_phys = moea64_bootstrap_alloc(msgbufsize, PAGE_SIZE);
931 msgbufp = (struct msgbuf *)virtual_avail;
933 virtual_avail += round_page(msgbufsize);
934 while (va < virtual_avail) {
935 moea64_kenter(mmup, va, pa);
941 * Allocate virtual address space for the dynamic percpu area.
943 pa = moea64_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
944 dpcpu = (void *)virtual_avail;
946 virtual_avail += DPCPU_SIZE;
947 while (va < virtual_avail) {
948 moea64_kenter(mmup, va, pa);
952 dpcpu_init(dpcpu, 0);
955 * Allocate some things for page zeroing. We put this directly
956 * in the page table, marked with LPTE_LOCKED, to avoid any
957 * of the PVO book-keeping or other parts of the VM system
958 * from even knowing that this hack exists.
961 if (!hw_direct_map) {
962 mtx_init(&moea64_scratchpage_mtx, "pvo zero page", NULL,
964 for (i = 0; i < 2; i++) {
965 moea64_scratchpage_va[i] = (virtual_end+1) - PAGE_SIZE;
966 virtual_end -= PAGE_SIZE;
968 moea64_kenter(mmup, moea64_scratchpage_va[i], 0);
970 moea64_scratchpage_pvo[i] = moea64_pvo_find_va(
971 kernel_pmap, (vm_offset_t)moea64_scratchpage_va[i]);
973 moea64_scratchpage_pte[i] = MOEA64_PVO_TO_PTE(
974 mmup, moea64_scratchpage_pvo[i]);
975 moea64_scratchpage_pvo[i]->pvo_pte.lpte.pte_hi
977 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[i],
978 &moea64_scratchpage_pvo[i]->pvo_pte.lpte,
979 moea64_scratchpage_pvo[i]->pvo_vpn);
986 * Activate a user pmap. The pmap must be activated before its address
987 * space can be accessed in any way.
990 moea64_activate(mmu_t mmu, struct thread *td)
994 pm = &td->td_proc->p_vmspace->vm_pmap;
995 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
998 PCPU_SET(userslb, pm->pm_slb);
1000 PCPU_SET(curpmap, pm->pmap_phys);
1005 moea64_deactivate(mmu_t mmu, struct thread *td)
1009 pm = &td->td_proc->p_vmspace->vm_pmap;
1010 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1011 #ifdef __powerpc64__
1012 PCPU_SET(userslb, NULL);
1014 PCPU_SET(curpmap, NULL);
1019 moea64_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1021 struct pvo_entry *pvo;
1028 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
1031 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1034 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1035 pm->pm_stats.wired_count++;
1036 pvo->pvo_vaddr |= PVO_WIRED;
1037 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
1039 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1040 pm->pm_stats.wired_count--;
1041 pvo->pvo_vaddr &= ~PVO_WIRED;
1042 pvo->pvo_pte.lpte.pte_hi &= ~LPTE_WIRED;
1046 /* Update wiring flag in page table. */
1047 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1051 * If we are wiring the page, and it wasn't in the
1052 * page table before, add it.
1054 vsid = PVO_VSID(pvo);
1055 ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
1056 pvo->pvo_vaddr & PVO_LARGE);
1058 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
1061 PVO_PTEGIDX_CLR(pvo);
1062 PVO_PTEGIDX_SET(pvo, i);
1072 * This goes through and sets the physical address of our
1073 * special scratch PTE to the PA we want to zero or copy. Because
1074 * of locking issues (this can get called in pvo_enter() by
1075 * the UMA allocator), we can't use most other utility functions here
1079 void moea64_set_scratchpage_pa(mmu_t mmup, int which, vm_offset_t pa) {
1081 KASSERT(!hw_direct_map, ("Using OEA64 scratchpage with a direct map!"));
1082 mtx_assert(&moea64_scratchpage_mtx, MA_OWNED);
1084 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo &=
1085 ~(LPTE_WIMG | LPTE_RPGN);
1086 moea64_scratchpage_pvo[which]->pvo_pte.lpte.pte_lo |=
1087 moea64_calc_wimg(pa, VM_MEMATTR_DEFAULT) | (uint64_t)pa;
1088 MOEA64_PTE_CHANGE(mmup, moea64_scratchpage_pte[which],
1089 &moea64_scratchpage_pvo[which]->pvo_pte.lpte,
1090 moea64_scratchpage_pvo[which]->pvo_vpn);
1095 moea64_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1100 dst = VM_PAGE_TO_PHYS(mdst);
1101 src = VM_PAGE_TO_PHYS(msrc);
1103 if (hw_direct_map) {
1104 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1106 mtx_lock(&moea64_scratchpage_mtx);
1108 moea64_set_scratchpage_pa(mmu, 0, src);
1109 moea64_set_scratchpage_pa(mmu, 1, dst);
1111 bcopy((void *)moea64_scratchpage_va[0],
1112 (void *)moea64_scratchpage_va[1], PAGE_SIZE);
1114 mtx_unlock(&moea64_scratchpage_mtx);
1119 moea64_copy_pages_dmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1120 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1123 vm_offset_t a_pg_offset, b_pg_offset;
1126 while (xfersize > 0) {
1127 a_pg_offset = a_offset & PAGE_MASK;
1128 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1129 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1131 b_pg_offset = b_offset & PAGE_MASK;
1132 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1133 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1135 bcopy(a_cp, b_cp, cnt);
1143 moea64_copy_pages_nodmap(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1144 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1147 vm_offset_t a_pg_offset, b_pg_offset;
1150 mtx_lock(&moea64_scratchpage_mtx);
1151 while (xfersize > 0) {
1152 a_pg_offset = a_offset & PAGE_MASK;
1153 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1154 moea64_set_scratchpage_pa(mmu, 0,
1155 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
1156 a_cp = (char *)moea64_scratchpage_va[0] + a_pg_offset;
1157 b_pg_offset = b_offset & PAGE_MASK;
1158 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1159 moea64_set_scratchpage_pa(mmu, 1,
1160 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
1161 b_cp = (char *)moea64_scratchpage_va[1] + b_pg_offset;
1162 bcopy(a_cp, b_cp, cnt);
1167 mtx_unlock(&moea64_scratchpage_mtx);
1171 moea64_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1172 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1175 if (hw_direct_map) {
1176 moea64_copy_pages_dmap(mmu, ma, a_offset, mb, b_offset,
1179 moea64_copy_pages_nodmap(mmu, ma, a_offset, mb, b_offset,
1185 moea64_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1187 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1189 if (size + off > PAGE_SIZE)
1190 panic("moea64_zero_page: size + off > PAGE_SIZE");
1192 if (hw_direct_map) {
1193 bzero((caddr_t)pa + off, size);
1195 mtx_lock(&moea64_scratchpage_mtx);
1196 moea64_set_scratchpage_pa(mmu, 0, pa);
1197 bzero((caddr_t)moea64_scratchpage_va[0] + off, size);
1198 mtx_unlock(&moea64_scratchpage_mtx);
1203 * Zero a page of physical memory by temporarily mapping it
1206 moea64_zero_page(mmu_t mmu, vm_page_t m)
1208 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1209 vm_offset_t va, off;
1211 if (!hw_direct_map) {
1212 mtx_lock(&moea64_scratchpage_mtx);
1214 moea64_set_scratchpage_pa(mmu, 0, pa);
1215 va = moea64_scratchpage_va[0];
1220 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1221 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
1224 mtx_unlock(&moea64_scratchpage_mtx);
1228 moea64_zero_page_idle(mmu_t mmu, vm_page_t m)
1231 moea64_zero_page(mmu, m);
1235 * Map the given physical page at the specified virtual address in the
1236 * target pmap with the protection requested. If specified the page
1237 * will be wired down.
1241 moea64_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1242 vm_prot_t prot, boolean_t wired)
1244 struct pvo_head *pvo_head;
1251 if (!moea64_initialized) {
1254 zone = moea64_upvo_zone;
1257 pvo_head = vm_page_to_pvoh(m);
1259 zone = moea64_mpvo_zone;
1260 pvo_flags = PVO_MANAGED;
1263 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1264 VM_OBJECT_ASSERT_LOCKED(m->object);
1266 /* XXX change the pvo head for fake pages */
1267 if ((m->oflags & VPO_UNMANAGED) != 0) {
1268 pvo_flags &= ~PVO_MANAGED;
1270 zone = moea64_upvo_zone;
1273 pte_lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1275 if (prot & VM_PROT_WRITE) {
1277 if (pmap_bootstrapped &&
1278 (m->oflags & VPO_UNMANAGED) == 0)
1279 vm_page_aflag_set(m, PGA_WRITEABLE);
1283 if ((prot & VM_PROT_EXECUTE) == 0)
1284 pte_lo |= LPTE_NOEXEC;
1287 pvo_flags |= PVO_WIRED;
1291 error = moea64_pvo_enter(mmu, pmap, zone, pvo_head, va,
1292 VM_PAGE_TO_PHYS(m), pte_lo, pvo_flags);
1297 * Flush the page from the instruction cache if this page is
1298 * mapped executable and cacheable.
1300 if (pmap != kernel_pmap && !(m->aflags & PGA_EXECUTABLE) &&
1301 (pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1302 vm_page_aflag_set(m, PGA_EXECUTABLE);
1303 moea64_syncicache(mmu, pmap, va, VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1308 moea64_syncicache(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t pa,
1313 * This is much trickier than on older systems because
1314 * we can't sync the icache on physical addresses directly
1315 * without a direct map. Instead we check a couple of cases
1316 * where the memory is already mapped in and, failing that,
1317 * use the same trick we use for page zeroing to create
1318 * a temporary mapping for this physical address.
1321 if (!pmap_bootstrapped) {
1323 * If PMAP is not bootstrapped, we are likely to be
1326 __syncicache((void *)pa, sz);
1327 } else if (pmap == kernel_pmap) {
1328 __syncicache((void *)va, sz);
1329 } else if (hw_direct_map) {
1330 __syncicache((void *)pa, sz);
1332 /* Use the scratch page to set up a temp mapping */
1334 mtx_lock(&moea64_scratchpage_mtx);
1336 moea64_set_scratchpage_pa(mmu, 1, pa & ~ADDR_POFF);
1337 __syncicache((void *)(moea64_scratchpage_va[1] +
1338 (va & ADDR_POFF)), sz);
1340 mtx_unlock(&moea64_scratchpage_mtx);
1345 * Maps a sequence of resident pages belonging to the same object.
1346 * The sequence begins with the given page m_start. This page is
1347 * mapped at the given virtual address start. Each subsequent page is
1348 * mapped at a virtual address that is offset from start by the same
1349 * amount as the page is offset from m_start within the object. The
1350 * last page in the sequence is the page with the largest offset from
1351 * m_start that can be mapped at a virtual address less than the given
1352 * virtual address end. Not every virtual page between start and end
1353 * is mapped; only those for which a resident page exists with the
1354 * corresponding offset from m_start are mapped.
1357 moea64_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1358 vm_page_t m_start, vm_prot_t prot)
1361 vm_pindex_t diff, psize;
1363 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1365 psize = atop(end - start);
1367 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1368 moea64_enter(mmu, pm, start + ptoa(diff), m, prot &
1369 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1370 m = TAILQ_NEXT(m, listq);
1375 moea64_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1379 moea64_enter(mmu, pm, va, m,
1380 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1384 moea64_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1386 struct pvo_entry *pvo;
1390 pvo = moea64_pvo_find_va(pm, va);
1394 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
1395 (va - PVO_VADDR(pvo));
1401 * Atomically extract and hold the physical page with the given
1402 * pmap and virtual address pair if that mapping permits the given
1406 moea64_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1408 struct pvo_entry *pvo;
1416 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1417 if (pvo != NULL && (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
1418 ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) == LPTE_RW ||
1419 (prot & VM_PROT_WRITE) == 0)) {
1420 if (vm_page_pa_tryrelock(pmap,
1421 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, &pa))
1423 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1431 static mmu_t installed_mmu;
1434 moea64_uma_page_alloc(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
1437 * This entire routine is a horrible hack to avoid bothering kmem
1438 * for new KVA addresses. Because this can get called from inside
1439 * kmem allocation routines, calling kmem for a new address here
1440 * can lead to multiply locking non-recursive mutexes.
1445 int pflags, needed_lock;
1447 *flags = UMA_SLAB_PRIV;
1448 needed_lock = !PMAP_LOCKED(kernel_pmap);
1449 pflags = malloc2vm_flags(wait) | VM_ALLOC_WIRED;
1452 m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
1454 if (wait & M_NOWAIT)
1461 va = VM_PAGE_TO_PHYS(m);
1465 PMAP_LOCK(kernel_pmap);
1467 moea64_pvo_enter(installed_mmu, kernel_pmap, moea64_upvo_zone,
1468 NULL, va, VM_PAGE_TO_PHYS(m), LPTE_M, PVO_WIRED | PVO_BOOTSTRAP);
1471 PMAP_UNLOCK(kernel_pmap);
1474 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
1475 bzero((void *)va, PAGE_SIZE);
1480 extern int elf32_nxstack;
1483 moea64_init(mmu_t mmu)
1486 CTR0(KTR_PMAP, "moea64_init");
1488 moea64_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1489 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1490 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1491 moea64_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1492 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1493 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1495 if (!hw_direct_map) {
1496 installed_mmu = mmu;
1497 uma_zone_set_allocf(moea64_upvo_zone,moea64_uma_page_alloc);
1498 uma_zone_set_allocf(moea64_mpvo_zone,moea64_uma_page_alloc);
1501 #ifdef COMPAT_FREEBSD32
1505 moea64_initialized = TRUE;
1509 moea64_is_referenced(mmu_t mmu, vm_page_t m)
1512 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1513 ("moea64_is_referenced: page %p is not managed", m));
1514 return (moea64_query_bit(mmu, m, PTE_REF));
1518 moea64_is_modified(mmu_t mmu, vm_page_t m)
1521 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1522 ("moea64_is_modified: page %p is not managed", m));
1525 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1526 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1527 * is clear, no PTEs can have LPTE_CHG set.
1529 VM_OBJECT_ASSERT_WLOCKED(m->object);
1530 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1532 return (moea64_query_bit(mmu, m, LPTE_CHG));
1536 moea64_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1538 struct pvo_entry *pvo;
1542 pvo = moea64_pvo_find_va(pmap, va & ~ADDR_POFF);
1543 rv = pvo == NULL || (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0;
1549 moea64_clear_reference(mmu_t mmu, vm_page_t m)
1552 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1553 ("moea64_clear_reference: page %p is not managed", m));
1554 moea64_clear_bit(mmu, m, LPTE_REF);
1558 moea64_clear_modify(mmu_t mmu, vm_page_t m)
1561 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1562 ("moea64_clear_modify: page %p is not managed", m));
1563 VM_OBJECT_ASSERT_WLOCKED(m->object);
1564 KASSERT(!vm_page_xbusied(m),
1565 ("moea64_clear_modify: page %p is exclusive busied", m));
1568 * If the page is not PGA_WRITEABLE, then no PTEs can have LPTE_CHG
1569 * set. If the object containing the page is locked and the page is
1570 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1572 if ((m->aflags & PGA_WRITEABLE) == 0)
1574 moea64_clear_bit(mmu, m, LPTE_CHG);
1578 * Clear the write and modified bits in each of the given page's mappings.
1581 moea64_remove_write(mmu_t mmu, vm_page_t m)
1583 struct pvo_entry *pvo;
1588 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1589 ("moea64_remove_write: page %p is not managed", m));
1592 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1593 * set by another thread while the object is locked. Thus,
1594 * if PGA_WRITEABLE is clear, no page table entries need updating.
1596 VM_OBJECT_ASSERT_WLOCKED(m->object);
1597 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1601 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1602 pmap = pvo->pvo_pmap;
1604 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
1605 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1606 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1607 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1609 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
1610 lo |= pvo->pvo_pte.lpte.pte_lo;
1611 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_CHG;
1612 MOEA64_PTE_CHANGE(mmu, pt,
1613 &pvo->pvo_pte.lpte, pvo->pvo_vpn);
1614 if (pvo->pvo_pmap == kernel_pmap)
1618 if ((lo & LPTE_CHG) != 0)
1623 vm_page_aflag_clear(m, PGA_WRITEABLE);
1627 * moea64_ts_referenced:
1629 * Return a count of reference bits for a page, clearing those bits.
1630 * It is not necessary for every reference bit to be cleared, but it
1631 * is necessary that 0 only be returned when there are truly no
1632 * reference bits set.
1634 * XXX: The exact number of bits to check and clear is a matter that
1635 * should be tested and standardized at some point in the future for
1636 * optimal aging of shared pages.
1639 moea64_ts_referenced(mmu_t mmu, vm_page_t m)
1642 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1643 ("moea64_ts_referenced: page %p is not managed", m));
1644 return (moea64_clear_bit(mmu, m, LPTE_REF));
1648 * Modify the WIMG settings of all mappings for a page.
1651 moea64_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1653 struct pvo_entry *pvo;
1654 struct pvo_head *pvo_head;
1659 if ((m->oflags & VPO_UNMANAGED) != 0) {
1660 m->md.mdpg_cache_attrs = ma;
1664 pvo_head = vm_page_to_pvoh(m);
1665 lo = moea64_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1667 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1668 pmap = pvo->pvo_pmap;
1670 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1671 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_WIMG;
1672 pvo->pvo_pte.lpte.pte_lo |= lo;
1674 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1676 if (pvo->pvo_pmap == kernel_pmap)
1682 m->md.mdpg_cache_attrs = ma;
1686 * Map a wired page into kernel virtual address space.
1689 moea64_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1694 pte_lo = moea64_calc_wimg(pa, ma);
1697 PMAP_LOCK(kernel_pmap);
1698 error = moea64_pvo_enter(mmu, kernel_pmap, moea64_upvo_zone,
1699 NULL, va, pa, pte_lo, PVO_WIRED);
1700 PMAP_UNLOCK(kernel_pmap);
1703 if (error != 0 && error != ENOENT)
1704 panic("moea64_kenter: failed to enter va %#zx pa %#zx: %d", va,
1709 moea64_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1712 moea64_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1716 * Extract the physical page address associated with the given kernel virtual
1720 moea64_kextract(mmu_t mmu, vm_offset_t va)
1722 struct pvo_entry *pvo;
1726 * Shortcut the direct-mapped case when applicable. We never put
1727 * anything but 1:1 mappings below VM_MIN_KERNEL_ADDRESS.
1729 if (va < VM_MIN_KERNEL_ADDRESS)
1732 PMAP_LOCK(kernel_pmap);
1733 pvo = moea64_pvo_find_va(kernel_pmap, va);
1734 KASSERT(pvo != NULL, ("moea64_kextract: no addr found for %#" PRIxPTR,
1736 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) | (va - PVO_VADDR(pvo));
1737 PMAP_UNLOCK(kernel_pmap);
1742 * Remove a wired page from kernel virtual address space.
1745 moea64_kremove(mmu_t mmu, vm_offset_t va)
1747 moea64_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1751 * Map a range of physical addresses into kernel virtual address space.
1753 * The value passed in *virt is a suggested virtual address for the mapping.
1754 * Architectures which can support a direct-mapped physical to virtual region
1755 * can return the appropriate address within that region, leaving '*virt'
1756 * unchanged. We cannot and therefore do not; *virt is updated with the
1757 * first usable address after the mapped region.
1760 moea64_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1761 vm_paddr_t pa_end, int prot)
1763 vm_offset_t sva, va;
1767 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1768 moea64_kenter(mmu, va, pa_start);
1775 * Returns true if the pmap's pv is one of the first
1776 * 16 pvs linked to from this page. This count may
1777 * be changed upwards or downwards in the future; it
1778 * is only necessary that true be returned for a small
1779 * subset of pmaps for proper page aging.
1782 moea64_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1785 struct pvo_entry *pvo;
1788 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1789 ("moea64_page_exists_quick: page %p is not managed", m));
1793 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1794 if (pvo->pvo_pmap == pmap) {
1806 * Return the number of managed mappings to the given physical page
1810 moea64_page_wired_mappings(mmu_t mmu, vm_page_t m)
1812 struct pvo_entry *pvo;
1816 if ((m->oflags & VPO_UNMANAGED) != 0)
1819 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1820 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1826 static uintptr_t moea64_vsidcontext;
1829 moea64_get_unique_vsid(void) {
1836 __asm __volatile("mftb %0" : "=r"(entropy));
1838 mtx_lock(&moea64_slb_mutex);
1839 for (i = 0; i < NVSIDS; i += VSID_NBPW) {
1843 * Create a new value by mutiplying by a prime and adding in
1844 * entropy from the timebase register. This is to make the
1845 * VSID more random so that the PT hash function collides
1846 * less often. (Note that the prime casues gcc to do shifts
1847 * instead of a multiply.)
1849 moea64_vsidcontext = (moea64_vsidcontext * 0x1105) + entropy;
1850 hash = moea64_vsidcontext & (NVSIDS - 1);
1851 if (hash == 0) /* 0 is special, avoid it */
1854 mask = 1 << (hash & (VSID_NBPW - 1));
1855 hash = (moea64_vsidcontext & VSID_HASHMASK);
1856 if (moea64_vsid_bitmap[n] & mask) { /* collision? */
1857 /* anything free in this bucket? */
1858 if (moea64_vsid_bitmap[n] == 0xffffffff) {
1859 entropy = (moea64_vsidcontext >> 20);
1862 i = ffs(~moea64_vsid_bitmap[n]) - 1;
1864 hash &= VSID_HASHMASK & ~(VSID_NBPW - 1);
1867 KASSERT(!(moea64_vsid_bitmap[n] & mask),
1868 ("Allocating in-use VSID %#zx\n", hash));
1869 moea64_vsid_bitmap[n] |= mask;
1870 mtx_unlock(&moea64_slb_mutex);
1874 mtx_unlock(&moea64_slb_mutex);
1875 panic("%s: out of segments",__func__);
1878 #ifdef __powerpc64__
1880 moea64_pinit(mmu_t mmu, pmap_t pmap)
1883 RB_INIT(&pmap->pmap_pvo);
1885 pmap->pm_slb_tree_root = slb_alloc_tree();
1886 pmap->pm_slb = slb_alloc_user_cache();
1887 pmap->pm_slb_len = 0;
1891 moea64_pinit(mmu_t mmu, pmap_t pmap)
1896 RB_INIT(&pmap->pmap_pvo);
1898 if (pmap_bootstrapped)
1899 pmap->pmap_phys = (pmap_t)moea64_kextract(mmu,
1902 pmap->pmap_phys = pmap;
1905 * Allocate some segment registers for this pmap.
1907 hash = moea64_get_unique_vsid();
1909 for (i = 0; i < 16; i++)
1910 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1912 KASSERT(pmap->pm_sr[0] != 0, ("moea64_pinit: pm_sr[0] = 0"));
1917 * Initialize the pmap associated with process 0.
1920 moea64_pinit0(mmu_t mmu, pmap_t pm)
1924 moea64_pinit(mmu, pm);
1925 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1929 * Set the physical protection on the specified range of this map as requested.
1932 moea64_pvo_protect(mmu_t mmu, pmap_t pm, struct pvo_entry *pvo, vm_prot_t prot)
1938 PMAP_LOCK_ASSERT(pm, MA_OWNED);
1941 * Grab the PTE pointer before we diddle with the cached PTE
1944 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
1947 * Change the protection of the page.
1949 oldlo = pvo->pvo_pte.lpte.pte_lo;
1950 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_PP;
1951 pvo->pvo_pte.lpte.pte_lo &= ~LPTE_NOEXEC;
1952 if ((prot & VM_PROT_EXECUTE) == 0)
1953 pvo->pvo_pte.lpte.pte_lo |= LPTE_NOEXEC;
1954 if (prot & VM_PROT_WRITE)
1955 pvo->pvo_pte.lpte.pte_lo |= LPTE_BW;
1957 pvo->pvo_pte.lpte.pte_lo |= LPTE_BR;
1959 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
1962 * If the PVO is in the page table, update that pte as well.
1965 MOEA64_PTE_CHANGE(mmu, pt, &pvo->pvo_pte.lpte,
1967 if (pm != kernel_pmap && pg != NULL && !(pg->aflags & PGA_EXECUTABLE) &&
1968 (pvo->pvo_pte.lpte.pte_lo & (LPTE_I | LPTE_G | LPTE_NOEXEC)) == 0) {
1969 if ((pg->oflags & VPO_UNMANAGED) == 0)
1970 vm_page_aflag_set(pg, PGA_EXECUTABLE);
1971 moea64_syncicache(mmu, pm, PVO_VADDR(pvo),
1972 pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN, PAGE_SIZE);
1976 * Update vm about the REF/CHG bits if the page is managed and we have
1977 * removed write access.
1979 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED &&
1980 (oldlo & LPTE_PP) != LPTE_BR && !(prot & VM_PROT_WRITE)) {
1982 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
1984 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
1985 vm_page_aflag_set(pg, PGA_REFERENCED);
1991 moea64_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1994 struct pvo_entry *pvo, *tpvo, key;
1996 CTR4(KTR_PMAP, "moea64_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm,
1999 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
2000 ("moea64_protect: non current pmap"));
2002 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2003 moea64_remove(mmu, pm, sva, eva);
2009 key.pvo_vaddr = sva;
2010 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2011 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2012 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2013 moea64_pvo_protect(mmu, pm, pvo, prot);
2020 * Map a list of wired pages into kernel virtual address space. This is
2021 * intended for temporary mappings which do not need page modification or
2022 * references recorded. Existing mappings in the region are overwritten.
2025 moea64_qenter(mmu_t mmu, vm_offset_t va, vm_page_t *m, int count)
2027 while (count-- > 0) {
2028 moea64_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2035 * Remove page mappings from kernel virtual address space. Intended for
2036 * temporary mappings entered by moea64_qenter.
2039 moea64_qremove(mmu_t mmu, vm_offset_t va, int count)
2041 while (count-- > 0) {
2042 moea64_kremove(mmu, va);
2048 moea64_release_vsid(uint64_t vsid)
2052 mtx_lock(&moea64_slb_mutex);
2053 idx = vsid & (NVSIDS-1);
2054 mask = 1 << (idx % VSID_NBPW);
2056 KASSERT(moea64_vsid_bitmap[idx] & mask,
2057 ("Freeing unallocated VSID %#jx", vsid));
2058 moea64_vsid_bitmap[idx] &= ~mask;
2059 mtx_unlock(&moea64_slb_mutex);
2064 moea64_release(mmu_t mmu, pmap_t pmap)
2068 * Free segment registers' VSIDs
2070 #ifdef __powerpc64__
2071 slb_free_tree(pmap);
2072 slb_free_user_cache(pmap->pm_slb);
2074 KASSERT(pmap->pm_sr[0] != 0, ("moea64_release: pm_sr[0] = 0"));
2076 moea64_release_vsid(VSID_TO_HASH(pmap->pm_sr[0]));
2081 * Remove all pages mapped by the specified pmap
2084 moea64_remove_pages(mmu_t mmu, pmap_t pm)
2086 struct pvo_entry *pvo, *tpvo;
2090 RB_FOREACH_SAFE(pvo, pvo_tree, &pm->pmap_pvo, tpvo) {
2091 if (!(pvo->pvo_vaddr & PVO_WIRED))
2092 moea64_pvo_remove(mmu, pvo);
2099 * Remove the given range of addresses from the specified map.
2102 moea64_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
2104 struct pvo_entry *pvo, *tpvo, key;
2107 * Perform an unsynchronized read. This is, however, safe.
2109 if (pm->pm_stats.resident_count == 0)
2114 key.pvo_vaddr = sva;
2115 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
2116 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
2117 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
2118 moea64_pvo_remove(mmu, pvo);
2125 * Remove physical page from all pmaps in which it resides. moea64_pvo_remove()
2126 * will reflect changes in pte's back to the vm_page.
2129 moea64_remove_all(mmu_t mmu, vm_page_t m)
2131 struct pvo_entry *pvo, *next_pvo;
2135 LIST_FOREACH_SAFE(pvo, vm_page_to_pvoh(m), pvo_vlink, next_pvo) {
2136 pmap = pvo->pvo_pmap;
2138 moea64_pvo_remove(mmu, pvo);
2142 if ((m->aflags & PGA_WRITEABLE) && moea64_is_modified(mmu, m))
2144 vm_page_aflag_clear(m, PGA_WRITEABLE);
2145 vm_page_aflag_clear(m, PGA_EXECUTABLE);
2149 * Allocate a physical page of memory directly from the phys_avail map.
2150 * Can only be called from moea64_bootstrap before avail start and end are
2154 moea64_bootstrap_alloc(vm_size_t size, u_int align)
2159 size = round_page(size);
2160 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
2162 s = (phys_avail[i] + align - 1) & ~(align - 1);
2167 if (s < phys_avail[i] || e > phys_avail[i + 1])
2170 if (s + size > platform_real_maxaddr())
2173 if (s == phys_avail[i]) {
2174 phys_avail[i] += size;
2175 } else if (e == phys_avail[i + 1]) {
2176 phys_avail[i + 1] -= size;
2178 for (j = phys_avail_count * 2; j > i; j -= 2) {
2179 phys_avail[j] = phys_avail[j - 2];
2180 phys_avail[j + 1] = phys_avail[j - 1];
2183 phys_avail[i + 3] = phys_avail[i + 1];
2184 phys_avail[i + 1] = s;
2185 phys_avail[i + 2] = e;
2191 panic("moea64_bootstrap_alloc: could not allocate memory");
2195 moea64_pvo_enter(mmu_t mmu, pmap_t pm, uma_zone_t zone,
2196 struct pvo_head *pvo_head, vm_offset_t va, vm_offset_t pa,
2197 uint64_t pte_lo, int flags)
2199 struct pvo_entry *pvo;
2207 * One nasty thing that can happen here is that the UMA calls to
2208 * allocate new PVOs need to map more memory, which calls pvo_enter(),
2209 * which calls UMA...
2211 * We break the loop by detecting recursion and allocating out of
2212 * the bootstrap pool.
2216 bootstrap = (flags & PVO_BOOTSTRAP);
2218 if (!moea64_initialized)
2221 PMAP_LOCK_ASSERT(pm, MA_OWNED);
2222 rw_assert(&moea64_table_lock, RA_WLOCKED);
2225 * Compute the PTE Group index.
2228 vsid = va_to_vsid(pm, va);
2229 ptegidx = va_to_pteg(vsid, va, flags & PVO_LARGE);
2232 * Remove any existing mapping for this page. Reuse the pvo entry if
2233 * there is a mapping.
2235 moea64_pvo_enter_calls++;
2237 LIST_FOREACH(pvo, &moea64_pvo_table[ptegidx], pvo_olink) {
2238 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2239 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) == pa &&
2240 (pvo->pvo_pte.lpte.pte_lo & (LPTE_NOEXEC | LPTE_PP))
2241 == (pte_lo & (LPTE_NOEXEC | LPTE_PP))) {
2242 if (!(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID)) {
2243 /* Re-insert if spilled */
2244 i = MOEA64_PTE_INSERT(mmu, ptegidx,
2245 &pvo->pvo_pte.lpte);
2247 PVO_PTEGIDX_SET(pvo, i);
2248 moea64_pte_overflow--;
2252 moea64_pvo_remove(mmu, pvo);
2258 * If we aren't overwriting a mapping, try to allocate.
2261 if (moea64_bpvo_pool_index >= BPVO_POOL_SIZE) {
2262 panic("moea64_enter: bpvo pool exhausted, %d, %d, %zd",
2263 moea64_bpvo_pool_index, BPVO_POOL_SIZE,
2264 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
2266 pvo = &moea64_bpvo_pool[moea64_bpvo_pool_index];
2267 moea64_bpvo_pool_index++;
2270 pvo = uma_zalloc(zone, M_NOWAIT);
2276 moea64_pvo_entries++;
2277 pvo->pvo_vaddr = va;
2278 pvo->pvo_vpn = (uint64_t)((va & ADDR_PIDX) >> ADDR_PIDX_SHFT)
2281 LIST_INSERT_HEAD(&moea64_pvo_table[ptegidx], pvo, pvo_olink);
2282 pvo->pvo_vaddr &= ~ADDR_POFF;
2284 if (flags & PVO_WIRED)
2285 pvo->pvo_vaddr |= PVO_WIRED;
2286 if (pvo_head != NULL)
2287 pvo->pvo_vaddr |= PVO_MANAGED;
2289 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
2290 if (flags & PVO_LARGE)
2291 pvo->pvo_vaddr |= PVO_LARGE;
2293 moea64_pte_create(&pvo->pvo_pte.lpte, vsid, va,
2294 (uint64_t)(pa) | pte_lo, flags);
2299 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2302 * Remember if the list was empty and therefore will be the first
2305 if (pvo_head != NULL) {
2306 if (LIST_FIRST(pvo_head) == NULL)
2308 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2311 if (pvo->pvo_vaddr & PVO_WIRED) {
2312 pvo->pvo_pte.lpte.pte_hi |= LPTE_WIRED;
2313 pm->pm_stats.wired_count++;
2315 pm->pm_stats.resident_count++;
2318 * We hope this succeeds but it isn't required.
2320 i = MOEA64_PTE_INSERT(mmu, ptegidx, &pvo->pvo_pte.lpte);
2322 PVO_PTEGIDX_SET(pvo, i);
2324 panic("moea64_pvo_enter: overflow");
2325 moea64_pte_overflow++;
2328 if (pm == kernel_pmap)
2331 #ifdef __powerpc64__
2333 * Make sure all our bootstrap mappings are in the SLB as soon
2334 * as virtual memory is switched on.
2336 if (!pmap_bootstrapped)
2337 moea64_bootstrap_slb_prefault(va, flags & PVO_LARGE);
2340 return (first ? ENOENT : 0);
2344 moea64_pvo_remove(mmu_t mmu, struct pvo_entry *pvo)
2349 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
2350 rw_assert(&moea64_table_lock, RA_WLOCKED);
2353 * If there is an active pte entry, we need to deactivate it (and
2354 * save the ref & cfg bits).
2356 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2358 MOEA64_PTE_UNSET(mmu, pt, &pvo->pvo_pte.lpte, pvo->pvo_vpn);
2359 PVO_PTEGIDX_CLR(pvo);
2361 moea64_pte_overflow--;
2365 * Update our statistics.
2367 pvo->pvo_pmap->pm_stats.resident_count--;
2368 if (pvo->pvo_vaddr & PVO_WIRED)
2369 pvo->pvo_pmap->pm_stats.wired_count--;
2372 * Remove this PVO from the pmap list.
2374 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2377 * Remove this from the overflow list and return it to the pool
2378 * if we aren't going to reuse it.
2380 LIST_REMOVE(pvo, pvo_olink);
2383 * Update vm about the REF/CHG bits if the page is managed.
2385 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN);
2387 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED && pg != NULL) {
2388 LIST_REMOVE(pvo, pvo_vlink);
2389 if ((pvo->pvo_pte.lpte.pte_lo & LPTE_PP) != LPTE_BR) {
2390 if (pvo->pvo_pte.lpte.pte_lo & LPTE_CHG)
2392 if (pvo->pvo_pte.lpte.pte_lo & LPTE_REF)
2393 vm_page_aflag_set(pg, PGA_REFERENCED);
2394 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2395 vm_page_aflag_clear(pg, PGA_WRITEABLE);
2397 if (LIST_EMPTY(vm_page_to_pvoh(pg)))
2398 vm_page_aflag_clear(pg, PGA_EXECUTABLE);
2401 moea64_pvo_entries--;
2402 moea64_pvo_remove_calls++;
2404 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2405 uma_zfree((pvo->pvo_vaddr & PVO_MANAGED) ? moea64_mpvo_zone :
2406 moea64_upvo_zone, pvo);
2409 static struct pvo_entry *
2410 moea64_pvo_find_va(pmap_t pm, vm_offset_t va)
2412 struct pvo_entry key;
2414 key.pvo_vaddr = va & ~ADDR_POFF;
2415 return (RB_FIND(pvo_tree, &pm->pmap_pvo, &key));
2419 moea64_query_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2421 struct pvo_entry *pvo;
2425 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2427 * See if we saved the bit off. If so, return success.
2429 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2436 * No luck, now go through the hard part of looking at the PTEs
2437 * themselves. Sync so that any pending REF/CHG bits are flushed to
2441 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2444 * See if this pvo has a valid PTE. if so, fetch the
2445 * REF/CHG bits from the valid PTE. If the appropriate
2446 * ptebit is set, return success.
2448 PMAP_LOCK(pvo->pvo_pmap);
2449 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2451 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2452 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2453 PMAP_UNLOCK(pvo->pvo_pmap);
2458 PMAP_UNLOCK(pvo->pvo_pmap);
2466 moea64_clear_bit(mmu_t mmu, vm_page_t m, u_int64_t ptebit)
2469 struct pvo_entry *pvo;
2473 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2474 * we can reset the right ones). note that since the pvo entries and
2475 * list heads are accessed via BAT0 and are never placed in the page
2476 * table, we don't have to worry about further accesses setting the
2482 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2483 * valid pte clear the ptebit from the valid pte.
2487 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2488 PMAP_LOCK(pvo->pvo_pmap);
2489 pt = MOEA64_PVO_TO_PTE(mmu, pvo);
2491 MOEA64_PTE_SYNCH(mmu, pt, &pvo->pvo_pte.lpte);
2492 if (pvo->pvo_pte.lpte.pte_lo & ptebit) {
2494 MOEA64_PTE_CLEAR(mmu, pt, &pvo->pvo_pte.lpte,
2495 pvo->pvo_vpn, ptebit);
2498 pvo->pvo_pte.lpte.pte_lo &= ~ptebit;
2499 PMAP_UNLOCK(pvo->pvo_pmap);
2507 moea64_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2509 struct pvo_entry *pvo, key;
2513 PMAP_LOCK(kernel_pmap);
2514 key.pvo_vaddr = ppa = pa & ~ADDR_POFF;
2515 for (pvo = RB_FIND(pvo_tree, &kernel_pmap->pmap_pvo, &key);
2516 ppa < pa + size; ppa += PAGE_SIZE,
2517 pvo = RB_NEXT(pvo_tree, &kernel_pmap->pmap_pvo, pvo)) {
2519 (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) != ppa) {
2524 PMAP_UNLOCK(kernel_pmap);
2530 * Map a set of physical memory pages into the kernel virtual
2531 * address space. Return a pointer to where it is mapped. This
2532 * routine is intended to be used for mapping device memory,
2536 moea64_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2538 vm_offset_t va, tmpva, ppa, offset;
2540 ppa = trunc_page(pa);
2541 offset = pa & PAGE_MASK;
2542 size = roundup2(offset + size, PAGE_SIZE);
2544 va = kva_alloc(size);
2547 panic("moea64_mapdev: Couldn't alloc kernel virtual memory");
2549 for (tmpva = va; size > 0;) {
2550 moea64_kenter_attr(mmu, tmpva, ppa, ma);
2556 return ((void *)(va + offset));
2560 moea64_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2563 return moea64_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT);
2567 moea64_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2569 vm_offset_t base, offset;
2571 base = trunc_page(va);
2572 offset = va & PAGE_MASK;
2573 size = roundup2(offset + size, PAGE_SIZE);
2575 kva_free(base, size);
2579 moea64_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2581 struct pvo_entry *pvo;
2588 lim = round_page(va);
2589 len = MIN(lim - va, sz);
2590 pvo = moea64_pvo_find_va(pm, va & ~ADDR_POFF);
2591 if (pvo != NULL && !(pvo->pvo_pte.lpte.pte_lo & LPTE_I)) {
2592 pa = (pvo->pvo_pte.lpte.pte_lo & LPTE_RPGN) |
2594 moea64_syncicache(mmu, pm, va, pa, len);