2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
31 * Copyright (C) 1995, 1996 TooLs GmbH.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by TooLs GmbH.
45 * 4. The name of TooLs GmbH may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62 * Copyright (C) 2001 Benno Rice.
63 * All rights reserved.
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Native 64-bit page table operations for running without a hypervisor.
93 #include <sys/param.h>
94 #include <sys/kernel.h>
97 #include <sys/mutex.h>
99 #include <sys/sched.h>
100 #include <sys/sysctl.h>
101 #include <sys/systm.h>
102 #include <sys/rwlock.h>
103 #include <sys/endian.h>
108 #include <vm/vm_param.h>
109 #include <vm/vm_kern.h>
110 #include <vm/vm_page.h>
111 #include <vm/vm_map.h>
112 #include <vm/vm_object.h>
113 #include <vm/vm_extern.h>
114 #include <vm/vm_pageout.h>
116 #include <machine/md_var.h>
117 #include <machine/mmuvar.h>
119 #include "mmu_oea64.h"
121 #include "moea64_if.h"
123 #define PTESYNC() __asm __volatile("ptesync");
124 #define TLBSYNC() __asm __volatile("tlbsync; ptesync");
125 #define SYNC() __asm __volatile("sync");
126 #define EIEIO() __asm __volatile("eieio");
128 #define VSID_HASH_MASK 0x0000007fffffffffULL
131 TLBIE(uint64_t vpn) {
132 #ifndef __powerpc64__
133 register_t vpn_hi, vpn_lo;
135 register_t scratch, intr;
138 static volatile u_int tlbie_lock = 0;
140 vpn <<= ADDR_PIDX_SHFT;
141 vpn &= ~(0xffffULL << 48);
143 /* Hobo spinlock: we need stronger guarantees than mutexes provide */
144 while (!atomic_cmpset_int(&tlbie_lock, 0, 1));
145 isync(); /* Flush instruction queue once lock acquired */
148 __asm __volatile("tlbie %0" :: "r"(vpn) : "memory");
149 __asm __volatile("eieio; tlbsync; ptesync" ::: "memory");
151 vpn_hi = (uint32_t)(vpn >> 32);
152 vpn_lo = (uint32_t)vpn;
154 intr = intr_disable();
169 : "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1)
174 /* No barriers or special ops -- taken care of by ptesync above */
178 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
179 #define ENABLE_TRANS(msr) mtmsr(msr)
184 static volatile struct lpte *moea64_pteg_table;
185 static struct rwlock moea64_eviction_lock;
190 static int moea64_pte_insert_native(mmu_t, struct pvo_entry *);
191 static int64_t moea64_pte_synch_native(mmu_t, struct pvo_entry *);
192 static int64_t moea64_pte_clear_native(mmu_t, struct pvo_entry *, uint64_t);
193 static int64_t moea64_pte_replace_native(mmu_t, struct pvo_entry *, int);
194 static int64_t moea64_pte_unset_native(mmu_t mmu, struct pvo_entry *);
199 static void moea64_bootstrap_native(mmu_t mmup,
200 vm_offset_t kernelstart, vm_offset_t kernelend);
201 static void moea64_cpu_bootstrap_native(mmu_t, int ap);
202 static void tlbia(void);
204 static mmu_method_t moea64_native_methods[] = {
205 /* Internal interfaces */
206 MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native),
207 MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native),
209 MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native),
210 MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native),
211 MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native),
212 MMUMETHOD(moea64_pte_replace, moea64_pte_replace_native),
213 MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native),
218 MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods,
222 moea64_pte_synch_native(mmu_t mmu, struct pvo_entry *pvo)
224 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot;
225 struct lpte properpt;
228 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
230 moea64_pte_from_pvo(pvo, &properpt);
232 rw_rlock(&moea64_eviction_lock);
233 if ((pt->pte_hi & LPTE_AVPN_MASK) !=
234 (properpt.pte_hi & LPTE_AVPN_MASK)) {
236 rw_runlock(&moea64_eviction_lock);
241 ptelo = be64toh(pt->pte_lo);
243 rw_runlock(&moea64_eviction_lock);
245 return (ptelo & (LPTE_REF | LPTE_CHG));
249 moea64_pte_clear_native(mmu_t mmu, struct pvo_entry *pvo, uint64_t ptebit)
251 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot;
252 struct lpte properpt;
255 PMAP_LOCK_ASSERT(pvo->pvo_pmap, MA_OWNED);
257 moea64_pte_from_pvo(pvo, &properpt);
259 rw_rlock(&moea64_eviction_lock);
260 if ((pt->pte_hi & LPTE_AVPN_MASK) !=
261 (properpt.pte_hi & LPTE_AVPN_MASK)) {
263 rw_runlock(&moea64_eviction_lock);
267 if (ptebit == LPTE_REF) {
268 /* See "Resetting the Reference Bit" in arch manual */
270 /* 2-step here safe: precision is not guaranteed */
273 /* One-byte store to avoid touching the C bit */
274 ((volatile uint8_t *)(&pt->pte_lo))[6] =
275 ((uint8_t *)(&properpt.pte_lo))[6];
276 rw_runlock(&moea64_eviction_lock);
282 rw_runlock(&moea64_eviction_lock);
283 ptelo = moea64_pte_unset_native(mmu, pvo);
284 moea64_pte_insert_native(mmu, pvo);
287 return (ptelo & (LPTE_REF | LPTE_CHG));
291 moea64_pte_unset_native(mmu_t mmu, struct pvo_entry *pvo)
293 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot;
294 struct lpte properpt;
297 moea64_pte_from_pvo(pvo, &properpt);
299 rw_rlock(&moea64_eviction_lock);
300 if ((pt->pte_hi & LPTE_AVPN_MASK) !=
301 (properpt.pte_hi & LPTE_AVPN_MASK)) {
303 moea64_pte_overflow--;
304 rw_runlock(&moea64_eviction_lock);
309 * Invalidate the pte, briefly locking it to collect RC bits. No
310 * atomics needed since this is protected against eviction by the lock.
314 pt->pte_hi = (pt->pte_hi & ~LPTE_VALID) | LPTE_LOCKED;
317 ptelo = be64toh(pt->pte_lo);
318 *((volatile int32_t *)(&pt->pte_hi) + 1) = 0; /* Release lock */
320 rw_runlock(&moea64_eviction_lock);
322 /* Keep statistics */
325 return (ptelo & (LPTE_CHG | LPTE_REF));
329 moea64_pte_replace_native(mmu_t mmu, struct pvo_entry *pvo, int flags)
331 volatile struct lpte *pt = moea64_pteg_table + pvo->pvo_pte.slot;
332 struct lpte properpt;
336 /* Just some software bits changing. */
337 moea64_pte_from_pvo(pvo, &properpt);
339 rw_rlock(&moea64_eviction_lock);
340 if ((pt->pte_hi & LPTE_AVPN_MASK) !=
341 (properpt.pte_hi & LPTE_AVPN_MASK)) {
342 rw_runlock(&moea64_eviction_lock);
345 pt->pte_hi = properpt.pte_hi;
347 rw_runlock(&moea64_eviction_lock);
349 /* Otherwise, need reinsertion and deletion */
350 ptelo = moea64_pte_unset_native(mmu, pvo);
351 moea64_pte_insert_native(mmu, pvo);
358 moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
362 struct slb *slb = PCPU_GET(slb);
367 * Initialize segment registers and MMU
370 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR);
373 * Install kernel SLB entries
377 __asm __volatile ("slbia");
378 __asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
381 for (i = 0; i < 64; i++) {
382 if (!(slb[i].slbe & SLBE_VALID))
385 __asm __volatile ("slbmte %0, %1" ::
386 "r"(slb[i].slbv), "r"(slb[i].slbe));
389 for (i = 0; i < 16; i++)
390 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
397 __asm __volatile ("ptesync; mtsdr1 %0; isync"
398 :: "r"((uintptr_t)moea64_pteg_table
399 | (uintptr_t)(flsl(moea64_pteg_mask >> 11))));
404 moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart,
405 vm_offset_t kernelend)
412 moea64_early_bootstrap(mmup, kernelstart, kernelend);
415 * Allocate PTEG table.
418 size = moea64_pteg_count * sizeof(struct lpteg);
419 CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes",
420 moea64_pteg_count, size);
421 rw_init(&moea64_eviction_lock, "pte eviction");
424 * We now need to allocate memory. This memory, to be allocated,
425 * has to reside in a page table. The page table we are about to
426 * allocate. We don't have BAT. So drop to data real mode for a minute
427 * as a measure of last resort. We do this a couple times.
430 moea64_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size, size);
432 bzero(__DEVOLATILE(void *, moea64_pteg_table), moea64_pteg_count *
433 sizeof(struct lpteg));
436 CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table);
438 moea64_mid_bootstrap(mmup, kernelstart, kernelend);
441 * Add a mapping for the page table itself if there is no direct map.
443 if (!hw_direct_map) {
444 size = moea64_pteg_count * sizeof(struct lpteg);
445 off = (vm_offset_t)(moea64_pteg_table);
447 for (pa = off; pa < off + size; pa += PAGE_SIZE)
452 /* Bring up virtual memory */
453 moea64_late_bootstrap(mmup, kernelstart, kernelend);
460 #ifndef __powerpc64__
461 register_t msr, scratch;
466 for (i = 0; i < 0xFF000; i += 0x00001000) {
468 __asm __volatile("tlbiel %0" :: "r"(i));
481 : "=r"(msr), "=r"(scratch) : "r"(i), "r"(1));
490 atomic_pte_lock(volatile struct lpte *pte, uint64_t bitmask, uint64_t *oldhi)
496 * Note: in principle, if just the locked bit were set here, we
497 * could avoid needing the eviction lock. However, eviction occurs
498 * so rarely that it isn't worth bothering about in practice.
502 "1:\tlwarx %1, 0, %3\n\t" /* load old value */
503 "and. %0,%1,%4\n\t" /* check if any bits set */
504 "bne 2f\n\t" /* exit if any set */
505 "stwcx. %5, 0, %3\n\t" /* attempt to store */
506 "bne- 1b\n\t" /* spin if failed */
507 "li %0, 1\n\t" /* success - retval = 1 */
508 "b 3f\n\t" /* we've succeeded */
510 "stwcx. %1, 0, %3\n\t" /* clear reservation (74xx) */
511 "li %0, 0\n\t" /* failure - retval = 0 */
513 : "=&r" (ret), "=&r"(oldhihalf), "=m" (pte->pte_hi)
514 : "r" ((volatile char *)&pte->pte_hi + 4),
515 "r" ((uint32_t)bitmask), "r" ((uint32_t)LPTE_LOCKED),
517 : "cr0", "cr1", "cr2", "memory");
519 *oldhi = (pte->pte_hi & 0xffffffff00000000ULL) | oldhihalf;
525 moea64_insert_to_pteg_native(struct lpte *pvo_pt, uintptr_t slotbase,
528 volatile struct lpte *pt;
529 uint64_t oldptehi, va;
533 /* Start at a random slot */
535 for (j = 0; j < 8; j++) {
536 k = slotbase + (i + j) % 8;
537 pt = &moea64_pteg_table[k];
538 /* Invalidate and seize lock only if no bits in mask set */
539 if (atomic_pte_lock(pt, mask, &oldptehi)) /* Lock obtained */
546 if (oldptehi & LPTE_VALID) {
547 KASSERT(!(oldptehi & LPTE_WIRED), ("Unmapped wired entry"));
549 * Need to invalidate old entry completely: see
550 * "Modifying a Page Table Entry". Need to reconstruct
551 * the virtual address for the outgoing entry to do that.
553 if (oldptehi & LPTE_BIG)
554 va = oldptehi >> moea64_large_page_shift;
556 va = oldptehi >> ADDR_PIDX_SHFT;
557 if (oldptehi & LPTE_HID)
558 va = (((k >> 3) ^ moea64_pteg_mask) ^ va) &
561 va = ((k >> 3) ^ va) & VSID_HASH_MASK;
562 va |= (oldptehi & LPTE_AVPN_MASK) <<
563 (ADDR_API_SHFT64 - ADDR_PIDX_SHFT);
567 moea64_pte_overflow++;
571 * Update the PTE as per "Adding a Page Table Entry". Lock is released
572 * by setting the high doubleworld.
574 pt->pte_lo = pvo_pt->pte_lo;
576 pt->pte_hi = pvo_pt->pte_hi;
579 /* Keep statistics */
586 moea64_pte_insert_native(mmu_t mmu, struct pvo_entry *pvo)
588 struct lpte insertpt;
592 moea64_pte_from_pvo(pvo, &insertpt);
594 /* Make sure further insertion is locked out during evictions */
595 rw_rlock(&moea64_eviction_lock);
598 * First try primary hash.
600 pvo->pvo_pte.slot &= ~7ULL; /* Base slot address */
601 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot,
602 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED);
604 rw_runlock(&moea64_eviction_lock);
605 pvo->pvo_pte.slot = slot;
610 * Now try secondary hash.
612 pvo->pvo_vaddr ^= PVO_HID;
613 insertpt.pte_hi ^= LPTE_HID;
614 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
615 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot,
616 LPTE_VALID | LPTE_WIRED | LPTE_LOCKED);
618 rw_runlock(&moea64_eviction_lock);
619 pvo->pvo_pte.slot = slot;
624 * Out of luck. Find a PTE to sacrifice.
627 /* Lock out all insertions for a bit */
628 if (!rw_try_upgrade(&moea64_eviction_lock)) {
629 rw_runlock(&moea64_eviction_lock);
630 rw_wlock(&moea64_eviction_lock);
633 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot,
634 LPTE_WIRED | LPTE_LOCKED);
636 rw_wunlock(&moea64_eviction_lock);
637 pvo->pvo_pte.slot = slot;
641 /* Try other hash table. Now we're getting desperate... */
642 pvo->pvo_vaddr ^= PVO_HID;
643 insertpt.pte_hi ^= LPTE_HID;
644 pvo->pvo_pte.slot ^= (moea64_pteg_mask << 3);
645 slot = moea64_insert_to_pteg_native(&insertpt, pvo->pvo_pte.slot,
646 LPTE_WIRED | LPTE_LOCKED);
648 rw_wunlock(&moea64_eviction_lock);
649 pvo->pvo_pte.slot = slot;
653 /* No freeable slots in either PTEG? We're hosed. */
654 rw_wunlock(&moea64_eviction_lock);
655 panic("moea64_pte_insert: overflow");