2 * Copyright (c) 2008 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
38 #include <machine/bus.h>
39 #include <machine/cpu.h>
40 #include <machine/hid.h>
41 #include <machine/intr_machdep.h>
42 #include <machine/pcb.h>
43 #include <machine/psl.h>
44 #include <machine/smp.h>
45 #include <machine/spr.h>
46 #include <machine/trap.h>
48 #include <dev/ofw/openfirm.h>
49 #include <machine/ofw_machdep.h>
53 static register_t bsp_state[8] __aligned(8);
55 static void cpudep_save_config(void *dummy);
56 SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
59 cpudep_ap_early_bootstrap(void)
65 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
68 switch (mfpvr() >> 16) {
72 /* Restore HID4 and HID5, which are necessary for the MMU */
75 mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync();
76 mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync();
78 __asm __volatile("ld %0, 16(%2); sync; isync; \
79 mtspr %1, %0; sync; isync;"
80 : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state));
81 __asm __volatile("ld %0, 24(%2); sync; isync; \
82 mtspr %1, %0; sync; isync;"
83 : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state));
91 cpudep_ap_bootstrap(void)
95 msr = PSL_KERNSET & ~PSL_EE;
98 pcpup->pc_curthread = pcpup->pc_idlethread;
100 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
102 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
104 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
105 sp = pcpup->pc_curpcb->pcb_sp;
111 mpc74xx_l2_enable(register_t l2cr_config)
116 vers = mfpvr() >> 16;
127 ccr = mfspr(SPR_L2CR);
131 /* Configure L2 cache. */
132 ccr = l2cr_config & ~L2CR_L2E;
133 mtspr(SPR_L2CR, ccr | L2CR_L2I);
135 ccr = mfspr(SPR_L2CR);
138 mtspr(SPR_L2CR, l2cr_config);
141 return (l2cr_config);
145 mpc745x_l3_enable(register_t l3cr_config)
149 ccr = mfspr(SPR_L3CR);
153 /* Configure L3 cache. */
154 ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
155 mtspr(SPR_L3CR, ccr);
156 ccr |= 0x4000000; /* Magic, but documented. */
157 mtspr(SPR_L3CR, ccr);
159 mtspr(SPR_L3CR, ccr);
160 mtspr(SPR_L3CR, ccr | L3CR_L3I);
161 while (mfspr(SPR_L3CR) & L3CR_L3I)
163 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
166 mtspr(SPR_L3CR, ccr);
170 mtspr(SPR_L3CR, ccr);
177 mpc74xx_l1d_enable(void)
181 hid = mfspr(SPR_HID0);
185 /* Enable L1 D-cache */
188 mtspr(SPR_HID0, hid | HID0_DCFI);
195 mpc74xx_l1i_enable(void)
199 hid = mfspr(SPR_HID0);
203 /* Enable L1 I-cache */
206 mtspr(SPR_HID0, hid | HID0_ICFI);
213 cpudep_save_config(void *dummy)
217 vers = mfpvr() >> 16;
224 bsp_state[0] = mfspr(SPR_HID0);
225 bsp_state[1] = mfspr(SPR_HID1);
226 bsp_state[2] = mfspr(SPR_HID4);
227 bsp_state[3] = mfspr(SPR_HID5);
229 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
230 : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));
231 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
232 : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));
233 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
234 : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));
235 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
236 : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
243 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
244 if (mfmsr() & PSL_HV) {
245 bsp_state[0] = mfspr(SPR_HID0);
246 bsp_state[1] = mfspr(SPR_HID1);
247 bsp_state[2] = mfspr(SPR_HID4);
248 bsp_state[3] = mfspr(SPR_HID6);
250 bsp_state[4] = mfspr(SPR_CELL_TSCR);
254 bsp_state[5] = mfspr(SPR_CELL_TSRL);
260 /* Only MPC745x CPUs have an L3 cache. */
261 bsp_state[3] = mfspr(SPR_L3CR);
268 bsp_state[2] = mfspr(SPR_L2CR);
269 bsp_state[1] = mfspr(SPR_HID1);
270 bsp_state[0] = mfspr(SPR_HID0);
281 vers = mfpvr() >> 16;
283 /* The following is needed for restoring from sleep. */
285 /* Writing to the time base register is hypervisor-privileged */
286 if (mfmsr() & PSL_HV)
296 __asm __volatile("mtspr 311,%0" :: "r"(0));
300 * The 970 has strange rules about how to update HID registers.
301 * See Table 2-3, 970MP manual
303 * Note: HID4 and HID5 restored already in
304 * cpudep_ap_early_bootstrap()
307 __asm __volatile("mtasr %0; sync" :: "r"(0));
312 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
313 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
315 :: "r"(bsp_state[0]), "K"(SPR_HID0));
316 __asm __volatile("sync; isync; \
317 mtspr %1, %0; mtspr %1, %0; sync; isync"
318 :: "r"(bsp_state[1]), "K"(SPR_HID1));
324 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
325 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
327 : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state));
328 __asm __volatile("ld %0, 8(%2); sync; isync; \
329 mtspr %1, %0; mtspr %1, %0; sync; isync"
330 : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state));
336 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
337 if (mfmsr() & PSL_HV) {
338 mtspr(SPR_HID0, bsp_state[0]);
339 mtspr(SPR_HID1, bsp_state[1]);
340 mtspr(SPR_HID4, bsp_state[2]);
341 mtspr(SPR_HID6, bsp_state[3]);
343 mtspr(SPR_CELL_TSCR, bsp_state[4]);
347 mtspr(SPR_CELL_TSRL, bsp_state[5]);
357 /* XXX: Program the CPU ID into PIR */
358 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
363 mtspr(SPR_HID0, bsp_state[0]); isync();
364 mtspr(SPR_HID1, bsp_state[1]); isync();
366 /* Now enable the L3 cache. */
371 /* Only MPC745x CPUs have an L3 cache. */
372 reg = mpc745x_l3_enable(bsp_state[3]);
377 reg = mpc74xx_l2_enable(bsp_state[2]);
378 reg = mpc74xx_l1d_enable();
379 reg = mpc74xx_l1i_enable();
384 if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
387 printf("WARNING: Unknown CPU type. Cache performace may be "