2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/hid.h>
43 #include <machine/intr_machdep.h>
44 #include <machine/pcb.h>
45 #include <machine/psl.h>
46 #include <machine/smp.h>
47 #include <machine/spr.h>
48 #include <machine/trap.h>
50 #include <dev/ofw/openfirm.h>
51 #include <machine/ofw_machdep.h>
55 static register_t bsp_state[8] __aligned(8);
57 static void cpudep_save_config(void *dummy);
58 SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
61 cpudep_ap_early_bootstrap(void)
67 switch (mfpvr() >> 16) {
72 __asm __volatile("mtspr 311,%0" :: "r"(0));
75 /* Restore HID4 and HID5, which are necessary for the MMU */
78 mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync();
79 mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync();
81 __asm __volatile("ld %0, 16(%2); sync; isync; \
82 mtspr %1, %0; sync; isync;"
83 : "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state));
84 __asm __volatile("ld %0, 24(%2); sync; isync; \
85 mtspr %1, %0; sync; isync;"
86 : "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state));
95 if (mfmsr() & PSL_HV) {
98 * Direct interrupts to SRR instead of HSRR and
99 * reset LPCR otherwise
104 mtspr(SPR_LPCR, lpcr);
108 * Nuke FSCR, to be managed on a per-process basis
117 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
122 cpudep_ap_bootstrap(void)
126 msr = psl_kernset & ~PSL_EE;
129 pcpup->pc_curthread = pcpup->pc_idlethread;
131 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
133 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
135 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
136 sp = pcpup->pc_curpcb->pcb_sp;
142 mpc74xx_l2_enable(register_t l2cr_config)
147 vers = mfpvr() >> 16;
158 ccr = mfspr(SPR_L2CR);
162 /* Configure L2 cache. */
163 ccr = l2cr_config & ~L2CR_L2E;
164 mtspr(SPR_L2CR, ccr | L2CR_L2I);
166 ccr = mfspr(SPR_L2CR);
169 mtspr(SPR_L2CR, l2cr_config);
172 return (l2cr_config);
176 mpc745x_l3_enable(register_t l3cr_config)
180 ccr = mfspr(SPR_L3CR);
184 /* Configure L3 cache. */
185 ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
186 mtspr(SPR_L3CR, ccr);
187 ccr |= 0x4000000; /* Magic, but documented. */
188 mtspr(SPR_L3CR, ccr);
190 mtspr(SPR_L3CR, ccr);
191 mtspr(SPR_L3CR, ccr | L3CR_L3I);
192 while (mfspr(SPR_L3CR) & L3CR_L3I)
194 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
197 mtspr(SPR_L3CR, ccr);
201 mtspr(SPR_L3CR, ccr);
208 mpc74xx_l1d_enable(void)
212 hid = mfspr(SPR_HID0);
216 /* Enable L1 D-cache */
219 mtspr(SPR_HID0, hid | HID0_DCFI);
226 mpc74xx_l1i_enable(void)
230 hid = mfspr(SPR_HID0);
234 /* Enable L1 I-cache */
237 mtspr(SPR_HID0, hid | HID0_ICFI);
244 cpudep_save_config(void *dummy)
248 vers = mfpvr() >> 16;
255 bsp_state[0] = mfspr(SPR_HID0);
256 bsp_state[1] = mfspr(SPR_HID1);
257 bsp_state[2] = mfspr(SPR_HID4);
258 bsp_state[3] = mfspr(SPR_HID5);
260 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
261 : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));
262 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
263 : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));
264 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
265 : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));
266 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
267 : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
274 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
275 if (mfmsr() & PSL_HV) {
276 bsp_state[0] = mfspr(SPR_HID0);
277 bsp_state[1] = mfspr(SPR_HID1);
278 bsp_state[2] = mfspr(SPR_HID4);
279 bsp_state[3] = mfspr(SPR_HID6);
281 bsp_state[4] = mfspr(SPR_CELL_TSCR);
285 bsp_state[5] = mfspr(SPR_CELL_TSRL);
291 /* Only MPC745x CPUs have an L3 cache. */
292 bsp_state[3] = mfspr(SPR_L3CR);
299 bsp_state[2] = mfspr(SPR_L2CR);
300 bsp_state[1] = mfspr(SPR_HID1);
301 bsp_state[0] = mfspr(SPR_HID0);
312 vers = mfpvr() >> 16;
319 * The 970 has strange rules about how to update HID registers.
320 * See Table 2-3, 970MP manual
322 * Note: HID4 and HID5 restored already in
323 * cpudep_ap_early_bootstrap()
326 __asm __volatile("mtasr %0; sync" :: "r"(0));
331 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
332 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
334 :: "r"(bsp_state[0]), "K"(SPR_HID0));
335 __asm __volatile("sync; isync; \
336 mtspr %1, %0; mtspr %1, %0; sync; isync"
337 :: "r"(bsp_state[1]), "K"(SPR_HID1));
343 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
344 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
346 : "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state));
347 __asm __volatile("ld %0, 8(%2); sync; isync; \
348 mtspr %1, %0; mtspr %1, %0; sync; isync"
349 : "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state));
355 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
356 if (mfmsr() & PSL_HV) {
357 mtspr(SPR_HID0, bsp_state[0]);
358 mtspr(SPR_HID1, bsp_state[1]);
359 mtspr(SPR_HID4, bsp_state[2]);
360 mtspr(SPR_HID6, bsp_state[3]);
362 mtspr(SPR_CELL_TSCR, bsp_state[4]);
366 mtspr(SPR_CELL_TSRL, bsp_state[5]);
376 /* XXX: Program the CPU ID into PIR */
377 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
382 mtspr(SPR_HID0, bsp_state[0]); isync();
383 mtspr(SPR_HID1, bsp_state[1]); isync();
385 /* Now enable the L3 cache. */
390 /* Only MPC745x CPUs have an L3 cache. */
391 reg = mpc745x_l3_enable(bsp_state[3]);
396 reg = mpc74xx_l2_enable(bsp_state[2]);
397 reg = mpc74xx_l1d_enable();
398 reg = mpc74xx_l1i_enable();
408 if (mfmsr() & PSL_HV) {
409 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | lpcr |
417 if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
420 printf("WARNING: Unknown CPU type. Cache performace may be "