2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Marcel Moolenaar
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
40 #include <machine/bus.h>
41 #include <machine/cpu.h>
42 #include <machine/hid.h>
43 #include <machine/intr_machdep.h>
44 #include <machine/pcb.h>
45 #include <machine/psl.h>
46 #include <machine/smp.h>
47 #include <machine/spr.h>
48 #include <machine/trap.h>
50 #include <dev/ofw/openfirm.h>
51 #include <machine/ofw_machdep.h>
55 static register_t bsp_state[8] __aligned(8);
57 static void cpudep_save_config(void *dummy);
58 SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
61 cpudep_ap_early_bootstrap(void)
67 switch (mfpvr() >> 16) {
71 /* Restore HID4 and HID5, which are necessary for the MMU */
74 mtspr(SPR_HID4, bsp_state[2]); powerpc_sync(); isync();
75 mtspr(SPR_HID5, bsp_state[3]); powerpc_sync(); isync();
77 __asm __volatile("ld %0, 16(%2); sync; isync; \
78 mtspr %1, %0; sync; isync;"
79 : "=r"(reg) : "K"(SPR_HID4), "b"(bsp_state));
80 __asm __volatile("ld %0, 24(%2); sync; isync; \
81 mtspr %1, %0; sync; isync;"
82 : "=r"(reg) : "K"(SPR_HID5), "b"(bsp_state));
90 if (mfmsr() & PSL_HV) {
93 * Direct interrupts to SRR instead of HSRR and
94 * reset LPCR otherwise
99 mtspr(SPR_LPCR, lpcr);
106 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
111 cpudep_ap_bootstrap(void)
115 msr = psl_kernset & ~PSL_EE;
118 pcpup->pc_curthread = pcpup->pc_idlethread;
120 __asm __volatile("mr 13,%0" :: "r"(pcpup->pc_curthread));
122 __asm __volatile("mr 2,%0" :: "r"(pcpup->pc_curthread));
124 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
125 sp = pcpup->pc_curpcb->pcb_sp;
131 mpc74xx_l2_enable(register_t l2cr_config)
136 vers = mfpvr() >> 16;
147 ccr = mfspr(SPR_L2CR);
151 /* Configure L2 cache. */
152 ccr = l2cr_config & ~L2CR_L2E;
153 mtspr(SPR_L2CR, ccr | L2CR_L2I);
155 ccr = mfspr(SPR_L2CR);
158 mtspr(SPR_L2CR, l2cr_config);
161 return (l2cr_config);
165 mpc745x_l3_enable(register_t l3cr_config)
169 ccr = mfspr(SPR_L3CR);
173 /* Configure L3 cache. */
174 ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
175 mtspr(SPR_L3CR, ccr);
176 ccr |= 0x4000000; /* Magic, but documented. */
177 mtspr(SPR_L3CR, ccr);
179 mtspr(SPR_L3CR, ccr);
180 mtspr(SPR_L3CR, ccr | L3CR_L3I);
181 while (mfspr(SPR_L3CR) & L3CR_L3I)
183 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
186 mtspr(SPR_L3CR, ccr);
190 mtspr(SPR_L3CR, ccr);
197 mpc74xx_l1d_enable(void)
201 hid = mfspr(SPR_HID0);
205 /* Enable L1 D-cache */
208 mtspr(SPR_HID0, hid | HID0_DCFI);
215 mpc74xx_l1i_enable(void)
219 hid = mfspr(SPR_HID0);
223 /* Enable L1 I-cache */
226 mtspr(SPR_HID0, hid | HID0_ICFI);
233 cpudep_save_config(void *dummy)
237 vers = mfpvr() >> 16;
244 bsp_state[0] = mfspr(SPR_HID0);
245 bsp_state[1] = mfspr(SPR_HID1);
246 bsp_state[2] = mfspr(SPR_HID4);
247 bsp_state[3] = mfspr(SPR_HID5);
249 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
250 : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));
251 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
252 : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));
253 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
254 : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));
255 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
256 : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
263 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
264 if (mfmsr() & PSL_HV) {
265 bsp_state[0] = mfspr(SPR_HID0);
266 bsp_state[1] = mfspr(SPR_HID1);
267 bsp_state[2] = mfspr(SPR_HID4);
268 bsp_state[3] = mfspr(SPR_HID6);
270 bsp_state[4] = mfspr(SPR_CELL_TSCR);
274 bsp_state[5] = mfspr(SPR_CELL_TSRL);
280 /* Only MPC745x CPUs have an L3 cache. */
281 bsp_state[3] = mfspr(SPR_L3CR);
288 bsp_state[2] = mfspr(SPR_L2CR);
289 bsp_state[1] = mfspr(SPR_HID1);
290 bsp_state[0] = mfspr(SPR_HID0);
301 vers = mfpvr() >> 16;
303 /* The following is needed for restoring from sleep. */
304 platform_smp_timebase_sync(0, 1);
311 __asm __volatile("mtspr 311,%0" :: "r"(0));
315 * The 970 has strange rules about how to update HID registers.
316 * See Table 2-3, 970MP manual
318 * Note: HID4 and HID5 restored already in
319 * cpudep_ap_early_bootstrap()
322 __asm __volatile("mtasr %0; sync" :: "r"(0));
327 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
328 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
330 :: "r"(bsp_state[0]), "K"(SPR_HID0));
331 __asm __volatile("sync; isync; \
332 mtspr %1, %0; mtspr %1, %0; sync; isync"
333 :: "r"(bsp_state[1]), "K"(SPR_HID1));
339 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
340 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
342 : "=r"(reg) : "K"(SPR_HID0), "b"(bsp_state));
343 __asm __volatile("ld %0, 8(%2); sync; isync; \
344 mtspr %1, %0; mtspr %1, %0; sync; isync"
345 : "=r"(reg) : "K"(SPR_HID1), "b"(bsp_state));
351 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
352 if (mfmsr() & PSL_HV) {
353 mtspr(SPR_HID0, bsp_state[0]);
354 mtspr(SPR_HID1, bsp_state[1]);
355 mtspr(SPR_HID4, bsp_state[2]);
356 mtspr(SPR_HID6, bsp_state[3]);
358 mtspr(SPR_CELL_TSCR, bsp_state[4]);
362 mtspr(SPR_CELL_TSRL, bsp_state[5]);
372 /* XXX: Program the CPU ID into PIR */
373 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
378 mtspr(SPR_HID0, bsp_state[0]); isync();
379 mtspr(SPR_HID1, bsp_state[1]); isync();
381 /* Now enable the L3 cache. */
386 /* Only MPC745x CPUs have an L3 cache. */
387 reg = mpc745x_l3_enable(bsp_state[3]);
392 reg = mpc74xx_l2_enable(bsp_state[2]);
393 reg = mpc74xx_l1d_enable();
394 reg = mpc74xx_l1i_enable();
403 if (mfmsr() & PSL_HV) {
404 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | lpcr |
412 if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
415 printf("WARNING: Unknown CPU type. Cache performace may be "