2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/param.h>
32 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/mutex.h>
37 #include <sys/systm.h>
43 #include <vm/vm_map.h>
44 #include <vm/vm_page.h>
45 #include <vm/vm_pageout.h>
47 #include <machine/md_var.h>
48 #include <machine/platform.h>
49 #include <machine/vmparam.h>
51 uintptr_t moea64_get_unique_vsid(void);
52 void moea64_release_vsid(uint64_t vsid);
53 static void slb_zone_init(void *);
55 static uma_zone_t slbt_zone;
56 static uma_zone_t slb_cache_zone;
59 SYSINIT(slb_zone_init, SI_SUB_KMEM, SI_ORDER_ANY, slb_zone_init, NULL);
64 /* Only 36 bits needed for full 64-bit address space. */
67 struct slbtnode *ua_child[16];
68 struct slb slb_entries[16];
73 * For a full 64-bit address space, there are 36 bits in play in an
74 * esid, so 8 levels, with the leaf being at level 0.
76 * |3333|3322|2222|2222|1111|1111|11 | | | esid
77 * |5432|1098|7654|3210|9876|5432|1098|7654|3210| bits
78 * +----+----+----+----+----+----+----+----+----+--------
79 * | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | level
81 #define UAD_ROOT_LEVEL 8
82 #define UAD_LEAF_LEVEL 0
85 esid2idx(uint64_t esid, int level)
90 return ((esid >> shift) & 0xF);
94 * The ua_base field should have 0 bits after the first 4*(level+1)
97 #define uad_baseok(ua) \
98 (esid2base(ua->ua_base, ua->ua_level) == ua->ua_base)
101 static inline uint64_t
102 esid2base(uint64_t esid, int level)
107 shift = (level + 1) * 4;
108 mask = ~((1ULL << shift) - 1);
109 return (esid & mask);
113 * Allocate a new leaf node for the specified esid/vmhandle from the
117 make_new_leaf(uint64_t esid, uint64_t slbv, struct slbtnode *parent)
119 struct slbtnode *child;
123 idx = esid2idx(esid, parent->ua_level);
124 KASSERT(parent->u.ua_child[idx] == NULL, ("Child already exists!"));
126 /* unlock and M_WAITOK and loop? */
127 child = uma_zalloc(slbt_zone, M_NOWAIT | M_ZERO);
128 KASSERT(child != NULL, ("unhandled NULL case"));
130 child->ua_level = UAD_LEAF_LEVEL;
131 child->ua_base = esid2base(esid, child->ua_level);
132 idx = esid2idx(esid, child->ua_level);
133 child->u.slb_entries[idx].slbv = slbv;
134 child->u.slb_entries[idx].slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
135 setbit(&child->ua_alloc, idx);
137 retval = &child->u.slb_entries[idx];
140 * The above stores must be visible before the next one, so
141 * that a lockless searcher always sees a valid path through
146 idx = esid2idx(esid, parent->ua_level);
147 parent->u.ua_child[idx] = child;
148 setbit(&parent->ua_alloc, idx);
154 * Allocate a new intermediate node to fit between the parent and
157 static struct slbtnode*
158 make_intermediate(uint64_t esid, struct slbtnode *parent)
160 struct slbtnode *child, *inter;
163 idx = esid2idx(esid, parent->ua_level);
164 child = parent->u.ua_child[idx];
165 KASSERT(esid2base(esid, child->ua_level) != child->ua_base,
166 ("No need for an intermediate node?"));
169 * Find the level where the existing child and our new esid
170 * meet. It must be lower than parent->ua_level or we would
171 * have chosen a different index in parent.
173 level = child->ua_level + 1;
174 while (esid2base(esid, level) !=
175 esid2base(child->ua_base, level))
177 KASSERT(level < parent->ua_level,
178 ("Found splitting level %d for %09jx and %09jx, "
179 "but it's the same as %p's",
180 level, esid, child->ua_base, parent));
182 /* unlock and M_WAITOK and loop? */
183 inter = uma_zalloc(slbt_zone, M_NOWAIT | M_ZERO);
184 KASSERT(inter != NULL, ("unhandled NULL case"));
186 /* Set up intermediate node to point to child ... */
187 inter->ua_level = level;
188 inter->ua_base = esid2base(esid, inter->ua_level);
189 idx = esid2idx(child->ua_base, inter->ua_level);
190 inter->u.ua_child[idx] = child;
191 setbit(&inter->ua_alloc, idx);
194 /* Set up parent to point to intermediate node ... */
195 idx = esid2idx(inter->ua_base, parent->ua_level);
196 parent->u.ua_child[idx] = inter;
197 setbit(&parent->ua_alloc, idx);
203 kernel_va_to_slbv(vm_offset_t va)
207 /* Set kernel VSID to deterministic value */
208 slbv = (KERNEL_VSID((uintptr_t)va >> ADDR_SR_SHFT)) << SLBV_VSID_SHIFT;
211 * Figure out if this is a large-page mapping.
213 if (hw_direct_map && va > DMAP_BASE_ADDRESS && va < DMAP_MAX_ADDRESS) {
215 * XXX: If we have set up a direct map, assumes
216 * all physical memory is mapped with large pages.
219 if (mem_valid(DMAP_TO_PHYS(va), 0) == 0)
227 user_va_to_slb_entry(pmap_t pm, vm_offset_t va)
229 uint64_t esid = va >> ADDR_SR_SHFT;
233 ua = pm->pm_slb_tree_root;
236 KASSERT(uad_baseok(ua), ("uad base %016jx level %d bad!",
237 ua->ua_base, ua->ua_level));
238 idx = esid2idx(esid, ua->ua_level);
241 * This code is specific to ppc64 where a load is
242 * atomic, so no need for atomic_load macro.
244 if (ua->ua_level == UAD_LEAF_LEVEL)
245 return ((ua->u.slb_entries[idx].slbe & SLBE_VALID) ?
246 &ua->u.slb_entries[idx] : NULL);
249 * The following accesses are implicitly ordered under the POWER
250 * ISA by load dependencies (the store ordering is provided by
251 * the powerpc_lwsync() calls elsewhere) and so are run without
254 ua = ua->u.ua_child[idx];
256 esid2base(esid, ua->ua_level) != ua->ua_base)
264 va_to_vsid(pmap_t pm, vm_offset_t va)
268 /* Shortcut kernel case */
269 if (pm == kernel_pmap)
270 return (KERNEL_VSID((uintptr_t)va >> ADDR_SR_SHFT));
273 * If there is no vsid for this VA, we need to add a new entry
274 * to the PMAP's segment table.
277 entry = user_va_to_slb_entry(pm, va);
280 return (allocate_user_vsid(pm,
281 (uintptr_t)va >> ADDR_SR_SHFT, 0));
283 return ((entry->slbv & SLBV_VSID_MASK) >> SLBV_VSID_SHIFT);
287 allocate_user_vsid(pmap_t pm, uint64_t esid, int large)
290 struct slbtnode *ua, *next, *inter;
294 KASSERT(pm != kernel_pmap, ("Attempting to allocate a kernel VSID"));
296 PMAP_LOCK_ASSERT(pm, MA_OWNED);
297 vsid = moea64_get_unique_vsid();
299 slbv = vsid << SLBV_VSID_SHIFT;
303 ua = pm->pm_slb_tree_root;
305 /* Descend to the correct leaf or NULL pointer. */
307 KASSERT(uad_baseok(ua),
308 ("uad base %09jx level %d bad!", ua->ua_base, ua->ua_level));
309 idx = esid2idx(esid, ua->ua_level);
311 if (ua->ua_level == UAD_LEAF_LEVEL) {
312 ua->u.slb_entries[idx].slbv = slbv;
314 ua->u.slb_entries[idx].slbe = (esid << SLBE_ESID_SHIFT)
316 setbit(&ua->ua_alloc, idx);
317 slb = &ua->u.slb_entries[idx];
321 next = ua->u.ua_child[idx];
323 slb = make_new_leaf(esid, slbv, ua);
328 * Check if the next item down has an okay ua_base.
329 * If not, we need to allocate an intermediate node.
331 if (esid2base(esid, next->ua_level) != next->ua_base) {
332 inter = make_intermediate(esid, ua);
333 slb = make_new_leaf(esid, slbv, inter);
341 * Someone probably wants this soon, and it may be a wired
342 * SLB mapping, so pre-spill this entry.
345 slb_insert_user(pm, slb);
351 free_vsid(pmap_t pm, uint64_t esid, int large)
356 PMAP_LOCK_ASSERT(pm, MA_OWNED);
358 ua = pm->pm_slb_tree_root;
359 /* Descend to the correct leaf. */
361 KASSERT(uad_baseok(ua),
362 ("uad base %09jx level %d bad!", ua->ua_base, ua->ua_level));
364 idx = esid2idx(esid, ua->ua_level);
365 if (ua->ua_level == UAD_LEAF_LEVEL) {
366 ua->u.slb_entries[idx].slbv = 0;
368 ua->u.slb_entries[idx].slbe = 0;
369 clrbit(&ua->ua_alloc, idx);
373 ua = ua->u.ua_child[idx];
375 esid2base(esid, ua->ua_level) != ua->ua_base) {
376 /* Perhaps just return instead of assert? */
378 ("Asked to remove an entry that was never inserted!"));
385 free_slb_tree_node(struct slbtnode *ua)
389 for (idx = 0; idx < 16; idx++) {
390 if (ua->ua_level != UAD_LEAF_LEVEL) {
391 if (ua->u.ua_child[idx] != NULL)
392 free_slb_tree_node(ua->u.ua_child[idx]);
394 if (ua->u.slb_entries[idx].slbv != 0)
395 moea64_release_vsid(ua->u.slb_entries[idx].slbv
400 uma_zfree(slbt_zone, ua);
404 slb_free_tree(pmap_t pm)
407 free_slb_tree_node(pm->pm_slb_tree_root);
413 struct slbtnode *root;
415 root = uma_zalloc(slbt_zone, M_NOWAIT | M_ZERO);
416 root->ua_level = UAD_ROOT_LEVEL;
421 /* Lock entries mapping kernel text and stacks */
424 slb_insert_kernel(uint64_t slbe, uint64_t slbv)
426 struct slb *slbcache;
429 /* We don't want to be preempted while modifying the kernel map */
432 slbcache = PCPU_GET(aim.slb);
434 /* Check for an unused slot, abusing the user slot as a full flag */
435 if (slbcache[USER_SLB_SLOT].slbe == 0) {
436 for (i = 0; i < n_slbs; i++) {
437 if (i == USER_SLB_SLOT)
439 if (!(slbcache[i].slbe & SLBE_VALID))
444 slbcache[USER_SLB_SLOT].slbe = 1;
448 if (i == USER_SLB_SLOT)
452 KASSERT(i != USER_SLB_SLOT,
453 ("Filling user SLB slot with a kernel mapping"));
454 slbcache[i].slbv = slbv;
455 slbcache[i].slbe = slbe | (uint64_t)i;
457 /* If it is for this CPU, put it in the SLB right away */
458 if (pmap_bootstrapped) {
459 /* slbie not required */
460 __asm __volatile ("slbmte %0, %1" ::
461 "r"(slbcache[i].slbv), "r"(slbcache[i].slbe));
468 slb_insert_user(pmap_t pm, struct slb *slb)
472 PMAP_LOCK_ASSERT(pm, MA_OWNED);
474 if (pm->pm_slb_len < n_slbs) {
481 /* Note that this replacement is atomic with respect to trap_subr */
486 slb_uma_real_alloc(uma_zone_t zone, vm_size_t bytes, int domain,
487 u_int8_t *flags, int wait)
489 static vm_offset_t realmax = 0;
494 realmax = platform_real_maxaddr();
496 *flags = UMA_SLAB_PRIV;
497 m = vm_page_alloc_contig_domain(NULL, 0, domain,
498 malloc2vm_flags(wait) | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED,
499 1, 0, realmax, PAGE_SIZE, PAGE_SIZE, VM_MEMATTR_DEFAULT);
503 va = (void *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
506 pmap_kenter((vm_offset_t)va, VM_PAGE_TO_PHYS(m));
508 if ((wait & M_ZERO) && (m->flags & PG_ZERO) == 0)
509 bzero(va, PAGE_SIZE);
515 slb_zone_init(void *dummy)
518 slbt_zone = uma_zcreate("SLB tree node", sizeof(struct slbtnode),
519 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM);
520 slb_cache_zone = uma_zcreate("SLB cache",
521 (n_slbs + 1)*sizeof(struct slb *), NULL, NULL, NULL, NULL,
522 UMA_ALIGN_PTR, UMA_ZONE_VM);
524 if (platform_real_maxaddr() != VM_MAX_ADDRESS) {
525 uma_zone_set_allocf(slb_cache_zone, slb_uma_real_alloc);
526 uma_zone_set_allocf(slbt_zone, slb_uma_real_alloc);
531 slb_alloc_user_cache(void)
533 return (uma_zalloc(slb_cache_zone, M_ZERO));
537 slb_free_user_cache(struct slb **slb)
539 uma_zfree(slb_cache_zone, slb);