2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
39 * #include <powerpc/aim/trap_subr.S>
42 /* Locate the per-CPU data structure */
43 #define GET_CPUINFO(r) \
45 #define GET_TOCBASE(r) \
46 li r,TRAP_TOCBASE; /* Magic address for TOC */ \
50 * Restore SRs for a pmap
52 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
56 * User SRs are loaded through a pointer to the current pmap.
60 ld %r28,PC_USERSLB(%r28)
61 li %r29, 0 /* Set the counter to zero */
67 1: ld %r31, 0(%r28) /* Load SLB entry pointer */
68 cmpdi %r31, 0 /* If NULL, stop */
71 ld %r30, 0(%r31) /* Load SLBV */
72 ld %r31, 8(%r31) /* Load SLBE */
73 or %r31, %r31, %r29 /* Set SLBE slot */
74 slbmte %r30, %r31 /* Install SLB entry */
76 addi %r28, %r28, 8 /* Advance pointer */
81 * Kernel SRs are loaded directly from the PCPU fields
85 addi %r28,%r28,PC_KERNSLB
86 li %r29, 0 /* Set the counter to zero */
92 1: cmpdi %r29, USER_SLB_SLOT /* Skip the user slot */
95 ld %r31, 8(%r28) /* Load SLBE */
96 cmpdi %r31, 0 /* If SLBE is not valid, stop */
98 ld %r30, 0(%r28) /* Load SLBV */
99 slbmte %r30, %r31 /* Install SLB entry */
101 2: addi %r28, %r28, 16 /* Advance pointer */
103 cmpdi %r29, 64 /* Repeat if we are not at the end */
108 * FRAME_SETUP assumes:
111 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
117 * SRR0/1 as at start of trap
119 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse
120 * in any real-mode fault handler, including those handling double faults.
122 #define FRAME_SETUP(savearea) \
123 /* Have to enable translation to allow access of kernel stack: */ \
126 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
128 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
129 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \
131 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
132 mtmsr %r30; /* stack can now be accessed */ \
134 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
135 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
136 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
137 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
138 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
139 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
141 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
142 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
143 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
144 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
145 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
146 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
147 std %r4, FRAME_4+48(%r1); \
148 std %r5, FRAME_5+48(%r1); \
149 std %r6, FRAME_6+48(%r1); \
150 std %r7, FRAME_7+48(%r1); \
151 std %r8, FRAME_8+48(%r1); \
152 std %r9, FRAME_9+48(%r1); \
153 std %r10, FRAME_10+48(%r1); \
154 std %r11, FRAME_11+48(%r1); \
155 std %r12, FRAME_12+48(%r1); \
156 std %r13, FRAME_13+48(%r1); \
157 std %r14, FRAME_14+48(%r1); \
158 std %r15, FRAME_15+48(%r1); \
159 std %r16, FRAME_16+48(%r1); \
160 std %r17, FRAME_17+48(%r1); \
161 std %r18, FRAME_18+48(%r1); \
162 std %r19, FRAME_19+48(%r1); \
163 std %r20, FRAME_20+48(%r1); \
164 std %r21, FRAME_21+48(%r1); \
165 std %r22, FRAME_22+48(%r1); \
166 std %r23, FRAME_23+48(%r1); \
167 std %r24, FRAME_24+48(%r1); \
168 std %r25, FRAME_25+48(%r1); \
169 std %r26, FRAME_26+48(%r1); \
170 std %r27, FRAME_27+48(%r1); \
171 std %r28, FRAME_28+48(%r1); \
172 std %r29, FRAME_29+48(%r1); \
173 std %r30, FRAME_30+48(%r1); \
174 std %r31, FRAME_31+48(%r1); \
175 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
176 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
177 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
178 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
182 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
183 std %r4, FRAME_CTR+48(1); \
184 std %r5, FRAME_EXC+48(1); \
185 std %r28,FRAME_AIM_DAR+48(1); \
186 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
187 std %r30,FRAME_SRR0+48(1); \
188 std %r31,FRAME_SRR1+48(1); \
189 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */
191 #define FRAME_LEAVE(savearea) \
192 /* Disable exceptions: */ \
194 andi. %r2,%r2,~PSL_EE@l; \
197 /* Now restore regs: */ \
198 ld %r2,FRAME_SRR0+48(%r1); \
199 ld %r3,FRAME_SRR1+48(%r1); \
200 ld %r4,FRAME_CTR+48(%r1); \
201 ld %r5,FRAME_XER+48(%r1); \
202 ld %r6,FRAME_LR+48(%r1); \
204 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
205 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
206 ld %r7,FRAME_CR+48(%r1); \
210 mtsprg2 %r7; /* save cr */ \
211 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
212 ld %r30,FRAME_30+48(%r1); \
213 ld %r29,FRAME_29+48(%r1); \
214 ld %r28,FRAME_28+48(%r1); \
215 ld %r27,FRAME_27+48(%r1); \
216 ld %r26,FRAME_26+48(%r1); \
217 ld %r25,FRAME_25+48(%r1); \
218 ld %r24,FRAME_24+48(%r1); \
219 ld %r23,FRAME_23+48(%r1); \
220 ld %r22,FRAME_22+48(%r1); \
221 ld %r21,FRAME_21+48(%r1); \
222 ld %r20,FRAME_20+48(%r1); \
223 ld %r19,FRAME_19+48(%r1); \
224 ld %r18,FRAME_18+48(%r1); \
225 ld %r17,FRAME_17+48(%r1); \
226 ld %r16,FRAME_16+48(%r1); \
227 ld %r15,FRAME_15+48(%r1); \
228 ld %r14,FRAME_14+48(%r1); \
229 ld %r13,FRAME_13+48(%r1); \
230 ld %r12,FRAME_12+48(%r1); \
231 ld %r11,FRAME_11+48(%r1); \
232 ld %r10,FRAME_10+48(%r1); \
233 ld %r9, FRAME_9+48(%r1); \
234 ld %r8, FRAME_8+48(%r1); \
235 ld %r7, FRAME_7+48(%r1); \
236 ld %r6, FRAME_6+48(%r1); \
237 ld %r5, FRAME_5+48(%r1); \
238 ld %r4, FRAME_4+48(%r1); \
239 ld %r3, FRAME_3+48(%r1); \
240 ld %r2, FRAME_2+48(%r1); \
241 ld %r0, FRAME_0+48(%r1); \
242 ld %r1, FRAME_1+48(%r1); \
243 /* Can't touch %r1 from here on */ \
244 mtsprg3 %r3; /* save r3 */ \
245 /* Disable translation, machine check and recoverability: */ \
247 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
250 /* Decide whether we return to user mode: */ \
252 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \
254 bf 17,1f; /* branch if PSL_PR is false */ \
255 /* Restore user SRs */ \
257 std %r27,(savearea+CPUSAVE_R27)(%r3); \
258 std %r28,(savearea+CPUSAVE_R28)(%r3); \
259 std %r29,(savearea+CPUSAVE_R29)(%r3); \
260 std %r30,(savearea+CPUSAVE_R30)(%r3); \
261 std %r31,(savearea+CPUSAVE_R31)(%r3); \
262 mflr %r27; /* preserve LR */ \
263 bl restore_usersrs; /* uses r28-r31 */ \
265 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
266 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
267 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
268 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
269 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
270 1: mfsprg2 %r3; /* restore cr */ \
273 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \
276 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \
278 mfsprg3 %r3 /* restore r3 */
282 .globl dtrace_invop_calltrap_addr
284 .type dtrace_invop_calltrap_addr, @object
285 .size dtrace_invop_calltrap_addr, 8
286 dtrace_invop_calltrap_addr:
294 * Processor reset exception handler. These are typically
295 * the first instructions the processor executes after a
296 * software reset. We do this in two bits so that we are
297 * not still hanging around in the trap handling region
298 * once the MMU is turned on.
300 .globl CNAME(rstcode), CNAME(rstcodeend)
302 /* Explicitly set MSR[SF] */
320 ld %r1,TOC_REF(tmpstk)(%r2) /* get new SP */
321 addi %r1,%r1,(TMPSTKSZ-48)
323 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */
326 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */
328 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */
330 mr %r1,%r3 /* Use new stack */
331 bl CNAME(cpudep_ap_setup)
334 ld %r3,(PC_RESTORE)(%r5)
343 bl CNAME(machdep_ap_bootstrap) /* And away! */
347 /* Should not be reached */
352 * This code gets copied to all the trap vectors
353 * (except ISI/DSI, ALI, and the interrupts). Has to fit in 8 instructions!
356 .globl CNAME(trapcode),CNAME(trapcodeend)
359 mtsprg1 %r1 /* save SP */
360 mflr %r1 /* Save the old LR in r1 */
361 mtsprg2 %r1 /* And then in SPRG2 */
362 ld %r1,TRAP_GENTRAP(0)
364 li %r1, 0xe0 /* How to get the vector from LR */
365 blrl /* Branch to generictrap */
369 * For SLB misses: do special things for the kernel
371 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is
372 * the only time this can be called.
374 .globl CNAME(slbtrap),CNAME(slbtrapend)
377 mtsprg1 %r1 /* save SP */
379 std %r2,(PC_SLBSAVE+16)(%r1)
380 mfcr %r2 /* save CR */
381 std %r2,(PC_SLBSAVE+104)(%r1)
382 mfsrr1 %r2 /* test kernel mode */
384 bf 17,2f /* branch if PSL_PR is false */
386 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
388 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
389 mflr %r1 /* Save the old LR in r1 */
390 mtsprg2 %r1 /* And then in SPRG2 */
391 /* 52 bytes so far */
397 li %r1, 0x80 /* How to get the vector from LR */
398 blrl /* Branch to generictrap */
400 2: mflr %r2 /* Save the old LR in r2 */
402 bl 3f /* Begin dance to jump to kern_slbtrap*/
408 blrl /* 124 bytes -- 4 to spare */
412 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */
413 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */
415 /* Check if this needs to be handled as a regular trap (userseg miss) */
423 2: /* r2 now contains the fault address */
424 lis %r3,SEGMENT_MASK@highesta
425 ori %r3,%r3,SEGMENT_MASK@highera
427 oris %r3,%r3,SEGMENT_MASK@ha
428 ori %r3,%r3,SEGMENT_MASK@l
429 and %r2,%r2,%r3 /* R2 = segment base address */
430 lis %r3,USER_ADDR@highesta
431 ori %r3,%r3,USER_ADDR@highera
433 oris %r3,%r3,USER_ADDR@ha
434 ori %r3,%r3,USER_ADDR@l
435 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */
438 /* User seg miss, handle as a regular trap */
439 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
441 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */
442 ld %r3,(PC_SLBSAVE+24)(%r1)
443 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */
444 mtsprg2 %r1 /* And then in SPRG2 */
445 li %r1, 0x80 /* How to get the vector from LR */
446 b generictrap /* Retain old LR using b */
448 3: /* Real kernel SLB miss */
449 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */
450 mfsprg1 %r2 /* Old R1 */
451 std %r2,(PC_SLBSAVE+8)(%r1)
452 /* R2,R3 already saved */
453 std %r4,(PC_SLBSAVE+32)(%r1)
454 std %r5,(PC_SLBSAVE+40)(%r1)
455 std %r6,(PC_SLBSAVE+48)(%r1)
456 std %r7,(PC_SLBSAVE+56)(%r1)
457 std %r8,(PC_SLBSAVE+64)(%r1)
458 std %r9,(PC_SLBSAVE+72)(%r1)
459 std %r10,(PC_SLBSAVE+80)(%r1)
460 std %r11,(PC_SLBSAVE+88)(%r1)
461 std %r12,(PC_SLBSAVE+96)(%r1)
462 /* CR already saved */
463 mfxer %r2 /* save XER */
464 std %r2,(PC_SLBSAVE+112)(%r1)
465 mflr %r2 /* save LR (SP already saved) */
466 std %r2,(PC_SLBSAVE+120)(%r1)
467 mfctr %r2 /* save CTR */
468 std %r2,(PC_SLBSAVE+128)(%r1)
471 addi %r1,%r1,PC_SLBSTACK-48+1024
479 bl handle_kernel_slb_spill
482 /* Save r28-31, restore r4-r12 */
484 ld %r4,(PC_SLBSAVE+32)(%r1)
485 ld %r5,(PC_SLBSAVE+40)(%r1)
486 ld %r6,(PC_SLBSAVE+48)(%r1)
487 ld %r7,(PC_SLBSAVE+56)(%r1)
488 ld %r8,(PC_SLBSAVE+64)(%r1)
489 ld %r9,(PC_SLBSAVE+72)(%r1)
490 ld %r10,(PC_SLBSAVE+80)(%r1)
491 ld %r11,(PC_SLBSAVE+88)(%r1)
492 ld %r12,(PC_SLBSAVE+96)(%r1)
493 std %r28,(PC_SLBSAVE+64)(%r1)
494 std %r29,(PC_SLBSAVE+72)(%r1)
495 std %r30,(PC_SLBSAVE+80)(%r1)
496 std %r31,(PC_SLBSAVE+88)(%r1)
498 /* Restore kernel mapping */
501 /* Restore remaining registers */
502 ld %r28,(PC_SLBSAVE+64)(%r1)
503 ld %r29,(PC_SLBSAVE+72)(%r1)
504 ld %r30,(PC_SLBSAVE+80)(%r1)
505 ld %r31,(PC_SLBSAVE+88)(%r1)
507 ld %r2,(PC_SLBSAVE+104)(%r1)
509 ld %r2,(PC_SLBSAVE+112)(%r1)
511 ld %r2,(PC_SLBSAVE+120)(%r1)
513 ld %r2,(PC_SLBSAVE+128)(%r1)
515 ld %r2,(PC_SLBSAVE+136)(%r1)
519 ld %r0,(PC_SLBSAVE+0)(%r1)
520 ld %r2,(PC_SLBSAVE+16)(%r1)
521 ld %r3,(PC_SLBSAVE+24)(%r1)
524 /* Back to whatever we were doing */
528 * For ALI: has to save DSISR and DAR
530 .globl CNAME(alitrap),CNAME(aliend)
532 mtsprg1 %r1 /* save SP */
534 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
535 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
536 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
537 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
538 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
541 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
542 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
543 mfsprg1 %r1 /* restore SP, in case of branch */
544 mflr %r28 /* save LR */
545 mfcr %r29 /* save CR */
547 /* Begin dance to branch to s_trap in a bit */
557 /* Put our exception vector in SPRG3 */
561 /* Test whether we already had PR set */
568 * Similar to the above for DSI
569 * Has to handle standard pagetable spills
571 .globl CNAME(dsitrap),CNAME(dsiend)
573 mtsprg1 %r1 /* save SP */
575 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
576 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
577 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
578 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
579 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
580 mfcr %r29 /* save CR */
581 mfxer %r30 /* save XER */
582 mtsprg2 %r30 /* in SPRG2 */
583 mfsrr1 %r31 /* test kernel mode */
585 mflr %r28 /* save LR (SP already saved) */
586 bl 1f /* Begin branching to disitrap */
591 blrl /* Branch to generictrap */
595 * Preamble code for DSI/ISI traps
598 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
604 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
605 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
606 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
607 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
608 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
609 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
610 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
611 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
612 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
613 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
616 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
617 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
620 /* Try to detect a kernel stack overflow */
623 bt 17,realtrap /* branch is user mode */
624 mfsprg1 %r31 /* get old SP */
625 clrrdi %r31,%r31,12 /* Round SP down to nearest page */
626 sub. %r30,%r31,%r30 /* SP - DAR */
628 neg %r30,%r30 /* modulo value */
629 1: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
630 bge %cr0,realtrap /* no, too far away. */
632 /* Now convert this DSI into a DDB trap. */
634 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
635 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
636 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
637 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
638 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
639 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
640 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
641 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
642 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
643 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
644 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
645 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
646 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
647 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
651 /* XXX need stack probe here */
653 /* Test whether we already had PR set */
656 mfsprg1 %r1 /* restore SP (might have been
658 bf 17,k_trap /* branch if PSL_PR is false */
660 ld %r1,PC_CURPCB(%r1)
661 mr %r27,%r28 /* Save LR, r29 */
663 bl restore_kernsrs /* enable kernel mapping */
669 * generictrap does some standard setup for trap handling to minimize
670 * the code that need be installed in the actual vectors. It expects
671 * the following conditions.
673 * R1 - Trap vector = LR & (0xff00 | R1)
674 * SPRG1 - Original R1 contents
675 * SPRG2 - Original LR
678 .globl CNAME(generictrap)
680 /* Save R1 for computing the exception vector */
683 /* Save interesting registers */
685 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
686 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
687 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
688 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
689 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
691 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
692 mfsprg1 %r1 /* restore SP, in case of branch */
693 mfsprg2 %r28 /* save LR */
694 mfcr %r29 /* save CR */
696 /* Compute the exception vector from the link register */
700 addi %r30,%r30,-4 /* The branch instruction, not the next */
704 /* Test whether we already had PR set */
709 bf 17,k_trap /* branch if PSL_PR is false */
712 ld %r1,PC_CURPCB(%r1)
713 mr %r27,%r28 /* Save LR, r29 */
715 bl restore_kernsrs /* enable kernel mapping */
720 * Now the common trap catching code.
723 FRAME_SETUP(PC_TEMPSAVE)
724 /* Call C interrupt dispatcher: */
728 bl CNAME(powerpc_interrupt)
731 .globl CNAME(trapexit) /* backtrace code sentinel */
733 /* Disable interrupts: */
735 andi. %r3,%r3,~PSL_EE@l
738 /* Test AST pending: */
739 ld %r5,FRAME_SRR1+48(%r1)
741 bf 17,1f /* branch if PSL_PR is false */
743 GET_CPUINFO(%r3) /* get per-CPU pointer */
744 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */
745 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
746 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
749 mfmsr %r3 /* re-enable interrupts */
757 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
759 b trapexit /* test ast ret value ? */
761 FRAME_LEAVE(PC_TEMPSAVE)
766 * Deliberate entry to dbtrap
768 ASENTRY_NOPROF(breakpoint)
772 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
773 mtmsr %r3 /* disable interrupts */
776 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3)
777 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
778 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
779 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
780 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
788 * Now the kdb trap catching code.
791 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
796 ld %r1,TRAP_TOCBASE(0) /* get new SP */
797 ld %r1,TOC_REF(tmpstk)(%r1)
798 addi %r1,%r1,(TMPSTKSZ-48)
800 FRAME_SETUP(PC_DBSAVE)
801 /* Call C trap code: */
804 bl CNAME(db_trap_glue)
808 /* This wasn't for KDB, so switch to real trap: */
809 ld %r3,FRAME_EXC+48(%r1) /* save exception */
811 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
812 FRAME_LEAVE(PC_DBSAVE)
813 mtsprg1 %r1 /* prepare for entrance to realtrap */
815 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
816 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
817 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
818 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
819 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
822 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
823 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
827 FRAME_LEAVE(PC_DBSAVE)
831 * In case of KDB we want a separate trap catcher for it
833 .globl CNAME(dblow),CNAME(dbend)
835 mtsprg1 %r1 /* save SP */
836 mtsprg2 %r29 /* save r29 */
837 mfcr %r29 /* save CR in r29 */
840 bf 17,1f /* branch if privileged */
842 /* Unprivileged case */
843 mtcr %r29 /* put the condition register back */
844 mfsprg2 %r29 /* ... and r29 */
845 mflr %r1 /* save LR */
846 mtsprg2 %r1 /* And then in SPRG2 */
848 ld %r1, TRAP_GENTRAP(0) /* Get branch address */
850 li %r1, 0 /* How to get the vector from LR */
851 blrl /* Branch to generictrap */
855 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */
856 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
857 mfsprg2 %r28 /* r29 holds cr... */
858 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
859 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
860 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
861 mflr %r28 /* save LR */
862 bl 9f /* Begin branch */
867 blrl /* Branch to generictrap */