2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
39 * #include <powerpc/aim/trap_subr.S>
43 * Save/restore segment registers
47 * Restore SRs for a pmap
49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
53 * User SRs are loaded through a pointer to the current pmap.
57 ld %r28,PC_USERSLB(%r28)
58 li %r29, 0 /* Set the counter to zero */
64 1: ld %r31, 0(%r28) /* Load SLB entry pointer */
65 cmpli 0, %r31, 0 /* If NULL, stop */
68 ld %r30, 0(%r31) /* Load SLBV */
69 ld %r31, 8(%r31) /* Load SLBE */
70 or %r31, %r31, %r29 /* Set SLBE slot */
71 slbmte %r30, %r31 /* Install SLB entry */
73 addi %r28, %r28, 8 /* Advance pointer */
78 * Kernel SRs are loaded directly from the PCPU fields
82 addi %r28,%r28,PC_KERNSLB
83 li %r29, 0 /* Set the counter to zero */
89 1: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */
92 ld %r31, 8(%r28) /* Load SLBE */
93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */
95 ld %r30, 0(%r28) /* Load SLBV */
96 slbmte %r30, %r31 /* Install SLB entry */
98 2: addi %r28, %r28, 16 /* Advance pointer */
100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */
105 * FRAME_SETUP assumes:
108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
114 * SRR0/1 as at start of trap
116 #define FRAME_SETUP(savearea) \
117 /* Have to enable translation to allow access of kernel stack: */ \
120 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
122 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
124 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
125 mtmsr %r30; /* stack can now be accessed */ \
127 mfsprg1 %r31; /* get saved SP */ \
128 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
129 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
130 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
131 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
132 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
133 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
135 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
136 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
137 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
138 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
139 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
140 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
141 std %r4, FRAME_4+48(%r1); \
142 std %r5, FRAME_5+48(%r1); \
143 std %r6, FRAME_6+48(%r1); \
144 std %r7, FRAME_7+48(%r1); \
145 std %r8, FRAME_8+48(%r1); \
146 std %r9, FRAME_9+48(%r1); \
147 std %r10, FRAME_10+48(%r1); \
148 std %r11, FRAME_11+48(%r1); \
149 std %r12, FRAME_12+48(%r1); \
150 std %r13, FRAME_13+48(%r1); \
151 std %r14, FRAME_14+48(%r1); \
152 std %r15, FRAME_15+48(%r1); \
153 std %r16, FRAME_16+48(%r1); \
154 std %r17, FRAME_17+48(%r1); \
155 std %r18, FRAME_18+48(%r1); \
156 std %r19, FRAME_19+48(%r1); \
157 std %r20, FRAME_20+48(%r1); \
158 std %r21, FRAME_21+48(%r1); \
159 std %r22, FRAME_22+48(%r1); \
160 std %r23, FRAME_23+48(%r1); \
161 std %r24, FRAME_24+48(%r1); \
162 std %r25, FRAME_25+48(%r1); \
163 std %r26, FRAME_26+48(%r1); \
164 std %r27, FRAME_27+48(%r1); \
165 std %r28, FRAME_28+48(%r1); \
166 std %r29, FRAME_29+48(%r1); \
167 std %r30, FRAME_30+48(%r1); \
168 std %r31, FRAME_31+48(%r1); \
169 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
170 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
171 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
172 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
176 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
177 std %r4, FRAME_CTR+48(1); \
178 std %r5, FRAME_EXC+48(1); \
179 std %r28,FRAME_AIM_DAR+48(1); \
180 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
181 std %r30,FRAME_SRR0+48(1); \
182 std %r31,FRAME_SRR1+48(1); \
183 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */
185 #define FRAME_LEAVE(savearea) \
186 /* Disable exceptions: */ \
188 andi. %r2,%r2,~PSL_EE@l; \
191 /* Now restore regs: */ \
192 ld %r2,FRAME_SRR0+48(%r1); \
193 ld %r3,FRAME_SRR1+48(%r1); \
194 ld %r4,FRAME_CTR+48(%r1); \
195 ld %r5,FRAME_XER+48(%r1); \
196 ld %r6,FRAME_LR+48(%r1); \
198 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
199 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
200 ld %r7,FRAME_CR+48(%r1); \
204 mtsprg1 %r7; /* save cr */ \
205 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
206 ld %r30,FRAME_30+48(%r1); \
207 ld %r29,FRAME_29+48(%r1); \
208 ld %r28,FRAME_28+48(%r1); \
209 ld %r27,FRAME_27+48(%r1); \
210 ld %r26,FRAME_26+48(%r1); \
211 ld %r25,FRAME_25+48(%r1); \
212 ld %r24,FRAME_24+48(%r1); \
213 ld %r23,FRAME_23+48(%r1); \
214 ld %r22,FRAME_22+48(%r1); \
215 ld %r21,FRAME_21+48(%r1); \
216 ld %r20,FRAME_20+48(%r1); \
217 ld %r19,FRAME_19+48(%r1); \
218 ld %r18,FRAME_18+48(%r1); \
219 ld %r17,FRAME_17+48(%r1); \
220 ld %r16,FRAME_16+48(%r1); \
221 ld %r15,FRAME_15+48(%r1); \
222 ld %r14,FRAME_14+48(%r1); \
223 ld %r13,FRAME_13+48(%r1); \
224 ld %r12,FRAME_12+48(%r1); \
225 ld %r11,FRAME_11+48(%r1); \
226 ld %r10,FRAME_10+48(%r1); \
227 ld %r9, FRAME_9+48(%r1); \
228 ld %r8, FRAME_8+48(%r1); \
229 ld %r7, FRAME_7+48(%r1); \
230 ld %r6, FRAME_6+48(%r1); \
231 ld %r5, FRAME_5+48(%r1); \
232 ld %r4, FRAME_4+48(%r1); \
233 ld %r3, FRAME_3+48(%r1); \
234 ld %r2, FRAME_2+48(%r1); \
235 ld %r0, FRAME_0+48(%r1); \
236 ld %r1, FRAME_1+48(%r1); \
237 /* Can't touch %r1 from here on */ \
238 mtsprg2 %r2; /* save r2 & r3 */ \
240 /* Disable translation, machine check and recoverability: */ \
242 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
245 /* Decide whether we return to user mode: */ \
247 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); \
249 bf 17,1f; /* branch if PSL_PR is false */ \
250 /* Restore user SRs */ \
252 std %r27,(savearea+CPUSAVE_R27)(%r3); \
253 std %r28,(savearea+CPUSAVE_R28)(%r3); \
254 std %r29,(savearea+CPUSAVE_R29)(%r3); \
255 std %r30,(savearea+CPUSAVE_R30)(%r3); \
256 std %r31,(savearea+CPUSAVE_R31)(%r3); \
257 mflr %r27; /* preserve LR */ \
258 bl restore_usersrs; /* uses r28-r31 */ \
260 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
261 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
262 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
263 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
264 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
265 1: mfsprg1 %r2; /* restore cr */ \
268 ld %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
270 ld %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
272 mfsprg2 %r2; /* restore r2 & r3 */ \
277 * Processor reset exception handler. These are typically
278 * the first instructions the processor executes after a
279 * software reset. We do this in two bits so that we are
280 * not still hanging around in the trap handling region
281 * once the MMU is turned on.
283 .globl CNAME(rstcode), CNAME(rstsize)
285 /* Explicitly set MSR[SF] */
293 CNAME(rstsize) = . - CNAME(rstcode)
296 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
297 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
300 ld %r2,tocbase@l(%r3)
302 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */
305 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */
307 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */
309 mr %r1,%r3 /* Use new stack */
310 bl CNAME(machdep_ap_bootstrap) /* And away! */
313 /* Should not be reached */
319 * This code gets copied to all the trap vectors
320 * (except ISI/DSI, ALI, and the interrupts)
323 .globl CNAME(trapcode),CNAME(trapsize)
325 mtsprg1 %r1 /* save SP */
326 mflr %r1 /* Save the old LR in r1 */
327 mtsprg2 %r1 /* And then in SPRG2 */
328 li %r1, 0xA0 /* How to get the vector from LR */
329 bla generictrap /* LR & SPRG3 is exception # */
330 CNAME(trapsize) = .-CNAME(trapcode)
333 * For ALI: has to save DSISR and DAR
335 .globl CNAME(alitrap),CNAME(alisize)
337 mtsprg1 %r1 /* save SP */
339 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
340 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
341 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
342 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
343 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
346 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
347 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
348 mfsprg1 %r1 /* restore SP, in case of branch */
349 mflr %r28 /* save LR */
350 mfcr %r29 /* save CR */
352 /* Put our exception vector in SPRG3 */
356 /* Test whether we already had PR set */
360 CNAME(alisize) = .-CNAME(alitrap)
363 * Similar to the above for DSI
364 * Has to handle BAT spills
365 * and standard pagetable spills
367 .globl CNAME(dsitrap),CNAME(dsisize)
369 mtsprg1 %r1 /* save SP */
371 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
372 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
373 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
374 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
375 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
376 mfsprg1 %r1 /* restore SP */
377 mfcr %r29 /* save CR */
378 mfxer %r30 /* save XER */
379 mtsprg2 %r30 /* in SPRG2 */
380 mfsrr1 %r31 /* test kernel mode */
382 mflr %r28 /* save LR (SP already saved) */
384 CNAME(dsisize) = .-CNAME(dsitrap)
387 * Preamble code for DSI/ISI traps
390 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
396 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
397 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
398 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
399 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
400 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
401 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
402 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
403 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
404 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
405 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
408 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
409 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
412 /* Try and detect a kernel stack overflow */
415 bt 17,realtrap /* branch is user mode */
416 mfsprg1 %r31 /* get old SP */
417 sub. %r30,%r31,%r30 /* SP - DAR */
419 neg %r30,%r30 /* modulo value */
420 1: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
421 bge %cr0,realtrap /* no, too far away. */
423 /* Now convert this DSI into a DDB trap. */
425 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
426 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
427 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
428 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
429 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
430 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
431 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
432 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
433 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
434 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
435 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
436 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
437 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
438 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
442 /* XXX need stack probe here */
444 /* Test whether we already had PR set */
447 mfsprg1 %r1 /* restore SP (might have been
449 bf 17,k_trap /* branch if PSL_PR is false */
451 ld %r1,PC_CURPCB(%r1)
452 mr %r27,%r28 /* Save LR, r29 */
454 bl restore_kernsrs /* enable kernel mapping */
460 * generictrap does some standard setup for trap handling to minimize
461 * the code that need be installed in the actual vectors. It expects
462 * the following conditions.
464 * R1 - Trap vector = LR & (0xff00 | R1)
465 * SPRG1 - Original R1 contents
466 * SPRG2 - Original LR
470 /* Save R1 for computing the exception vector */
473 /* Save interesting registers */
475 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
476 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
477 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
478 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
479 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
481 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
482 mfsprg1 %r1 /* restore SP, in case of branch */
483 mfsprg2 %r28 /* save LR */
484 mfcr %r29 /* save CR */
486 /* Compute the exception vector from the link register */
493 /* Test whether we already had PR set */
498 bf 17,k_trap /* branch if PSL_PR is false */
501 ld %r1,PC_CURPCB(%r1)
502 mr %r27,%r28 /* Save LR, r29 */
504 bl restore_kernsrs /* enable kernel mapping */
509 * Now the common trap catching code.
512 FRAME_SETUP(PC_TEMPSAVE)
513 /* Call C interrupt dispatcher: */
516 ld %r2,tocbase@l(%r3)
518 bl CNAME(powerpc_interrupt)
521 .globl CNAME(trapexit) /* backtrace code sentinel */
523 /* Disable interrupts: */
525 andi. %r3,%r3,~PSL_EE@l
528 /* Test AST pending: */
529 ld %r5,FRAME_SRR1+48(%r1)
531 bf 17,1f /* branch if PSL_PR is false */
533 GET_CPUINFO(%r3) /* get per-CPU pointer */
534 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */
535 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
536 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
539 mfmsr %r3 /* re-enable interrupts */
544 ld %r2,tocbase@l(%r3)
548 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
550 b trapexit /* test ast ret value ? */
552 FRAME_LEAVE(PC_TEMPSAVE)
557 * Deliberate entry to dbtrap
563 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
564 mtmsr %r3 /* disable interrupts */
567 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3)
568 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
569 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
570 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
571 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
579 * Now the kdb trap catching code.
582 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
587 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
588 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
590 FRAME_SETUP(PC_DBSAVE)
591 /* Call C trap code: */
593 ld %r2,tocbase@l(%r3)
595 bl CNAME(db_trap_glue)
599 /* This wasn't for KDB, so switch to real trap: */
600 ld %r3,FRAME_EXC+48(%r1) /* save exception */
602 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
603 FRAME_LEAVE(PC_DBSAVE)
604 mtsprg1 %r1 /* prepare for entrance to realtrap */
606 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
607 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
608 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
609 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
610 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
613 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
614 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
618 FRAME_LEAVE(PC_DBSAVE)
622 * In case of KDB we want a separate trap catcher for it
624 .globl CNAME(dblow),CNAME(dbsize)
626 mtsprg1 %r1 /* save SP */
627 mtsprg2 %r29 /* save r29 */
628 mfcr %r29 /* save CR in r29 */
631 bf 17,1f /* branch if privileged */
633 /* Unprivileged case */
634 mtcr %r29 /* put the condition register back */
635 mfsprg2 %r29 /* ... and r29 */
636 mflr %r1 /* save LR */
637 mtsprg2 %r1 /* And then in SPRG2 */
638 li %r1, 0 /* How to get the vector from LR */
640 bla generictrap /* and we look like a generic trap */
642 /* Privileged, so drop to KDB */
644 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */
645 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
646 mfsprg2 %r28 /* r29 holds cr... */
647 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
648 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
649 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
650 mflr %r28 /* save LR */
652 CNAME(dbsize) = .-CNAME(dblow)