2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011-2012 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/types.h>
33 #include <sys/systm.h>
35 #include <machine/machdep.h>
37 #include <powerpc/booke/dcr.h>
38 #include <powerpc/apm86xxx/apm86xxx.h>
40 #include <dev/fdt/fdt_common.h>
42 #define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF))
43 #define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32))
45 extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t,
47 extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *,
48 uint32_t *, uint32_t *);
50 unsigned int tlb_static_entries;
51 unsigned int tlb_current_entry = TLB_SIZE;
52 unsigned int tlb_misses = 0;
53 unsigned int tlb_invals = 0;
55 void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);
56 void tlb_map_mem(uint32_t, uint32_t, uint32_t);
60 booke_init_tlb(vm_paddr_t fdt_immr_pa)
63 /* Map register space */
64 tlb_map(APM86XXX_DEEP_SLEEP_VA,
65 OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA),
66 OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M,
67 TLB_SW | TLB_SR | TLB_I | TLB_G);
69 tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA),
70 OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M,
71 TLB_SW | TLB_SR | TLB_I | TLB_G);
73 tlb_map(APM86XXX_PRIMARY_FABRIC_VA,
74 OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA),
75 OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA),
76 TLB_VALID | TLB_SIZE_16M,
77 TLB_SW | TLB_SR | TLB_I | TLB_G);
79 tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA),
80 OCP_ADDR_WORDHI(APM86XXX_AHB_PA),
81 TLB_VALID | TLB_SIZE_16M,
82 TLB_SW | TLB_SR | TLB_I | TLB_G);
84 /* Map MailBox space */
85 tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA),
86 OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
87 TLB_VALID | TLB_SIZE_4K,
88 TLB_UX | TLB_UW | TLB_UR |
89 TLB_SX | TLB_SW | TLB_SR |
92 tlb_map(APM86XXX_MBOX_VA + 0x1000,
93 OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000,
94 OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
95 TLB_VALID | TLB_SIZE_4K,
96 TLB_UX | TLB_UW | TLB_UR |
97 TLB_SX | TLB_SW | TLB_SR |
100 tlb_map(APM86XXX_MBOX_VA + 0x2000,
101 OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000,
102 OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
103 TLB_VALID | TLB_SIZE_4K,
104 TLB_UX | TLB_UW | TLB_UR |
105 TLB_SX | TLB_SW | TLB_SR |
110 booke_enable_l1_cache(void)
115 booke_enable_l2_cache(void)
120 booke_disable_l2_cache(void)
124 /* Disable L2 cache op broadcast */
125 ccr1 = mfspr(SPR_CCR1);
126 ccr1 &= ~CCR1_L2COBE;
127 mtspr(SPR_CCR1, ccr1);
129 /* Set L2 array size to 0 i.e. disable L2 cache */
130 mtdcr(DCR_L2DCDCRAI, DCR_L2CR0);
131 l2cr0 = mfdcr(DCR_L2DCDCRDI);
133 mtdcr(DCR_L2DCDCRDI, l2cr0);
136 void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags,
140 tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms);
143 static void tlb_dump_entry(u_int entry)
145 uint32_t epn, rpn, erpn, tid, flags, perms;
148 tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms);
150 switch (flags & TLB_SIZE_MASK) {
181 printf("TLB[%02u]: 0x%08X => "
182 "0x%01X_%08X %s %c %c %s %s %s %s %s "
183 "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n",
184 entry, epn, erpn, rpn, size,
185 (flags & TLB_TS) ? '1' : '0',
186 (flags & TLB_VALID) ? 'V' : '.',
187 (perms & TLB_WL1) ? "WL1" : "___",
188 (perms & TLB_IL1I) ? "IL1I" : "____",
189 (perms & TLB_IL1D) ? "IL1D" : "____",
190 (perms & TLB_IL2I) ? "IL2I" : "____",
191 (perms & TLB_IL2D) ? "IL2D" : "____",
192 (perms & TLB_U0) ? '1' : '.',
193 (perms & TLB_U1) ? '2' : '.',
194 (perms & TLB_U2) ? '3' : '.',
195 (perms & TLB_U3) ? '4' : '.',
196 (perms & TLB_W) ? 'W' : '.',
197 (perms & TLB_I) ? 'I' : '.',
198 (perms & TLB_M) ? 'M' : '.',
199 (perms & TLB_G) ? 'G' : '.',
200 (perms & TLB_E) ? 'E' : '.',
201 (perms & TLB_UX) ? 'x' : '.',
202 (perms & TLB_UW) ? 'w' : '.',
203 (perms & TLB_UR) ? 'r' : '.',
204 (perms & TLB_SX) ? 'X' : '.',
205 (perms & TLB_SW) ? 'W' : '.',
206 (perms & TLB_SR) ? 'R' : '.',
214 for (i = 0; i < TLB_SIZE; i++)