2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_kern.h>
104 #include <vm/vm_pageout.h>
105 #include <vm/vm_extern.h>
106 #include <vm/vm_object.h>
107 #include <vm/vm_param.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
114 #include <machine/_inttypes.h>
115 #include <machine/cpu.h>
116 #include <machine/pcb.h>
117 #include <machine/platform.h>
119 #include <machine/tlb.h>
120 #include <machine/spr.h>
121 #include <machine/md_var.h>
122 #include <machine/mmuvar.h>
123 #include <machine/pmap.h>
124 #include <machine/pte.h>
130 #define SPARSE_MAPDEV
132 #define debugf(fmt, args...) printf(fmt, ##args)
134 #define debugf(fmt, args...)
138 #define PRI0ptrX "016lx"
140 #define PRI0ptrX "08x"
143 #define TODO panic("%s: not implemented", __func__);
145 extern unsigned char _etext[];
146 extern unsigned char _end[];
148 extern uint32_t *bootinfo;
151 vm_offset_t kernstart;
154 /* Message buffer and tables. */
155 static vm_offset_t data_start;
156 static vm_size_t data_end;
158 /* Phys/avail memory regions. */
159 static struct mem_region *availmem_regions;
160 static int availmem_regions_sz;
161 static struct mem_region *physmem_regions;
162 static int physmem_regions_sz;
164 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
165 static vm_offset_t zero_page_va;
166 static struct mtx zero_page_mutex;
168 static struct mtx tlbivax_mutex;
170 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
171 static vm_offset_t copy_page_src_va;
172 static vm_offset_t copy_page_dst_va;
173 static struct mtx copy_page_mutex;
175 /**************************************************************************/
177 /**************************************************************************/
179 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
180 vm_prot_t, u_int flags, int8_t psind);
182 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
183 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
185 unsigned int kernel_pdirs;
189 * If user pmap is processed with mmu_booke_remove and the resident count
190 * drops to 0, there are no more pages to remove, so we need not continue.
192 #define PMAP_REMOVE_DONE(pmap) \
193 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
195 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
196 extern int elf32_nxstack;
199 /**************************************************************************/
200 /* TLB and TID handling */
201 /**************************************************************************/
203 /* Translation ID busy table */
204 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
207 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
208 * core revisions and should be read from h/w registers during early config.
210 uint32_t tlb0_entries;
212 uint32_t tlb0_entries_per_way;
213 uint32_t tlb1_entries;
215 #define TLB0_ENTRIES (tlb0_entries)
216 #define TLB0_WAYS (tlb0_ways)
217 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
219 #define TLB1_ENTRIES (tlb1_entries)
221 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE;
223 static tlbtid_t tid_alloc(struct pmap *);
224 static void tid_flush(tlbtid_t tid);
228 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
230 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
234 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
235 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
236 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
237 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
239 static vm_size_t tsize2size(unsigned int);
240 static unsigned int size2tsize(vm_size_t);
241 static unsigned int ilog2(unsigned long);
243 static void set_mas4_defaults(void);
245 static inline void tlb0_flush_entry(vm_offset_t);
246 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
248 /**************************************************************************/
249 /* Page table management */
250 /**************************************************************************/
252 static struct rwlock_padalign pvh_global_lock;
254 /* Data for the pv entry allocation mechanism */
255 static uma_zone_t pvzone;
256 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
258 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
260 #ifndef PMAP_SHPGPERPROC
261 #define PMAP_SHPGPERPROC 200
265 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **,
266 unsigned int, boolean_t);
267 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int);
268 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int);
269 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t);
271 static void ptbl_init(void);
272 static struct ptbl_buf *ptbl_buf_alloc(void);
273 static void ptbl_buf_free(struct ptbl_buf *);
274 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
276 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t);
277 static void ptbl_free(mmu_t, pmap_t, unsigned int);
278 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
279 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
282 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
283 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
284 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
285 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
286 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t);
288 static pv_entry_t pv_alloc(void);
289 static void pv_free(pv_entry_t);
290 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
291 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
293 static void booke_pmap_init_qpages(void);
296 TAILQ_ENTRY(ptbl_buf) link; /* list link */
297 vm_offset_t kva; /* va of mapping */
300 #ifndef __powerpc64__
301 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
302 #define PTBL_BUFS (128 * 16)
304 /* ptbl free list and a lock used for access synchronization. */
305 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
306 static struct mtx ptbl_buf_freelist_lock;
308 /* Base address of kva space allocated fot ptbl bufs. */
309 static vm_offset_t ptbl_buf_pool_vabase;
311 /* Pointer to ptbl_buf structures. */
312 static struct ptbl_buf *ptbl_bufs;
316 extern tlb_entry_t __boot_tlb1[];
317 void pmap_bootstrap_ap(volatile uint32_t *);
321 * Kernel MMU interface
323 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
324 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
325 vm_size_t, vm_offset_t);
326 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
327 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
328 vm_offset_t, vm_page_t *, vm_offset_t, int);
329 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
330 vm_prot_t, u_int flags, int8_t psind);
331 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
332 vm_page_t, vm_prot_t);
333 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
335 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
336 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
338 static void mmu_booke_init(mmu_t);
339 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
340 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
341 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
342 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
343 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
345 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
347 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
348 vm_object_t, vm_pindex_t, vm_size_t);
349 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
350 static void mmu_booke_page_init(mmu_t, vm_page_t);
351 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
352 static void mmu_booke_pinit(mmu_t, pmap_t);
353 static void mmu_booke_pinit0(mmu_t, pmap_t);
354 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
356 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
357 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
358 static void mmu_booke_release(mmu_t, pmap_t);
359 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
360 static void mmu_booke_remove_all(mmu_t, vm_page_t);
361 static void mmu_booke_remove_write(mmu_t, vm_page_t);
362 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
363 static void mmu_booke_zero_page(mmu_t, vm_page_t);
364 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
365 static void mmu_booke_activate(mmu_t, struct thread *);
366 static void mmu_booke_deactivate(mmu_t, struct thread *);
367 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
368 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
369 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
370 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
371 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
372 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
373 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
374 static void mmu_booke_kremove(mmu_t, vm_offset_t);
375 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
376 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
378 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t,
380 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t,
382 static void mmu_booke_scan_init(mmu_t);
383 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m);
384 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr);
385 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr,
386 vm_size_t sz, vm_memattr_t mode);
387 static int mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm,
388 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
389 static int mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
390 int *is_user, vm_offset_t *decoded_addr);
393 static mmu_method_t mmu_booke_methods[] = {
394 /* pmap dispatcher interface */
395 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
396 MMUMETHOD(mmu_copy, mmu_booke_copy),
397 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
398 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
399 MMUMETHOD(mmu_enter, mmu_booke_enter),
400 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
401 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
402 MMUMETHOD(mmu_extract, mmu_booke_extract),
403 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
404 MMUMETHOD(mmu_init, mmu_booke_init),
405 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
406 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
407 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
408 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
409 MMUMETHOD(mmu_map, mmu_booke_map),
410 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
411 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
412 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
413 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
414 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
415 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
416 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
417 MMUMETHOD(mmu_protect, mmu_booke_protect),
418 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
419 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
420 MMUMETHOD(mmu_release, mmu_booke_release),
421 MMUMETHOD(mmu_remove, mmu_booke_remove),
422 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
423 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
424 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
425 MMUMETHOD(mmu_unwire, mmu_booke_unwire),
426 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
427 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
428 MMUMETHOD(mmu_activate, mmu_booke_activate),
429 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
430 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page),
431 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page),
433 /* Internal interfaces */
434 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
435 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
436 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
437 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
438 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
439 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
440 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
441 MMUMETHOD(mmu_kremove, mmu_booke_kremove),
442 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
443 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr),
444 MMUMETHOD(mmu_map_user_ptr, mmu_booke_map_user_ptr),
445 MMUMETHOD(mmu_decode_kernel_ptr, mmu_booke_decode_kernel_ptr),
447 /* dumpsys() support */
448 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
449 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
450 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init),
455 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
457 static __inline uint32_t
458 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
463 if (ma != VM_MEMATTR_DEFAULT) {
465 case VM_MEMATTR_UNCACHEABLE:
466 return (MAS2_I | MAS2_G);
467 case VM_MEMATTR_WRITE_COMBINING:
468 case VM_MEMATTR_WRITE_BACK:
469 case VM_MEMATTR_PREFETCHABLE:
471 case VM_MEMATTR_WRITE_THROUGH:
472 return (MAS2_W | MAS2_M);
473 case VM_MEMATTR_CACHEABLE:
479 * Assume the page is cache inhibited and access is guarded unless
480 * it's in our available memory array.
482 attrib = _TLB_ENTRY_IO;
483 for (i = 0; i < physmem_regions_sz; i++) {
484 if ((pa >= physmem_regions[i].mr_start) &&
485 (pa < (physmem_regions[i].mr_start +
486 physmem_regions[i].mr_size))) {
487 attrib = _TLB_ENTRY_MEM;
504 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
507 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
508 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
510 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
511 ("tlb_miss_lock: tried to lock self"));
513 tlb_lock(pc->pc_booke.tlb_lock);
515 CTR1(KTR_PMAP, "%s: locked", __func__);
522 tlb_miss_unlock(void)
530 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
532 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
533 __func__, pc->pc_cpuid);
535 tlb_unlock(pc->pc_booke.tlb_lock);
537 CTR1(KTR_PMAP, "%s: unlocked", __func__);
543 /* Return number of entries in TLB0. */
545 tlb0_get_tlbconf(void)
549 tlb0_cfg = mfspr(SPR_TLB0CFG);
550 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
551 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
552 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
555 /* Return number of entries in TLB1. */
557 tlb1_get_tlbconf(void)
561 tlb1_cfg = mfspr(SPR_TLB1CFG);
562 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
565 /**************************************************************************/
566 /* Page table related */
567 /**************************************************************************/
570 /* Initialize pool of kva ptbl buffers. */
576 /* Get a pointer to a PTE in a page table. */
577 static __inline pte_t *
578 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
583 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
585 pdir = pmap->pm_pp2d[PP2D_IDX(va)];
588 ptbl = pdir[PDIR_IDX(va)];
589 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL);
593 * allocate a page of pointers to page directories, do not preallocate the
597 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep)
603 KASSERT((pdir[pdir_idx] == NULL),
604 ("%s: valid pdir entry exists!", __func__));
606 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
607 while ((m = vm_page_alloc(NULL, pp2d_idx, req)) == NULL) {
616 /* Zero whole ptbl. */
617 pdir = (pte_t **)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
618 bzero(pdir, PAGE_SIZE);
623 /* Free pdir pages and invalidate pdir entry. */
625 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx)
632 pdir = pmap->pm_pp2d[pp2d_idx];
634 KASSERT((pdir != NULL), ("pdir_free: null pdir"));
636 pmap->pm_pp2d[pp2d_idx] = NULL;
638 va = (vm_offset_t) pdir;
639 pa = DMAP_TO_PHYS(va);
640 m = PHYS_TO_VM_PAGE(pa);
641 vm_page_free_zero(m);
645 * Decrement pdir pages hold count and attempt to free pdir pages. Called
646 * when removing directory entry from pdir.
648 * Return 1 if pdir pages were freed.
651 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx)
657 KASSERT((pmap != kernel_pmap),
658 ("pdir_unhold: unholding kernel pdir!"));
660 pdir = pmap->pm_pp2d[pp2d_idx];
662 /* decrement hold count */
663 pa = DMAP_TO_PHYS((vm_offset_t) pdir);
664 m = PHYS_TO_VM_PAGE(pa);
667 * Free pdir page if there are no dir entries in this pdir.
669 if (vm_page_unwire_noq(m)) {
670 pdir_free(mmu, pmap, pp2d_idx);
677 * Increment hold count for pdir pages. This routine is used when new ptlb
678 * entry is being inserted into pdir.
681 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir)
685 KASSERT((pmap != kernel_pmap),
686 ("pdir_hold: holding kernel pdir!"));
688 KASSERT((pdir != NULL), ("pdir_hold: null pdir"));
690 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pdir));
694 /* Allocate page table. */
696 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx,
703 KASSERT((pdir[pdir_idx] == NULL),
704 ("%s: valid ptbl entry exists!", __func__));
706 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
707 while ((m = vm_page_alloc(NULL, pdir_idx, req)) == NULL) {
709 rw_wunlock(&pvh_global_lock);
714 rw_wlock(&pvh_global_lock);
718 /* Zero whole ptbl. */
719 ptbl = (pte_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
720 bzero(ptbl, PAGE_SIZE);
725 /* Free ptbl pages and invalidate pdir entry. */
727 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx)
734 ptbl = pdir[pdir_idx];
736 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
738 pdir[pdir_idx] = NULL;
740 va = (vm_offset_t) ptbl;
741 pa = DMAP_TO_PHYS(va);
742 m = PHYS_TO_VM_PAGE(pa);
743 vm_page_free_zero(m);
747 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called
748 * when removing pte entry from ptbl.
750 * Return 1 if ptbl pages were freed.
753 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va)
761 pp2d_idx = PP2D_IDX(va);
762 pdir_idx = PDIR_IDX(va);
764 KASSERT((pmap != kernel_pmap),
765 ("ptbl_unhold: unholding kernel ptbl!"));
767 pdir = pmap->pm_pp2d[pp2d_idx];
768 ptbl = pdir[pdir_idx];
770 /* decrement hold count */
771 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t) ptbl));
774 * Free ptbl pages if there are no pte entries in this ptbl.
775 * wire_count has the same value for all ptbl pages, so check the
778 if (vm_page_unwire_noq(m)) {
779 ptbl_free(mmu, pmap, pdir, pdir_idx);
780 pdir_unhold(mmu, pmap, pp2d_idx);
787 * Increment hold count for ptbl pages. This routine is used when new pte
788 * entry is being inserted into ptbl.
791 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx)
796 KASSERT((pmap != kernel_pmap),
797 ("ptbl_hold: holding kernel ptbl!"));
799 ptbl = pdir[pdir_idx];
801 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
803 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t) ptbl));
808 /* Initialize pool of kva ptbl buffers. */
814 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
815 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
816 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
817 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
819 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
820 TAILQ_INIT(&ptbl_buf_freelist);
822 for (i = 0; i < PTBL_BUFS; i++) {
824 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
825 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
829 /* Get a ptbl_buf from the freelist. */
830 static struct ptbl_buf *
833 struct ptbl_buf *buf;
835 mtx_lock(&ptbl_buf_freelist_lock);
836 buf = TAILQ_FIRST(&ptbl_buf_freelist);
838 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
839 mtx_unlock(&ptbl_buf_freelist_lock);
841 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
846 /* Return ptbl buff to free pool. */
848 ptbl_buf_free(struct ptbl_buf *buf)
851 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
853 mtx_lock(&ptbl_buf_freelist_lock);
854 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
855 mtx_unlock(&ptbl_buf_freelist_lock);
859 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
862 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
864 struct ptbl_buf *pbuf;
866 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
870 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
871 if (pbuf->kva == (vm_offset_t)ptbl) {
872 /* Remove from pmap ptbl buf list. */
873 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
875 /* Free corresponding ptbl buf. */
881 /* Allocate page table. */
883 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
885 vm_page_t mtbl[PTBL_PAGES];
887 struct ptbl_buf *pbuf;
892 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
893 (pmap == kernel_pmap), pdir_idx);
895 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
896 ("ptbl_alloc: invalid pdir_idx"));
897 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
898 ("pte_alloc: valid ptbl entry exists!"));
900 pbuf = ptbl_buf_alloc();
902 panic("pte_alloc: couldn't alloc kernel virtual memory");
904 ptbl = (pte_t *)pbuf->kva;
906 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
908 for (i = 0; i < PTBL_PAGES; i++) {
909 pidx = (PTBL_PAGES * pdir_idx) + i;
910 while ((m = vm_page_alloc(NULL, pidx,
911 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
913 rw_wunlock(&pvh_global_lock);
915 ptbl_free_pmap_ptbl(pmap, ptbl);
916 for (j = 0; j < i; j++)
917 vm_page_free(mtbl[j]);
922 rw_wlock(&pvh_global_lock);
928 /* Map allocated pages into kernel_pmap. */
929 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
931 /* Zero whole ptbl. */
932 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
934 /* Add pbuf to the pmap ptbl bufs list. */
935 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
940 /* Free ptbl pages and invalidate pdir entry. */
942 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
950 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
951 (pmap == kernel_pmap), pdir_idx);
953 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
954 ("ptbl_free: invalid pdir_idx"));
956 ptbl = pmap->pm_pdir[pdir_idx];
958 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
960 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
963 * Invalidate the pdir entry as soon as possible, so that other CPUs
964 * don't attempt to look up the page tables we are releasing.
966 mtx_lock_spin(&tlbivax_mutex);
969 pmap->pm_pdir[pdir_idx] = NULL;
972 mtx_unlock_spin(&tlbivax_mutex);
974 for (i = 0; i < PTBL_PAGES; i++) {
975 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
976 pa = pte_vatopa(mmu, kernel_pmap, va);
977 m = PHYS_TO_VM_PAGE(pa);
978 vm_page_free_zero(m);
980 mmu_booke_kremove(mmu, va);
983 ptbl_free_pmap_ptbl(pmap, ptbl);
987 * Decrement ptbl pages hold count and attempt to free ptbl pages.
988 * Called when removing pte entry from ptbl.
990 * Return 1 if ptbl pages were freed.
993 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1000 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
1001 (pmap == kernel_pmap), pdir_idx);
1003 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1004 ("ptbl_unhold: invalid pdir_idx"));
1005 KASSERT((pmap != kernel_pmap),
1006 ("ptbl_unhold: unholding kernel ptbl!"));
1008 ptbl = pmap->pm_pdir[pdir_idx];
1010 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
1011 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
1012 ("ptbl_unhold: non kva ptbl"));
1014 /* decrement hold count */
1015 for (i = 0; i < PTBL_PAGES; i++) {
1016 pa = pte_vatopa(mmu, kernel_pmap,
1017 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1018 m = PHYS_TO_VM_PAGE(pa);
1023 * Free ptbl pages if there are no pte etries in this ptbl.
1024 * wire_count has the same value for all ptbl pages, so check the last
1027 if (m->wire_count == 0) {
1028 ptbl_free(mmu, pmap, pdir_idx);
1030 //debugf("ptbl_unhold: e (freed ptbl)\n");
1038 * Increment hold count for ptbl pages. This routine is used when a new pte
1039 * entry is being inserted into the ptbl.
1042 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1049 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
1052 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1053 ("ptbl_hold: invalid pdir_idx"));
1054 KASSERT((pmap != kernel_pmap),
1055 ("ptbl_hold: holding kernel ptbl!"));
1057 ptbl = pmap->pm_pdir[pdir_idx];
1059 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
1061 for (i = 0; i < PTBL_PAGES; i++) {
1062 pa = pte_vatopa(mmu, kernel_pmap,
1063 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1064 m = PHYS_TO_VM_PAGE(pa);
1070 /* Allocate pv_entry structure. */
1077 if (pv_entry_count > pv_entry_high_water)
1078 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
1079 pv = uma_zalloc(pvzone, M_NOWAIT);
1084 /* Free pv_entry structure. */
1085 static __inline void
1086 pv_free(pv_entry_t pve)
1090 uma_zfree(pvzone, pve);
1094 /* Allocate and initialize pv_entry structure. */
1096 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
1100 //int su = (pmap == kernel_pmap);
1101 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
1102 // (u_int32_t)pmap, va, (u_int32_t)m);
1106 panic("pv_insert: no pv entries!");
1108 pve->pv_pmap = pmap;
1111 /* add to pv_list */
1112 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1113 rw_assert(&pvh_global_lock, RA_WLOCKED);
1115 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
1117 //debugf("pv_insert: e\n");
1120 /* Destroy pv entry. */
1122 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
1126 //int su = (pmap == kernel_pmap);
1127 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
1129 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1130 rw_assert(&pvh_global_lock, RA_WLOCKED);
1133 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
1134 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
1135 /* remove from pv_list */
1136 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
1137 if (TAILQ_EMPTY(&m->md.pv_list))
1138 vm_page_aflag_clear(m, PGA_WRITEABLE);
1140 /* free pv entry struct */
1146 //debugf("pv_remove: e\n");
1149 #ifdef __powerpc64__
1151 * Clean pte entry, try to free page table page if requested.
1153 * Return 1 if ptbl pages were freed, otherwise return 0.
1156 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags)
1161 pte = pte_find(mmu, pmap, va);
1162 KASSERT(pte != NULL, ("%s: NULL pte", __func__));
1164 if (!PTE_ISVALID(pte))
1167 /* Get vm_page_t for mapped pte. */
1168 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1170 if (PTE_ISWIRED(pte))
1171 pmap->pm_stats.wired_count--;
1173 /* Handle managed entry. */
1174 if (PTE_ISMANAGED(pte)) {
1176 /* Handle modified pages. */
1177 if (PTE_ISMODIFIED(pte))
1180 /* Referenced pages. */
1181 if (PTE_ISREFERENCED(pte))
1182 vm_page_aflag_set(m, PGA_REFERENCED);
1184 /* Remove pv_entry from pv_list. */
1185 pv_remove(pmap, va, m);
1186 } else if (m->md.pv_tracked) {
1187 pv_remove(pmap, va, m);
1188 if (TAILQ_EMPTY(&m->md.pv_list))
1189 m->md.pv_tracked = false;
1191 mtx_lock_spin(&tlbivax_mutex);
1194 tlb0_flush_entry(va);
1198 mtx_unlock_spin(&tlbivax_mutex);
1200 pmap->pm_stats.resident_count--;
1202 if (flags & PTBL_UNHOLD) {
1203 return (ptbl_unhold(mmu, pmap, va));
1209 * Insert PTE for a given page and virtual address.
1212 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1215 unsigned int pp2d_idx = PP2D_IDX(va);
1216 unsigned int pdir_idx = PDIR_IDX(va);
1217 unsigned int ptbl_idx = PTBL_IDX(va);
1218 pte_t *ptbl, *pte, pte_tmp;
1221 /* Get the page directory pointer. */
1222 pdir = pmap->pm_pp2d[pp2d_idx];
1224 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep);
1226 /* Get the page table pointer. */
1227 ptbl = pdir[pdir_idx];
1230 /* Allocate page table pages. */
1231 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep);
1233 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1236 pte = &ptbl[ptbl_idx];
1239 * Check if there is valid mapping for requested va, if there
1242 pte = &ptbl[ptbl_idx];
1243 if (PTE_ISVALID(pte)) {
1244 pte_remove(mmu, pmap, va, PTBL_HOLD);
1247 * pte is not used, increment hold count for ptbl
1250 if (pmap != kernel_pmap)
1251 ptbl_hold(mmu, pmap, pdir, pdir_idx);
1255 if (pdir[pdir_idx] == NULL) {
1256 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL)
1257 pdir_hold(mmu, pmap, pdir);
1258 pdir[pdir_idx] = ptbl;
1260 if (pmap->pm_pp2d[pp2d_idx] == NULL)
1261 pmap->pm_pp2d[pp2d_idx] = pdir;
1264 * Insert pv_entry into pv_list for mapped page if part of managed
1267 if ((m->oflags & VPO_UNMANAGED) == 0) {
1268 flags |= PTE_MANAGED;
1270 /* Create and insert pv entry. */
1271 pv_insert(pmap, va, m);
1274 pmap->pm_stats.resident_count++;
1276 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1277 pte_tmp |= (PTE_VALID | flags);
1279 mtx_lock_spin(&tlbivax_mutex);
1282 tlb0_flush_entry(va);
1286 mtx_unlock_spin(&tlbivax_mutex);
1291 /* Return the pa for the given pmap/va. */
1293 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1298 pte = pte_find(mmu, pmap, va);
1299 if ((pte != NULL) && PTE_ISVALID(pte))
1300 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1305 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */
1307 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1314 /* Initialize kernel pdir */
1315 for (i = 0; i < kernel_pdirs; i++) {
1316 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] =
1317 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES));
1318 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES));
1319 j < PDIR_NENTRIES; j++) {
1320 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] =
1321 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE) +
1322 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE));
1327 * Fill in PTEs covering kernel code and data. They are not required
1328 * for address translation, as this area is covered by static TLB1
1329 * entries, but for pte_vatopa() to work correctly with kernel area
1332 for (va = addr; va < data_end; va += PAGE_SIZE) {
1333 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]);
1334 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1335 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1336 PTE_VALID | PTE_PS_4KB;
1341 * Clean pte entry, try to free page table page if requested.
1343 * Return 1 if ptbl pages were freed, otherwise return 0.
1346 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
1348 unsigned int pdir_idx = PDIR_IDX(va);
1349 unsigned int ptbl_idx = PTBL_IDX(va);
1354 //int su = (pmap == kernel_pmap);
1355 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
1356 // su, (u_int32_t)pmap, va, flags);
1358 ptbl = pmap->pm_pdir[pdir_idx];
1359 KASSERT(ptbl, ("pte_remove: null ptbl"));
1361 pte = &ptbl[ptbl_idx];
1363 if (pte == NULL || !PTE_ISVALID(pte))
1366 if (PTE_ISWIRED(pte))
1367 pmap->pm_stats.wired_count--;
1369 /* Get vm_page_t for mapped pte. */
1370 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1372 /* Handle managed entry. */
1373 if (PTE_ISMANAGED(pte)) {
1375 if (PTE_ISMODIFIED(pte))
1378 if (PTE_ISREFERENCED(pte))
1379 vm_page_aflag_set(m, PGA_REFERENCED);
1381 pv_remove(pmap, va, m);
1382 } else if (m->md.pv_tracked) {
1384 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is
1385 * used. This is needed by the NCSW support code for fast
1386 * VA<->PA translation.
1388 pv_remove(pmap, va, m);
1389 if (TAILQ_EMPTY(&m->md.pv_list))
1390 m->md.pv_tracked = false;
1393 mtx_lock_spin(&tlbivax_mutex);
1396 tlb0_flush_entry(va);
1400 mtx_unlock_spin(&tlbivax_mutex);
1402 pmap->pm_stats.resident_count--;
1404 if (flags & PTBL_UNHOLD) {
1405 //debugf("pte_remove: e (unhold)\n");
1406 return (ptbl_unhold(mmu, pmap, pdir_idx));
1409 //debugf("pte_remove: e\n");
1414 * Insert PTE for a given page and virtual address.
1417 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1420 unsigned int pdir_idx = PDIR_IDX(va);
1421 unsigned int ptbl_idx = PTBL_IDX(va);
1422 pte_t *ptbl, *pte, pte_tmp;
1424 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
1425 pmap == kernel_pmap, pmap, va);
1427 /* Get the page table pointer. */
1428 ptbl = pmap->pm_pdir[pdir_idx];
1431 /* Allocate page table pages. */
1432 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
1434 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1437 pmap->pm_pdir[pdir_idx] = ptbl;
1438 pte = &ptbl[ptbl_idx];
1441 * Check if there is valid mapping for requested
1442 * va, if there is, remove it.
1444 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
1445 if (PTE_ISVALID(pte)) {
1446 pte_remove(mmu, pmap, va, PTBL_HOLD);
1449 * pte is not used, increment hold count
1452 if (pmap != kernel_pmap)
1453 ptbl_hold(mmu, pmap, pdir_idx);
1458 * Insert pv_entry into pv_list for mapped page if part of managed
1461 if ((m->oflags & VPO_UNMANAGED) == 0) {
1462 flags |= PTE_MANAGED;
1464 /* Create and insert pv entry. */
1465 pv_insert(pmap, va, m);
1468 pmap->pm_stats.resident_count++;
1470 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1471 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
1473 mtx_lock_spin(&tlbivax_mutex);
1476 tlb0_flush_entry(va);
1480 mtx_unlock_spin(&tlbivax_mutex);
1484 /* Return the pa for the given pmap/va. */
1486 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1491 pte = pte_find(mmu, pmap, va);
1492 if ((pte != NULL) && PTE_ISVALID(pte))
1493 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1497 /* Get a pointer to a PTE in a page table. */
1499 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1501 unsigned int pdir_idx = PDIR_IDX(va);
1502 unsigned int ptbl_idx = PTBL_IDX(va);
1504 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
1506 if (pmap->pm_pdir[pdir_idx])
1507 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
1512 /* Set up kernel page tables. */
1514 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1520 /* Initialize kernel pdir */
1521 for (i = 0; i < kernel_ptbls; i++)
1522 kernel_pmap->pm_pdir[kptbl_min + i] =
1523 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES));
1526 * Fill in PTEs covering kernel code and data. They are not required
1527 * for address translation, as this area is covered by static TLB1
1528 * entries, but for pte_vatopa() to work correctly with kernel area
1531 for (va = addr; va < data_end; va += PAGE_SIZE) {
1532 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1533 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1534 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1535 PTE_VALID | PTE_PS_4KB;
1540 /**************************************************************************/
1542 /**************************************************************************/
1545 * This is called during booke_init, before the system is really initialized.
1548 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1550 vm_paddr_t phys_kernelend;
1551 struct mem_region *mp, *mp1;
1553 vm_paddr_t s, e, sz;
1554 vm_paddr_t physsz, hwphyssz;
1555 u_int phys_avail_count;
1556 vm_size_t kstack0_sz;
1557 vm_offset_t kernel_pdir, kstack0;
1558 vm_paddr_t kstack0_phys;
1561 debugf("mmu_booke_bootstrap: entered\n");
1563 /* Set interesting system properties */
1564 #ifdef __powerpc64__
1569 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
1573 /* Initialize invalidation mutex */
1574 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1576 /* Read TLB0 size and associativity. */
1580 * Align kernel start and end address (kernel image).
1581 * Note that kernel end does not necessarily relate to kernsize.
1582 * kernsize is the size of the kernel that is actually mapped.
1584 kernstart = trunc_page(start);
1585 data_start = round_page(kernelend);
1586 data_end = data_start;
1588 /* Allocate the dynamic per-cpu area. */
1589 dpcpu = (void *)data_end;
1590 data_end += DPCPU_SIZE;
1592 /* Allocate space for the message buffer. */
1593 msgbufp = (struct msgbuf *)data_end;
1594 data_end += msgbufsize;
1595 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1596 (uintptr_t)msgbufp, data_end);
1598 data_end = round_page(data_end);
1600 #ifndef __powerpc64__
1601 /* Allocate space for ptbl_bufs. */
1602 ptbl_bufs = (struct ptbl_buf *)data_end;
1603 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1604 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1605 (uintptr_t)ptbl_bufs, data_end);
1607 data_end = round_page(data_end);
1610 /* Allocate PTE tables for kernel KVA. */
1611 kernel_pdir = data_end;
1612 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS,
1614 #ifdef __powerpc64__
1615 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES);
1616 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE;
1618 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1619 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1620 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1621 kernel_pdir, data_end);
1623 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
1624 if (data_end - kernstart > kernsize) {
1625 kernsize += tlb1_mapin_region(kernstart + kernsize,
1626 kernload + kernsize, (data_end - kernstart) - kernsize);
1628 data_end = kernstart + kernsize;
1629 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
1632 * Clear the structures - note we can only do it safely after the
1633 * possible additional TLB1 translations are in place (above) so that
1634 * all range up to the currently calculated 'data_end' is covered.
1636 dpcpu_init(dpcpu, 0);
1637 #ifdef __powerpc64__
1638 memset((void *)kernel_pdir, 0,
1639 kernel_pdirs * PDIR_PAGES * PAGE_SIZE +
1640 kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1642 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1643 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1646 /*******************************************************/
1647 /* Set the start and end of kva. */
1648 /*******************************************************/
1649 virtual_avail = round_page(data_end);
1650 virtual_end = VM_MAX_KERNEL_ADDRESS;
1652 /* Allocate KVA space for page zero/copy operations. */
1653 zero_page_va = virtual_avail;
1654 virtual_avail += PAGE_SIZE;
1655 copy_page_src_va = virtual_avail;
1656 virtual_avail += PAGE_SIZE;
1657 copy_page_dst_va = virtual_avail;
1658 virtual_avail += PAGE_SIZE;
1659 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
1660 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
1661 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
1663 /* Initialize page zero/copy mutexes. */
1664 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1665 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1667 #ifndef __powerpc64__
1668 /* Allocate KVA space for ptbl bufs. */
1669 ptbl_buf_pool_vabase = virtual_avail;
1670 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1671 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1672 ptbl_buf_pool_vabase, virtual_avail);
1675 /* Calculate corresponding physical addresses for the kernel region. */
1676 phys_kernelend = kernload + kernsize;
1677 debugf("kernel image and allocated data:\n");
1678 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload);
1679 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
1680 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
1683 * Remove kernel physical address range from avail regions list. Page
1684 * align all regions. Non-page aligned memory isn't very interesting
1685 * to us. Also, sort the entries for ascending addresses.
1688 /* Retrieve phys/avail mem regions */
1689 mem_regions(&physmem_regions, &physmem_regions_sz,
1690 &availmem_regions, &availmem_regions_sz);
1692 if (nitems(phys_avail) < availmem_regions_sz)
1693 panic("mmu_booke_bootstrap: phys_avail too small");
1696 cnt = availmem_regions_sz;
1697 debugf("processing avail regions:\n");
1698 for (mp = availmem_regions; mp->mr_size; mp++) {
1700 e = mp->mr_start + mp->mr_size;
1701 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
1702 /* Check whether this region holds all of the kernel. */
1703 if (s < kernload && e > phys_kernelend) {
1704 availmem_regions[cnt].mr_start = phys_kernelend;
1705 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1708 /* Look whether this regions starts within the kernel. */
1709 if (s >= kernload && s < phys_kernelend) {
1710 if (e <= phys_kernelend)
1714 /* Now look whether this region ends within the kernel. */
1715 if (e > kernload && e <= phys_kernelend) {
1720 /* Now page align the start and size of the region. */
1726 debugf("%09jx-%09jx = %jx\n",
1727 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
1729 /* Check whether some memory is left here. */
1733 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1739 /* Do an insertion sort. */
1740 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1741 if (s < mp1->mr_start)
1744 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1752 availmem_regions_sz = cnt;
1754 /*******************************************************/
1755 /* Steal physical memory for kernel stack from the end */
1756 /* of the first avail region */
1757 /*******************************************************/
1758 kstack0_sz = kstack_pages * PAGE_SIZE;
1759 kstack0_phys = availmem_regions[0].mr_start +
1760 availmem_regions[0].mr_size;
1761 kstack0_phys -= kstack0_sz;
1762 availmem_regions[0].mr_size -= kstack0_sz;
1764 /*******************************************************/
1765 /* Fill in phys_avail table, based on availmem_regions */
1766 /*******************************************************/
1767 phys_avail_count = 0;
1770 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1772 debugf("fill in phys_avail:\n");
1773 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1775 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
1776 (uintmax_t)availmem_regions[i].mr_start,
1777 (uintmax_t)availmem_regions[i].mr_start +
1778 availmem_regions[i].mr_size,
1779 (uintmax_t)availmem_regions[i].mr_size);
1781 if (hwphyssz != 0 &&
1782 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1783 debugf(" hw.physmem adjust\n");
1784 if (physsz < hwphyssz) {
1785 phys_avail[j] = availmem_regions[i].mr_start;
1787 availmem_regions[i].mr_start +
1795 phys_avail[j] = availmem_regions[i].mr_start;
1796 phys_avail[j + 1] = availmem_regions[i].mr_start +
1797 availmem_regions[i].mr_size;
1799 physsz += availmem_regions[i].mr_size;
1801 physmem = btoc(physsz);
1803 /* Calculate the last available physical address. */
1804 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1806 Maxmem = powerpc_btop(phys_avail[i + 1]);
1808 debugf("Maxmem = 0x%08lx\n", Maxmem);
1809 debugf("phys_avail_count = %d\n", phys_avail_count);
1810 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
1811 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
1813 #ifdef __powerpc64__
1815 * Map the physical memory contiguously in TLB1.
1816 * Round so it fits into a single mapping.
1818 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
1822 /*******************************************************/
1823 /* Initialize (statically allocated) kernel pmap. */
1824 /*******************************************************/
1825 PMAP_LOCK_INIT(kernel_pmap);
1826 #ifndef __powerpc64__
1827 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1830 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
1831 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir);
1832 for (i = 0; i < MAXCPU; i++) {
1833 kernel_pmap->pm_tid[i] = TID_KERNEL;
1835 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1836 tidbusy[i][TID_KERNEL] = kernel_pmap;
1839 /* Mark kernel_pmap active on all CPUs */
1840 CPU_FILL(&kernel_pmap->pm_active);
1843 * Initialize the global pv list lock.
1845 rw_init(&pvh_global_lock, "pmap pv global");
1847 /*******************************************************/
1849 /*******************************************************/
1851 /* Enter kstack0 into kernel map, provide guard page */
1852 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1853 thread0.td_kstack = kstack0;
1854 thread0.td_kstack_pages = kstack_pages;
1856 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1857 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n",
1858 kstack0_phys, kstack0_phys + kstack0_sz);
1859 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
1860 kstack0, kstack0 + kstack0_sz);
1862 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1863 for (i = 0; i < kstack_pages; i++) {
1864 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1865 kstack0 += PAGE_SIZE;
1866 kstack0_phys += PAGE_SIZE;
1869 pmap_bootstrapped = 1;
1871 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
1872 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
1874 debugf("mmu_booke_bootstrap: exit\n");
1881 tlb_entry_t *e, tmp;
1884 /* Prepare TLB1 image for AP processors */
1886 for (i = 0; i < TLB1_ENTRIES; i++) {
1887 tlb1_read_entry(&tmp, i);
1889 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
1890 memcpy(e++, &tmp, sizeof(tmp));
1895 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1900 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1901 * have the snapshot of its contents in the s/w __boot_tlb1[] table
1902 * created by tlb1_ap_prep(), so use these values directly to
1903 * (re)program AP's TLB1 hardware.
1905 * Start at index 1 because index 0 has the kernel map.
1907 for (i = 1; i < TLB1_ENTRIES; i++) {
1908 if (__boot_tlb1[i].mas1 & MAS1_VALID)
1909 tlb1_write_entry(&__boot_tlb1[i], i);
1912 set_mas4_defaults();
1917 booke_pmap_init_qpages(void)
1924 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1925 if (pc->pc_qmap_addr == 0)
1926 panic("pmap_init_qpages: unable to allocate KVA");
1930 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1933 * Get the physical page address for the given pmap/virtual address.
1936 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1941 pa = pte_vatopa(mmu, pmap, va);
1948 * Extract the physical page address associated with the given
1949 * kernel virtual address.
1952 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1958 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1959 p = pte_vatopa(mmu, kernel_pmap, va);
1962 /* Check TLB1 mappings */
1963 for (i = 0; i < TLB1_ENTRIES; i++) {
1964 tlb1_read_entry(&e, i);
1965 if (!(e.mas1 & MAS1_VALID))
1967 if (va >= e.virt && va < e.virt + e.size)
1968 return (e.phys + (va - e.virt));
1976 * Initialize the pmap module.
1977 * Called by vm_init, to initialize any structures that the pmap
1978 * system needs to map virtual memory.
1981 mmu_booke_init(mmu_t mmu)
1983 int shpgperproc = PMAP_SHPGPERPROC;
1986 * Initialize the address space (zone) for the pv entries. Set a
1987 * high water mark so that the system can recover from excessive
1988 * numbers of pv entries.
1990 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1991 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1993 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1994 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1996 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1997 pv_entry_high_water = 9 * (pv_entry_max / 10);
1999 uma_zone_reserve_kva(pvzone, pv_entry_max);
2001 /* Pre-fill pvzone with initial number of pv entries. */
2002 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
2004 /* Initialize ptbl allocation. */
2009 * Map a list of wired pages into kernel virtual address space. This is
2010 * intended for temporary mappings which do not need page modification or
2011 * references recorded. Existing mappings in the region are overwritten.
2014 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
2019 while (count-- > 0) {
2020 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2027 * Remove page mappings from kernel virtual address space. Intended for
2028 * temporary mappings entered by mmu_booke_qenter.
2031 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
2036 while (count-- > 0) {
2037 mmu_booke_kremove(mmu, va);
2043 * Map a wired page into kernel virtual address space.
2046 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
2049 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
2053 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
2058 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2059 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
2061 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
2062 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
2063 flags |= PTE_PS_4KB;
2065 pte = pte_find(mmu, kernel_pmap, va);
2066 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
2068 mtx_lock_spin(&tlbivax_mutex);
2071 if (PTE_ISVALID(pte)) {
2073 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
2075 /* Flush entry from TLB0 */
2076 tlb0_flush_entry(va);
2079 *pte = PTE_RPN_FROM_PA(pa) | flags;
2081 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
2082 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
2083 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
2085 /* Flush the real memory from the instruction cache. */
2086 if ((flags & (PTE_I | PTE_G)) == 0)
2087 __syncicache((void *)va, PAGE_SIZE);
2090 mtx_unlock_spin(&tlbivax_mutex);
2094 * Remove a page from kernel page table.
2097 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
2101 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
2103 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2104 (va <= VM_MAX_KERNEL_ADDRESS)),
2105 ("mmu_booke_kremove: invalid va"));
2107 pte = pte_find(mmu, kernel_pmap, va);
2109 if (!PTE_ISVALID(pte)) {
2111 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
2116 mtx_lock_spin(&tlbivax_mutex);
2119 /* Invalidate entry in TLB0, update PTE. */
2120 tlb0_flush_entry(va);
2124 mtx_unlock_spin(&tlbivax_mutex);
2128 * Provide a kernel pointer corresponding to a given userland pointer.
2129 * The returned pointer is valid until the next time this function is
2130 * called in this thread. This is used internally in copyin/copyout.
2133 mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
2134 void **kaddr, size_t ulen, size_t *klen)
2137 if ((uintptr_t)uaddr + ulen > VM_MAXUSER_ADDRESS + PAGE_SIZE)
2140 *kaddr = (void *)(uintptr_t)uaddr;
2148 * Figure out where a given kernel pointer (usually in a fault) points
2149 * to from the VM's perspective, potentially remapping into userland's
2153 mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
2154 vm_offset_t *decoded_addr)
2157 if (addr < VM_MAXUSER_ADDRESS)
2162 *decoded_addr = addr;
2167 * Initialize pmap associated with process 0.
2170 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
2173 PMAP_LOCK_INIT(pmap);
2174 mmu_booke_pinit(mmu, pmap);
2175 PCPU_SET(curpmap, pmap);
2179 * Initialize a preallocated and zeroed pmap structure,
2180 * such as one in a vmspace structure.
2183 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
2187 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
2188 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
2190 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
2192 for (i = 0; i < MAXCPU; i++)
2193 pmap->pm_tid[i] = TID_NONE;
2194 CPU_ZERO(&kernel_pmap->pm_active);
2195 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2196 #ifdef __powerpc64__
2197 bzero(&pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES);
2198 TAILQ_INIT(&pmap->pm_pdir_list);
2200 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
2202 TAILQ_INIT(&pmap->pm_ptbl_list);
2206 * Release any resources held by the given physical map.
2207 * Called when a pmap initialized by mmu_booke_pinit is being released.
2208 * Should only be called if the map contains no valid mappings.
2211 mmu_booke_release(mmu_t mmu, pmap_t pmap)
2214 KASSERT(pmap->pm_stats.resident_count == 0,
2215 ("pmap_release: pmap resident count %ld != 0",
2216 pmap->pm_stats.resident_count));
2220 * Insert the given physical page at the specified virtual address in the
2221 * target physical map with the protection requested. If specified the page
2222 * will be wired down.
2225 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2226 vm_prot_t prot, u_int flags, int8_t psind)
2230 rw_wlock(&pvh_global_lock);
2232 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
2234 rw_wunlock(&pvh_global_lock);
2239 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2240 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
2245 int error, su, sync;
2247 pa = VM_PAGE_TO_PHYS(m);
2248 su = (pmap == kernel_pmap);
2251 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
2252 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
2253 // (u_int32_t)pmap, su, pmap->pm_tid,
2254 // (u_int32_t)m, va, pa, prot, flags);
2257 KASSERT(((va >= virtual_avail) &&
2258 (va <= VM_MAX_KERNEL_ADDRESS)),
2259 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
2261 KASSERT((va <= VM_MAXUSER_ADDRESS),
2262 ("mmu_booke_enter_locked: user pmap, non user va"));
2264 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2265 VM_OBJECT_ASSERT_LOCKED(m->object);
2267 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2270 * If there is an existing mapping, and the physical address has not
2271 * changed, must be protection or wiring change.
2273 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
2274 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
2277 * Before actually updating pte->flags we calculate and
2278 * prepare its new value in a helper var.
2281 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
2283 /* Wiring change, just update stats. */
2284 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
2285 if (!PTE_ISWIRED(pte)) {
2287 pmap->pm_stats.wired_count++;
2290 if (PTE_ISWIRED(pte)) {
2291 flags &= ~PTE_WIRED;
2292 pmap->pm_stats.wired_count--;
2296 if (prot & VM_PROT_WRITE) {
2297 /* Add write permissions. */
2302 if ((flags & PTE_MANAGED) != 0)
2303 vm_page_aflag_set(m, PGA_WRITEABLE);
2305 /* Handle modified pages, sense modify status. */
2308 * The PTE_MODIFIED flag could be set by underlying
2309 * TLB misses since we last read it (above), possibly
2310 * other CPUs could update it so we check in the PTE
2311 * directly rather than rely on that saved local flags
2314 if (PTE_ISMODIFIED(pte))
2318 if (prot & VM_PROT_EXECUTE) {
2324 * Check existing flags for execute permissions: if we
2325 * are turning execute permissions on, icache should
2328 if ((*pte & (PTE_UX | PTE_SX)) == 0)
2332 flags &= ~PTE_REFERENCED;
2335 * The new flags value is all calculated -- only now actually
2338 mtx_lock_spin(&tlbivax_mutex);
2341 tlb0_flush_entry(va);
2342 *pte &= ~PTE_FLAGS_MASK;
2346 mtx_unlock_spin(&tlbivax_mutex);
2350 * If there is an existing mapping, but it's for a different
2351 * physical address, pte_enter() will delete the old mapping.
2353 //if ((pte != NULL) && PTE_ISVALID(pte))
2354 // debugf("mmu_booke_enter_locked: replace\n");
2356 // debugf("mmu_booke_enter_locked: new\n");
2358 /* Now set up the flags and install the new mapping. */
2359 flags = (PTE_SR | PTE_VALID);
2365 if (prot & VM_PROT_WRITE) {
2370 if ((m->oflags & VPO_UNMANAGED) == 0)
2371 vm_page_aflag_set(m, PGA_WRITEABLE);
2374 if (prot & VM_PROT_EXECUTE) {
2380 /* If its wired update stats. */
2381 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
2384 error = pte_enter(mmu, pmap, m, va, flags,
2385 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
2387 return (KERN_RESOURCE_SHORTAGE);
2389 if ((flags & PMAP_ENTER_WIRED) != 0)
2390 pmap->pm_stats.wired_count++;
2392 /* Flush the real memory from the instruction cache. */
2393 if (prot & VM_PROT_EXECUTE)
2397 if (sync && (su || pmap == PCPU_GET(curpmap))) {
2398 __syncicache((void *)va, PAGE_SIZE);
2402 return (KERN_SUCCESS);
2406 * Maps a sequence of resident pages belonging to the same object.
2407 * The sequence begins with the given page m_start. This page is
2408 * mapped at the given virtual address start. Each subsequent page is
2409 * mapped at a virtual address that is offset from start by the same
2410 * amount as the page is offset from m_start within the object. The
2411 * last page in the sequence is the page with the largest offset from
2412 * m_start that can be mapped at a virtual address less than the given
2413 * virtual address end. Not every virtual page between start and end
2414 * is mapped; only those for which a resident page exists with the
2415 * corresponding offset from m_start are mapped.
2418 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
2419 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
2422 vm_pindex_t diff, psize;
2424 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2426 psize = atop(end - start);
2428 rw_wlock(&pvh_global_lock);
2430 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2431 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
2432 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
2433 PMAP_ENTER_NOSLEEP, 0);
2434 m = TAILQ_NEXT(m, listq);
2436 rw_wunlock(&pvh_global_lock);
2441 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2445 rw_wlock(&pvh_global_lock);
2447 mmu_booke_enter_locked(mmu, pmap, va, m,
2448 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP,
2450 rw_wunlock(&pvh_global_lock);
2455 * Remove the given range of addresses from the specified map.
2457 * It is assumed that the start and end are properly rounded to the page size.
2460 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
2465 int su = (pmap == kernel_pmap);
2467 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
2468 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
2471 KASSERT(((va >= virtual_avail) &&
2472 (va <= VM_MAX_KERNEL_ADDRESS)),
2473 ("mmu_booke_remove: kernel pmap, non kernel va"));
2475 KASSERT((va <= VM_MAXUSER_ADDRESS),
2476 ("mmu_booke_remove: user pmap, non user va"));
2479 if (PMAP_REMOVE_DONE(pmap)) {
2480 //debugf("mmu_booke_remove: e (empty)\n");
2484 hold_flag = PTBL_HOLD_FLAG(pmap);
2485 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
2487 rw_wlock(&pvh_global_lock);
2489 for (; va < endva; va += PAGE_SIZE) {
2490 pte = pte_find(mmu, pmap, va);
2491 if ((pte != NULL) && PTE_ISVALID(pte))
2492 pte_remove(mmu, pmap, va, hold_flag);
2495 rw_wunlock(&pvh_global_lock);
2497 //debugf("mmu_booke_remove: e\n");
2501 * Remove physical page from all pmaps in which it resides.
2504 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
2509 rw_wlock(&pvh_global_lock);
2510 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
2511 pvn = TAILQ_NEXT(pv, pv_link);
2513 PMAP_LOCK(pv->pv_pmap);
2514 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
2515 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
2516 PMAP_UNLOCK(pv->pv_pmap);
2518 vm_page_aflag_clear(m, PGA_WRITEABLE);
2519 rw_wunlock(&pvh_global_lock);
2523 * Map a range of physical addresses into kernel virtual address space.
2526 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2527 vm_paddr_t pa_end, int prot)
2529 vm_offset_t sva = *virt;
2530 vm_offset_t va = sva;
2532 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
2533 // sva, pa_start, pa_end);
2535 while (pa_start < pa_end) {
2536 mmu_booke_kenter(mmu, va, pa_start);
2538 pa_start += PAGE_SIZE;
2542 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
2547 * The pmap must be activated before it's address space can be accessed in any
2551 mmu_booke_activate(mmu_t mmu, struct thread *td)
2556 pmap = &td->td_proc->p_vmspace->vm_pmap;
2558 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
2559 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2561 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
2565 cpuid = PCPU_GET(cpuid);
2566 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
2567 PCPU_SET(curpmap, pmap);
2569 if (pmap->pm_tid[cpuid] == TID_NONE)
2572 /* Load PID0 register with pmap tid value. */
2573 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
2574 __asm __volatile("isync");
2576 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
2580 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
2581 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
2585 * Deactivate the specified process's address space.
2588 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
2592 pmap = &td->td_proc->p_vmspace->vm_pmap;
2594 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
2595 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2597 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
2599 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
2600 PCPU_SET(curpmap, NULL);
2604 * Copy the range specified by src_addr/len
2605 * from the source map to the range dst_addr/len
2606 * in the destination map.
2608 * This routine is only advisory and need not do anything.
2611 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
2612 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
2618 * Set the physical protection on the specified range of this map as requested.
2621 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2628 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2629 mmu_booke_remove(mmu, pmap, sva, eva);
2633 if (prot & VM_PROT_WRITE)
2637 for (va = sva; va < eva; va += PAGE_SIZE) {
2638 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2639 if (PTE_ISVALID(pte)) {
2640 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2642 mtx_lock_spin(&tlbivax_mutex);
2645 /* Handle modified pages. */
2646 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2649 tlb0_flush_entry(va);
2650 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2653 mtx_unlock_spin(&tlbivax_mutex);
2661 * Clear the write and modified bits in each of the given page's mappings.
2664 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2669 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2670 ("mmu_booke_remove_write: page %p is not managed", m));
2673 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2674 * set by another thread while the object is locked. Thus,
2675 * if PGA_WRITEABLE is clear, no page table entries need updating.
2677 VM_OBJECT_ASSERT_WLOCKED(m->object);
2678 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2680 rw_wlock(&pvh_global_lock);
2681 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2682 PMAP_LOCK(pv->pv_pmap);
2683 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2684 if (PTE_ISVALID(pte)) {
2685 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2687 mtx_lock_spin(&tlbivax_mutex);
2690 /* Handle modified pages. */
2691 if (PTE_ISMODIFIED(pte))
2694 /* Flush mapping from TLB0. */
2695 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2698 mtx_unlock_spin(&tlbivax_mutex);
2701 PMAP_UNLOCK(pv->pv_pmap);
2703 vm_page_aflag_clear(m, PGA_WRITEABLE);
2704 rw_wunlock(&pvh_global_lock);
2708 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2713 #ifndef __powerpc64__
2720 #ifndef __powerpc64__
2721 rw_wlock(&pvh_global_lock);
2722 pmap = PCPU_GET(curpmap);
2723 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2727 pte = pte_find(mmu, pm, va);
2728 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2732 sync_sz = PAGE_SIZE - (va & PAGE_MASK);
2733 sync_sz = min(sync_sz, sz);
2735 #ifdef __powerpc64__
2736 pa += (va & PAGE_MASK);
2737 __syncicache((void *)PHYS_TO_DMAP(pa), sync_sz);
2740 /* Create a mapping in the active pmap. */
2742 m = PHYS_TO_VM_PAGE(pa);
2744 pte_enter(mmu, pmap, m, addr,
2745 PTE_SR | PTE_VALID, FALSE);
2746 addr += (va & PAGE_MASK);
2747 __syncicache((void *)addr, sync_sz);
2748 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2751 __syncicache((void *)va, sync_sz);
2757 #ifndef __powerpc64__
2758 rw_wunlock(&pvh_global_lock);
2763 * Atomically extract and hold the physical page with the given
2764 * pmap and virtual address pair if that mapping permits the given
2768 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2780 pte = pte_find(mmu, pmap, va);
2781 if ((pte != NULL) && PTE_ISVALID(pte)) {
2782 if (pmap == kernel_pmap)
2787 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2788 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2790 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2801 * Initialize a vm_page's machine-dependent fields.
2804 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2807 m->md.pv_tracked = 0;
2808 TAILQ_INIT(&m->md.pv_list);
2812 * mmu_booke_zero_page_area zeros the specified hardware page by
2813 * mapping it into virtual memory and using bzero to clear
2816 * off and size must reside within a single page.
2819 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2823 /* XXX KASSERT off and size are within a single page? */
2825 #ifdef __powerpc64__
2826 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2827 bzero((caddr_t)va + off, size);
2829 mtx_lock(&zero_page_mutex);
2832 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2833 bzero((caddr_t)va + off, size);
2834 mmu_booke_kremove(mmu, va);
2836 mtx_unlock(&zero_page_mutex);
2841 * mmu_booke_zero_page zeros the specified hardware page.
2844 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2846 vm_offset_t off, va;
2848 #ifdef __powerpc64__
2849 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2851 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
2852 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
2855 mtx_lock(&zero_page_mutex);
2857 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2859 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
2860 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
2862 mmu_booke_kremove(mmu, va);
2864 mtx_unlock(&zero_page_mutex);
2869 * mmu_booke_copy_page copies the specified (machine independent) page by
2870 * mapping the page into virtual memory and using memcopy to copy the page,
2871 * one machine dependent page at a time.
2874 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2876 vm_offset_t sva, dva;
2878 #ifdef __powerpc64__
2879 sva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(sm));
2880 dva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dm));
2881 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2883 sva = copy_page_src_va;
2884 dva = copy_page_dst_va;
2886 mtx_lock(©_page_mutex);
2887 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2888 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2890 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2892 mmu_booke_kremove(mmu, dva);
2893 mmu_booke_kremove(mmu, sva);
2894 mtx_unlock(©_page_mutex);
2899 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2900 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2903 vm_offset_t a_pg_offset, b_pg_offset;
2906 #ifdef __powerpc64__
2909 while (xfersize > 0) {
2910 a_pg_offset = a_offset & PAGE_MASK;
2911 pa = ma[a_offset >> PAGE_SHIFT];
2912 b_pg_offset = b_offset & PAGE_MASK;
2913 pb = mb[b_offset >> PAGE_SHIFT];
2914 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2915 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2916 a_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pa)) +
2918 b_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pb)) +
2920 bcopy(a_cp, b_cp, cnt);
2926 mtx_lock(©_page_mutex);
2927 while (xfersize > 0) {
2928 a_pg_offset = a_offset & PAGE_MASK;
2929 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2930 mmu_booke_kenter(mmu, copy_page_src_va,
2931 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2932 a_cp = (char *)copy_page_src_va + a_pg_offset;
2933 b_pg_offset = b_offset & PAGE_MASK;
2934 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2935 mmu_booke_kenter(mmu, copy_page_dst_va,
2936 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2937 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2938 bcopy(a_cp, b_cp, cnt);
2939 mmu_booke_kremove(mmu, copy_page_dst_va);
2940 mmu_booke_kremove(mmu, copy_page_src_va);
2945 mtx_unlock(©_page_mutex);
2950 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m)
2952 #ifdef __powerpc64__
2953 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
2960 paddr = VM_PAGE_TO_PHYS(m);
2962 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
2963 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
2964 flags |= PTE_PS_4KB;
2967 qaddr = PCPU_GET(qmap_addr);
2969 pte = pte_find(mmu, kernel_pmap, qaddr);
2971 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy"));
2974 * XXX: tlbivax is broadcast to other cores, but qaddr should
2975 * not be present in other TLBs. Is there a better instruction
2976 * sequence to use? Or just forget it & use mmu_booke_kenter()...
2978 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK));
2979 __asm __volatile("isync; msync");
2981 *pte = PTE_RPN_FROM_PA(paddr) | flags;
2983 /* Flush the real memory from the instruction cache. */
2984 if ((flags & (PTE_I | PTE_G)) == 0)
2985 __syncicache((void *)qaddr, PAGE_SIZE);
2992 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr)
2994 #ifndef __powerpc64__
2997 pte = pte_find(mmu, kernel_pmap, addr);
2999 KASSERT(PCPU_GET(qmap_addr) == addr,
3000 ("mmu_booke_quick_remove_page: invalid address"));
3002 ("mmu_booke_quick_remove_page: PTE not in use"));
3010 * Return whether or not the specified physical page was modified
3011 * in any of physical maps.
3014 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
3020 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3021 ("mmu_booke_is_modified: page %p is not managed", m));
3025 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3026 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3027 * is clear, no PTEs can be modified.
3029 VM_OBJECT_ASSERT_WLOCKED(m->object);
3030 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3032 rw_wlock(&pvh_global_lock);
3033 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3034 PMAP_LOCK(pv->pv_pmap);
3035 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3037 if (PTE_ISMODIFIED(pte))
3040 PMAP_UNLOCK(pv->pv_pmap);
3044 rw_wunlock(&pvh_global_lock);
3049 * Return whether or not the specified virtual address is eligible
3053 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
3060 * Return whether or not the specified physical page was referenced
3061 * in any physical maps.
3064 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
3070 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3071 ("mmu_booke_is_referenced: page %p is not managed", m));
3073 rw_wlock(&pvh_global_lock);
3074 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3075 PMAP_LOCK(pv->pv_pmap);
3076 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3078 if (PTE_ISREFERENCED(pte))
3081 PMAP_UNLOCK(pv->pv_pmap);
3085 rw_wunlock(&pvh_global_lock);
3090 * Clear the modify bits on the specified physical page.
3093 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
3098 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3099 ("mmu_booke_clear_modify: page %p is not managed", m));
3100 VM_OBJECT_ASSERT_WLOCKED(m->object);
3101 KASSERT(!vm_page_xbusied(m),
3102 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
3105 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
3106 * If the object containing the page is locked and the page is not
3107 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
3109 if ((m->aflags & PGA_WRITEABLE) == 0)
3111 rw_wlock(&pvh_global_lock);
3112 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3113 PMAP_LOCK(pv->pv_pmap);
3114 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3116 mtx_lock_spin(&tlbivax_mutex);
3119 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
3120 tlb0_flush_entry(pv->pv_va);
3121 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
3126 mtx_unlock_spin(&tlbivax_mutex);
3128 PMAP_UNLOCK(pv->pv_pmap);
3130 rw_wunlock(&pvh_global_lock);
3134 * Return a count of reference bits for a page, clearing those bits.
3135 * It is not necessary for every reference bit to be cleared, but it
3136 * is necessary that 0 only be returned when there are truly no
3137 * reference bits set.
3139 * As an optimization, update the page's dirty field if a modified bit is
3140 * found while counting reference bits. This opportunistic update can be
3141 * performed at low cost and can eliminate the need for some future calls
3142 * to pmap_is_modified(). However, since this function stops after
3143 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3144 * dirty pages. Those dirty pages will only be detected by a future call
3145 * to pmap_is_modified().
3148 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
3154 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3155 ("mmu_booke_ts_referenced: page %p is not managed", m));
3157 rw_wlock(&pvh_global_lock);
3158 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3159 PMAP_LOCK(pv->pv_pmap);
3160 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3162 if (PTE_ISMODIFIED(pte))
3164 if (PTE_ISREFERENCED(pte)) {
3165 mtx_lock_spin(&tlbivax_mutex);
3168 tlb0_flush_entry(pv->pv_va);
3169 *pte &= ~PTE_REFERENCED;
3172 mtx_unlock_spin(&tlbivax_mutex);
3174 if (++count >= PMAP_TS_REFERENCED_MAX) {
3175 PMAP_UNLOCK(pv->pv_pmap);
3180 PMAP_UNLOCK(pv->pv_pmap);
3182 rw_wunlock(&pvh_global_lock);
3187 * Clear the wired attribute from the mappings for the specified range of
3188 * addresses in the given pmap. Every valid mapping within that range must
3189 * have the wired attribute set. In contrast, invalid mappings cannot have
3190 * the wired attribute set, so they are ignored.
3192 * The wired attribute of the page table entry is not a hardware feature, so
3193 * there is no need to invalidate any TLB entries.
3196 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3202 for (va = sva; va < eva; va += PAGE_SIZE) {
3203 if ((pte = pte_find(mmu, pmap, va)) != NULL &&
3205 if (!PTE_ISWIRED(pte))
3206 panic("mmu_booke_unwire: pte %p isn't wired",
3209 pmap->pm_stats.wired_count--;
3217 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
3218 * page. This count may be changed upwards or downwards in the future; it is
3219 * only necessary that true be returned for a small subset of pmaps for proper
3223 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
3229 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3230 ("mmu_booke_page_exists_quick: page %p is not managed", m));
3233 rw_wlock(&pvh_global_lock);
3234 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3235 if (pv->pv_pmap == pmap) {
3242 rw_wunlock(&pvh_global_lock);
3247 * Return the number of managed mappings to the given physical page that are
3251 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
3257 if ((m->oflags & VPO_UNMANAGED) != 0)
3259 rw_wlock(&pvh_global_lock);
3260 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3261 PMAP_LOCK(pv->pv_pmap);
3262 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
3263 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
3265 PMAP_UNLOCK(pv->pv_pmap);
3267 rw_wunlock(&pvh_global_lock);
3272 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3278 * This currently does not work for entries that
3279 * overlap TLB1 entries.
3281 for (i = 0; i < TLB1_ENTRIES; i ++) {
3282 if (tlb1_iomapped(i, pa, size, &va) == 0)
3290 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
3296 /* Minidumps are based on virtual memory addresses. */
3298 *va = (void *)(vm_offset_t)pa;
3302 /* Raw physical memory dumps don't have a virtual address. */
3303 /* We always map a 256MB page at 256M. */
3304 gran = 256 * 1024 * 1024;
3305 ppa = rounddown2(pa, gran);
3308 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
3310 if (sz > (gran - ofs))
3311 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
3316 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va)
3324 /* Minidumps are based on virtual memory addresses. */
3325 /* Nothing to do... */
3329 for (i = 0; i < TLB1_ENTRIES; i++) {
3330 tlb1_read_entry(&e, i);
3331 if (!(e.mas1 & MAS1_VALID))
3335 /* Raw physical memory dumps don't have a virtual address. */
3340 tlb1_write_entry(&e, i);
3342 gran = 256 * 1024 * 1024;
3343 ppa = rounddown2(pa, gran);
3345 if (sz > (gran - ofs)) {
3350 tlb1_write_entry(&e, i);
3354 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
3357 mmu_booke_scan_init(mmu_t mmu)
3364 /* Initialize phys. segments for dumpsys(). */
3365 memset(&dump_map, 0, sizeof(dump_map));
3366 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
3367 &availmem_regions_sz);
3368 for (i = 0; i < physmem_regions_sz; i++) {
3369 dump_map[i].pa_start = physmem_regions[i].mr_start;
3370 dump_map[i].pa_size = physmem_regions[i].mr_size;
3375 /* Virtual segments for minidumps: */
3376 memset(&dump_map, 0, sizeof(dump_map));
3378 /* 1st: kernel .data and .bss. */
3379 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
3380 dump_map[0].pa_size =
3381 round_page((uintptr_t)_end) - dump_map[0].pa_start;
3383 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
3384 dump_map[1].pa_start = data_start;
3385 dump_map[1].pa_size = data_end - data_start;
3387 /* 3rd: kernel VM. */
3388 va = dump_map[1].pa_start + dump_map[1].pa_size;
3389 /* Find start of next chunk (from va). */
3390 while (va < virtual_end) {
3391 /* Don't dump the buffer cache. */
3392 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
3393 va = kmi.buffer_eva;
3396 pte = pte_find(mmu, kernel_pmap, va);
3397 if (pte != NULL && PTE_ISVALID(pte))
3401 if (va < virtual_end) {
3402 dump_map[2].pa_start = va;
3404 /* Find last page in chunk. */
3405 while (va < virtual_end) {
3406 /* Don't run into the buffer cache. */
3407 if (va == kmi.buffer_sva)
3409 pte = pte_find(mmu, kernel_pmap, va);
3410 if (pte == NULL || !PTE_ISVALID(pte))
3414 dump_map[2].pa_size = va - dump_map[2].pa_start;
3419 * Map a set of physical memory pages into the kernel virtual address space.
3420 * Return a pointer to where it is mapped. This routine is intended to be used
3421 * for mapping device memory, NOT real memory.
3424 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3427 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
3431 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3435 uintptr_t va, tmpva;
3440 * Check if this is premapped in TLB1. Note: this should probably also
3441 * check whether a sequence of TLB1 entries exist that match the
3442 * requirement, but now only checks the easy case.
3444 for (i = 0; i < TLB1_ENTRIES; i++) {
3445 tlb1_read_entry(&e, i);
3446 if (!(e.mas1 & MAS1_VALID))
3449 (pa + size) <= (e.phys + e.size) &&
3450 (ma == VM_MEMATTR_DEFAULT ||
3451 tlb_calc_wimg(pa, ma) ==
3452 (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))))
3453 return (void *)(e.virt +
3454 (vm_offset_t)(pa - e.phys));
3457 size = roundup(size, PAGE_SIZE);
3460 * The device mapping area is between VM_MAXUSER_ADDRESS and
3461 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
3463 #ifdef SPARSE_MAPDEV
3465 * With a sparse mapdev, align to the largest starting region. This
3466 * could feasibly be optimized for a 'best-fit' alignment, but that
3467 * calculation could be very costly.
3468 * Align to the smaller of:
3469 * - first set bit in overlap of (pa & size mask)
3470 * - largest size envelope
3472 * It's possible the device mapping may start at a PA that's not larger
3473 * than the size mask, so we need to offset in to maximize the TLB entry
3474 * range and minimize the number of used TLB entries.
3477 tmpva = tlb1_map_base;
3478 sz = ffsl(((1 << flsl(size-1)) - 1) & pa);
3479 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
3480 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
3481 #ifdef __powerpc64__
3482 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size));
3484 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
3487 #ifdef __powerpc64__
3488 va = atomic_fetchadd_long(&tlb1_map_base, size);
3490 va = atomic_fetchadd_int(&tlb1_map_base, size);
3496 sz = 1 << (ilog2(size) & ~1);
3497 /* Align size to PA */
3501 } while (pa % sz != 0);
3503 /* Now align from there to VA */
3507 } while (va % sz != 0);
3510 printf("Wiring VA=%lx to PA=%jx (size=%lx)\n",
3511 va, (uintmax_t)pa, sz);
3512 if (tlb1_set_entry(va, pa, sz,
3513 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)) < 0)
3524 * 'Unmap' a range mapped by mmu_booke_mapdev().
3527 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
3529 #ifdef SUPPORTS_SHRINKING_TLB1
3530 vm_offset_t base, offset;
3533 * Unmap only if this is inside kernel virtual space.
3535 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
3536 base = trunc_page(va);
3537 offset = va & PAGE_MASK;
3538 size = roundup(offset + size, PAGE_SIZE);
3539 kva_free(base, size);
3545 * mmu_booke_object_init_pt preloads the ptes for a given object into the
3546 * specified pmap. This eliminates the blast of soft faults on process startup
3547 * and immediately after an mmap.
3550 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3551 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
3554 VM_OBJECT_ASSERT_WLOCKED(object);
3555 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3556 ("mmu_booke_object_init_pt: non-device object"));
3560 * Perform the pmap work for mincore.
3563 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3564 vm_paddr_t *locked_pa)
3567 /* XXX: this should be implemented at some point */
3572 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz,
3580 /* Check TLB1 mappings */
3581 for (i = 0; i < TLB1_ENTRIES; i++) {
3582 tlb1_read_entry(&e, i);
3583 if (!(e.mas1 & MAS1_VALID))
3585 if (addr >= e.virt && addr < e.virt + e.size)
3588 if (i < TLB1_ENTRIES) {
3589 /* Only allow full mappings to be modified for now. */
3590 /* Validate the range. */
3591 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
3592 tlb1_read_entry(&e, j);
3593 if (va != e.virt || (sz - (va - addr) < e.size))
3596 for (va = addr; va < addr + sz; va += e.size, i++) {
3597 tlb1_read_entry(&e, i);
3598 e.mas2 &= ~MAS2_WIMGE_MASK;
3599 e.mas2 |= tlb_calc_wimg(e.phys, mode);
3602 * Write it out to the TLB. Should really re-sync with other
3605 tlb1_write_entry(&e, i);
3610 /* Not in TLB1, try through pmap */
3611 /* First validate the range. */
3612 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3613 pte = pte_find(mmu, kernel_pmap, va);
3614 if (pte == NULL || !PTE_ISVALID(pte))
3618 mtx_lock_spin(&tlbivax_mutex);
3620 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3621 pte = pte_find(mmu, kernel_pmap, va);
3622 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
3623 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
3624 tlb0_flush_entry(va);
3627 mtx_unlock_spin(&tlbivax_mutex);
3632 /**************************************************************************/
3634 /**************************************************************************/
3637 * Allocate a TID. If necessary, steal one from someone else.
3638 * The new TID is flushed from the TLB before returning.
3641 tid_alloc(pmap_t pmap)
3646 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
3648 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
3650 thiscpu = PCPU_GET(cpuid);
3652 tid = PCPU_GET(booke.tid_next);
3655 PCPU_SET(booke.tid_next, tid + 1);
3657 /* If we are stealing TID then clear the relevant pmap's field */
3658 if (tidbusy[thiscpu][tid] != NULL) {
3660 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
3662 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
3664 /* Flush all entries from TLB0 matching this TID. */
3668 tidbusy[thiscpu][tid] = pmap;
3669 pmap->pm_tid[thiscpu] = tid;
3670 __asm __volatile("msync; isync");
3672 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
3673 PCPU_GET(booke.tid_next));
3678 /**************************************************************************/
3680 /**************************************************************************/
3682 /* Convert TLB0 va and way number to tlb0[] table index. */
3683 static inline unsigned int
3684 tlb0_tableidx(vm_offset_t va, unsigned int way)
3688 idx = (way * TLB0_ENTRIES_PER_WAY);
3689 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
3694 * Invalidate TLB0 entry.
3697 tlb0_flush_entry(vm_offset_t va)
3700 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
3702 mtx_assert(&tlbivax_mutex, MA_OWNED);
3704 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
3705 __asm __volatile("isync; msync");
3706 __asm __volatile("tlbsync; msync");
3708 CTR1(KTR_PMAP, "%s: e", __func__);
3712 /**************************************************************************/
3714 /**************************************************************************/
3717 * TLB1 mapping notes:
3719 * TLB1[0] Kernel text and data.
3720 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
3721 * windows, other devices mappings.
3725 * Read an entry from given TLB1 slot.
3728 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
3733 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
3736 __asm __volatile("wrteei 0");
3738 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
3739 mtspr(SPR_MAS0, mas0);
3740 __asm __volatile("isync; tlbre");
3742 entry->mas1 = mfspr(SPR_MAS1);
3743 entry->mas2 = mfspr(SPR_MAS2);
3744 entry->mas3 = mfspr(SPR_MAS3);
3746 switch ((mfpvr() >> 16) & 0xFFFF) {
3751 entry->mas7 = mfspr(SPR_MAS7);
3757 __asm __volatile("wrtee %0" :: "r"(msr));
3759 entry->virt = entry->mas2 & MAS2_EPN_MASK;
3760 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
3761 (entry->mas3 & MAS3_RPN);
3763 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
3766 struct tlbwrite_args {
3772 tlb1_write_entry_int(void *arg)
3774 struct tlbwrite_args *args = arg;
3778 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx);
3780 mtspr(SPR_MAS0, mas0);
3781 mtspr(SPR_MAS1, args->e->mas1);
3782 mtspr(SPR_MAS2, args->e->mas2);
3783 mtspr(SPR_MAS3, args->e->mas3);
3784 switch ((mfpvr() >> 16) & 0xFFFF) {
3791 mtspr(SPR_MAS7, args->e->mas7);
3797 __asm __volatile("isync; tlbwe; isync; msync");
3802 tlb1_write_entry_sync(void *arg)
3804 /* Empty synchronization point for smp_rendezvous(). */
3808 * Write given entry to TLB1 hardware.
3811 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
3813 struct tlbwrite_args args;
3819 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
3821 smp_rendezvous(tlb1_write_entry_sync,
3822 tlb1_write_entry_int,
3823 tlb1_write_entry_sync, &args);
3830 __asm __volatile("wrteei 0");
3831 tlb1_write_entry_int(&args);
3832 __asm __volatile("wrtee %0" :: "r"(msr));
3837 * Return the largest uint value log such that 2^log <= num.
3840 ilog2(unsigned long num)
3844 #ifdef __powerpc64__
3845 __asm ("cntlzd %0, %1" : "=r" (lz) : "r" (num));
3848 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
3854 * Convert TLB TSIZE value to mapped region size.
3857 tsize2size(unsigned int tsize)
3862 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
3865 return ((1 << (2 * tsize)) * 1024);
3869 * Convert region size (must be power of 4) to TLB TSIZE value.
3872 size2tsize(vm_size_t size)
3875 return (ilog2(size) / 2 - 5);
3879 * Register permanent kernel mapping in TLB1.
3881 * Entries are created starting from index 0 (current free entry is
3882 * kept in tlb1_idx) and are not supposed to be invalidated.
3885 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
3892 for (index = 0; index < TLB1_ENTRIES; index++) {
3893 tlb1_read_entry(&e, index);
3894 if ((e.mas1 & MAS1_VALID) == 0)
3896 /* Check if we're just updating the flags, and update them. */
3897 if (e.phys == pa && e.virt == va && e.size == size) {
3898 e.mas2 = (va & MAS2_EPN_MASK) | flags;
3899 tlb1_write_entry(&e, index);
3903 if (index >= TLB1_ENTRIES) {
3904 printf("tlb1_set_entry: TLB1 full!\n");
3908 /* Convert size to TSIZE */
3909 tsize = size2tsize(size);
3911 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3912 /* XXX TS is hard coded to 0 for now as we only use single address space */
3913 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3918 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3919 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3920 e.mas2 = (va & MAS2_EPN_MASK) | flags;
3922 /* Set supervisor RWX permission bits */
3923 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3924 e.mas7 = (pa >> 32) & MAS7_RPN;
3926 tlb1_write_entry(&e, index);
3929 * XXX in general TLB1 updates should be propagated between CPUs,
3930 * since current design assumes to have the same TLB1 set-up on all
3937 * Map in contiguous RAM region into the TLB1 using maximum of
3938 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3940 * If necessary round up last entry size and return total size
3941 * used by all allocated entries.
3944 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3946 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3947 vm_size_t mapped, pgsz, base, mask;
3950 /* Round up to the next 1M */
3951 size = roundup2(size, 1 << 20);
3956 pgsz = 64*1024*1024;
3957 while (mapped < size) {
3958 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3959 while (pgsz > (size - mapped))
3965 /* We under-map. Correct for this. */
3966 if (mapped < size) {
3967 while (pgs[idx - 1] == pgsz) {
3971 /* XXX We may increase beyond out starting point. */
3980 /* Align address to the boundary */
3982 va = (va + mask) & ~mask;
3983 pa = (pa + mask) & ~mask;
3986 for (idx = 0; idx < nents; idx++) {
3988 debugf("%u: %llx -> %jx, size=%jx\n", idx, pa,
3989 (uintmax_t)va, (uintmax_t)pgsz);
3990 tlb1_set_entry(va, pa, pgsz,
3991 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM);
3996 mapped = (va - base);
3998 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
3999 mapped, mapped - size);
4004 * TLB1 initialization routine, to be called after the very first
4005 * assembler level setup done in locore.S.
4010 uint32_t mas0, mas1, mas2, mas3, mas7;
4015 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
4016 mtspr(SPR_MAS0, mas0);
4017 __asm __volatile("isync; tlbre");
4019 mas1 = mfspr(SPR_MAS1);
4020 mas2 = mfspr(SPR_MAS2);
4021 mas3 = mfspr(SPR_MAS3);
4022 mas7 = mfspr(SPR_MAS7);
4024 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
4027 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4028 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
4030 /* Setup TLB miss defaults */
4031 set_mas4_defaults();
4035 * pmap_early_io_unmap() should be used in short conjunction with
4036 * pmap_early_io_map(), as in the following snippet:
4038 * x = pmap_early_io_map(...);
4039 * <do something with x>
4040 * pmap_early_io_unmap(x, size);
4042 * And avoiding more allocations between.
4045 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
4051 size = roundup(size, PAGE_SIZE);
4053 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
4054 tlb1_read_entry(&e, i);
4055 if (!(e.mas1 & MAS1_VALID))
4057 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
4059 e.mas1 &= ~MAS1_VALID;
4060 tlb1_write_entry(&e, i);
4063 if (tlb1_map_base == va + isize)
4064 tlb1_map_base -= isize;
4068 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
4075 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
4077 for (i = 0; i < TLB1_ENTRIES; i++) {
4078 tlb1_read_entry(&e, i);
4079 if (!(e.mas1 & MAS1_VALID))
4081 if (pa >= e.phys && (pa + size) <=
4083 return (e.virt + (pa - e.phys));
4086 pa_base = rounddown(pa, PAGE_SIZE);
4087 size = roundup(size + (pa - pa_base), PAGE_SIZE);
4088 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
4089 va = tlb1_map_base + (pa - pa_base);
4092 sz = 1 << (ilog2(size) & ~1);
4093 tlb1_set_entry(tlb1_map_base, pa_base, sz,
4094 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
4097 tlb1_map_base += sz;
4104 pmap_track_page(pmap_t pmap, vm_offset_t va)
4108 struct pv_entry *pve;
4110 va = trunc_page(va);
4111 pa = pmap_kextract(va);
4112 page = PHYS_TO_VM_PAGE(pa);
4114 rw_wlock(&pvh_global_lock);
4117 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
4118 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
4122 page->md.pv_tracked = true;
4123 pv_insert(pmap, va, page);
4126 rw_wunlock(&pvh_global_lock);
4131 * Setup MAS4 defaults.
4132 * These values are loaded to MAS0-2 on a TLB miss.
4135 set_mas4_defaults(void)
4139 /* Defaults: TLB0, PID0, TSIZED=4K */
4140 mas4 = MAS4_TLBSELD0;
4141 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
4145 mtspr(SPR_MAS4, mas4);
4146 __asm __volatile("isync");
4151 * Return 0 if the physical IO range is encompassed by one of the
4152 * the TLB1 entries, otherwise return related error code.
4155 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
4158 vm_paddr_t pa_start;
4160 unsigned int entry_tsize;
4161 vm_size_t entry_size;
4164 *va = (vm_offset_t)NULL;
4166 tlb1_read_entry(&e, i);
4167 /* Skip invalid entries */
4168 if (!(e.mas1 & MAS1_VALID))
4172 * The entry must be cache-inhibited, guarded, and r/w
4173 * so it can function as an i/o page
4175 prot = e.mas2 & (MAS2_I | MAS2_G);
4176 if (prot != (MAS2_I | MAS2_G))
4179 prot = e.mas3 & (MAS3_SR | MAS3_SW);
4180 if (prot != (MAS3_SR | MAS3_SW))
4183 /* The address should be within the entry range. */
4184 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4185 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
4187 entry_size = tsize2size(entry_tsize);
4188 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
4189 (e.mas3 & MAS3_RPN);
4190 pa_end = pa_start + entry_size;
4192 if ((pa < pa_start) || ((pa + size) > pa_end))
4195 /* Return virtual address of this mapping. */
4196 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
4201 * Invalidate all TLB0 entries which match the given TID. Note this is
4202 * dedicated for cases when invalidations should NOT be propagated to other
4206 tid_flush(tlbtid_t tid)
4209 uint32_t mas0, mas1, mas2;
4213 /* Don't evict kernel translations */
4214 if (tid == TID_KERNEL)
4218 __asm __volatile("wrteei 0");
4221 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use
4222 * it for PID invalidation.
4224 switch ((mfpvr() >> 16) & 0xffff) {
4228 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
4230 __asm __volatile("isync; .long 0x7c000024; isync; msync");
4231 __asm __volatile("wrtee %0" :: "r"(msr));
4235 for (way = 0; way < TLB0_WAYS; way++)
4236 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
4238 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4239 mtspr(SPR_MAS0, mas0);
4241 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
4242 mtspr(SPR_MAS2, mas2);
4244 __asm __volatile("isync; tlbre");
4246 mas1 = mfspr(SPR_MAS1);
4248 if (!(mas1 & MAS1_VALID))
4250 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
4252 mas1 &= ~MAS1_VALID;
4253 mtspr(SPR_MAS1, mas1);
4254 __asm __volatile("isync; tlbwe; isync; msync");
4256 __asm __volatile("wrtee %0" :: "r"(msr));
4260 /* Print out contents of the MAS registers for each TLB0 entry */
4262 #ifdef __powerpc64__
4263 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
4265 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
4276 if (mas1 & MAS1_VALID)
4281 if (mas1 & MAS1_IPROT)
4286 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
4287 tid = MAS1_GETTID(mas1);
4289 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4292 size = tsize2size(tsize);
4294 printf("%3d: (%s) [AS=%d] "
4295 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
4296 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
4297 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
4300 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
4302 uint32_t mas0, mas1, mas3, mas7;
4303 #ifdef __powerpc64__
4308 int entryidx, way, idx;
4310 printf("TLB0 entries:\n");
4311 for (way = 0; way < TLB0_WAYS; way ++)
4312 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
4314 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4315 mtspr(SPR_MAS0, mas0);
4317 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
4318 mtspr(SPR_MAS2, mas2);
4320 __asm __volatile("isync; tlbre");
4322 mas1 = mfspr(SPR_MAS1);
4323 mas2 = mfspr(SPR_MAS2);
4324 mas3 = mfspr(SPR_MAS3);
4325 mas7 = mfspr(SPR_MAS7);
4327 idx = tlb0_tableidx(mas2, way);
4328 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
4333 * Print out contents of the MAS registers for each TLB1 entry
4335 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
4337 uint32_t mas0, mas1, mas3, mas7;
4338 #ifdef __powerpc64__
4345 printf("TLB1 entries:\n");
4346 for (i = 0; i < TLB1_ENTRIES; i++) {
4348 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
4349 mtspr(SPR_MAS0, mas0);
4351 __asm __volatile("isync; tlbre");
4353 mas1 = mfspr(SPR_MAS1);
4354 mas2 = mfspr(SPR_MAS2);
4355 mas3 = mfspr(SPR_MAS3);
4356 mas7 = mfspr(SPR_MAS7);
4358 tlb_print_entry(i, mas1, mas2, mas3, mas7);