2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_kern.h>
104 #include <vm/vm_pageout.h>
105 #include <vm/vm_extern.h>
106 #include <vm/vm_object.h>
107 #include <vm/vm_param.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
114 #include <machine/_inttypes.h>
115 #include <machine/cpu.h>
116 #include <machine/pcb.h>
117 #include <machine/platform.h>
119 #include <machine/tlb.h>
120 #include <machine/spr.h>
121 #include <machine/md_var.h>
122 #include <machine/mmuvar.h>
123 #include <machine/pmap.h>
124 #include <machine/pte.h>
130 #define SPARSE_MAPDEV
132 #define debugf(fmt, args...) printf(fmt, ##args)
134 #define debugf(fmt, args...)
138 #define PRI0ptrX "016lx"
140 #define PRI0ptrX "08x"
143 #define TODO panic("%s: not implemented", __func__);
145 extern unsigned char _etext[];
146 extern unsigned char _end[];
148 extern uint32_t *bootinfo;
151 vm_offset_t kernstart;
154 /* Message buffer and tables. */
155 static vm_offset_t data_start;
156 static vm_size_t data_end;
158 /* Phys/avail memory regions. */
159 static struct mem_region *availmem_regions;
160 static int availmem_regions_sz;
161 static struct mem_region *physmem_regions;
162 static int physmem_regions_sz;
164 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
165 static vm_offset_t zero_page_va;
166 static struct mtx zero_page_mutex;
168 static struct mtx tlbivax_mutex;
170 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
171 static vm_offset_t copy_page_src_va;
172 static vm_offset_t copy_page_dst_va;
173 static struct mtx copy_page_mutex;
175 /**************************************************************************/
177 /**************************************************************************/
179 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
180 vm_prot_t, u_int flags, int8_t psind);
182 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
183 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
185 unsigned int kernel_pdirs;
187 static uma_zone_t ptbl_root_zone;
190 * If user pmap is processed with mmu_booke_remove and the resident count
191 * drops to 0, there are no more pages to remove, so we need not continue.
193 #define PMAP_REMOVE_DONE(pmap) \
194 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
196 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
197 extern int elf32_nxstack;
200 /**************************************************************************/
201 /* TLB and TID handling */
202 /**************************************************************************/
204 /* Translation ID busy table */
205 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
208 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
209 * core revisions and should be read from h/w registers during early config.
211 uint32_t tlb0_entries;
213 uint32_t tlb0_entries_per_way;
214 uint32_t tlb1_entries;
216 #define TLB0_ENTRIES (tlb0_entries)
217 #define TLB0_WAYS (tlb0_ways)
218 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
220 #define TLB1_ENTRIES (tlb1_entries)
222 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE;
224 static tlbtid_t tid_alloc(struct pmap *);
225 static void tid_flush(tlbtid_t tid);
229 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
231 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
235 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
236 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
237 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
238 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
240 static vm_size_t tsize2size(unsigned int);
241 static unsigned int size2tsize(vm_size_t);
242 static unsigned int ilog2(unsigned long);
244 static void set_mas4_defaults(void);
246 static inline void tlb0_flush_entry(vm_offset_t);
247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
249 /**************************************************************************/
250 /* Page table management */
251 /**************************************************************************/
253 static struct rwlock_padalign pvh_global_lock;
255 /* Data for the pv entry allocation mechanism */
256 static uma_zone_t pvzone;
257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
261 #ifndef PMAP_SHPGPERPROC
262 #define PMAP_SHPGPERPROC 200
266 #define PMAP_ROOT_SIZE (sizeof(pte_t***) * PP2D_NENTRIES)
267 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **,
268 unsigned int, boolean_t);
269 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int, vm_page_t);
270 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int);
271 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t);
273 #define PMAP_ROOT_SIZE (sizeof(pte_t**) * PDIR_NENTRIES)
274 static void ptbl_init(void);
275 static struct ptbl_buf *ptbl_buf_alloc(void);
276 static void ptbl_buf_free(struct ptbl_buf *);
277 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
279 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t);
280 static void ptbl_free(mmu_t, pmap_t, unsigned int);
281 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
282 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
285 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
286 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
287 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
288 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
289 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t);
291 static pv_entry_t pv_alloc(void);
292 static void pv_free(pv_entry_t);
293 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
294 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
296 static void booke_pmap_init_qpages(void);
299 TAILQ_ENTRY(ptbl_buf) link; /* list link */
300 vm_offset_t kva; /* va of mapping */
303 #ifndef __powerpc64__
304 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
305 #define PTBL_BUFS (128 * 16)
307 /* ptbl free list and a lock used for access synchronization. */
308 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
309 static struct mtx ptbl_buf_freelist_lock;
311 /* Base address of kva space allocated fot ptbl bufs. */
312 static vm_offset_t ptbl_buf_pool_vabase;
314 /* Pointer to ptbl_buf structures. */
315 static struct ptbl_buf *ptbl_bufs;
319 extern tlb_entry_t __boot_tlb1[];
320 void pmap_bootstrap_ap(volatile uint32_t *);
324 * Kernel MMU interface
326 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
327 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
328 vm_size_t, vm_offset_t);
329 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
330 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
331 vm_offset_t, vm_page_t *, vm_offset_t, int);
332 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
333 vm_prot_t, u_int flags, int8_t psind);
334 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
335 vm_page_t, vm_prot_t);
336 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
338 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
339 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
341 static void mmu_booke_init(mmu_t);
342 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
343 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
344 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
345 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
346 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
348 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
350 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
351 vm_object_t, vm_pindex_t, vm_size_t);
352 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
353 static void mmu_booke_page_init(mmu_t, vm_page_t);
354 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
355 static void mmu_booke_pinit(mmu_t, pmap_t);
356 static void mmu_booke_pinit0(mmu_t, pmap_t);
357 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
359 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
360 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
361 static void mmu_booke_release(mmu_t, pmap_t);
362 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
363 static void mmu_booke_remove_all(mmu_t, vm_page_t);
364 static void mmu_booke_remove_write(mmu_t, vm_page_t);
365 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
366 static void mmu_booke_zero_page(mmu_t, vm_page_t);
367 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
368 static void mmu_booke_activate(mmu_t, struct thread *);
369 static void mmu_booke_deactivate(mmu_t, struct thread *);
370 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
371 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
372 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
373 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
374 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
375 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
376 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
377 static void mmu_booke_kremove(mmu_t, vm_offset_t);
378 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
379 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
381 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t,
383 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t,
385 static void mmu_booke_scan_init(mmu_t);
386 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m);
387 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr);
388 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr,
389 vm_size_t sz, vm_memattr_t mode);
390 static int mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm,
391 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
392 static int mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
393 int *is_user, vm_offset_t *decoded_addr);
396 static mmu_method_t mmu_booke_methods[] = {
397 /* pmap dispatcher interface */
398 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
399 MMUMETHOD(mmu_copy, mmu_booke_copy),
400 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
401 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
402 MMUMETHOD(mmu_enter, mmu_booke_enter),
403 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
404 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
405 MMUMETHOD(mmu_extract, mmu_booke_extract),
406 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
407 MMUMETHOD(mmu_init, mmu_booke_init),
408 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
409 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
410 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
411 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
412 MMUMETHOD(mmu_map, mmu_booke_map),
413 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
414 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
415 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
416 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
417 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
418 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
419 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
420 MMUMETHOD(mmu_protect, mmu_booke_protect),
421 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
422 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
423 MMUMETHOD(mmu_release, mmu_booke_release),
424 MMUMETHOD(mmu_remove, mmu_booke_remove),
425 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
426 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
427 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
428 MMUMETHOD(mmu_unwire, mmu_booke_unwire),
429 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
430 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
431 MMUMETHOD(mmu_activate, mmu_booke_activate),
432 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
433 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page),
434 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page),
436 /* Internal interfaces */
437 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
438 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
439 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
440 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
441 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
442 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
443 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
444 MMUMETHOD(mmu_kremove, mmu_booke_kremove),
445 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
446 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr),
447 MMUMETHOD(mmu_map_user_ptr, mmu_booke_map_user_ptr),
448 MMUMETHOD(mmu_decode_kernel_ptr, mmu_booke_decode_kernel_ptr),
450 /* dumpsys() support */
451 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
452 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
453 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init),
458 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
460 static __inline uint32_t
461 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
466 if (ma != VM_MEMATTR_DEFAULT) {
468 case VM_MEMATTR_UNCACHEABLE:
469 return (MAS2_I | MAS2_G);
470 case VM_MEMATTR_WRITE_COMBINING:
471 case VM_MEMATTR_WRITE_BACK:
472 case VM_MEMATTR_PREFETCHABLE:
474 case VM_MEMATTR_WRITE_THROUGH:
475 return (MAS2_W | MAS2_M);
476 case VM_MEMATTR_CACHEABLE:
482 * Assume the page is cache inhibited and access is guarded unless
483 * it's in our available memory array.
485 attrib = _TLB_ENTRY_IO;
486 for (i = 0; i < physmem_regions_sz; i++) {
487 if ((pa >= physmem_regions[i].mr_start) &&
488 (pa < (physmem_regions[i].mr_start +
489 physmem_regions[i].mr_size))) {
490 attrib = _TLB_ENTRY_MEM;
507 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
510 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
511 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
513 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
514 ("tlb_miss_lock: tried to lock self"));
516 tlb_lock(pc->pc_booke.tlb_lock);
518 CTR1(KTR_PMAP, "%s: locked", __func__);
525 tlb_miss_unlock(void)
533 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
535 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
536 __func__, pc->pc_cpuid);
538 tlb_unlock(pc->pc_booke.tlb_lock);
540 CTR1(KTR_PMAP, "%s: unlocked", __func__);
546 /* Return number of entries in TLB0. */
548 tlb0_get_tlbconf(void)
552 tlb0_cfg = mfspr(SPR_TLB0CFG);
553 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
554 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
555 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
558 /* Return number of entries in TLB1. */
560 tlb1_get_tlbconf(void)
564 tlb1_cfg = mfspr(SPR_TLB1CFG);
565 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
568 /**************************************************************************/
569 /* Page table related */
570 /**************************************************************************/
573 /* Initialize pool of kva ptbl buffers. */
579 /* Get a pointer to a PTE in a page table. */
580 static __inline pte_t *
581 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
586 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
588 pdir = pmap->pm_pp2d[PP2D_IDX(va)];
591 ptbl = pdir[PDIR_IDX(va)];
592 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL);
596 * allocate a page of pointers to page directories, do not preallocate the
600 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep)
606 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
607 while ((m = vm_page_alloc(NULL, pp2d_idx, req)) == NULL) {
616 /* Zero whole ptbl. */
617 pdir = (pte_t **)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
618 mmu_booke_zero_page(mmu, m);
623 /* Free pdir pages and invalidate pdir entry. */
625 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, vm_page_t m)
629 pdir = pmap->pm_pp2d[pp2d_idx];
631 KASSERT((pdir != NULL), ("pdir_free: null pdir"));
633 pmap->pm_pp2d[pp2d_idx] = NULL;
636 vm_page_free_zero(m);
640 * Decrement pdir pages hold count and attempt to free pdir pages. Called
641 * when removing directory entry from pdir.
643 * Return 1 if pdir pages were freed.
646 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx)
652 KASSERT((pmap != kernel_pmap),
653 ("pdir_unhold: unholding kernel pdir!"));
655 pdir = pmap->pm_pp2d[pp2d_idx];
657 /* decrement hold count */
658 pa = DMAP_TO_PHYS((vm_offset_t) pdir);
659 m = PHYS_TO_VM_PAGE(pa);
662 * Free pdir page if there are no dir entries in this pdir.
665 if (m->wire_count == 0) {
666 pdir_free(mmu, pmap, pp2d_idx, m);
673 * Increment hold count for pdir pages. This routine is used when new ptlb
674 * entry is being inserted into pdir.
677 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir)
681 KASSERT((pmap != kernel_pmap),
682 ("pdir_hold: holding kernel pdir!"));
684 KASSERT((pdir != NULL), ("pdir_hold: null pdir"));
686 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pdir));
690 /* Allocate page table. */
692 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx,
699 KASSERT((pdir[pdir_idx] == NULL),
700 ("%s: valid ptbl entry exists!", __func__));
702 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
703 while ((m = vm_page_alloc(NULL, pdir_idx, req)) == NULL) {
705 rw_wunlock(&pvh_global_lock);
710 rw_wlock(&pvh_global_lock);
714 /* Zero whole ptbl. */
715 ptbl = (pte_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
716 mmu_booke_zero_page(mmu, m);
721 /* Free ptbl pages and invalidate pdir entry. */
723 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx, vm_page_t m)
727 ptbl = pdir[pdir_idx];
729 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
731 pdir[pdir_idx] = NULL;
734 vm_page_free_zero(m);
738 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called
739 * when removing pte entry from ptbl.
741 * Return 1 if ptbl pages were freed.
744 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va)
752 pp2d_idx = PP2D_IDX(va);
753 pdir_idx = PDIR_IDX(va);
755 KASSERT((pmap != kernel_pmap),
756 ("ptbl_unhold: unholding kernel ptbl!"));
758 pdir = pmap->pm_pp2d[pp2d_idx];
759 ptbl = pdir[pdir_idx];
761 /* decrement hold count */
762 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t) ptbl));
765 * Free ptbl pages if there are no pte entries in this ptbl.
766 * wire_count has the same value for all ptbl pages, so check the
770 if (m->wire_count == 0) {
771 ptbl_free(mmu, pmap, pdir, pdir_idx, m);
772 pdir_unhold(mmu, pmap, pp2d_idx);
779 * Increment hold count for ptbl pages. This routine is used when new pte
780 * entry is being inserted into ptbl.
783 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx)
788 KASSERT((pmap != kernel_pmap),
789 ("ptbl_hold: holding kernel ptbl!"));
791 ptbl = pdir[pdir_idx];
793 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
795 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t) ptbl));
800 /* Initialize pool of kva ptbl buffers. */
806 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
807 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
808 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
809 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
811 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
812 TAILQ_INIT(&ptbl_buf_freelist);
814 for (i = 0; i < PTBL_BUFS; i++) {
816 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
817 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
821 /* Get a ptbl_buf from the freelist. */
822 static struct ptbl_buf *
825 struct ptbl_buf *buf;
827 mtx_lock(&ptbl_buf_freelist_lock);
828 buf = TAILQ_FIRST(&ptbl_buf_freelist);
830 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
831 mtx_unlock(&ptbl_buf_freelist_lock);
833 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
838 /* Return ptbl buff to free pool. */
840 ptbl_buf_free(struct ptbl_buf *buf)
843 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
845 mtx_lock(&ptbl_buf_freelist_lock);
846 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
847 mtx_unlock(&ptbl_buf_freelist_lock);
851 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
854 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
856 struct ptbl_buf *pbuf;
858 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
860 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
862 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
863 if (pbuf->kva == (vm_offset_t)ptbl) {
864 /* Remove from pmap ptbl buf list. */
865 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
867 /* Free corresponding ptbl buf. */
873 /* Allocate page table. */
875 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
877 vm_page_t mtbl[PTBL_PAGES];
879 struct ptbl_buf *pbuf;
884 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
885 (pmap == kernel_pmap), pdir_idx);
887 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
888 ("ptbl_alloc: invalid pdir_idx"));
889 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
890 ("pte_alloc: valid ptbl entry exists!"));
892 pbuf = ptbl_buf_alloc();
894 panic("pte_alloc: couldn't alloc kernel virtual memory");
896 ptbl = (pte_t *)pbuf->kva;
898 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
900 for (i = 0; i < PTBL_PAGES; i++) {
901 pidx = (PTBL_PAGES * pdir_idx) + i;
902 while ((m = vm_page_alloc(NULL, pidx,
903 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
905 rw_wunlock(&pvh_global_lock);
907 ptbl_free_pmap_ptbl(pmap, ptbl);
908 for (j = 0; j < i; j++)
909 vm_page_free(mtbl[j]);
914 rw_wlock(&pvh_global_lock);
920 /* Map allocated pages into kernel_pmap. */
921 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
923 /* Zero whole ptbl. */
924 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
926 /* Add pbuf to the pmap ptbl bufs list. */
927 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
932 /* Free ptbl pages and invalidate pdir entry. */
934 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
942 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
943 (pmap == kernel_pmap), pdir_idx);
945 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
946 ("ptbl_free: invalid pdir_idx"));
948 ptbl = pmap->pm_pdir[pdir_idx];
950 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
952 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
955 * Invalidate the pdir entry as soon as possible, so that other CPUs
956 * don't attempt to look up the page tables we are releasing.
958 mtx_lock_spin(&tlbivax_mutex);
961 pmap->pm_pdir[pdir_idx] = NULL;
964 mtx_unlock_spin(&tlbivax_mutex);
966 for (i = 0; i < PTBL_PAGES; i++) {
967 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
968 pa = pte_vatopa(mmu, kernel_pmap, va);
969 m = PHYS_TO_VM_PAGE(pa);
970 vm_page_free_zero(m);
972 mmu_booke_kremove(mmu, va);
975 ptbl_free_pmap_ptbl(pmap, ptbl);
979 * Decrement ptbl pages hold count and attempt to free ptbl pages.
980 * Called when removing pte entry from ptbl.
982 * Return 1 if ptbl pages were freed.
985 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
992 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
993 (pmap == kernel_pmap), pdir_idx);
995 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
996 ("ptbl_unhold: invalid pdir_idx"));
997 KASSERT((pmap != kernel_pmap),
998 ("ptbl_unhold: unholding kernel ptbl!"));
1000 ptbl = pmap->pm_pdir[pdir_idx];
1002 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
1003 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
1004 ("ptbl_unhold: non kva ptbl"));
1006 /* decrement hold count */
1007 for (i = 0; i < PTBL_PAGES; i++) {
1008 pa = pte_vatopa(mmu, kernel_pmap,
1009 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1010 m = PHYS_TO_VM_PAGE(pa);
1015 * Free ptbl pages if there are no pte etries in this ptbl.
1016 * wire_count has the same value for all ptbl pages, so check the last
1019 if (m->wire_count == 0) {
1020 ptbl_free(mmu, pmap, pdir_idx);
1022 //debugf("ptbl_unhold: e (freed ptbl)\n");
1030 * Increment hold count for ptbl pages. This routine is used when a new pte
1031 * entry is being inserted into the ptbl.
1034 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1041 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
1044 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1045 ("ptbl_hold: invalid pdir_idx"));
1046 KASSERT((pmap != kernel_pmap),
1047 ("ptbl_hold: holding kernel ptbl!"));
1049 ptbl = pmap->pm_pdir[pdir_idx];
1051 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
1053 for (i = 0; i < PTBL_PAGES; i++) {
1054 pa = pte_vatopa(mmu, kernel_pmap,
1055 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1056 m = PHYS_TO_VM_PAGE(pa);
1062 /* Allocate pv_entry structure. */
1069 if (pv_entry_count > pv_entry_high_water)
1070 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
1071 pv = uma_zalloc(pvzone, M_NOWAIT);
1076 /* Free pv_entry structure. */
1077 static __inline void
1078 pv_free(pv_entry_t pve)
1082 uma_zfree(pvzone, pve);
1086 /* Allocate and initialize pv_entry structure. */
1088 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
1092 //int su = (pmap == kernel_pmap);
1093 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
1094 // (u_int32_t)pmap, va, (u_int32_t)m);
1098 panic("pv_insert: no pv entries!");
1100 pve->pv_pmap = pmap;
1103 /* add to pv_list */
1104 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1105 rw_assert(&pvh_global_lock, RA_WLOCKED);
1107 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
1109 //debugf("pv_insert: e\n");
1112 /* Destroy pv entry. */
1114 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
1118 //int su = (pmap == kernel_pmap);
1119 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
1121 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1122 rw_assert(&pvh_global_lock, RA_WLOCKED);
1125 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
1126 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
1127 /* remove from pv_list */
1128 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
1129 if (TAILQ_EMPTY(&m->md.pv_list))
1130 vm_page_aflag_clear(m, PGA_WRITEABLE);
1132 /* free pv entry struct */
1138 //debugf("pv_remove: e\n");
1141 #ifdef __powerpc64__
1143 * Clean pte entry, try to free page table page if requested.
1145 * Return 1 if ptbl pages were freed, otherwise return 0.
1148 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags)
1153 pte = pte_find(mmu, pmap, va);
1154 KASSERT(pte != NULL, ("%s: NULL pte", __func__));
1156 if (!PTE_ISVALID(pte))
1159 /* Get vm_page_t for mapped pte. */
1160 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1162 if (PTE_ISWIRED(pte))
1163 pmap->pm_stats.wired_count--;
1165 /* Handle managed entry. */
1166 if (PTE_ISMANAGED(pte)) {
1168 /* Handle modified pages. */
1169 if (PTE_ISMODIFIED(pte))
1172 /* Referenced pages. */
1173 if (PTE_ISREFERENCED(pte))
1174 vm_page_aflag_set(m, PGA_REFERENCED);
1176 /* Remove pv_entry from pv_list. */
1177 pv_remove(pmap, va, m);
1178 } else if (m->md.pv_tracked) {
1179 pv_remove(pmap, va, m);
1180 if (TAILQ_EMPTY(&m->md.pv_list))
1181 m->md.pv_tracked = false;
1183 mtx_lock_spin(&tlbivax_mutex);
1186 tlb0_flush_entry(va);
1190 mtx_unlock_spin(&tlbivax_mutex);
1192 pmap->pm_stats.resident_count--;
1194 if (flags & PTBL_UNHOLD) {
1195 return (ptbl_unhold(mmu, pmap, va));
1201 * Insert PTE for a given page and virtual address.
1204 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1207 unsigned int pp2d_idx = PP2D_IDX(va);
1208 unsigned int pdir_idx = PDIR_IDX(va);
1209 unsigned int ptbl_idx = PTBL_IDX(va);
1210 pte_t *ptbl, *pte, pte_tmp;
1213 /* Get the page directory pointer. */
1214 pdir = pmap->pm_pp2d[pp2d_idx];
1216 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep);
1218 /* Get the page table pointer. */
1219 ptbl = pdir[pdir_idx];
1222 /* Allocate page table pages. */
1223 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep);
1225 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1228 pte = &ptbl[ptbl_idx];
1231 * Check if there is valid mapping for requested va, if there
1234 pte = &ptbl[ptbl_idx];
1235 if (PTE_ISVALID(pte)) {
1236 pte_remove(mmu, pmap, va, PTBL_HOLD);
1239 * pte is not used, increment hold count for ptbl
1242 if (pmap != kernel_pmap)
1243 ptbl_hold(mmu, pmap, pdir, pdir_idx);
1247 if (pdir[pdir_idx] == NULL) {
1248 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL)
1249 pdir_hold(mmu, pmap, pdir);
1250 pdir[pdir_idx] = ptbl;
1252 if (pmap->pm_pp2d[pp2d_idx] == NULL)
1253 pmap->pm_pp2d[pp2d_idx] = pdir;
1256 * Insert pv_entry into pv_list for mapped page if part of managed
1259 if ((m->oflags & VPO_UNMANAGED) == 0) {
1260 flags |= PTE_MANAGED;
1262 /* Create and insert pv entry. */
1263 pv_insert(pmap, va, m);
1266 pmap->pm_stats.resident_count++;
1268 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1269 pte_tmp |= (PTE_VALID | flags);
1271 mtx_lock_spin(&tlbivax_mutex);
1274 tlb0_flush_entry(va);
1278 mtx_unlock_spin(&tlbivax_mutex);
1283 /* Return the pa for the given pmap/va. */
1285 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1290 pte = pte_find(mmu, pmap, va);
1291 if ((pte != NULL) && PTE_ISVALID(pte))
1292 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1297 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */
1299 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1306 /* Initialize kernel pdir */
1307 for (i = 0; i < kernel_pdirs; i++) {
1308 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] =
1309 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES));
1310 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES));
1311 j < PDIR_NENTRIES; j++) {
1312 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] =
1313 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE) +
1314 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE));
1319 * Fill in PTEs covering kernel code and data. They are not required
1320 * for address translation, as this area is covered by static TLB1
1321 * entries, but for pte_vatopa() to work correctly with kernel area
1324 for (va = addr; va < data_end; va += PAGE_SIZE) {
1325 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]);
1326 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1327 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1328 PTE_VALID | PTE_PS_4KB;
1333 * Clean pte entry, try to free page table page if requested.
1335 * Return 1 if ptbl pages were freed, otherwise return 0.
1338 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
1340 unsigned int pdir_idx = PDIR_IDX(va);
1341 unsigned int ptbl_idx = PTBL_IDX(va);
1346 //int su = (pmap == kernel_pmap);
1347 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
1348 // su, (u_int32_t)pmap, va, flags);
1350 ptbl = pmap->pm_pdir[pdir_idx];
1351 KASSERT(ptbl, ("pte_remove: null ptbl"));
1353 pte = &ptbl[ptbl_idx];
1355 if (pte == NULL || !PTE_ISVALID(pte))
1358 if (PTE_ISWIRED(pte))
1359 pmap->pm_stats.wired_count--;
1361 /* Get vm_page_t for mapped pte. */
1362 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1364 /* Handle managed entry. */
1365 if (PTE_ISMANAGED(pte)) {
1367 if (PTE_ISMODIFIED(pte))
1370 if (PTE_ISREFERENCED(pte))
1371 vm_page_aflag_set(m, PGA_REFERENCED);
1373 pv_remove(pmap, va, m);
1374 } else if (m->md.pv_tracked) {
1376 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is
1377 * used. This is needed by the NCSW support code for fast
1378 * VA<->PA translation.
1380 pv_remove(pmap, va, m);
1381 if (TAILQ_EMPTY(&m->md.pv_list))
1382 m->md.pv_tracked = false;
1385 mtx_lock_spin(&tlbivax_mutex);
1388 tlb0_flush_entry(va);
1392 mtx_unlock_spin(&tlbivax_mutex);
1394 pmap->pm_stats.resident_count--;
1396 if (flags & PTBL_UNHOLD) {
1397 //debugf("pte_remove: e (unhold)\n");
1398 return (ptbl_unhold(mmu, pmap, pdir_idx));
1401 //debugf("pte_remove: e\n");
1406 * Insert PTE for a given page and virtual address.
1409 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1412 unsigned int pdir_idx = PDIR_IDX(va);
1413 unsigned int ptbl_idx = PTBL_IDX(va);
1414 pte_t *ptbl, *pte, pte_tmp;
1416 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
1417 pmap == kernel_pmap, pmap, va);
1419 /* Get the page table pointer. */
1420 ptbl = pmap->pm_pdir[pdir_idx];
1423 /* Allocate page table pages. */
1424 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
1426 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1429 pmap->pm_pdir[pdir_idx] = ptbl;
1430 pte = &ptbl[ptbl_idx];
1433 * Check if there is valid mapping for requested
1434 * va, if there is, remove it.
1436 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
1437 if (PTE_ISVALID(pte)) {
1438 pte_remove(mmu, pmap, va, PTBL_HOLD);
1441 * pte is not used, increment hold count
1444 if (pmap != kernel_pmap)
1445 ptbl_hold(mmu, pmap, pdir_idx);
1450 * Insert pv_entry into pv_list for mapped page if part of managed
1453 if ((m->oflags & VPO_UNMANAGED) == 0) {
1454 flags |= PTE_MANAGED;
1456 /* Create and insert pv entry. */
1457 pv_insert(pmap, va, m);
1460 pmap->pm_stats.resident_count++;
1462 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1463 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
1465 mtx_lock_spin(&tlbivax_mutex);
1468 tlb0_flush_entry(va);
1472 mtx_unlock_spin(&tlbivax_mutex);
1476 /* Return the pa for the given pmap/va. */
1478 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1483 pte = pte_find(mmu, pmap, va);
1484 if ((pte != NULL) && PTE_ISVALID(pte))
1485 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1489 /* Get a pointer to a PTE in a page table. */
1491 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1493 unsigned int pdir_idx = PDIR_IDX(va);
1494 unsigned int ptbl_idx = PTBL_IDX(va);
1496 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
1498 if (pmap->pm_pdir[pdir_idx])
1499 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
1504 /* Set up kernel page tables. */
1506 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1512 /* Initialize kernel pdir */
1513 for (i = 0; i < kernel_ptbls; i++)
1514 kernel_pmap->pm_pdir[kptbl_min + i] =
1515 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES));
1518 * Fill in PTEs covering kernel code and data. They are not required
1519 * for address translation, as this area is covered by static TLB1
1520 * entries, but for pte_vatopa() to work correctly with kernel area
1523 for (va = addr; va < data_end; va += PAGE_SIZE) {
1524 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1525 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1526 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1527 PTE_VALID | PTE_PS_4KB;
1532 /**************************************************************************/
1534 /**************************************************************************/
1537 * This is called during booke_init, before the system is really initialized.
1540 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1542 vm_paddr_t phys_kernelend;
1543 struct mem_region *mp, *mp1;
1545 vm_paddr_t s, e, sz;
1546 vm_paddr_t physsz, hwphyssz;
1547 u_int phys_avail_count;
1548 vm_size_t kstack0_sz;
1549 vm_offset_t kernel_pdir, kstack0;
1550 vm_paddr_t kstack0_phys;
1552 vm_offset_t kernel_ptbl_root;
1554 debugf("mmu_booke_bootstrap: entered\n");
1556 /* Set interesting system properties */
1557 #ifdef __powerpc64__
1562 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
1566 /* Initialize invalidation mutex */
1567 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1569 /* Read TLB0 size and associativity. */
1573 * Align kernel start and end address (kernel image).
1574 * Note that kernel end does not necessarily relate to kernsize.
1575 * kernsize is the size of the kernel that is actually mapped.
1577 kernstart = trunc_page(start);
1578 data_start = round_page(kernelend);
1579 data_end = data_start;
1581 /* Allocate the dynamic per-cpu area. */
1582 dpcpu = (void *)data_end;
1583 data_end += DPCPU_SIZE;
1585 /* Allocate space for the message buffer. */
1586 msgbufp = (struct msgbuf *)data_end;
1587 data_end += msgbufsize;
1588 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1589 (uintptr_t)msgbufp, data_end);
1591 data_end = round_page(data_end);
1593 #ifdef __powerpc64__
1594 kernel_ptbl_root = data_end;
1595 data_end += PP2D_NENTRIES * sizeof(pte_t**);
1597 /* Allocate space for ptbl_bufs. */
1598 ptbl_bufs = (struct ptbl_buf *)data_end;
1599 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1600 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1601 (uintptr_t)ptbl_bufs, data_end);
1603 data_end = round_page(data_end);
1604 kernel_ptbl_root = data_end;
1605 data_end += PDIR_NENTRIES * sizeof(pte_t*);
1608 /* Allocate PTE tables for kernel KVA. */
1609 kernel_pdir = data_end;
1610 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS,
1612 #ifdef __powerpc64__
1613 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES);
1614 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE;
1616 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1617 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1618 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1619 kernel_pdir, data_end);
1621 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
1622 if (data_end - kernstart > kernsize) {
1623 kernsize += tlb1_mapin_region(kernstart + kernsize,
1624 kernload + kernsize, (data_end - kernstart) - kernsize);
1626 data_end = kernstart + kernsize;
1627 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
1630 * Clear the structures - note we can only do it safely after the
1631 * possible additional TLB1 translations are in place (above) so that
1632 * all range up to the currently calculated 'data_end' is covered.
1634 dpcpu_init(dpcpu, 0);
1635 #ifdef __powerpc64__
1636 memset((void *)kernel_pdir, 0,
1637 kernel_pdirs * PDIR_PAGES * PAGE_SIZE +
1638 kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1640 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1641 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1644 /*******************************************************/
1645 /* Set the start and end of kva. */
1646 /*******************************************************/
1647 virtual_avail = round_page(data_end);
1648 virtual_end = VM_MAX_KERNEL_ADDRESS;
1650 /* Allocate KVA space for page zero/copy operations. */
1651 zero_page_va = virtual_avail;
1652 virtual_avail += PAGE_SIZE;
1653 copy_page_src_va = virtual_avail;
1654 virtual_avail += PAGE_SIZE;
1655 copy_page_dst_va = virtual_avail;
1656 virtual_avail += PAGE_SIZE;
1657 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
1658 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
1659 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
1661 /* Initialize page zero/copy mutexes. */
1662 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1663 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1665 #ifndef __powerpc64__
1666 /* Allocate KVA space for ptbl bufs. */
1667 ptbl_buf_pool_vabase = virtual_avail;
1668 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1669 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1670 ptbl_buf_pool_vabase, virtual_avail);
1673 /* Calculate corresponding physical addresses for the kernel region. */
1674 phys_kernelend = kernload + kernsize;
1675 debugf("kernel image and allocated data:\n");
1676 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload);
1677 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
1678 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
1681 * Remove kernel physical address range from avail regions list. Page
1682 * align all regions. Non-page aligned memory isn't very interesting
1683 * to us. Also, sort the entries for ascending addresses.
1686 /* Retrieve phys/avail mem regions */
1687 mem_regions(&physmem_regions, &physmem_regions_sz,
1688 &availmem_regions, &availmem_regions_sz);
1690 if (nitems(phys_avail) < availmem_regions_sz)
1691 panic("mmu_booke_bootstrap: phys_avail too small");
1694 cnt = availmem_regions_sz;
1695 debugf("processing avail regions:\n");
1696 for (mp = availmem_regions; mp->mr_size; mp++) {
1698 e = mp->mr_start + mp->mr_size;
1699 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
1700 /* Check whether this region holds all of the kernel. */
1701 if (s < kernload && e > phys_kernelend) {
1702 availmem_regions[cnt].mr_start = phys_kernelend;
1703 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1706 /* Look whether this regions starts within the kernel. */
1707 if (s >= kernload && s < phys_kernelend) {
1708 if (e <= phys_kernelend)
1712 /* Now look whether this region ends within the kernel. */
1713 if (e > kernload && e <= phys_kernelend) {
1718 /* Now page align the start and size of the region. */
1724 debugf("%09jx-%09jx = %jx\n",
1725 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
1727 /* Check whether some memory is left here. */
1731 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1737 /* Do an insertion sort. */
1738 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1739 if (s < mp1->mr_start)
1742 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1750 availmem_regions_sz = cnt;
1752 /*******************************************************/
1753 /* Steal physical memory for kernel stack from the end */
1754 /* of the first avail region */
1755 /*******************************************************/
1756 kstack0_sz = kstack_pages * PAGE_SIZE;
1757 kstack0_phys = availmem_regions[0].mr_start +
1758 availmem_regions[0].mr_size;
1759 kstack0_phys -= kstack0_sz;
1760 availmem_regions[0].mr_size -= kstack0_sz;
1762 /*******************************************************/
1763 /* Fill in phys_avail table, based on availmem_regions */
1764 /*******************************************************/
1765 phys_avail_count = 0;
1768 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1770 debugf("fill in phys_avail:\n");
1771 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1773 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
1774 (uintmax_t)availmem_regions[i].mr_start,
1775 (uintmax_t)availmem_regions[i].mr_start +
1776 availmem_regions[i].mr_size,
1777 (uintmax_t)availmem_regions[i].mr_size);
1779 if (hwphyssz != 0 &&
1780 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1781 debugf(" hw.physmem adjust\n");
1782 if (physsz < hwphyssz) {
1783 phys_avail[j] = availmem_regions[i].mr_start;
1785 availmem_regions[i].mr_start +
1793 phys_avail[j] = availmem_regions[i].mr_start;
1794 phys_avail[j + 1] = availmem_regions[i].mr_start +
1795 availmem_regions[i].mr_size;
1797 physsz += availmem_regions[i].mr_size;
1799 physmem = btoc(physsz);
1801 /* Calculate the last available physical address. */
1802 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1804 Maxmem = powerpc_btop(phys_avail[i + 1]);
1806 debugf("Maxmem = 0x%08lx\n", Maxmem);
1807 debugf("phys_avail_count = %d\n", phys_avail_count);
1808 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
1809 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
1811 #ifdef __powerpc64__
1813 * Map the physical memory contiguously in TLB1.
1814 * Round so it fits into a single mapping.
1816 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
1820 /*******************************************************/
1821 /* Initialize (statically allocated) kernel pmap. */
1822 /*******************************************************/
1823 PMAP_LOCK_INIT(kernel_pmap);
1824 #ifndef __powerpc64__
1825 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1827 #ifdef __powerpc64__
1828 kernel_pmap->pm_pp2d = (pte_t ***)kernel_ptbl_root;
1830 kernel_pmap->pm_pdir = (pte_t **)kernel_ptbl_root;
1833 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
1834 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir);
1835 for (i = 0; i < MAXCPU; i++) {
1836 kernel_pmap->pm_tid[i] = TID_KERNEL;
1838 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1839 tidbusy[i][TID_KERNEL] = kernel_pmap;
1842 /* Mark kernel_pmap active on all CPUs */
1843 CPU_FILL(&kernel_pmap->pm_active);
1846 * Initialize the global pv list lock.
1848 rw_init(&pvh_global_lock, "pmap pv global");
1850 /*******************************************************/
1852 /*******************************************************/
1854 /* Enter kstack0 into kernel map, provide guard page */
1855 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1856 thread0.td_kstack = kstack0;
1857 thread0.td_kstack_pages = kstack_pages;
1859 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1860 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n",
1861 kstack0_phys, kstack0_phys + kstack0_sz);
1862 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
1863 kstack0, kstack0 + kstack0_sz);
1865 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1866 for (i = 0; i < kstack_pages; i++) {
1867 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1868 kstack0 += PAGE_SIZE;
1869 kstack0_phys += PAGE_SIZE;
1872 pmap_bootstrapped = 1;
1874 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
1875 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
1877 debugf("mmu_booke_bootstrap: exit\n");
1884 tlb_entry_t *e, tmp;
1887 /* Prepare TLB1 image for AP processors */
1889 for (i = 0; i < TLB1_ENTRIES; i++) {
1890 tlb1_read_entry(&tmp, i);
1892 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
1893 memcpy(e++, &tmp, sizeof(tmp));
1898 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1903 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1904 * have the snapshot of its contents in the s/w __boot_tlb1[] table
1905 * created by tlb1_ap_prep(), so use these values directly to
1906 * (re)program AP's TLB1 hardware.
1908 * Start at index 1 because index 0 has the kernel map.
1910 for (i = 1; i < TLB1_ENTRIES; i++) {
1911 if (__boot_tlb1[i].mas1 & MAS1_VALID)
1912 tlb1_write_entry(&__boot_tlb1[i], i);
1915 set_mas4_defaults();
1920 booke_pmap_init_qpages(void)
1927 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1928 if (pc->pc_qmap_addr == 0)
1929 panic("pmap_init_qpages: unable to allocate KVA");
1933 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1936 * Get the physical page address for the given pmap/virtual address.
1939 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1944 pa = pte_vatopa(mmu, pmap, va);
1951 * Extract the physical page address associated with the given
1952 * kernel virtual address.
1955 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1961 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1962 p = pte_vatopa(mmu, kernel_pmap, va);
1965 /* Check TLB1 mappings */
1966 for (i = 0; i < TLB1_ENTRIES; i++) {
1967 tlb1_read_entry(&e, i);
1968 if (!(e.mas1 & MAS1_VALID))
1970 if (va >= e.virt && va < e.virt + e.size)
1971 return (e.phys + (va - e.virt));
1979 * Initialize the pmap module.
1980 * Called by vm_init, to initialize any structures that the pmap
1981 * system needs to map virtual memory.
1984 mmu_booke_init(mmu_t mmu)
1986 int shpgperproc = PMAP_SHPGPERPROC;
1989 * Initialize the address space (zone) for the pv entries. Set a
1990 * high water mark so that the system can recover from excessive
1991 * numbers of pv entries.
1993 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1994 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1996 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1997 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1999 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
2000 pv_entry_high_water = 9 * (pv_entry_max / 10);
2002 uma_zone_reserve_kva(pvzone, pv_entry_max);
2004 /* Pre-fill pvzone with initial number of pv entries. */
2005 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
2007 /* Create a UMA zone for page table roots. */
2008 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
2009 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
2011 /* Initialize ptbl allocation. */
2016 * Map a list of wired pages into kernel virtual address space. This is
2017 * intended for temporary mappings which do not need page modification or
2018 * references recorded. Existing mappings in the region are overwritten.
2021 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
2026 while (count-- > 0) {
2027 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2034 * Remove page mappings from kernel virtual address space. Intended for
2035 * temporary mappings entered by mmu_booke_qenter.
2038 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
2043 while (count-- > 0) {
2044 mmu_booke_kremove(mmu, va);
2050 * Map a wired page into kernel virtual address space.
2053 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
2056 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
2060 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
2065 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2066 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
2068 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
2069 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
2070 flags |= PTE_PS_4KB;
2072 pte = pte_find(mmu, kernel_pmap, va);
2073 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
2075 mtx_lock_spin(&tlbivax_mutex);
2078 if (PTE_ISVALID(pte)) {
2080 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
2082 /* Flush entry from TLB0 */
2083 tlb0_flush_entry(va);
2086 *pte = PTE_RPN_FROM_PA(pa) | flags;
2088 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
2089 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
2090 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
2092 /* Flush the real memory from the instruction cache. */
2093 if ((flags & (PTE_I | PTE_G)) == 0)
2094 __syncicache((void *)va, PAGE_SIZE);
2097 mtx_unlock_spin(&tlbivax_mutex);
2101 * Remove a page from kernel page table.
2104 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
2108 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
2110 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2111 (va <= VM_MAX_KERNEL_ADDRESS)),
2112 ("mmu_booke_kremove: invalid va"));
2114 pte = pte_find(mmu, kernel_pmap, va);
2116 if (!PTE_ISVALID(pte)) {
2118 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
2123 mtx_lock_spin(&tlbivax_mutex);
2126 /* Invalidate entry in TLB0, update PTE. */
2127 tlb0_flush_entry(va);
2131 mtx_unlock_spin(&tlbivax_mutex);
2135 * Provide a kernel pointer corresponding to a given userland pointer.
2136 * The returned pointer is valid until the next time this function is
2137 * called in this thread. This is used internally in copyin/copyout.
2140 mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
2141 void **kaddr, size_t ulen, size_t *klen)
2144 if ((uintptr_t)uaddr + ulen > VM_MAXUSER_ADDRESS + PAGE_SIZE)
2147 *kaddr = (void *)(uintptr_t)uaddr;
2155 * Figure out where a given kernel pointer (usually in a fault) points
2156 * to from the VM's perspective, potentially remapping into userland's
2160 mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
2161 vm_offset_t *decoded_addr)
2164 if (addr < VM_MAXUSER_ADDRESS)
2169 *decoded_addr = addr;
2174 * Initialize pmap associated with process 0.
2177 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
2180 PMAP_LOCK_INIT(pmap);
2181 mmu_booke_pinit(mmu, pmap);
2182 PCPU_SET(curpmap, pmap);
2186 * Initialize a preallocated and zeroed pmap structure,
2187 * such as one in a vmspace structure.
2190 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
2194 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
2195 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
2197 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
2199 for (i = 0; i < MAXCPU; i++)
2200 pmap->pm_tid[i] = TID_NONE;
2201 CPU_ZERO(&kernel_pmap->pm_active);
2202 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2203 #ifdef __powerpc64__
2204 pmap->pm_pp2d = uma_zalloc(ptbl_root_zone, M_WAITOK);
2205 bzero(pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES);
2207 pmap->pm_pdir = uma_zalloc(ptbl_root_zone, M_WAITOK);
2208 bzero(pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
2209 TAILQ_INIT(&pmap->pm_ptbl_list);
2214 * Release any resources held by the given physical map.
2215 * Called when a pmap initialized by mmu_booke_pinit is being released.
2216 * Should only be called if the map contains no valid mappings.
2219 mmu_booke_release(mmu_t mmu, pmap_t pmap)
2222 KASSERT(pmap->pm_stats.resident_count == 0,
2223 ("pmap_release: pmap resident count %ld != 0",
2224 pmap->pm_stats.resident_count));
2225 #ifdef __powerpc64__
2226 uma_zfree(ptbl_root_zone, pmap->pm_pp2d);
2228 uma_zfree(ptbl_root_zone, pmap->pm_pdir);
2233 * Insert the given physical page at the specified virtual address in the
2234 * target physical map with the protection requested. If specified the page
2235 * will be wired down.
2238 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2239 vm_prot_t prot, u_int flags, int8_t psind)
2243 rw_wlock(&pvh_global_lock);
2245 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
2247 rw_wunlock(&pvh_global_lock);
2252 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2253 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
2258 int error, su, sync;
2260 pa = VM_PAGE_TO_PHYS(m);
2261 su = (pmap == kernel_pmap);
2264 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
2265 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
2266 // (u_int32_t)pmap, su, pmap->pm_tid,
2267 // (u_int32_t)m, va, pa, prot, flags);
2270 KASSERT(((va >= virtual_avail) &&
2271 (va <= VM_MAX_KERNEL_ADDRESS)),
2272 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
2274 KASSERT((va <= VM_MAXUSER_ADDRESS),
2275 ("mmu_booke_enter_locked: user pmap, non user va"));
2277 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2278 VM_OBJECT_ASSERT_LOCKED(m->object);
2280 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2283 * If there is an existing mapping, and the physical address has not
2284 * changed, must be protection or wiring change.
2286 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
2287 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
2290 * Before actually updating pte->flags we calculate and
2291 * prepare its new value in a helper var.
2294 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
2296 /* Wiring change, just update stats. */
2297 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
2298 if (!PTE_ISWIRED(pte)) {
2300 pmap->pm_stats.wired_count++;
2303 if (PTE_ISWIRED(pte)) {
2304 flags &= ~PTE_WIRED;
2305 pmap->pm_stats.wired_count--;
2309 if (prot & VM_PROT_WRITE) {
2310 /* Add write permissions. */
2315 if ((flags & PTE_MANAGED) != 0)
2316 vm_page_aflag_set(m, PGA_WRITEABLE);
2318 /* Handle modified pages, sense modify status. */
2321 * The PTE_MODIFIED flag could be set by underlying
2322 * TLB misses since we last read it (above), possibly
2323 * other CPUs could update it so we check in the PTE
2324 * directly rather than rely on that saved local flags
2327 if (PTE_ISMODIFIED(pte))
2331 if (prot & VM_PROT_EXECUTE) {
2337 * Check existing flags for execute permissions: if we
2338 * are turning execute permissions on, icache should
2341 if ((*pte & (PTE_UX | PTE_SX)) == 0)
2345 flags &= ~PTE_REFERENCED;
2348 * The new flags value is all calculated -- only now actually
2351 mtx_lock_spin(&tlbivax_mutex);
2354 tlb0_flush_entry(va);
2355 *pte &= ~PTE_FLAGS_MASK;
2359 mtx_unlock_spin(&tlbivax_mutex);
2363 * If there is an existing mapping, but it's for a different
2364 * physical address, pte_enter() will delete the old mapping.
2366 //if ((pte != NULL) && PTE_ISVALID(pte))
2367 // debugf("mmu_booke_enter_locked: replace\n");
2369 // debugf("mmu_booke_enter_locked: new\n");
2371 /* Now set up the flags and install the new mapping. */
2372 flags = (PTE_SR | PTE_VALID);
2378 if (prot & VM_PROT_WRITE) {
2383 if ((m->oflags & VPO_UNMANAGED) == 0)
2384 vm_page_aflag_set(m, PGA_WRITEABLE);
2387 if (prot & VM_PROT_EXECUTE) {
2393 /* If its wired update stats. */
2394 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
2397 error = pte_enter(mmu, pmap, m, va, flags,
2398 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
2400 return (KERN_RESOURCE_SHORTAGE);
2402 if ((flags & PMAP_ENTER_WIRED) != 0)
2403 pmap->pm_stats.wired_count++;
2405 /* Flush the real memory from the instruction cache. */
2406 if (prot & VM_PROT_EXECUTE)
2410 if (sync && (su || pmap == PCPU_GET(curpmap))) {
2411 __syncicache((void *)va, PAGE_SIZE);
2415 return (KERN_SUCCESS);
2419 * Maps a sequence of resident pages belonging to the same object.
2420 * The sequence begins with the given page m_start. This page is
2421 * mapped at the given virtual address start. Each subsequent page is
2422 * mapped at a virtual address that is offset from start by the same
2423 * amount as the page is offset from m_start within the object. The
2424 * last page in the sequence is the page with the largest offset from
2425 * m_start that can be mapped at a virtual address less than the given
2426 * virtual address end. Not every virtual page between start and end
2427 * is mapped; only those for which a resident page exists with the
2428 * corresponding offset from m_start are mapped.
2431 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
2432 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
2435 vm_pindex_t diff, psize;
2437 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2439 psize = atop(end - start);
2441 rw_wlock(&pvh_global_lock);
2443 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2444 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
2445 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
2446 PMAP_ENTER_NOSLEEP, 0);
2447 m = TAILQ_NEXT(m, listq);
2449 rw_wunlock(&pvh_global_lock);
2454 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2458 rw_wlock(&pvh_global_lock);
2460 mmu_booke_enter_locked(mmu, pmap, va, m,
2461 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP,
2463 rw_wunlock(&pvh_global_lock);
2468 * Remove the given range of addresses from the specified map.
2470 * It is assumed that the start and end are properly rounded to the page size.
2473 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
2478 int su = (pmap == kernel_pmap);
2480 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
2481 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
2484 KASSERT(((va >= virtual_avail) &&
2485 (va <= VM_MAX_KERNEL_ADDRESS)),
2486 ("mmu_booke_remove: kernel pmap, non kernel va"));
2488 KASSERT((va <= VM_MAXUSER_ADDRESS),
2489 ("mmu_booke_remove: user pmap, non user va"));
2492 if (PMAP_REMOVE_DONE(pmap)) {
2493 //debugf("mmu_booke_remove: e (empty)\n");
2497 hold_flag = PTBL_HOLD_FLAG(pmap);
2498 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
2500 rw_wlock(&pvh_global_lock);
2502 for (; va < endva; va += PAGE_SIZE) {
2503 pte = pte_find(mmu, pmap, va);
2504 if ((pte != NULL) && PTE_ISVALID(pte))
2505 pte_remove(mmu, pmap, va, hold_flag);
2508 rw_wunlock(&pvh_global_lock);
2510 //debugf("mmu_booke_remove: e\n");
2514 * Remove physical page from all pmaps in which it resides.
2517 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
2522 rw_wlock(&pvh_global_lock);
2523 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
2524 pvn = TAILQ_NEXT(pv, pv_link);
2526 PMAP_LOCK(pv->pv_pmap);
2527 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
2528 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
2529 PMAP_UNLOCK(pv->pv_pmap);
2531 vm_page_aflag_clear(m, PGA_WRITEABLE);
2532 rw_wunlock(&pvh_global_lock);
2536 * Map a range of physical addresses into kernel virtual address space.
2539 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2540 vm_paddr_t pa_end, int prot)
2542 vm_offset_t sva = *virt;
2543 vm_offset_t va = sva;
2545 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
2546 // sva, pa_start, pa_end);
2548 while (pa_start < pa_end) {
2549 mmu_booke_kenter(mmu, va, pa_start);
2551 pa_start += PAGE_SIZE;
2555 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
2560 * The pmap must be activated before it's address space can be accessed in any
2564 mmu_booke_activate(mmu_t mmu, struct thread *td)
2569 pmap = &td->td_proc->p_vmspace->vm_pmap;
2571 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
2572 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2574 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
2578 cpuid = PCPU_GET(cpuid);
2579 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
2580 PCPU_SET(curpmap, pmap);
2582 if (pmap->pm_tid[cpuid] == TID_NONE)
2585 /* Load PID0 register with pmap tid value. */
2586 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
2587 __asm __volatile("isync");
2589 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
2593 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
2594 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
2598 * Deactivate the specified process's address space.
2601 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
2605 pmap = &td->td_proc->p_vmspace->vm_pmap;
2607 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
2608 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2610 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
2612 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
2613 PCPU_SET(curpmap, NULL);
2617 * Copy the range specified by src_addr/len
2618 * from the source map to the range dst_addr/len
2619 * in the destination map.
2621 * This routine is only advisory and need not do anything.
2624 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
2625 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
2631 * Set the physical protection on the specified range of this map as requested.
2634 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2641 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2642 mmu_booke_remove(mmu, pmap, sva, eva);
2646 if (prot & VM_PROT_WRITE)
2650 for (va = sva; va < eva; va += PAGE_SIZE) {
2651 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2652 if (PTE_ISVALID(pte)) {
2653 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2655 mtx_lock_spin(&tlbivax_mutex);
2658 /* Handle modified pages. */
2659 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2662 tlb0_flush_entry(va);
2663 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2666 mtx_unlock_spin(&tlbivax_mutex);
2674 * Clear the write and modified bits in each of the given page's mappings.
2677 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2682 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2683 ("mmu_booke_remove_write: page %p is not managed", m));
2686 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2687 * set by another thread while the object is locked. Thus,
2688 * if PGA_WRITEABLE is clear, no page table entries need updating.
2690 VM_OBJECT_ASSERT_WLOCKED(m->object);
2691 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2693 rw_wlock(&pvh_global_lock);
2694 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2695 PMAP_LOCK(pv->pv_pmap);
2696 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2697 if (PTE_ISVALID(pte)) {
2698 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2700 mtx_lock_spin(&tlbivax_mutex);
2703 /* Handle modified pages. */
2704 if (PTE_ISMODIFIED(pte))
2707 /* Flush mapping from TLB0. */
2708 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2711 mtx_unlock_spin(&tlbivax_mutex);
2714 PMAP_UNLOCK(pv->pv_pmap);
2716 vm_page_aflag_clear(m, PGA_WRITEABLE);
2717 rw_wunlock(&pvh_global_lock);
2721 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2726 #ifndef __powerpc64__
2733 #ifndef __powerpc64__
2734 rw_wlock(&pvh_global_lock);
2735 pmap = PCPU_GET(curpmap);
2736 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2740 pte = pte_find(mmu, pm, va);
2741 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2745 sync_sz = PAGE_SIZE - (va & PAGE_MASK);
2746 sync_sz = min(sync_sz, sz);
2748 #ifdef __powerpc64__
2749 pa += (va & PAGE_MASK);
2750 __syncicache((void *)PHYS_TO_DMAP(pa), sync_sz);
2753 /* Create a mapping in the active pmap. */
2755 m = PHYS_TO_VM_PAGE(pa);
2757 pte_enter(mmu, pmap, m, addr,
2758 PTE_SR | PTE_VALID, FALSE);
2759 addr += (va & PAGE_MASK);
2760 __syncicache((void *)addr, sync_sz);
2761 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2764 __syncicache((void *)va, sync_sz);
2770 #ifndef __powerpc64__
2771 rw_wunlock(&pvh_global_lock);
2776 * Atomically extract and hold the physical page with the given
2777 * pmap and virtual address pair if that mapping permits the given
2781 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2793 pte = pte_find(mmu, pmap, va);
2794 if ((pte != NULL) && PTE_ISVALID(pte)) {
2795 if (pmap == kernel_pmap)
2800 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2801 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2803 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2814 * Initialize a vm_page's machine-dependent fields.
2817 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2820 m->md.pv_tracked = 0;
2821 TAILQ_INIT(&m->md.pv_list);
2825 * mmu_booke_zero_page_area zeros the specified hardware page by
2826 * mapping it into virtual memory and using bzero to clear
2829 * off and size must reside within a single page.
2832 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2836 /* XXX KASSERT off and size are within a single page? */
2838 #ifdef __powerpc64__
2839 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2840 bzero((caddr_t)va + off, size);
2842 mtx_lock(&zero_page_mutex);
2845 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2846 bzero((caddr_t)va + off, size);
2847 mmu_booke_kremove(mmu, va);
2849 mtx_unlock(&zero_page_mutex);
2854 * mmu_booke_zero_page zeros the specified hardware page.
2857 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2859 vm_offset_t off, va;
2861 #ifdef __powerpc64__
2862 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2864 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
2865 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
2868 mtx_lock(&zero_page_mutex);
2870 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2872 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
2873 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
2875 mmu_booke_kremove(mmu, va);
2877 mtx_unlock(&zero_page_mutex);
2882 * mmu_booke_copy_page copies the specified (machine independent) page by
2883 * mapping the page into virtual memory and using memcopy to copy the page,
2884 * one machine dependent page at a time.
2887 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2889 vm_offset_t sva, dva;
2891 #ifdef __powerpc64__
2892 sva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(sm));
2893 dva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dm));
2894 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2896 sva = copy_page_src_va;
2897 dva = copy_page_dst_va;
2899 mtx_lock(©_page_mutex);
2900 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2901 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2903 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2905 mmu_booke_kremove(mmu, dva);
2906 mmu_booke_kremove(mmu, sva);
2907 mtx_unlock(©_page_mutex);
2912 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2913 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2916 vm_offset_t a_pg_offset, b_pg_offset;
2919 #ifdef __powerpc64__
2922 while (xfersize > 0) {
2923 a_pg_offset = a_offset & PAGE_MASK;
2924 pa = ma[a_offset >> PAGE_SHIFT];
2925 b_pg_offset = b_offset & PAGE_MASK;
2926 pb = mb[b_offset >> PAGE_SHIFT];
2927 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2928 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2929 a_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pa)) +
2931 b_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pb)) +
2933 bcopy(a_cp, b_cp, cnt);
2939 mtx_lock(©_page_mutex);
2940 while (xfersize > 0) {
2941 a_pg_offset = a_offset & PAGE_MASK;
2942 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2943 mmu_booke_kenter(mmu, copy_page_src_va,
2944 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2945 a_cp = (char *)copy_page_src_va + a_pg_offset;
2946 b_pg_offset = b_offset & PAGE_MASK;
2947 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2948 mmu_booke_kenter(mmu, copy_page_dst_va,
2949 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2950 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2951 bcopy(a_cp, b_cp, cnt);
2952 mmu_booke_kremove(mmu, copy_page_dst_va);
2953 mmu_booke_kremove(mmu, copy_page_src_va);
2958 mtx_unlock(©_page_mutex);
2963 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m)
2965 #ifdef __powerpc64__
2966 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
2973 paddr = VM_PAGE_TO_PHYS(m);
2975 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
2976 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
2977 flags |= PTE_PS_4KB;
2980 qaddr = PCPU_GET(qmap_addr);
2982 pte = pte_find(mmu, kernel_pmap, qaddr);
2984 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy"));
2987 * XXX: tlbivax is broadcast to other cores, but qaddr should
2988 * not be present in other TLBs. Is there a better instruction
2989 * sequence to use? Or just forget it & use mmu_booke_kenter()...
2991 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK));
2992 __asm __volatile("isync; msync");
2994 *pte = PTE_RPN_FROM_PA(paddr) | flags;
2996 /* Flush the real memory from the instruction cache. */
2997 if ((flags & (PTE_I | PTE_G)) == 0)
2998 __syncicache((void *)qaddr, PAGE_SIZE);
3005 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr)
3007 #ifndef __powerpc64__
3010 pte = pte_find(mmu, kernel_pmap, addr);
3012 KASSERT(PCPU_GET(qmap_addr) == addr,
3013 ("mmu_booke_quick_remove_page: invalid address"));
3015 ("mmu_booke_quick_remove_page: PTE not in use"));
3023 * Return whether or not the specified physical page was modified
3024 * in any of physical maps.
3027 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
3033 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3034 ("mmu_booke_is_modified: page %p is not managed", m));
3038 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3039 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3040 * is clear, no PTEs can be modified.
3042 VM_OBJECT_ASSERT_WLOCKED(m->object);
3043 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3045 rw_wlock(&pvh_global_lock);
3046 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3047 PMAP_LOCK(pv->pv_pmap);
3048 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3050 if (PTE_ISMODIFIED(pte))
3053 PMAP_UNLOCK(pv->pv_pmap);
3057 rw_wunlock(&pvh_global_lock);
3062 * Return whether or not the specified virtual address is eligible
3066 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
3073 * Return whether or not the specified physical page was referenced
3074 * in any physical maps.
3077 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
3083 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3084 ("mmu_booke_is_referenced: page %p is not managed", m));
3086 rw_wlock(&pvh_global_lock);
3087 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3088 PMAP_LOCK(pv->pv_pmap);
3089 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3091 if (PTE_ISREFERENCED(pte))
3094 PMAP_UNLOCK(pv->pv_pmap);
3098 rw_wunlock(&pvh_global_lock);
3103 * Clear the modify bits on the specified physical page.
3106 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
3111 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3112 ("mmu_booke_clear_modify: page %p is not managed", m));
3113 VM_OBJECT_ASSERT_WLOCKED(m->object);
3114 KASSERT(!vm_page_xbusied(m),
3115 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
3118 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
3119 * If the object containing the page is locked and the page is not
3120 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
3122 if ((m->aflags & PGA_WRITEABLE) == 0)
3124 rw_wlock(&pvh_global_lock);
3125 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3126 PMAP_LOCK(pv->pv_pmap);
3127 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3129 mtx_lock_spin(&tlbivax_mutex);
3132 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
3133 tlb0_flush_entry(pv->pv_va);
3134 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
3139 mtx_unlock_spin(&tlbivax_mutex);
3141 PMAP_UNLOCK(pv->pv_pmap);
3143 rw_wunlock(&pvh_global_lock);
3147 * Return a count of reference bits for a page, clearing those bits.
3148 * It is not necessary for every reference bit to be cleared, but it
3149 * is necessary that 0 only be returned when there are truly no
3150 * reference bits set.
3152 * As an optimization, update the page's dirty field if a modified bit is
3153 * found while counting reference bits. This opportunistic update can be
3154 * performed at low cost and can eliminate the need for some future calls
3155 * to pmap_is_modified(). However, since this function stops after
3156 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3157 * dirty pages. Those dirty pages will only be detected by a future call
3158 * to pmap_is_modified().
3161 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
3167 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3168 ("mmu_booke_ts_referenced: page %p is not managed", m));
3170 rw_wlock(&pvh_global_lock);
3171 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3172 PMAP_LOCK(pv->pv_pmap);
3173 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3175 if (PTE_ISMODIFIED(pte))
3177 if (PTE_ISREFERENCED(pte)) {
3178 mtx_lock_spin(&tlbivax_mutex);
3181 tlb0_flush_entry(pv->pv_va);
3182 *pte &= ~PTE_REFERENCED;
3185 mtx_unlock_spin(&tlbivax_mutex);
3187 if (++count >= PMAP_TS_REFERENCED_MAX) {
3188 PMAP_UNLOCK(pv->pv_pmap);
3193 PMAP_UNLOCK(pv->pv_pmap);
3195 rw_wunlock(&pvh_global_lock);
3200 * Clear the wired attribute from the mappings for the specified range of
3201 * addresses in the given pmap. Every valid mapping within that range must
3202 * have the wired attribute set. In contrast, invalid mappings cannot have
3203 * the wired attribute set, so they are ignored.
3205 * The wired attribute of the page table entry is not a hardware feature, so
3206 * there is no need to invalidate any TLB entries.
3209 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3215 for (va = sva; va < eva; va += PAGE_SIZE) {
3216 if ((pte = pte_find(mmu, pmap, va)) != NULL &&
3218 if (!PTE_ISWIRED(pte))
3219 panic("mmu_booke_unwire: pte %p isn't wired",
3222 pmap->pm_stats.wired_count--;
3230 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
3231 * page. This count may be changed upwards or downwards in the future; it is
3232 * only necessary that true be returned for a small subset of pmaps for proper
3236 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
3242 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3243 ("mmu_booke_page_exists_quick: page %p is not managed", m));
3246 rw_wlock(&pvh_global_lock);
3247 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3248 if (pv->pv_pmap == pmap) {
3255 rw_wunlock(&pvh_global_lock);
3260 * Return the number of managed mappings to the given physical page that are
3264 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
3270 if ((m->oflags & VPO_UNMANAGED) != 0)
3272 rw_wlock(&pvh_global_lock);
3273 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3274 PMAP_LOCK(pv->pv_pmap);
3275 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
3276 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
3278 PMAP_UNLOCK(pv->pv_pmap);
3280 rw_wunlock(&pvh_global_lock);
3285 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3291 * This currently does not work for entries that
3292 * overlap TLB1 entries.
3294 for (i = 0; i < TLB1_ENTRIES; i ++) {
3295 if (tlb1_iomapped(i, pa, size, &va) == 0)
3303 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
3309 /* Minidumps are based on virtual memory addresses. */
3311 *va = (void *)(vm_offset_t)pa;
3315 /* Raw physical memory dumps don't have a virtual address. */
3316 /* We always map a 256MB page at 256M. */
3317 gran = 256 * 1024 * 1024;
3318 ppa = rounddown2(pa, gran);
3321 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
3323 if (sz > (gran - ofs))
3324 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
3329 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va)
3337 /* Minidumps are based on virtual memory addresses. */
3338 /* Nothing to do... */
3342 for (i = 0; i < TLB1_ENTRIES; i++) {
3343 tlb1_read_entry(&e, i);
3344 if (!(e.mas1 & MAS1_VALID))
3348 /* Raw physical memory dumps don't have a virtual address. */
3353 tlb1_write_entry(&e, i);
3355 gran = 256 * 1024 * 1024;
3356 ppa = rounddown2(pa, gran);
3358 if (sz > (gran - ofs)) {
3363 tlb1_write_entry(&e, i);
3367 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
3370 mmu_booke_scan_init(mmu_t mmu)
3377 /* Initialize phys. segments for dumpsys(). */
3378 memset(&dump_map, 0, sizeof(dump_map));
3379 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
3380 &availmem_regions_sz);
3381 for (i = 0; i < physmem_regions_sz; i++) {
3382 dump_map[i].pa_start = physmem_regions[i].mr_start;
3383 dump_map[i].pa_size = physmem_regions[i].mr_size;
3388 /* Virtual segments for minidumps: */
3389 memset(&dump_map, 0, sizeof(dump_map));
3391 /* 1st: kernel .data and .bss. */
3392 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
3393 dump_map[0].pa_size =
3394 round_page((uintptr_t)_end) - dump_map[0].pa_start;
3396 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
3397 dump_map[1].pa_start = data_start;
3398 dump_map[1].pa_size = data_end - data_start;
3400 /* 3rd: kernel VM. */
3401 va = dump_map[1].pa_start + dump_map[1].pa_size;
3402 /* Find start of next chunk (from va). */
3403 while (va < virtual_end) {
3404 /* Don't dump the buffer cache. */
3405 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
3406 va = kmi.buffer_eva;
3409 pte = pte_find(mmu, kernel_pmap, va);
3410 if (pte != NULL && PTE_ISVALID(pte))
3414 if (va < virtual_end) {
3415 dump_map[2].pa_start = va;
3417 /* Find last page in chunk. */
3418 while (va < virtual_end) {
3419 /* Don't run into the buffer cache. */
3420 if (va == kmi.buffer_sva)
3422 pte = pte_find(mmu, kernel_pmap, va);
3423 if (pte == NULL || !PTE_ISVALID(pte))
3427 dump_map[2].pa_size = va - dump_map[2].pa_start;
3432 * Map a set of physical memory pages into the kernel virtual address space.
3433 * Return a pointer to where it is mapped. This routine is intended to be used
3434 * for mapping device memory, NOT real memory.
3437 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3440 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
3444 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3448 uintptr_t va, tmpva;
3453 * Check if this is premapped in TLB1. Note: this should probably also
3454 * check whether a sequence of TLB1 entries exist that match the
3455 * requirement, but now only checks the easy case.
3457 for (i = 0; i < TLB1_ENTRIES; i++) {
3458 tlb1_read_entry(&e, i);
3459 if (!(e.mas1 & MAS1_VALID))
3462 (pa + size) <= (e.phys + e.size) &&
3463 (ma == VM_MEMATTR_DEFAULT ||
3464 tlb_calc_wimg(pa, ma) ==
3465 (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))))
3466 return (void *)(e.virt +
3467 (vm_offset_t)(pa - e.phys));
3470 size = roundup(size, PAGE_SIZE);
3473 * The device mapping area is between VM_MAXUSER_ADDRESS and
3474 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
3476 #ifdef SPARSE_MAPDEV
3478 * With a sparse mapdev, align to the largest starting region. This
3479 * could feasibly be optimized for a 'best-fit' alignment, but that
3480 * calculation could be very costly.
3481 * Align to the smaller of:
3482 * - first set bit in overlap of (pa & size mask)
3483 * - largest size envelope
3485 * It's possible the device mapping may start at a PA that's not larger
3486 * than the size mask, so we need to offset in to maximize the TLB entry
3487 * range and minimize the number of used TLB entries.
3490 tmpva = tlb1_map_base;
3491 sz = ffsl(((1 << flsl(size-1)) - 1) & pa);
3492 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
3493 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
3494 #ifdef __powerpc64__
3495 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size));
3497 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
3500 #ifdef __powerpc64__
3501 va = atomic_fetchadd_long(&tlb1_map_base, size);
3503 va = atomic_fetchadd_int(&tlb1_map_base, size);
3509 sz = 1 << (ilog2(size) & ~1);
3510 /* Align size to PA */
3514 } while (pa % sz != 0);
3516 /* Now align from there to VA */
3520 } while (va % sz != 0);
3523 printf("Wiring VA=%lx to PA=%jx (size=%lx)\n",
3524 va, (uintmax_t)pa, sz);
3525 if (tlb1_set_entry(va, pa, sz,
3526 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)) < 0)
3537 * 'Unmap' a range mapped by mmu_booke_mapdev().
3540 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
3542 #ifdef SUPPORTS_SHRINKING_TLB1
3543 vm_offset_t base, offset;
3546 * Unmap only if this is inside kernel virtual space.
3548 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
3549 base = trunc_page(va);
3550 offset = va & PAGE_MASK;
3551 size = roundup(offset + size, PAGE_SIZE);
3552 kva_free(base, size);
3558 * mmu_booke_object_init_pt preloads the ptes for a given object into the
3559 * specified pmap. This eliminates the blast of soft faults on process startup
3560 * and immediately after an mmap.
3563 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3564 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
3567 VM_OBJECT_ASSERT_WLOCKED(object);
3568 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3569 ("mmu_booke_object_init_pt: non-device object"));
3573 * Perform the pmap work for mincore.
3576 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3577 vm_paddr_t *locked_pa)
3580 /* XXX: this should be implemented at some point */
3585 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz,
3593 /* Check TLB1 mappings */
3594 for (i = 0; i < TLB1_ENTRIES; i++) {
3595 tlb1_read_entry(&e, i);
3596 if (!(e.mas1 & MAS1_VALID))
3598 if (addr >= e.virt && addr < e.virt + e.size)
3601 if (i < TLB1_ENTRIES) {
3602 /* Only allow full mappings to be modified for now. */
3603 /* Validate the range. */
3604 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
3605 tlb1_read_entry(&e, j);
3606 if (va != e.virt || (sz - (va - addr) < e.size))
3609 for (va = addr; va < addr + sz; va += e.size, i++) {
3610 tlb1_read_entry(&e, i);
3611 e.mas2 &= ~MAS2_WIMGE_MASK;
3612 e.mas2 |= tlb_calc_wimg(e.phys, mode);
3615 * Write it out to the TLB. Should really re-sync with other
3618 tlb1_write_entry(&e, i);
3623 /* Not in TLB1, try through pmap */
3624 /* First validate the range. */
3625 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3626 pte = pte_find(mmu, kernel_pmap, va);
3627 if (pte == NULL || !PTE_ISVALID(pte))
3631 mtx_lock_spin(&tlbivax_mutex);
3633 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3634 pte = pte_find(mmu, kernel_pmap, va);
3635 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
3636 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
3637 tlb0_flush_entry(va);
3640 mtx_unlock_spin(&tlbivax_mutex);
3645 /**************************************************************************/
3647 /**************************************************************************/
3650 * Allocate a TID. If necessary, steal one from someone else.
3651 * The new TID is flushed from the TLB before returning.
3654 tid_alloc(pmap_t pmap)
3659 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
3661 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
3663 thiscpu = PCPU_GET(cpuid);
3665 tid = PCPU_GET(booke.tid_next);
3668 PCPU_SET(booke.tid_next, tid + 1);
3670 /* If we are stealing TID then clear the relevant pmap's field */
3671 if (tidbusy[thiscpu][tid] != NULL) {
3673 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
3675 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
3677 /* Flush all entries from TLB0 matching this TID. */
3681 tidbusy[thiscpu][tid] = pmap;
3682 pmap->pm_tid[thiscpu] = tid;
3683 __asm __volatile("msync; isync");
3685 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
3686 PCPU_GET(booke.tid_next));
3691 /**************************************************************************/
3693 /**************************************************************************/
3695 /* Convert TLB0 va and way number to tlb0[] table index. */
3696 static inline unsigned int
3697 tlb0_tableidx(vm_offset_t va, unsigned int way)
3701 idx = (way * TLB0_ENTRIES_PER_WAY);
3702 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
3707 * Invalidate TLB0 entry.
3710 tlb0_flush_entry(vm_offset_t va)
3713 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
3715 mtx_assert(&tlbivax_mutex, MA_OWNED);
3717 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
3718 __asm __volatile("isync; msync");
3719 __asm __volatile("tlbsync; msync");
3721 CTR1(KTR_PMAP, "%s: e", __func__);
3725 /**************************************************************************/
3727 /**************************************************************************/
3730 * TLB1 mapping notes:
3732 * TLB1[0] Kernel text and data.
3733 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
3734 * windows, other devices mappings.
3738 * Read an entry from given TLB1 slot.
3741 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
3746 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
3749 __asm __volatile("wrteei 0");
3751 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
3752 mtspr(SPR_MAS0, mas0);
3753 __asm __volatile("isync; tlbre");
3755 entry->mas1 = mfspr(SPR_MAS1);
3756 entry->mas2 = mfspr(SPR_MAS2);
3757 entry->mas3 = mfspr(SPR_MAS3);
3759 switch ((mfpvr() >> 16) & 0xFFFF) {
3764 entry->mas7 = mfspr(SPR_MAS7);
3770 __asm __volatile("wrtee %0" :: "r"(msr));
3772 entry->virt = entry->mas2 & MAS2_EPN_MASK;
3773 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
3774 (entry->mas3 & MAS3_RPN);
3776 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
3779 struct tlbwrite_args {
3785 tlb1_write_entry_int(void *arg)
3787 struct tlbwrite_args *args = arg;
3791 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx);
3793 mtspr(SPR_MAS0, mas0);
3794 mtspr(SPR_MAS1, args->e->mas1);
3795 mtspr(SPR_MAS2, args->e->mas2);
3796 mtspr(SPR_MAS3, args->e->mas3);
3797 switch ((mfpvr() >> 16) & 0xFFFF) {
3804 mtspr(SPR_MAS7, args->e->mas7);
3810 __asm __volatile("isync; tlbwe; isync; msync");
3815 tlb1_write_entry_sync(void *arg)
3817 /* Empty synchronization point for smp_rendezvous(). */
3821 * Write given entry to TLB1 hardware.
3824 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
3826 struct tlbwrite_args args;
3832 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
3834 smp_rendezvous(tlb1_write_entry_sync,
3835 tlb1_write_entry_int,
3836 tlb1_write_entry_sync, &args);
3843 __asm __volatile("wrteei 0");
3844 tlb1_write_entry_int(&args);
3845 __asm __volatile("wrtee %0" :: "r"(msr));
3850 * Return the largest uint value log such that 2^log <= num.
3853 ilog2(unsigned long num)
3857 #ifdef __powerpc64__
3858 __asm ("cntlzd %0, %1" : "=r" (lz) : "r" (num));
3861 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
3867 * Convert TLB TSIZE value to mapped region size.
3870 tsize2size(unsigned int tsize)
3875 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
3878 return ((1 << (2 * tsize)) * 1024);
3882 * Convert region size (must be power of 4) to TLB TSIZE value.
3885 size2tsize(vm_size_t size)
3888 return (ilog2(size) / 2 - 5);
3892 * Register permanent kernel mapping in TLB1.
3894 * Entries are created starting from index 0 (current free entry is
3895 * kept in tlb1_idx) and are not supposed to be invalidated.
3898 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
3905 for (index = 0; index < TLB1_ENTRIES; index++) {
3906 tlb1_read_entry(&e, index);
3907 if ((e.mas1 & MAS1_VALID) == 0)
3909 /* Check if we're just updating the flags, and update them. */
3910 if (e.phys == pa && e.virt == va && e.size == size) {
3911 e.mas2 = (va & MAS2_EPN_MASK) | flags;
3912 tlb1_write_entry(&e, index);
3916 if (index >= TLB1_ENTRIES) {
3917 printf("tlb1_set_entry: TLB1 full!\n");
3921 /* Convert size to TSIZE */
3922 tsize = size2tsize(size);
3924 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3925 /* XXX TS is hard coded to 0 for now as we only use single address space */
3926 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3931 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3932 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3933 e.mas2 = (va & MAS2_EPN_MASK) | flags;
3935 /* Set supervisor RWX permission bits */
3936 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3937 e.mas7 = (pa >> 32) & MAS7_RPN;
3939 tlb1_write_entry(&e, index);
3942 * XXX in general TLB1 updates should be propagated between CPUs,
3943 * since current design assumes to have the same TLB1 set-up on all
3950 * Map in contiguous RAM region into the TLB1 using maximum of
3951 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3953 * If necessary round up last entry size and return total size
3954 * used by all allocated entries.
3957 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3959 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3960 vm_size_t mapped, pgsz, base, mask;
3963 /* Round up to the next 1M */
3964 size = roundup2(size, 1 << 20);
3969 pgsz = 64*1024*1024;
3970 while (mapped < size) {
3971 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3972 while (pgsz > (size - mapped))
3978 /* We under-map. Correct for this. */
3979 if (mapped < size) {
3980 while (pgs[idx - 1] == pgsz) {
3984 /* XXX We may increase beyond out starting point. */
3993 /* Align address to the boundary */
3995 va = (va + mask) & ~mask;
3996 pa = (pa + mask) & ~mask;
3999 for (idx = 0; idx < nents; idx++) {
4001 debugf("%u: %llx -> %jx, size=%jx\n", idx, pa,
4002 (uintmax_t)va, (uintmax_t)pgsz);
4003 tlb1_set_entry(va, pa, pgsz,
4004 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM);
4009 mapped = (va - base);
4011 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
4012 mapped, mapped - size);
4017 * TLB1 initialization routine, to be called after the very first
4018 * assembler level setup done in locore.S.
4023 uint32_t mas0, mas1, mas2, mas3, mas7;
4028 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
4029 mtspr(SPR_MAS0, mas0);
4030 __asm __volatile("isync; tlbre");
4032 mas1 = mfspr(SPR_MAS1);
4033 mas2 = mfspr(SPR_MAS2);
4034 mas3 = mfspr(SPR_MAS3);
4035 mas7 = mfspr(SPR_MAS7);
4037 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
4040 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4041 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
4043 /* Setup TLB miss defaults */
4044 set_mas4_defaults();
4048 * pmap_early_io_unmap() should be used in short conjunction with
4049 * pmap_early_io_map(), as in the following snippet:
4051 * x = pmap_early_io_map(...);
4052 * <do something with x>
4053 * pmap_early_io_unmap(x, size);
4055 * And avoiding more allocations between.
4058 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
4064 size = roundup(size, PAGE_SIZE);
4066 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
4067 tlb1_read_entry(&e, i);
4068 if (!(e.mas1 & MAS1_VALID))
4070 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
4072 e.mas1 &= ~MAS1_VALID;
4073 tlb1_write_entry(&e, i);
4076 if (tlb1_map_base == va + isize)
4077 tlb1_map_base -= isize;
4081 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
4088 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
4090 for (i = 0; i < TLB1_ENTRIES; i++) {
4091 tlb1_read_entry(&e, i);
4092 if (!(e.mas1 & MAS1_VALID))
4094 if (pa >= e.phys && (pa + size) <=
4096 return (e.virt + (pa - e.phys));
4099 pa_base = rounddown(pa, PAGE_SIZE);
4100 size = roundup(size + (pa - pa_base), PAGE_SIZE);
4101 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
4102 va = tlb1_map_base + (pa - pa_base);
4105 sz = 1 << (ilog2(size) & ~1);
4106 tlb1_set_entry(tlb1_map_base, pa_base, sz,
4107 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
4110 tlb1_map_base += sz;
4117 pmap_track_page(pmap_t pmap, vm_offset_t va)
4121 struct pv_entry *pve;
4123 va = trunc_page(va);
4124 pa = pmap_kextract(va);
4125 page = PHYS_TO_VM_PAGE(pa);
4127 rw_wlock(&pvh_global_lock);
4130 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
4131 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
4135 page->md.pv_tracked = true;
4136 pv_insert(pmap, va, page);
4139 rw_wunlock(&pvh_global_lock);
4144 * Setup MAS4 defaults.
4145 * These values are loaded to MAS0-2 on a TLB miss.
4148 set_mas4_defaults(void)
4152 /* Defaults: TLB0, PID0, TSIZED=4K */
4153 mas4 = MAS4_TLBSELD0;
4154 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
4158 mtspr(SPR_MAS4, mas4);
4159 __asm __volatile("isync");
4164 * Return 0 if the physical IO range is encompassed by one of the
4165 * the TLB1 entries, otherwise return related error code.
4168 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
4171 vm_paddr_t pa_start;
4173 unsigned int entry_tsize;
4174 vm_size_t entry_size;
4177 *va = (vm_offset_t)NULL;
4179 tlb1_read_entry(&e, i);
4180 /* Skip invalid entries */
4181 if (!(e.mas1 & MAS1_VALID))
4185 * The entry must be cache-inhibited, guarded, and r/w
4186 * so it can function as an i/o page
4188 prot = e.mas2 & (MAS2_I | MAS2_G);
4189 if (prot != (MAS2_I | MAS2_G))
4192 prot = e.mas3 & (MAS3_SR | MAS3_SW);
4193 if (prot != (MAS3_SR | MAS3_SW))
4196 /* The address should be within the entry range. */
4197 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4198 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
4200 entry_size = tsize2size(entry_tsize);
4201 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
4202 (e.mas3 & MAS3_RPN);
4203 pa_end = pa_start + entry_size;
4205 if ((pa < pa_start) || ((pa + size) > pa_end))
4208 /* Return virtual address of this mapping. */
4209 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
4214 * Invalidate all TLB0 entries which match the given TID. Note this is
4215 * dedicated for cases when invalidations should NOT be propagated to other
4219 tid_flush(tlbtid_t tid)
4222 uint32_t mas0, mas1, mas2;
4226 /* Don't evict kernel translations */
4227 if (tid == TID_KERNEL)
4231 __asm __volatile("wrteei 0");
4234 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use
4235 * it for PID invalidation.
4237 switch ((mfpvr() >> 16) & 0xffff) {
4241 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
4243 __asm __volatile("isync; .long 0x7c000024; isync; msync");
4244 __asm __volatile("wrtee %0" :: "r"(msr));
4248 for (way = 0; way < TLB0_WAYS; way++)
4249 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
4251 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4252 mtspr(SPR_MAS0, mas0);
4254 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
4255 mtspr(SPR_MAS2, mas2);
4257 __asm __volatile("isync; tlbre");
4259 mas1 = mfspr(SPR_MAS1);
4261 if (!(mas1 & MAS1_VALID))
4263 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
4265 mas1 &= ~MAS1_VALID;
4266 mtspr(SPR_MAS1, mas1);
4267 __asm __volatile("isync; tlbwe; isync; msync");
4269 __asm __volatile("wrtee %0" :: "r"(msr));
4273 /* Print out contents of the MAS registers for each TLB0 entry */
4275 #ifdef __powerpc64__
4276 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
4278 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
4289 if (mas1 & MAS1_VALID)
4294 if (mas1 & MAS1_IPROT)
4299 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
4300 tid = MAS1_GETTID(mas1);
4302 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4305 size = tsize2size(tsize);
4307 printf("%3d: (%s) [AS=%d] "
4308 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
4309 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
4310 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
4313 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
4315 uint32_t mas0, mas1, mas3, mas7;
4316 #ifdef __powerpc64__
4321 int entryidx, way, idx;
4323 printf("TLB0 entries:\n");
4324 for (way = 0; way < TLB0_WAYS; way ++)
4325 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
4327 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4328 mtspr(SPR_MAS0, mas0);
4330 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
4331 mtspr(SPR_MAS2, mas2);
4333 __asm __volatile("isync; tlbre");
4335 mas1 = mfspr(SPR_MAS1);
4336 mas2 = mfspr(SPR_MAS2);
4337 mas3 = mfspr(SPR_MAS3);
4338 mas7 = mfspr(SPR_MAS7);
4340 idx = tlb0_tableidx(mas2, way);
4341 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
4346 * Print out contents of the MAS registers for each TLB1 entry
4348 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
4350 uint32_t mas0, mas1, mas3, mas7;
4351 #ifdef __powerpc64__
4358 printf("TLB1 entries:\n");
4359 for (i = 0; i < TLB1_ENTRIES; i++) {
4361 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
4362 mtspr(SPR_MAS0, mas0);
4364 __asm __volatile("isync; tlbre");
4366 mas1 = mfspr(SPR_MAS1);
4367 mas2 = mfspr(SPR_MAS2);
4368 mas3 = mfspr(SPR_MAS3);
4369 mas7 = mfspr(SPR_MAS7);
4371 tlb_print_entry(i, mas1, mas2, mas3, mas7);