2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_kern.h>
104 #include <vm/vm_pageout.h>
105 #include <vm/vm_extern.h>
106 #include <vm/vm_object.h>
107 #include <vm/vm_param.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
114 #include <machine/_inttypes.h>
115 #include <machine/cpu.h>
116 #include <machine/pcb.h>
117 #include <machine/platform.h>
119 #include <machine/tlb.h>
120 #include <machine/spr.h>
121 #include <machine/md_var.h>
122 #include <machine/mmuvar.h>
123 #include <machine/pmap.h>
124 #include <machine/pte.h>
128 #define SPARSE_MAPDEV
130 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
131 #define POW2_MAPPINGS
134 #define debugf(fmt, args...) printf(fmt, ##args)
136 #define debugf(fmt, args...)
140 #define PRI0ptrX "016lx"
142 #define PRI0ptrX "08x"
145 #define TODO panic("%s: not implemented", __func__);
147 extern unsigned char _etext[];
148 extern unsigned char _end[];
150 extern uint32_t *bootinfo;
153 vm_offset_t kernstart;
156 /* Message buffer and tables. */
157 static vm_offset_t data_start;
158 static vm_size_t data_end;
160 /* Phys/avail memory regions. */
161 static struct mem_region *availmem_regions;
162 static int availmem_regions_sz;
163 static struct mem_region *physmem_regions;
164 static int physmem_regions_sz;
166 #ifndef __powerpc64__
167 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
168 static vm_offset_t zero_page_va;
169 static struct mtx zero_page_mutex;
171 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
172 static vm_offset_t copy_page_src_va;
173 static vm_offset_t copy_page_dst_va;
174 static struct mtx copy_page_mutex;
177 static struct mtx tlbivax_mutex;
179 /**************************************************************************/
181 /**************************************************************************/
183 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
184 vm_prot_t, u_int flags, int8_t psind);
186 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
187 static uma_zone_t ptbl_root_zone;
190 * If user pmap is processed with mmu_booke_remove and the resident count
191 * drops to 0, there are no more pages to remove, so we need not continue.
193 #define PMAP_REMOVE_DONE(pmap) \
194 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
196 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
197 extern int elf32_nxstack;
200 /**************************************************************************/
201 /* TLB and TID handling */
202 /**************************************************************************/
204 /* Translation ID busy table */
205 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
208 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
209 * core revisions and should be read from h/w registers during early config.
211 uint32_t tlb0_entries;
213 uint32_t tlb0_entries_per_way;
214 uint32_t tlb1_entries;
216 #define TLB0_ENTRIES (tlb0_entries)
217 #define TLB0_WAYS (tlb0_ways)
218 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
220 #define TLB1_ENTRIES (tlb1_entries)
222 static tlbtid_t tid_alloc(struct pmap *);
226 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
228 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
232 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
233 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
234 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
235 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
237 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
239 static vm_size_t tsize2size(unsigned int);
240 static unsigned int size2tsize(vm_size_t);
241 static unsigned long ilog2(unsigned long);
243 static void set_mas4_defaults(void);
245 static inline void tlb0_flush_entry(vm_offset_t);
246 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
248 /**************************************************************************/
249 /* Page table management */
250 /**************************************************************************/
252 static struct rwlock_padalign pvh_global_lock;
254 /* Data for the pv entry allocation mechanism */
255 static uma_zone_t pvzone;
256 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
258 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
260 #ifndef PMAP_SHPGPERPROC
261 #define PMAP_SHPGPERPROC 200
264 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
265 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
266 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
267 static pte_t *pte_find(pmap_t, vm_offset_t);
268 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
270 static pv_entry_t pv_alloc(void);
271 static void pv_free(pv_entry_t);
272 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
273 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
275 static void booke_pmap_init_qpages(void);
277 static inline void tlb_miss_lock(void);
278 static inline void tlb_miss_unlock(void);
281 extern tlb_entry_t __boot_tlb1[];
282 void pmap_bootstrap_ap(volatile uint32_t *);
286 * Kernel MMU interface
288 static void mmu_booke_clear_modify(vm_page_t);
289 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
290 vm_size_t, vm_offset_t);
291 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
292 static void mmu_booke_copy_pages(vm_page_t *,
293 vm_offset_t, vm_page_t *, vm_offset_t, int);
294 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
295 vm_prot_t, u_int flags, int8_t psind);
296 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
297 vm_page_t, vm_prot_t);
298 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
300 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
301 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
303 static void mmu_booke_init(void);
304 static boolean_t mmu_booke_is_modified(vm_page_t);
305 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
306 static boolean_t mmu_booke_is_referenced(vm_page_t);
307 static int mmu_booke_ts_referenced(vm_page_t);
308 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
310 static int mmu_booke_mincore(pmap_t, vm_offset_t,
312 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
313 vm_object_t, vm_pindex_t, vm_size_t);
314 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t);
315 static void mmu_booke_page_init(vm_page_t);
316 static int mmu_booke_page_wired_mappings(vm_page_t);
317 static int mmu_booke_pinit(pmap_t);
318 static void mmu_booke_pinit0(pmap_t);
319 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
321 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int);
322 static void mmu_booke_qremove(vm_offset_t, int);
323 static void mmu_booke_release(pmap_t);
324 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
325 static void mmu_booke_remove_all(vm_page_t);
326 static void mmu_booke_remove_write(vm_page_t);
327 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
328 static void mmu_booke_zero_page(vm_page_t);
329 static void mmu_booke_zero_page_area(vm_page_t, int, int);
330 static void mmu_booke_activate(struct thread *);
331 static void mmu_booke_deactivate(struct thread *);
332 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
333 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
334 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
335 static void mmu_booke_unmapdev(vm_offset_t, vm_size_t);
336 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
337 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
338 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
339 static void mmu_booke_kremove(vm_offset_t);
340 static boolean_t mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
341 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
343 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
345 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
347 static void mmu_booke_scan_init(void);
348 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m);
349 static void mmu_booke_quick_remove_page(vm_offset_t addr);
350 static int mmu_booke_change_attr(vm_offset_t addr,
351 vm_size_t sz, vm_memattr_t mode);
352 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
353 int *is_user, vm_offset_t *decoded_addr);
354 static void mmu_booke_page_array_startup(long);
355 static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
358 static struct pmap_funcs mmu_booke_methods = {
359 /* pmap dispatcher interface */
360 .clear_modify = mmu_booke_clear_modify,
361 .copy = mmu_booke_copy,
362 .copy_page = mmu_booke_copy_page,
363 .copy_pages = mmu_booke_copy_pages,
364 .enter = mmu_booke_enter,
365 .enter_object = mmu_booke_enter_object,
366 .enter_quick = mmu_booke_enter_quick,
367 .extract = mmu_booke_extract,
368 .extract_and_hold = mmu_booke_extract_and_hold,
369 .init = mmu_booke_init,
370 .is_modified = mmu_booke_is_modified,
371 .is_prefaultable = mmu_booke_is_prefaultable,
372 .is_referenced = mmu_booke_is_referenced,
373 .ts_referenced = mmu_booke_ts_referenced,
374 .map = mmu_booke_map,
375 .mincore = mmu_booke_mincore,
376 .object_init_pt = mmu_booke_object_init_pt,
377 .page_exists_quick = mmu_booke_page_exists_quick,
378 .page_init = mmu_booke_page_init,
379 .page_wired_mappings = mmu_booke_page_wired_mappings,
380 .pinit = mmu_booke_pinit,
381 .pinit0 = mmu_booke_pinit0,
382 .protect = mmu_booke_protect,
383 .qenter = mmu_booke_qenter,
384 .qremove = mmu_booke_qremove,
385 .release = mmu_booke_release,
386 .remove = mmu_booke_remove,
387 .remove_all = mmu_booke_remove_all,
388 .remove_write = mmu_booke_remove_write,
389 .sync_icache = mmu_booke_sync_icache,
390 .unwire = mmu_booke_unwire,
391 .zero_page = mmu_booke_zero_page,
392 .zero_page_area = mmu_booke_zero_page_area,
393 .activate = mmu_booke_activate,
394 .deactivate = mmu_booke_deactivate,
395 .quick_enter_page = mmu_booke_quick_enter_page,
396 .quick_remove_page = mmu_booke_quick_remove_page,
397 .page_array_startup = mmu_booke_page_array_startup,
398 .page_is_mapped = mmu_booke_page_is_mapped,
400 /* Internal interfaces */
401 .bootstrap = mmu_booke_bootstrap,
402 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
403 .mapdev = mmu_booke_mapdev,
404 .mapdev_attr = mmu_booke_mapdev_attr,
405 .kenter = mmu_booke_kenter,
406 .kenter_attr = mmu_booke_kenter_attr,
407 .kextract = mmu_booke_kextract,
408 .kremove = mmu_booke_kremove,
409 .unmapdev = mmu_booke_unmapdev,
410 .change_attr = mmu_booke_change_attr,
411 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
413 /* dumpsys() support */
414 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
415 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
416 .dumpsys_pa_init = mmu_booke_scan_init,
419 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
427 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
429 static __inline uint32_t
430 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
435 if (ma != VM_MEMATTR_DEFAULT) {
437 case VM_MEMATTR_UNCACHEABLE:
438 return (MAS2_I | MAS2_G);
439 case VM_MEMATTR_WRITE_COMBINING:
440 case VM_MEMATTR_WRITE_BACK:
441 case VM_MEMATTR_PREFETCHABLE:
443 case VM_MEMATTR_WRITE_THROUGH:
444 return (MAS2_W | MAS2_M);
445 case VM_MEMATTR_CACHEABLE:
451 * Assume the page is cache inhibited and access is guarded unless
452 * it's in our available memory array.
454 attrib = _TLB_ENTRY_IO;
455 for (i = 0; i < physmem_regions_sz; i++) {
456 if ((pa >= physmem_regions[i].mr_start) &&
457 (pa < (physmem_regions[i].mr_start +
458 physmem_regions[i].mr_size))) {
459 attrib = _TLB_ENTRY_MEM;
476 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
479 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
480 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
482 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
483 ("tlb_miss_lock: tried to lock self"));
485 tlb_lock(pc->pc_booke.tlb_lock);
487 CTR1(KTR_PMAP, "%s: locked", __func__);
494 tlb_miss_unlock(void)
502 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
504 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
505 __func__, pc->pc_cpuid);
507 tlb_unlock(pc->pc_booke.tlb_lock);
509 CTR1(KTR_PMAP, "%s: unlocked", __func__);
515 /* Return number of entries in TLB0. */
517 tlb0_get_tlbconf(void)
521 tlb0_cfg = mfspr(SPR_TLB0CFG);
522 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
523 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
524 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
527 /* Return number of entries in TLB1. */
529 tlb1_get_tlbconf(void)
533 tlb1_cfg = mfspr(SPR_TLB1CFG);
534 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
537 /**************************************************************************/
538 /* Page table related */
539 /**************************************************************************/
541 /* Allocate pv_entry structure. */
548 if (pv_entry_count > pv_entry_high_water)
549 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
550 pv = uma_zalloc(pvzone, M_NOWAIT);
555 /* Free pv_entry structure. */
557 pv_free(pv_entry_t pve)
561 uma_zfree(pvzone, pve);
565 /* Allocate and initialize pv_entry structure. */
567 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
571 //int su = (pmap == kernel_pmap);
572 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
573 // (u_int32_t)pmap, va, (u_int32_t)m);
577 panic("pv_insert: no pv entries!");
583 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
584 rw_assert(&pvh_global_lock, RA_WLOCKED);
586 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
588 //debugf("pv_insert: e\n");
591 /* Destroy pv entry. */
593 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
597 //int su = (pmap == kernel_pmap);
598 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
600 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
601 rw_assert(&pvh_global_lock, RA_WLOCKED);
604 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
605 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
606 /* remove from pv_list */
607 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
608 if (TAILQ_EMPTY(&m->md.pv_list))
609 vm_page_aflag_clear(m, PGA_WRITEABLE);
611 /* free pv entry struct */
617 //debugf("pv_remove: e\n");
620 /**************************************************************************/
622 /**************************************************************************/
625 * This is called during booke_init, before the system is really initialized.
628 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
630 vm_paddr_t phys_kernelend;
631 struct mem_region *mp, *mp1;
634 vm_paddr_t physsz, hwphyssz;
635 u_int phys_avail_count;
636 vm_size_t kstack0_sz;
637 vm_paddr_t kstack0_phys;
641 debugf("mmu_booke_bootstrap: entered\n");
643 /* Set interesting system properties */
649 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
653 /* Initialize invalidation mutex */
654 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
656 /* Read TLB0 size and associativity. */
660 * Align kernel start and end address (kernel image).
661 * Note that kernel end does not necessarily relate to kernsize.
662 * kernsize is the size of the kernel that is actually mapped.
664 data_start = round_page(kernelend);
665 data_end = data_start;
667 /* Allocate the dynamic per-cpu area. */
668 dpcpu = (void *)data_end;
669 data_end += DPCPU_SIZE;
671 /* Allocate space for the message buffer. */
672 msgbufp = (struct msgbuf *)data_end;
673 data_end += msgbufsize;
674 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
675 (uintptr_t)msgbufp, data_end);
677 data_end = round_page(data_end);
678 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
680 /* Retrieve phys/avail mem regions */
681 mem_regions(&physmem_regions, &physmem_regions_sz,
682 &availmem_regions, &availmem_regions_sz);
684 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
685 panic("mmu_booke_bootstrap: phys_avail too small");
687 data_end = round_page(data_end);
688 vm_page_array = (vm_page_t)data_end;
690 * Get a rough idea (upper bound) on the size of the page array. The
691 * vm_page_array will not handle any more pages than we have in the
692 * avail_regions array, and most likely much less.
695 for (mp = availmem_regions; mp->mr_size; mp++) {
698 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
699 data_end += round_page(sz * sizeof(struct vm_page));
701 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
702 data_end = roundup2(data_end, 1 << 20);
704 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
705 debugf(" kernstart: %#zx\n", kernstart);
706 debugf(" kernsize: %#zx\n", kernsize);
708 if (data_end - kernstart > kernsize) {
709 kernsize += tlb1_mapin_region(kernstart + kernsize,
710 kernload + kernsize, (data_end - kernstart) - kernsize,
713 data_end = kernstart + kernsize;
714 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
717 * Clear the structures - note we can only do it safely after the
718 * possible additional TLB1 translations are in place (above) so that
719 * all range up to the currently calculated 'data_end' is covered.
721 bzero((void *)data_start, data_end - data_start);
722 dpcpu_init(dpcpu, 0);
724 /*******************************************************/
725 /* Set the start and end of kva. */
726 /*******************************************************/
727 virtual_avail = round_page(data_end);
728 virtual_end = VM_MAX_KERNEL_ADDRESS;
730 #ifndef __powerpc64__
731 /* Allocate KVA space for page zero/copy operations. */
732 zero_page_va = virtual_avail;
733 virtual_avail += PAGE_SIZE;
734 copy_page_src_va = virtual_avail;
735 virtual_avail += PAGE_SIZE;
736 copy_page_dst_va = virtual_avail;
737 virtual_avail += PAGE_SIZE;
738 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
739 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
740 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
742 /* Initialize page zero/copy mutexes. */
743 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
744 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
746 /* Allocate KVA space for ptbl bufs. */
747 ptbl_buf_pool_vabase = virtual_avail;
748 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
749 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
750 ptbl_buf_pool_vabase, virtual_avail);
753 /* Calculate corresponding physical addresses for the kernel region. */
754 phys_kernelend = kernload + kernsize;
755 debugf("kernel image and allocated data:\n");
756 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
757 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
758 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
761 * Remove kernel physical address range from avail regions list. Page
762 * align all regions. Non-page aligned memory isn't very interesting
763 * to us. Also, sort the entries for ascending addresses.
767 cnt = availmem_regions_sz;
768 debugf("processing avail regions:\n");
769 for (mp = availmem_regions; mp->mr_size; mp++) {
771 e = mp->mr_start + mp->mr_size;
772 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
773 /* Check whether this region holds all of the kernel. */
774 if (s < kernload && e > phys_kernelend) {
775 availmem_regions[cnt].mr_start = phys_kernelend;
776 availmem_regions[cnt++].mr_size = e - phys_kernelend;
779 /* Look whether this regions starts within the kernel. */
780 if (s >= kernload && s < phys_kernelend) {
781 if (e <= phys_kernelend)
785 /* Now look whether this region ends within the kernel. */
786 if (e > kernload && e <= phys_kernelend) {
791 /* Now page align the start and size of the region. */
797 debugf("%09jx-%09jx = %jx\n",
798 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
800 /* Check whether some memory is left here. */
804 (cnt - (mp - availmem_regions)) * sizeof(*mp));
810 /* Do an insertion sort. */
811 for (mp1 = availmem_regions; mp1 < mp; mp1++)
812 if (s < mp1->mr_start)
815 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
823 availmem_regions_sz = cnt;
825 /*******************************************************/
826 /* Steal physical memory for kernel stack from the end */
827 /* of the first avail region */
828 /*******************************************************/
829 kstack0_sz = kstack_pages * PAGE_SIZE;
830 kstack0_phys = availmem_regions[0].mr_start +
831 availmem_regions[0].mr_size;
832 kstack0_phys -= kstack0_sz;
833 availmem_regions[0].mr_size -= kstack0_sz;
835 /*******************************************************/
836 /* Fill in phys_avail table, based on availmem_regions */
837 /*******************************************************/
838 phys_avail_count = 0;
841 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
843 debugf("fill in phys_avail:\n");
844 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
846 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
847 (uintmax_t)availmem_regions[i].mr_start,
848 (uintmax_t)availmem_regions[i].mr_start +
849 availmem_regions[i].mr_size,
850 (uintmax_t)availmem_regions[i].mr_size);
853 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
854 debugf(" hw.physmem adjust\n");
855 if (physsz < hwphyssz) {
856 phys_avail[j] = availmem_regions[i].mr_start;
858 availmem_regions[i].mr_start +
862 dump_avail[j] = phys_avail[j];
863 dump_avail[j + 1] = phys_avail[j + 1];
868 phys_avail[j] = availmem_regions[i].mr_start;
869 phys_avail[j + 1] = availmem_regions[i].mr_start +
870 availmem_regions[i].mr_size;
872 physsz += availmem_regions[i].mr_size;
873 dump_avail[j] = phys_avail[j];
874 dump_avail[j + 1] = phys_avail[j + 1];
876 physmem = btoc(physsz);
878 /* Calculate the last available physical address. */
879 for (i = 0; phys_avail[i + 2] != 0; i += 2)
881 Maxmem = powerpc_btop(phys_avail[i + 1]);
883 debugf("Maxmem = 0x%08lx\n", Maxmem);
884 debugf("phys_avail_count = %d\n", phys_avail_count);
885 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
886 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
890 * Map the physical memory contiguously in TLB1.
891 * Round so it fits into a single mapping.
893 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
894 phys_avail[i + 1], _TLB_ENTRY_MEM);
897 /*******************************************************/
898 /* Initialize (statically allocated) kernel pmap. */
899 /*******************************************************/
900 PMAP_LOCK_INIT(kernel_pmap);
902 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
903 kernel_pte_alloc(virtual_avail, kernstart);
904 for (i = 0; i < MAXCPU; i++) {
905 kernel_pmap->pm_tid[i] = TID_KERNEL;
907 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
908 tidbusy[i][TID_KERNEL] = kernel_pmap;
911 /* Mark kernel_pmap active on all CPUs */
912 CPU_FILL(&kernel_pmap->pm_active);
915 * Initialize the global pv list lock.
917 rw_init(&pvh_global_lock, "pmap pv global");
919 /*******************************************************/
921 /*******************************************************/
923 /* Enter kstack0 into kernel map, provide guard page */
924 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
925 thread0.td_kstack = kstack0;
926 thread0.td_kstack_pages = kstack_pages;
928 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
929 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
930 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
931 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
932 kstack0, kstack0 + kstack0_sz);
934 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
935 for (i = 0; i < kstack_pages; i++) {
936 mmu_booke_kenter(kstack0, kstack0_phys);
937 kstack0 += PAGE_SIZE;
938 kstack0_phys += PAGE_SIZE;
941 pmap_bootstrapped = 1;
943 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
944 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
946 debugf("mmu_booke_bootstrap: exit\n");
956 /* Prepare TLB1 image for AP processors */
958 for (i = 0; i < TLB1_ENTRIES; i++) {
959 tlb1_read_entry(&tmp, i);
961 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
962 memcpy(e++, &tmp, sizeof(tmp));
967 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
972 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
973 * have the snapshot of its contents in the s/w __boot_tlb1[] table
974 * created by tlb1_ap_prep(), so use these values directly to
975 * (re)program AP's TLB1 hardware.
977 * Start at index 1 because index 0 has the kernel map.
979 for (i = 1; i < TLB1_ENTRIES; i++) {
980 if (__boot_tlb1[i].mas1 & MAS1_VALID)
981 tlb1_write_entry(&__boot_tlb1[i], i);
989 booke_pmap_init_qpages(void)
996 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
997 if (pc->pc_qmap_addr == 0)
998 panic("pmap_init_qpages: unable to allocate KVA");
1002 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1005 * Get the physical page address for the given pmap/virtual address.
1008 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1013 pa = pte_vatopa(pmap, va);
1020 * Extract the physical page address associated with the given
1021 * kernel virtual address.
1024 mmu_booke_kextract(vm_offset_t va)
1030 #ifdef __powerpc64__
1031 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1032 return (DMAP_TO_PHYS(va));
1035 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1036 p = pte_vatopa(kernel_pmap, va);
1039 /* Check TLB1 mappings */
1040 for (i = 0; i < TLB1_ENTRIES; i++) {
1041 tlb1_read_entry(&e, i);
1042 if (!(e.mas1 & MAS1_VALID))
1044 if (va >= e.virt && va < e.virt + e.size)
1045 return (e.phys + (va - e.virt));
1053 * Initialize the pmap module.
1054 * Called by vm_init, to initialize any structures that the pmap
1055 * system needs to map virtual memory.
1060 int shpgperproc = PMAP_SHPGPERPROC;
1063 * Initialize the address space (zone) for the pv entries. Set a
1064 * high water mark so that the system can recover from excessive
1065 * numbers of pv entries.
1067 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1068 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1070 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1071 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1073 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1074 pv_entry_high_water = 9 * (pv_entry_max / 10);
1076 uma_zone_reserve_kva(pvzone, pv_entry_max);
1078 /* Pre-fill pvzone with initial number of pv entries. */
1079 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1081 /* Create a UMA zone for page table roots. */
1082 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1083 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1085 /* Initialize ptbl allocation. */
1090 * Map a list of wired pages into kernel virtual address space. This is
1091 * intended for temporary mappings which do not need page modification or
1092 * references recorded. Existing mappings in the region are overwritten.
1095 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count)
1100 while (count-- > 0) {
1101 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1108 * Remove page mappings from kernel virtual address space. Intended for
1109 * temporary mappings entered by mmu_booke_qenter.
1112 mmu_booke_qremove(vm_offset_t sva, int count)
1117 while (count-- > 0) {
1118 mmu_booke_kremove(va);
1124 * Map a wired page into kernel virtual address space.
1127 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1130 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1134 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1139 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1140 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1142 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1143 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1144 flags |= PTE_PS_4KB;
1146 pte = pte_find(kernel_pmap, va);
1147 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1149 mtx_lock_spin(&tlbivax_mutex);
1152 if (PTE_ISVALID(pte)) {
1154 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1156 /* Flush entry from TLB0 */
1157 tlb0_flush_entry(va);
1160 *pte = PTE_RPN_FROM_PA(pa) | flags;
1162 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1163 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1164 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1166 /* Flush the real memory from the instruction cache. */
1167 if ((flags & (PTE_I | PTE_G)) == 0)
1168 __syncicache((void *)va, PAGE_SIZE);
1171 mtx_unlock_spin(&tlbivax_mutex);
1175 * Remove a page from kernel page table.
1178 mmu_booke_kremove(vm_offset_t va)
1182 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1184 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1185 (va <= VM_MAX_KERNEL_ADDRESS)),
1186 ("mmu_booke_kremove: invalid va"));
1188 pte = pte_find(kernel_pmap, va);
1190 if (!PTE_ISVALID(pte)) {
1192 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1197 mtx_lock_spin(&tlbivax_mutex);
1200 /* Invalidate entry in TLB0, update PTE. */
1201 tlb0_flush_entry(va);
1205 mtx_unlock_spin(&tlbivax_mutex);
1209 * Figure out where a given kernel pointer (usually in a fault) points
1210 * to from the VM's perspective, potentially remapping into userland's
1214 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1215 vm_offset_t *decoded_addr)
1218 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1223 *decoded_addr = addr;
1228 mmu_booke_page_is_mapped(vm_page_t m)
1231 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1235 * Initialize pmap associated with process 0.
1238 mmu_booke_pinit0(pmap_t pmap)
1241 PMAP_LOCK_INIT(pmap);
1242 mmu_booke_pinit(pmap);
1243 PCPU_SET(curpmap, pmap);
1247 * Insert the given physical page at the specified virtual address in the
1248 * target physical map with the protection requested. If specified the page
1249 * will be wired down.
1252 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1253 vm_prot_t prot, u_int flags, int8_t psind)
1257 rw_wlock(&pvh_global_lock);
1259 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1261 rw_wunlock(&pvh_global_lock);
1266 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1267 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1272 int error, su, sync;
1274 pa = VM_PAGE_TO_PHYS(m);
1275 su = (pmap == kernel_pmap);
1278 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1279 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1280 // (u_int32_t)pmap, su, pmap->pm_tid,
1281 // (u_int32_t)m, va, pa, prot, flags);
1284 KASSERT(((va >= virtual_avail) &&
1285 (va <= VM_MAX_KERNEL_ADDRESS)),
1286 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1288 KASSERT((va <= VM_MAXUSER_ADDRESS),
1289 ("mmu_booke_enter_locked: user pmap, non user va"));
1291 if ((m->oflags & VPO_UNMANAGED) == 0) {
1292 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1293 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1295 VM_OBJECT_ASSERT_LOCKED(m->object);
1298 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1301 * If there is an existing mapping, and the physical address has not
1302 * changed, must be protection or wiring change.
1304 if (((pte = pte_find(pmap, va)) != NULL) &&
1305 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1308 * Before actually updating pte->flags we calculate and
1309 * prepare its new value in a helper var.
1312 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1314 /* Wiring change, just update stats. */
1315 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1316 if (!PTE_ISWIRED(pte)) {
1318 pmap->pm_stats.wired_count++;
1321 if (PTE_ISWIRED(pte)) {
1322 flags &= ~PTE_WIRED;
1323 pmap->pm_stats.wired_count--;
1327 if (prot & VM_PROT_WRITE) {
1328 /* Add write permissions. */
1333 if ((flags & PTE_MANAGED) != 0)
1334 vm_page_aflag_set(m, PGA_WRITEABLE);
1336 /* Handle modified pages, sense modify status. */
1339 * The PTE_MODIFIED flag could be set by underlying
1340 * TLB misses since we last read it (above), possibly
1341 * other CPUs could update it so we check in the PTE
1342 * directly rather than rely on that saved local flags
1345 if (PTE_ISMODIFIED(pte))
1349 if (prot & VM_PROT_EXECUTE) {
1355 * Check existing flags for execute permissions: if we
1356 * are turning execute permissions on, icache should
1359 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1363 flags &= ~PTE_REFERENCED;
1366 * The new flags value is all calculated -- only now actually
1369 mtx_lock_spin(&tlbivax_mutex);
1372 tlb0_flush_entry(va);
1373 *pte &= ~PTE_FLAGS_MASK;
1377 mtx_unlock_spin(&tlbivax_mutex);
1381 * If there is an existing mapping, but it's for a different
1382 * physical address, pte_enter() will delete the old mapping.
1384 //if ((pte != NULL) && PTE_ISVALID(pte))
1385 // debugf("mmu_booke_enter_locked: replace\n");
1387 // debugf("mmu_booke_enter_locked: new\n");
1389 /* Now set up the flags and install the new mapping. */
1390 flags = (PTE_SR | PTE_VALID);
1396 if (prot & VM_PROT_WRITE) {
1401 if ((m->oflags & VPO_UNMANAGED) == 0)
1402 vm_page_aflag_set(m, PGA_WRITEABLE);
1405 if (prot & VM_PROT_EXECUTE) {
1411 /* If its wired update stats. */
1412 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1415 error = pte_enter(pmap, m, va, flags,
1416 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1418 return (KERN_RESOURCE_SHORTAGE);
1420 if ((flags & PMAP_ENTER_WIRED) != 0)
1421 pmap->pm_stats.wired_count++;
1423 /* Flush the real memory from the instruction cache. */
1424 if (prot & VM_PROT_EXECUTE)
1428 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1429 __syncicache((void *)va, PAGE_SIZE);
1433 return (KERN_SUCCESS);
1437 * Maps a sequence of resident pages belonging to the same object.
1438 * The sequence begins with the given page m_start. This page is
1439 * mapped at the given virtual address start. Each subsequent page is
1440 * mapped at a virtual address that is offset from start by the same
1441 * amount as the page is offset from m_start within the object. The
1442 * last page in the sequence is the page with the largest offset from
1443 * m_start that can be mapped at a virtual address less than the given
1444 * virtual address end. Not every virtual page between start and end
1445 * is mapped; only those for which a resident page exists with the
1446 * corresponding offset from m_start are mapped.
1449 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1450 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1453 vm_pindex_t diff, psize;
1455 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1457 psize = atop(end - start);
1459 rw_wlock(&pvh_global_lock);
1461 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1462 mmu_booke_enter_locked(pmap, start + ptoa(diff), m,
1463 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1464 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1465 m = TAILQ_NEXT(m, listq);
1468 rw_wunlock(&pvh_global_lock);
1472 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1476 rw_wlock(&pvh_global_lock);
1478 mmu_booke_enter_locked(pmap, va, m,
1479 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1480 PMAP_ENTER_QUICK_LOCKED, 0);
1482 rw_wunlock(&pvh_global_lock);
1486 * Remove the given range of addresses from the specified map.
1488 * It is assumed that the start and end are properly rounded to the page size.
1491 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1496 int su = (pmap == kernel_pmap);
1498 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1499 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1502 KASSERT(((va >= virtual_avail) &&
1503 (va <= VM_MAX_KERNEL_ADDRESS)),
1504 ("mmu_booke_remove: kernel pmap, non kernel va"));
1506 KASSERT((va <= VM_MAXUSER_ADDRESS),
1507 ("mmu_booke_remove: user pmap, non user va"));
1510 if (PMAP_REMOVE_DONE(pmap)) {
1511 //debugf("mmu_booke_remove: e (empty)\n");
1515 hold_flag = PTBL_HOLD_FLAG(pmap);
1516 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1518 rw_wlock(&pvh_global_lock);
1520 for (; va < endva; va += PAGE_SIZE) {
1521 pte = pte_find_next(pmap, &va);
1522 if ((pte == NULL) || !PTE_ISVALID(pte))
1526 pte_remove(pmap, va, hold_flag);
1529 rw_wunlock(&pvh_global_lock);
1531 //debugf("mmu_booke_remove: e\n");
1535 * Remove physical page from all pmaps in which it resides.
1538 mmu_booke_remove_all(vm_page_t m)
1543 rw_wlock(&pvh_global_lock);
1544 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1545 PMAP_LOCK(pv->pv_pmap);
1546 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1547 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1548 PMAP_UNLOCK(pv->pv_pmap);
1550 vm_page_aflag_clear(m, PGA_WRITEABLE);
1551 rw_wunlock(&pvh_global_lock);
1555 * Map a range of physical addresses into kernel virtual address space.
1558 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1559 vm_paddr_t pa_end, int prot)
1561 vm_offset_t sva = *virt;
1562 vm_offset_t va = sva;
1564 #ifdef __powerpc64__
1565 /* XXX: Handle memory not starting at 0x0. */
1566 if (pa_end < ctob(Maxmem))
1567 return (PHYS_TO_DMAP(pa_start));
1570 while (pa_start < pa_end) {
1571 mmu_booke_kenter(va, pa_start);
1573 pa_start += PAGE_SIZE;
1581 * The pmap must be activated before it's address space can be accessed in any
1585 mmu_booke_activate(struct thread *td)
1590 pmap = &td->td_proc->p_vmspace->vm_pmap;
1592 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1593 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1595 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1599 cpuid = PCPU_GET(cpuid);
1600 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1601 PCPU_SET(curpmap, pmap);
1603 if (pmap->pm_tid[cpuid] == TID_NONE)
1606 /* Load PID0 register with pmap tid value. */
1607 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1608 __asm __volatile("isync");
1610 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1614 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1615 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1619 * Deactivate the specified process's address space.
1622 mmu_booke_deactivate(struct thread *td)
1626 pmap = &td->td_proc->p_vmspace->vm_pmap;
1628 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1629 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1631 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1633 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1634 PCPU_SET(curpmap, NULL);
1638 * Copy the range specified by src_addr/len
1639 * from the source map to the range dst_addr/len
1640 * in the destination map.
1642 * This routine is only advisory and need not do anything.
1645 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1646 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1652 * Set the physical protection on the specified range of this map as requested.
1655 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1662 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1663 mmu_booke_remove(pmap, sva, eva);
1667 if (prot & VM_PROT_WRITE)
1671 for (va = sva; va < eva; va += PAGE_SIZE) {
1672 if ((pte = pte_find(pmap, va)) != NULL) {
1673 if (PTE_ISVALID(pte)) {
1674 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1676 mtx_lock_spin(&tlbivax_mutex);
1679 /* Handle modified pages. */
1680 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1683 tlb0_flush_entry(va);
1684 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1687 mtx_unlock_spin(&tlbivax_mutex);
1695 * Clear the write and modified bits in each of the given page's mappings.
1698 mmu_booke_remove_write(vm_page_t m)
1703 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1704 ("mmu_booke_remove_write: page %p is not managed", m));
1705 vm_page_assert_busied(m);
1707 if (!pmap_page_is_write_mapped(m))
1709 rw_wlock(&pvh_global_lock);
1710 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1711 PMAP_LOCK(pv->pv_pmap);
1712 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1713 if (PTE_ISVALID(pte)) {
1714 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1716 mtx_lock_spin(&tlbivax_mutex);
1719 /* Handle modified pages. */
1720 if (PTE_ISMODIFIED(pte))
1723 /* Flush mapping from TLB0. */
1724 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1727 mtx_unlock_spin(&tlbivax_mutex);
1730 PMAP_UNLOCK(pv->pv_pmap);
1732 vm_page_aflag_clear(m, PGA_WRITEABLE);
1733 rw_wunlock(&pvh_global_lock);
1737 * Atomically extract and hold the physical page with the given
1738 * pmap and virtual address pair if that mapping permits the given
1742 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1751 pte = pte_find(pmap, va);
1752 if ((pte != NULL) && PTE_ISVALID(pte)) {
1753 if (pmap == kernel_pmap)
1758 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1759 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1760 if (!vm_page_wire_mapped(m))
1769 * Initialize a vm_page's machine-dependent fields.
1772 mmu_booke_page_init(vm_page_t m)
1775 m->md.pv_tracked = 0;
1776 TAILQ_INIT(&m->md.pv_list);
1780 * Return whether or not the specified physical page was modified
1781 * in any of physical maps.
1784 mmu_booke_is_modified(vm_page_t m)
1790 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1791 ("mmu_booke_is_modified: page %p is not managed", m));
1795 * If the page is not busied then this check is racy.
1797 if (!pmap_page_is_write_mapped(m))
1800 rw_wlock(&pvh_global_lock);
1801 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1802 PMAP_LOCK(pv->pv_pmap);
1803 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1805 if (PTE_ISMODIFIED(pte))
1808 PMAP_UNLOCK(pv->pv_pmap);
1812 rw_wunlock(&pvh_global_lock);
1817 * Return whether or not the specified virtual address is eligible
1821 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1828 * Return whether or not the specified physical page was referenced
1829 * in any physical maps.
1832 mmu_booke_is_referenced(vm_page_t m)
1838 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1839 ("mmu_booke_is_referenced: page %p is not managed", m));
1841 rw_wlock(&pvh_global_lock);
1842 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1843 PMAP_LOCK(pv->pv_pmap);
1844 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1846 if (PTE_ISREFERENCED(pte))
1849 PMAP_UNLOCK(pv->pv_pmap);
1853 rw_wunlock(&pvh_global_lock);
1858 * Clear the modify bits on the specified physical page.
1861 mmu_booke_clear_modify(vm_page_t m)
1866 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1867 ("mmu_booke_clear_modify: page %p is not managed", m));
1868 vm_page_assert_busied(m);
1870 if (!pmap_page_is_write_mapped(m))
1873 rw_wlock(&pvh_global_lock);
1874 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1875 PMAP_LOCK(pv->pv_pmap);
1876 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1878 mtx_lock_spin(&tlbivax_mutex);
1881 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1882 tlb0_flush_entry(pv->pv_va);
1883 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1888 mtx_unlock_spin(&tlbivax_mutex);
1890 PMAP_UNLOCK(pv->pv_pmap);
1892 rw_wunlock(&pvh_global_lock);
1896 * Return a count of reference bits for a page, clearing those bits.
1897 * It is not necessary for every reference bit to be cleared, but it
1898 * is necessary that 0 only be returned when there are truly no
1899 * reference bits set.
1901 * As an optimization, update the page's dirty field if a modified bit is
1902 * found while counting reference bits. This opportunistic update can be
1903 * performed at low cost and can eliminate the need for some future calls
1904 * to pmap_is_modified(). However, since this function stops after
1905 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1906 * dirty pages. Those dirty pages will only be detected by a future call
1907 * to pmap_is_modified().
1910 mmu_booke_ts_referenced(vm_page_t m)
1916 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1917 ("mmu_booke_ts_referenced: page %p is not managed", m));
1919 rw_wlock(&pvh_global_lock);
1920 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1921 PMAP_LOCK(pv->pv_pmap);
1922 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1924 if (PTE_ISMODIFIED(pte))
1926 if (PTE_ISREFERENCED(pte)) {
1927 mtx_lock_spin(&tlbivax_mutex);
1930 tlb0_flush_entry(pv->pv_va);
1931 *pte &= ~PTE_REFERENCED;
1934 mtx_unlock_spin(&tlbivax_mutex);
1936 if (++count >= PMAP_TS_REFERENCED_MAX) {
1937 PMAP_UNLOCK(pv->pv_pmap);
1942 PMAP_UNLOCK(pv->pv_pmap);
1944 rw_wunlock(&pvh_global_lock);
1949 * Clear the wired attribute from the mappings for the specified range of
1950 * addresses in the given pmap. Every valid mapping within that range must
1951 * have the wired attribute set. In contrast, invalid mappings cannot have
1952 * the wired attribute set, so they are ignored.
1954 * The wired attribute of the page table entry is not a hardware feature, so
1955 * there is no need to invalidate any TLB entries.
1958 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1964 for (va = sva; va < eva; va += PAGE_SIZE) {
1965 if ((pte = pte_find(pmap, va)) != NULL &&
1967 if (!PTE_ISWIRED(pte))
1968 panic("mmu_booke_unwire: pte %p isn't wired",
1971 pmap->pm_stats.wired_count--;
1979 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
1980 * page. This count may be changed upwards or downwards in the future; it is
1981 * only necessary that true be returned for a small subset of pmaps for proper
1985 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
1991 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1992 ("mmu_booke_page_exists_quick: page %p is not managed", m));
1995 rw_wlock(&pvh_global_lock);
1996 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1997 if (pv->pv_pmap == pmap) {
2004 rw_wunlock(&pvh_global_lock);
2009 * Return the number of managed mappings to the given physical page that are
2013 mmu_booke_page_wired_mappings(vm_page_t m)
2019 if ((m->oflags & VPO_UNMANAGED) != 0)
2021 rw_wlock(&pvh_global_lock);
2022 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2023 PMAP_LOCK(pv->pv_pmap);
2024 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2025 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2027 PMAP_UNLOCK(pv->pv_pmap);
2029 rw_wunlock(&pvh_global_lock);
2034 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2040 * This currently does not work for entries that
2041 * overlap TLB1 entries.
2043 for (i = 0; i < TLB1_ENTRIES; i ++) {
2044 if (tlb1_iomapped(i, pa, size, &va) == 0)
2052 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2058 /* Minidumps are based on virtual memory addresses. */
2060 *va = (void *)(vm_offset_t)pa;
2064 /* Raw physical memory dumps don't have a virtual address. */
2065 /* We always map a 256MB page at 256M. */
2066 gran = 256 * 1024 * 1024;
2067 ppa = rounddown2(pa, gran);
2070 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2072 if (sz > (gran - ofs))
2073 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2078 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2086 /* Minidumps are based on virtual memory addresses. */
2087 /* Nothing to do... */
2091 for (i = 0; i < TLB1_ENTRIES; i++) {
2092 tlb1_read_entry(&e, i);
2093 if (!(e.mas1 & MAS1_VALID))
2097 /* Raw physical memory dumps don't have a virtual address. */
2102 tlb1_write_entry(&e, i);
2104 gran = 256 * 1024 * 1024;
2105 ppa = rounddown2(pa, gran);
2107 if (sz > (gran - ofs)) {
2112 tlb1_write_entry(&e, i);
2116 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2119 mmu_booke_scan_init()
2126 /* Initialize phys. segments for dumpsys(). */
2127 memset(&dump_map, 0, sizeof(dump_map));
2128 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2129 &availmem_regions_sz);
2130 for (i = 0; i < physmem_regions_sz; i++) {
2131 dump_map[i].pa_start = physmem_regions[i].mr_start;
2132 dump_map[i].pa_size = physmem_regions[i].mr_size;
2137 /* Virtual segments for minidumps: */
2138 memset(&dump_map, 0, sizeof(dump_map));
2140 /* 1st: kernel .data and .bss. */
2141 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2142 dump_map[0].pa_size =
2143 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2145 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2146 dump_map[1].pa_start = data_start;
2147 dump_map[1].pa_size = data_end - data_start;
2149 /* 3rd: kernel VM. */
2150 va = dump_map[1].pa_start + dump_map[1].pa_size;
2151 /* Find start of next chunk (from va). */
2152 while (va < virtual_end) {
2153 /* Don't dump the buffer cache. */
2154 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2155 va = kmi.buffer_eva;
2158 pte = pte_find(kernel_pmap, va);
2159 if (pte != NULL && PTE_ISVALID(pte))
2163 if (va < virtual_end) {
2164 dump_map[2].pa_start = va;
2166 /* Find last page in chunk. */
2167 while (va < virtual_end) {
2168 /* Don't run into the buffer cache. */
2169 if (va == kmi.buffer_sva)
2171 pte = pte_find(kernel_pmap, va);
2172 if (pte == NULL || !PTE_ISVALID(pte))
2176 dump_map[2].pa_size = va - dump_map[2].pa_start;
2181 * Map a set of physical memory pages into the kernel virtual address space.
2182 * Return a pointer to where it is mapped. This routine is intended to be used
2183 * for mapping device memory, NOT real memory.
2186 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2189 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2193 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2197 for (i = 0; i < TLB1_ENTRIES; i++) {
2198 tlb1_read_entry(e, i);
2199 if ((e->mas1 & MAS1_VALID) == 0)
2208 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2212 #ifndef __powerpc64__
2215 uintptr_t va, retva;
2221 * Check if this is premapped in TLB1.
2226 wimge = tlb_calc_wimg(pa, ma);
2227 for (i = 0; i < TLB1_ENTRIES; i++) {
2228 tlb1_read_entry(&e, i);
2229 if (!(e.mas1 & MAS1_VALID))
2231 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2233 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2234 va = e.virt + (pa - e.phys);
2235 tmppa = e.phys + e.size;
2236 sz -= MIN(sz, e.size - (pa - e.phys));
2237 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2238 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2240 sz -= MIN(sz, e.size);
2241 tmppa = e.phys + e.size;
2245 return ((void *)va);
2249 size = roundup(size, PAGE_SIZE);
2251 #ifdef __powerpc64__
2252 KASSERT(pa < VM_MAPDEV_PA_MAX,
2253 ("Unsupported physical address! %lx", pa));
2254 va = VM_MAPDEV_BASE + pa;
2256 #ifdef POW2_MAPPINGS
2258 * Align the mapping to a power of 2 size, taking into account that we
2259 * may need to increase the size multiple times to satisfy the size and
2260 * alignment requirements.
2262 * This works in the general case because it's very rare (near never?)
2263 * to have different access properties (WIMG) within a single
2264 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2265 * can be undefined, and exact mappings will be used instead.
2268 size = roundup2(size, 1 << ilog2(size));
2269 while (rounddown2(va, size) + size < va + sz)
2271 va = rounddown2(va, size);
2272 pa = rounddown2(pa, size);
2276 * The device mapping area is between VM_MAXUSER_ADDRESS and
2277 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2279 #ifdef SPARSE_MAPDEV
2281 * With a sparse mapdev, align to the largest starting region. This
2282 * could feasibly be optimized for a 'best-fit' alignment, but that
2283 * calculation could be very costly.
2284 * Align to the smaller of:
2285 * - first set bit in overlap of (pa & size mask)
2286 * - largest size envelope
2288 * It's possible the device mapping may start at a PA that's not larger
2289 * than the size mask, so we need to offset in to maximize the TLB entry
2290 * range and minimize the number of used TLB entries.
2293 tmpva = tlb1_map_base;
2294 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2295 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2296 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2297 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2299 va = atomic_fetchadd_int(&tlb1_map_base, size);
2303 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2306 return ((void *)retva);
2310 * 'Unmap' a range mapped by mmu_booke_mapdev().
2313 mmu_booke_unmapdev(vm_offset_t va, vm_size_t size)
2315 #ifdef SUPPORTS_SHRINKING_TLB1
2316 vm_offset_t base, offset;
2319 * Unmap only if this is inside kernel virtual space.
2321 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2322 base = trunc_page(va);
2323 offset = va & PAGE_MASK;
2324 size = roundup(offset + size, PAGE_SIZE);
2325 mmu_booke_qremove(base, atop(size));
2326 kva_free(base, size);
2332 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2333 * specified pmap. This eliminates the blast of soft faults on process startup
2334 * and immediately after an mmap.
2337 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2338 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2341 VM_OBJECT_ASSERT_WLOCKED(object);
2342 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2343 ("mmu_booke_object_init_pt: non-device object"));
2347 * Perform the pmap work for mincore.
2350 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2353 /* XXX: this should be implemented at some point */
2358 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode)
2365 addr = trunc_page(addr);
2367 /* Only allow changes to mapped kernel addresses. This includes:
2369 * - DMAP (powerpc64)
2372 if (addr <= VM_MAXUSER_ADDRESS ||
2373 #ifdef __powerpc64__
2374 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2375 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2377 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2379 (addr > VM_MAX_KERNEL_ADDRESS))
2382 /* Check TLB1 mappings */
2383 for (i = 0; i < TLB1_ENTRIES; i++) {
2384 tlb1_read_entry(&e, i);
2385 if (!(e.mas1 & MAS1_VALID))
2387 if (addr >= e.virt && addr < e.virt + e.size)
2390 if (i < TLB1_ENTRIES) {
2391 /* Only allow full mappings to be modified for now. */
2392 /* Validate the range. */
2393 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2394 tlb1_read_entry(&e, j);
2395 if (va != e.virt || (sz - (va - addr) < e.size))
2398 for (va = addr; va < addr + sz; va += e.size, i++) {
2399 tlb1_read_entry(&e, i);
2400 e.mas2 &= ~MAS2_WIMGE_MASK;
2401 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2404 * Write it out to the TLB. Should really re-sync with other
2407 tlb1_write_entry(&e, i);
2412 /* Not in TLB1, try through pmap */
2413 /* First validate the range. */
2414 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2415 pte = pte_find(kernel_pmap, va);
2416 if (pte == NULL || !PTE_ISVALID(pte))
2420 mtx_lock_spin(&tlbivax_mutex);
2422 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2423 pte = pte_find(kernel_pmap, va);
2424 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2425 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2426 tlb0_flush_entry(va);
2429 mtx_unlock_spin(&tlbivax_mutex);
2435 mmu_booke_page_array_startup(long pages)
2437 vm_page_array_size = pages;
2440 /**************************************************************************/
2442 /**************************************************************************/
2445 * Allocate a TID. If necessary, steal one from someone else.
2446 * The new TID is flushed from the TLB before returning.
2449 tid_alloc(pmap_t pmap)
2454 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2456 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2458 thiscpu = PCPU_GET(cpuid);
2460 tid = PCPU_GET(booke.tid_next);
2463 PCPU_SET(booke.tid_next, tid + 1);
2465 /* If we are stealing TID then clear the relevant pmap's field */
2466 if (tidbusy[thiscpu][tid] != NULL) {
2468 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2470 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2472 /* Flush all entries from TLB0 matching this TID. */
2476 tidbusy[thiscpu][tid] = pmap;
2477 pmap->pm_tid[thiscpu] = tid;
2478 __asm __volatile("msync; isync");
2480 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2481 PCPU_GET(booke.tid_next));
2486 /**************************************************************************/
2488 /**************************************************************************/
2490 /* Convert TLB0 va and way number to tlb0[] table index. */
2491 static inline unsigned int
2492 tlb0_tableidx(vm_offset_t va, unsigned int way)
2496 idx = (way * TLB0_ENTRIES_PER_WAY);
2497 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2502 * Invalidate TLB0 entry.
2505 tlb0_flush_entry(vm_offset_t va)
2508 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2510 mtx_assert(&tlbivax_mutex, MA_OWNED);
2512 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2513 __asm __volatile("isync; msync");
2514 __asm __volatile("tlbsync; msync");
2516 CTR1(KTR_PMAP, "%s: e", __func__);
2520 /**************************************************************************/
2522 /**************************************************************************/
2525 * TLB1 mapping notes:
2527 * TLB1[0] Kernel text and data.
2528 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2529 * windows, other devices mappings.
2533 * Read an entry from given TLB1 slot.
2536 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2541 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2544 __asm __volatile("wrteei 0");
2546 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2547 mtspr(SPR_MAS0, mas0);
2548 __asm __volatile("isync; tlbre");
2550 entry->mas1 = mfspr(SPR_MAS1);
2551 entry->mas2 = mfspr(SPR_MAS2);
2552 entry->mas3 = mfspr(SPR_MAS3);
2554 switch ((mfpvr() >> 16) & 0xFFFF) {
2559 entry->mas7 = mfspr(SPR_MAS7);
2565 __asm __volatile("wrtee %0" :: "r"(msr));
2567 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2568 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2569 (entry->mas3 & MAS3_RPN);
2571 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2574 struct tlbwrite_args {
2580 tlb1_find_free(void)
2585 for (i = 0; i < TLB1_ENTRIES; i++) {
2586 tlb1_read_entry(&e, i);
2587 if ((e.mas1 & MAS1_VALID) == 0)
2594 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2599 for (i = 0; i < TLB1_ENTRIES; i++) {
2600 tlb1_read_entry(&e, i);
2601 if ((e.mas1 & MAS1_VALID) == 0)
2603 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2604 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2605 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2606 __asm __volatile("isync; tlbwe; isync; msync");
2612 tlb1_write_entry_int(void *arg)
2614 struct tlbwrite_args *args = arg;
2619 tlb1_purge_va_range(args->e->virt, args->e->size);
2620 idx = tlb1_find_free();
2622 panic("No free TLB1 entries!\n");
2625 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2627 mtspr(SPR_MAS0, mas0);
2628 mtspr(SPR_MAS1, args->e->mas1);
2629 mtspr(SPR_MAS2, args->e->mas2);
2630 mtspr(SPR_MAS3, args->e->mas3);
2631 switch ((mfpvr() >> 16) & 0xFFFF) {
2638 mtspr(SPR_MAS7, args->e->mas7);
2644 __asm __volatile("isync; tlbwe; isync; msync");
2649 tlb1_write_entry_sync(void *arg)
2651 /* Empty synchronization point for smp_rendezvous(). */
2655 * Write given entry to TLB1 hardware.
2658 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2660 struct tlbwrite_args args;
2666 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2668 smp_rendezvous(tlb1_write_entry_sync,
2669 tlb1_write_entry_int,
2670 tlb1_write_entry_sync, &args);
2677 __asm __volatile("wrteei 0");
2678 tlb1_write_entry_int(&args);
2679 __asm __volatile("wrtee %0" :: "r"(msr));
2684 * Convert TLB TSIZE value to mapped region size.
2687 tsize2size(unsigned int tsize)
2692 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2695 return ((1 << (2 * tsize)) * 1024);
2699 * Convert region size (must be power of 4) to TLB TSIZE value.
2702 size2tsize(vm_size_t size)
2705 return (ilog2(size) / 2 - 5);
2709 * Register permanent kernel mapping in TLB1.
2711 * Entries are created starting from index 0 (current free entry is
2712 * kept in tlb1_idx) and are not supposed to be invalidated.
2715 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2722 /* First try to update an existing entry. */
2723 for (index = 0; index < TLB1_ENTRIES; index++) {
2724 tlb1_read_entry(&e, index);
2725 /* Check if we're just updating the flags, and update them. */
2726 if (e.phys == pa && e.virt == va && e.size == size) {
2727 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2728 tlb1_write_entry(&e, index);
2733 /* Convert size to TSIZE */
2734 tsize = size2tsize(size);
2736 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2737 /* XXX TS is hard coded to 0 for now as we only use single address space */
2738 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2743 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2744 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2745 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2747 /* Set supervisor RWX permission bits */
2748 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2749 e.mas7 = (pa >> 32) & MAS7_RPN;
2751 tlb1_write_entry(&e, -1);
2757 * Map in contiguous RAM region into the TLB1.
2760 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2763 vm_size_t mapped, sz, ssize;
2770 sz = 1UL << (ilog2(size) & ~1);
2771 /* Align size to PA */
2775 } while (pa % sz != 0);
2777 /* Now align from there to VA */
2781 } while (va % sz != 0);
2783 #ifdef __powerpc64__
2785 * Clamp TLB1 entries to 4G.
2787 * While the e6500 supports up to 1TB mappings, the e5500
2788 * only supports up to 4G mappings. (0b1011)
2790 * If any e6500 machines capable of supporting a very
2791 * large amount of memory appear in the future, we can
2794 * For now, though, since we have plenty of space in TLB1,
2795 * always avoid creating entries larger than 4GB.
2797 sz = MIN(sz, 1UL << 32);
2800 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2801 (void *)va, (uintmax_t)pa, (long)sz);
2802 if (tlb1_set_entry(va, pa, sz,
2803 _TLB_ENTRY_SHARED | wimge) < 0)
2810 mapped = (va - base);
2812 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2813 mapped, mapped - ssize);
2819 * TLB1 initialization routine, to be called after the very first
2820 * assembler level setup done in locore.S.
2826 uint32_t mas0, mas1, mas3, mas7;
2831 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2832 mtspr(SPR_MAS0, mas0);
2833 __asm __volatile("isync; tlbre");
2835 mas1 = mfspr(SPR_MAS1);
2836 mas2 = mfspr(SPR_MAS2);
2837 mas3 = mfspr(SPR_MAS3);
2838 mas7 = mfspr(SPR_MAS7);
2840 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2843 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2844 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2845 kernstart = trunc_page(mas2);
2847 /* Setup TLB miss defaults */
2848 set_mas4_defaults();
2852 * pmap_early_io_unmap() should be used in short conjunction with
2853 * pmap_early_io_map(), as in the following snippet:
2855 * x = pmap_early_io_map(...);
2856 * <do something with x>
2857 * pmap_early_io_unmap(x, size);
2859 * And avoiding more allocations between.
2862 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2868 size = roundup(size, PAGE_SIZE);
2870 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2871 tlb1_read_entry(&e, i);
2872 if (!(e.mas1 & MAS1_VALID))
2874 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2876 e.mas1 &= ~MAS1_VALID;
2877 tlb1_write_entry(&e, i);
2880 if (tlb1_map_base == va + isize)
2881 tlb1_map_base -= isize;
2885 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2892 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2894 for (i = 0; i < TLB1_ENTRIES; i++) {
2895 tlb1_read_entry(&e, i);
2896 if (!(e.mas1 & MAS1_VALID))
2898 if (pa >= e.phys && (pa + size) <=
2900 return (e.virt + (pa - e.phys));
2903 pa_base = rounddown(pa, PAGE_SIZE);
2904 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2905 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2906 va = tlb1_map_base + (pa - pa_base);
2909 sz = 1 << (ilog2(size) & ~1);
2910 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2911 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2914 tlb1_map_base += sz;
2921 pmap_track_page(pmap_t pmap, vm_offset_t va)
2925 struct pv_entry *pve;
2927 va = trunc_page(va);
2928 pa = pmap_kextract(va);
2929 page = PHYS_TO_VM_PAGE(pa);
2931 rw_wlock(&pvh_global_lock);
2934 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
2935 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
2939 page->md.pv_tracked = true;
2940 pv_insert(pmap, va, page);
2943 rw_wunlock(&pvh_global_lock);
2948 * Setup MAS4 defaults.
2949 * These values are loaded to MAS0-2 on a TLB miss.
2952 set_mas4_defaults(void)
2956 /* Defaults: TLB0, PID0, TSIZED=4K */
2957 mas4 = MAS4_TLBSELD0;
2958 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
2962 mtspr(SPR_MAS4, mas4);
2963 __asm __volatile("isync");
2968 * Return 0 if the physical IO range is encompassed by one of the
2969 * the TLB1 entries, otherwise return related error code.
2972 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
2975 vm_paddr_t pa_start;
2977 unsigned int entry_tsize;
2978 vm_size_t entry_size;
2981 *va = (vm_offset_t)NULL;
2983 tlb1_read_entry(&e, i);
2984 /* Skip invalid entries */
2985 if (!(e.mas1 & MAS1_VALID))
2989 * The entry must be cache-inhibited, guarded, and r/w
2990 * so it can function as an i/o page
2992 prot = e.mas2 & (MAS2_I | MAS2_G);
2993 if (prot != (MAS2_I | MAS2_G))
2996 prot = e.mas3 & (MAS3_SR | MAS3_SW);
2997 if (prot != (MAS3_SR | MAS3_SW))
3000 /* The address should be within the entry range. */
3001 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3002 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3004 entry_size = tsize2size(entry_tsize);
3005 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
3006 (e.mas3 & MAS3_RPN);
3007 pa_end = pa_start + entry_size;
3009 if ((pa < pa_start) || ((pa + size) > pa_end))
3012 /* Return virtual address of this mapping. */
3013 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3018 /* Print out contents of the MAS registers for each TLB0 entry */
3020 #ifdef __powerpc64__
3021 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3023 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3034 if (mas1 & MAS1_VALID)
3039 if (mas1 & MAS1_IPROT)
3044 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3045 tid = MAS1_GETTID(mas1);
3047 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3050 size = tsize2size(tsize);
3052 printf("%3d: (%s) [AS=%d] "
3053 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3054 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3055 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3058 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3060 uint32_t mas0, mas1, mas3, mas7;
3061 #ifdef __powerpc64__
3066 int entryidx, way, idx;
3068 printf("TLB0 entries:\n");
3069 for (way = 0; way < TLB0_WAYS; way ++)
3070 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3072 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3073 mtspr(SPR_MAS0, mas0);
3075 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3076 mtspr(SPR_MAS2, mas2);
3078 __asm __volatile("isync; tlbre");
3080 mas1 = mfspr(SPR_MAS1);
3081 mas2 = mfspr(SPR_MAS2);
3082 mas3 = mfspr(SPR_MAS3);
3083 mas7 = mfspr(SPR_MAS7);
3085 idx = tlb0_tableidx(mas2, way);
3086 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3091 * Print out contents of the MAS registers for each TLB1 entry
3093 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3095 uint32_t mas0, mas1, mas3, mas7;
3096 #ifdef __powerpc64__
3103 printf("TLB1 entries:\n");
3104 for (i = 0; i < TLB1_ENTRIES; i++) {
3106 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3107 mtspr(SPR_MAS0, mas0);
3109 __asm __volatile("isync; tlbre");
3111 mas1 = mfspr(SPR_MAS1);
3112 mas2 = mfspr(SPR_MAS2);
3113 mas3 = mfspr(SPR_MAS3);
3114 mas7 = mfspr(SPR_MAS7);
3116 tlb_print_entry(i, mas1, mas2, mas3, mas7);