2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/param.h>
56 #include <sys/malloc.h>
60 #include <sys/queue.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/kerneldump.h>
64 #include <sys/linker.h>
65 #include <sys/msgbuf.h>
67 #include <sys/mutex.h>
68 #include <sys/rwlock.h>
69 #include <sys/sched.h>
71 #include <sys/vmmeter.h>
74 #include <vm/vm_page.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_pageout.h>
77 #include <vm/vm_extern.h>
78 #include <vm/vm_object.h>
79 #include <vm/vm_param.h>
80 #include <vm/vm_map.h>
81 #include <vm/vm_pager.h>
84 #include <machine/cpu.h>
85 #include <machine/pcb.h>
86 #include <machine/platform.h>
88 #include <machine/tlb.h>
89 #include <machine/spr.h>
90 #include <machine/md_var.h>
91 #include <machine/mmuvar.h>
92 #include <machine/pmap.h>
93 #include <machine/pte.h>
98 #define debugf(fmt, args...) printf(fmt, ##args)
100 #define debugf(fmt, args...)
103 #define TODO panic("%s: not implemented", __func__);
105 extern unsigned char _etext[];
106 extern unsigned char _end[];
108 extern uint32_t *bootinfo;
111 extern uint32_t bp_ntlb1s;
115 vm_offset_t kernstart;
118 /* Message buffer and tables. */
119 static vm_offset_t data_start;
120 static vm_size_t data_end;
122 /* Phys/avail memory regions. */
123 static struct mem_region *availmem_regions;
124 static int availmem_regions_sz;
125 static struct mem_region *physmem_regions;
126 static int physmem_regions_sz;
128 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
129 static vm_offset_t zero_page_va;
130 static struct mtx zero_page_mutex;
132 static struct mtx tlbivax_mutex;
135 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
136 * by idle thred only, no lock required.
138 static vm_offset_t zero_page_idle_va;
140 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
141 static vm_offset_t copy_page_src_va;
142 static vm_offset_t copy_page_dst_va;
143 static struct mtx copy_page_mutex;
145 /**************************************************************************/
147 /**************************************************************************/
149 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
150 vm_prot_t, u_int flags, int8_t psind);
152 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
153 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
156 * If user pmap is processed with mmu_booke_remove and the resident count
157 * drops to 0, there are no more pages to remove, so we need not continue.
159 #define PMAP_REMOVE_DONE(pmap) \
160 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
162 extern void tid_flush(tlbtid_t tid, int tlb0_ways, int tlb0_entries_per_way);
163 extern int elf32_nxstack;
165 /**************************************************************************/
166 /* TLB and TID handling */
167 /**************************************************************************/
169 /* Translation ID busy table */
170 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
173 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
174 * core revisions and should be read from h/w registers during early config.
176 uint32_t tlb0_entries;
178 uint32_t tlb0_entries_per_way;
180 #define TLB0_ENTRIES (tlb0_entries)
181 #define TLB0_WAYS (tlb0_ways)
182 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
184 #define TLB1_ENTRIES 16
186 /* In-ram copy of the TLB1 */
187 static tlb_entry_t tlb1[TLB1_ENTRIES];
189 /* Next free entry in the TLB1 */
190 static unsigned int tlb1_idx;
191 static vm_offset_t tlb1_map_base = VM_MAX_KERNEL_ADDRESS;
193 static tlbtid_t tid_alloc(struct pmap *);
195 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
197 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
198 static void tlb1_write_entry(unsigned int);
199 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
200 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
202 static vm_size_t tsize2size(unsigned int);
203 static unsigned int size2tsize(vm_size_t);
204 static unsigned int ilog2(unsigned int);
206 static void set_mas4_defaults(void);
208 static inline void tlb0_flush_entry(vm_offset_t);
209 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
211 /**************************************************************************/
212 /* Page table management */
213 /**************************************************************************/
215 static struct rwlock_padalign pvh_global_lock;
217 /* Data for the pv entry allocation mechanism */
218 static uma_zone_t pvzone;
219 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
221 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
223 #ifndef PMAP_SHPGPERPROC
224 #define PMAP_SHPGPERPROC 200
227 static void ptbl_init(void);
228 static struct ptbl_buf *ptbl_buf_alloc(void);
229 static void ptbl_buf_free(struct ptbl_buf *);
230 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
232 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t);
233 static void ptbl_free(mmu_t, pmap_t, unsigned int);
234 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
235 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
237 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
238 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
239 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
240 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
242 static pv_entry_t pv_alloc(void);
243 static void pv_free(pv_entry_t);
244 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
245 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
247 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
248 #define PTBL_BUFS (128 * 16)
251 TAILQ_ENTRY(ptbl_buf) link; /* list link */
252 vm_offset_t kva; /* va of mapping */
255 /* ptbl free list and a lock used for access synchronization. */
256 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
257 static struct mtx ptbl_buf_freelist_lock;
259 /* Base address of kva space allocated fot ptbl bufs. */
260 static vm_offset_t ptbl_buf_pool_vabase;
262 /* Pointer to ptbl_buf structures. */
263 static struct ptbl_buf *ptbl_bufs;
266 void pmap_bootstrap_ap(volatile uint32_t *);
270 * Kernel MMU interface
272 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
273 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
274 vm_size_t, vm_offset_t);
275 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
276 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
277 vm_offset_t, vm_page_t *, vm_offset_t, int);
278 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
279 vm_prot_t, u_int flags, int8_t psind);
280 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
281 vm_page_t, vm_prot_t);
282 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
284 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
285 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
287 static void mmu_booke_init(mmu_t);
288 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
289 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
290 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
291 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
292 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
294 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
296 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
297 vm_object_t, vm_pindex_t, vm_size_t);
298 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
299 static void mmu_booke_page_init(mmu_t, vm_page_t);
300 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
301 static void mmu_booke_pinit(mmu_t, pmap_t);
302 static void mmu_booke_pinit0(mmu_t, pmap_t);
303 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
305 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
306 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
307 static void mmu_booke_release(mmu_t, pmap_t);
308 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
309 static void mmu_booke_remove_all(mmu_t, vm_page_t);
310 static void mmu_booke_remove_write(mmu_t, vm_page_t);
311 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
312 static void mmu_booke_zero_page(mmu_t, vm_page_t);
313 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
314 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
315 static void mmu_booke_activate(mmu_t, struct thread *);
316 static void mmu_booke_deactivate(mmu_t, struct thread *);
317 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
318 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
319 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
320 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
321 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
322 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
323 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
324 static void mmu_booke_kremove(mmu_t, vm_offset_t);
325 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
326 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
328 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t,
330 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t,
332 static void mmu_booke_scan_init(mmu_t);
334 static mmu_method_t mmu_booke_methods[] = {
335 /* pmap dispatcher interface */
336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
337 MMUMETHOD(mmu_copy, mmu_booke_copy),
338 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
339 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
340 MMUMETHOD(mmu_enter, mmu_booke_enter),
341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
343 MMUMETHOD(mmu_extract, mmu_booke_extract),
344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
345 MMUMETHOD(mmu_init, mmu_booke_init),
346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
350 MMUMETHOD(mmu_map, mmu_booke_map),
351 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
354 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
356 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
358 MMUMETHOD(mmu_protect, mmu_booke_protect),
359 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
360 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
361 MMUMETHOD(mmu_release, mmu_booke_release),
362 MMUMETHOD(mmu_remove, mmu_booke_remove),
363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
366 MMUMETHOD(mmu_unwire, mmu_booke_unwire),
367 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
368 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
369 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
370 MMUMETHOD(mmu_activate, mmu_booke_activate),
371 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
373 /* Internal interfaces */
374 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
375 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
376 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
377 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
378 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
379 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
380 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
381 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
382 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
384 /* dumpsys() support */
385 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
386 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
387 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init),
392 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
394 static __inline uint32_t
395 tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
400 if (ma != VM_MEMATTR_DEFAULT) {
402 case VM_MEMATTR_UNCACHEABLE:
403 return (PTE_I | PTE_G);
404 case VM_MEMATTR_WRITE_COMBINING:
405 case VM_MEMATTR_WRITE_BACK:
406 case VM_MEMATTR_PREFETCHABLE:
408 case VM_MEMATTR_WRITE_THROUGH:
409 return (PTE_W | PTE_M);
414 * Assume the page is cache inhibited and access is guarded unless
415 * it's in our available memory array.
417 attrib = _TLB_ENTRY_IO;
418 for (i = 0; i < physmem_regions_sz; i++) {
419 if ((pa >= physmem_regions[i].mr_start) &&
420 (pa < (physmem_regions[i].mr_start +
421 physmem_regions[i].mr_size))) {
422 attrib = _TLB_ENTRY_MEM;
439 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
442 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
443 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
445 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
446 ("tlb_miss_lock: tried to lock self"));
448 tlb_lock(pc->pc_booke_tlb_lock);
450 CTR1(KTR_PMAP, "%s: locked", __func__);
457 tlb_miss_unlock(void)
465 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
467 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
468 __func__, pc->pc_cpuid);
470 tlb_unlock(pc->pc_booke_tlb_lock);
472 CTR1(KTR_PMAP, "%s: unlocked", __func__);
478 /* Return number of entries in TLB0. */
480 tlb0_get_tlbconf(void)
484 tlb0_cfg = mfspr(SPR_TLB0CFG);
485 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
486 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
487 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
490 /* Initialize pool of kva ptbl buffers. */
496 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
497 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
498 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
499 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
501 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
502 TAILQ_INIT(&ptbl_buf_freelist);
504 for (i = 0; i < PTBL_BUFS; i++) {
505 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
506 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
510 /* Get a ptbl_buf from the freelist. */
511 static struct ptbl_buf *
514 struct ptbl_buf *buf;
516 mtx_lock(&ptbl_buf_freelist_lock);
517 buf = TAILQ_FIRST(&ptbl_buf_freelist);
519 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
520 mtx_unlock(&ptbl_buf_freelist_lock);
522 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
527 /* Return ptbl buff to free pool. */
529 ptbl_buf_free(struct ptbl_buf *buf)
532 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
534 mtx_lock(&ptbl_buf_freelist_lock);
535 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
536 mtx_unlock(&ptbl_buf_freelist_lock);
540 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
543 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
545 struct ptbl_buf *pbuf;
547 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
549 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
551 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
552 if (pbuf->kva == (vm_offset_t)ptbl) {
553 /* Remove from pmap ptbl buf list. */
554 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
556 /* Free corresponding ptbl buf. */
562 /* Allocate page table. */
564 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
566 vm_page_t mtbl[PTBL_PAGES];
568 struct ptbl_buf *pbuf;
573 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
574 (pmap == kernel_pmap), pdir_idx);
576 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
577 ("ptbl_alloc: invalid pdir_idx"));
578 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
579 ("pte_alloc: valid ptbl entry exists!"));
581 pbuf = ptbl_buf_alloc();
583 panic("pte_alloc: couldn't alloc kernel virtual memory");
585 ptbl = (pte_t *)pbuf->kva;
587 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
589 /* Allocate ptbl pages, this will sleep! */
590 for (i = 0; i < PTBL_PAGES; i++) {
591 pidx = (PTBL_PAGES * pdir_idx) + i;
592 while ((m = vm_page_alloc(NULL, pidx,
593 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
595 rw_wunlock(&pvh_global_lock);
597 ptbl_free_pmap_ptbl(pmap, ptbl);
598 for (j = 0; j < i; j++)
599 vm_page_free(mtbl[j]);
600 atomic_subtract_int(&vm_cnt.v_wire_count, i);
604 rw_wlock(&pvh_global_lock);
610 /* Map allocated pages into kernel_pmap. */
611 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
613 /* Zero whole ptbl. */
614 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
616 /* Add pbuf to the pmap ptbl bufs list. */
617 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
622 /* Free ptbl pages and invalidate pdir entry. */
624 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
632 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
633 (pmap == kernel_pmap), pdir_idx);
635 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
636 ("ptbl_free: invalid pdir_idx"));
638 ptbl = pmap->pm_pdir[pdir_idx];
640 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
642 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
645 * Invalidate the pdir entry as soon as possible, so that other CPUs
646 * don't attempt to look up the page tables we are releasing.
648 mtx_lock_spin(&tlbivax_mutex);
651 pmap->pm_pdir[pdir_idx] = NULL;
654 mtx_unlock_spin(&tlbivax_mutex);
656 for (i = 0; i < PTBL_PAGES; i++) {
657 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
658 pa = pte_vatopa(mmu, kernel_pmap, va);
659 m = PHYS_TO_VM_PAGE(pa);
660 vm_page_free_zero(m);
661 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
662 mmu_booke_kremove(mmu, va);
665 ptbl_free_pmap_ptbl(pmap, ptbl);
669 * Decrement ptbl pages hold count and attempt to free ptbl pages.
670 * Called when removing pte entry from ptbl.
672 * Return 1 if ptbl pages were freed.
675 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
682 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
683 (pmap == kernel_pmap), pdir_idx);
685 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
686 ("ptbl_unhold: invalid pdir_idx"));
687 KASSERT((pmap != kernel_pmap),
688 ("ptbl_unhold: unholding kernel ptbl!"));
690 ptbl = pmap->pm_pdir[pdir_idx];
692 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
693 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
694 ("ptbl_unhold: non kva ptbl"));
696 /* decrement hold count */
697 for (i = 0; i < PTBL_PAGES; i++) {
698 pa = pte_vatopa(mmu, kernel_pmap,
699 (vm_offset_t)ptbl + (i * PAGE_SIZE));
700 m = PHYS_TO_VM_PAGE(pa);
705 * Free ptbl pages if there are no pte etries in this ptbl.
706 * wire_count has the same value for all ptbl pages, so check the last
709 if (m->wire_count == 0) {
710 ptbl_free(mmu, pmap, pdir_idx);
712 //debugf("ptbl_unhold: e (freed ptbl)\n");
720 * Increment hold count for ptbl pages. This routine is used when a new pte
721 * entry is being inserted into the ptbl.
724 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
731 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
734 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
735 ("ptbl_hold: invalid pdir_idx"));
736 KASSERT((pmap != kernel_pmap),
737 ("ptbl_hold: holding kernel ptbl!"));
739 ptbl = pmap->pm_pdir[pdir_idx];
741 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
743 for (i = 0; i < PTBL_PAGES; i++) {
744 pa = pte_vatopa(mmu, kernel_pmap,
745 (vm_offset_t)ptbl + (i * PAGE_SIZE));
746 m = PHYS_TO_VM_PAGE(pa);
751 /* Allocate pv_entry structure. */
758 if (pv_entry_count > pv_entry_high_water)
760 pv = uma_zalloc(pvzone, M_NOWAIT);
765 /* Free pv_entry structure. */
767 pv_free(pv_entry_t pve)
771 uma_zfree(pvzone, pve);
775 /* Allocate and initialize pv_entry structure. */
777 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
781 //int su = (pmap == kernel_pmap);
782 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
783 // (u_int32_t)pmap, va, (u_int32_t)m);
787 panic("pv_insert: no pv entries!");
793 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
794 rw_assert(&pvh_global_lock, RA_WLOCKED);
796 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
798 //debugf("pv_insert: e\n");
801 /* Destroy pv entry. */
803 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
807 //int su = (pmap == kernel_pmap);
808 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
810 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
811 rw_assert(&pvh_global_lock, RA_WLOCKED);
814 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
815 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
816 /* remove from pv_list */
817 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
818 if (TAILQ_EMPTY(&m->md.pv_list))
819 vm_page_aflag_clear(m, PGA_WRITEABLE);
821 /* free pv entry struct */
827 //debugf("pv_remove: e\n");
831 * Clean pte entry, try to free page table page if requested.
833 * Return 1 if ptbl pages were freed, otherwise return 0.
836 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
838 unsigned int pdir_idx = PDIR_IDX(va);
839 unsigned int ptbl_idx = PTBL_IDX(va);
844 //int su = (pmap == kernel_pmap);
845 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
846 // su, (u_int32_t)pmap, va, flags);
848 ptbl = pmap->pm_pdir[pdir_idx];
849 KASSERT(ptbl, ("pte_remove: null ptbl"));
851 pte = &ptbl[ptbl_idx];
853 if (pte == NULL || !PTE_ISVALID(pte))
856 if (PTE_ISWIRED(pte))
857 pmap->pm_stats.wired_count--;
859 /* Handle managed entry. */
860 if (PTE_ISMANAGED(pte)) {
861 /* Get vm_page_t for mapped pte. */
862 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
864 if (PTE_ISMODIFIED(pte))
867 if (PTE_ISREFERENCED(pte))
868 vm_page_aflag_set(m, PGA_REFERENCED);
870 pv_remove(pmap, va, m);
873 mtx_lock_spin(&tlbivax_mutex);
876 tlb0_flush_entry(va);
881 mtx_unlock_spin(&tlbivax_mutex);
883 pmap->pm_stats.resident_count--;
885 if (flags & PTBL_UNHOLD) {
886 //debugf("pte_remove: e (unhold)\n");
887 return (ptbl_unhold(mmu, pmap, pdir_idx));
890 //debugf("pte_remove: e\n");
895 * Insert PTE for a given page and virtual address.
898 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
901 unsigned int pdir_idx = PDIR_IDX(va);
902 unsigned int ptbl_idx = PTBL_IDX(va);
905 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
906 pmap == kernel_pmap, pmap, va);
908 /* Get the page table pointer. */
909 ptbl = pmap->pm_pdir[pdir_idx];
912 /* Allocate page table pages. */
913 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
915 KASSERT(nosleep, ("nosleep and NULL ptbl"));
920 * Check if there is valid mapping for requested
921 * va, if there is, remove it.
923 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
924 if (PTE_ISVALID(pte)) {
925 pte_remove(mmu, pmap, va, PTBL_HOLD);
928 * pte is not used, increment hold count
931 if (pmap != kernel_pmap)
932 ptbl_hold(mmu, pmap, pdir_idx);
937 * Insert pv_entry into pv_list for mapped page if part of managed
940 if ((m->oflags & VPO_UNMANAGED) == 0) {
941 flags |= PTE_MANAGED;
943 /* Create and insert pv entry. */
944 pv_insert(pmap, va, m);
947 pmap->pm_stats.resident_count++;
949 mtx_lock_spin(&tlbivax_mutex);
952 tlb0_flush_entry(va);
953 if (pmap->pm_pdir[pdir_idx] == NULL) {
955 * If we just allocated a new page table, hook it in
958 pmap->pm_pdir[pdir_idx] = ptbl;
960 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
961 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
962 pte->flags |= (PTE_VALID | flags);
965 mtx_unlock_spin(&tlbivax_mutex);
969 /* Return the pa for the given pmap/va. */
971 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
976 pte = pte_find(mmu, pmap, va);
977 if ((pte != NULL) && PTE_ISVALID(pte))
978 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
982 /* Get a pointer to a PTE in a page table. */
984 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
986 unsigned int pdir_idx = PDIR_IDX(va);
987 unsigned int ptbl_idx = PTBL_IDX(va);
989 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
991 if (pmap->pm_pdir[pdir_idx])
992 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
997 /**************************************************************************/
999 /**************************************************************************/
1002 * This is called during booke_init, before the system is really initialized.
1005 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1007 vm_offset_t phys_kernelend;
1008 struct mem_region *mp, *mp1;
1011 u_int phys_avail_count;
1012 vm_size_t physsz, hwphyssz, kstack0_sz;
1013 vm_offset_t kernel_pdir, kstack0, va;
1014 vm_paddr_t kstack0_phys;
1018 debugf("mmu_booke_bootstrap: entered\n");
1020 /* Set interesting system properties */
1024 /* Initialize invalidation mutex */
1025 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1027 /* Read TLB0 size and associativity. */
1031 * Align kernel start and end address (kernel image).
1032 * Note that kernel end does not necessarily relate to kernsize.
1033 * kernsize is the size of the kernel that is actually mapped.
1035 kernstart = trunc_page(start);
1036 data_start = round_page(kernelend);
1037 data_end = data_start;
1040 * Addresses of preloaded modules (like file systems) use
1041 * physical addresses. Make sure we relocate those into
1042 * virtual addresses.
1044 preload_addr_relocate = kernstart - kernload;
1046 /* Allocate the dynamic per-cpu area. */
1047 dpcpu = (void *)data_end;
1048 data_end += DPCPU_SIZE;
1050 /* Allocate space for the message buffer. */
1051 msgbufp = (struct msgbuf *)data_end;
1052 data_end += msgbufsize;
1053 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1056 data_end = round_page(data_end);
1058 /* Allocate space for ptbl_bufs. */
1059 ptbl_bufs = (struct ptbl_buf *)data_end;
1060 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1061 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1064 data_end = round_page(data_end);
1066 /* Allocate PTE tables for kernel KVA. */
1067 kernel_pdir = data_end;
1068 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1069 PDIR_SIZE - 1) / PDIR_SIZE;
1070 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1071 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1072 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1074 debugf(" data_end: 0x%08x\n", data_end);
1075 if (data_end - kernstart > kernsize) {
1076 kernsize += tlb1_mapin_region(kernstart + kernsize,
1077 kernload + kernsize, (data_end - kernstart) - kernsize);
1079 data_end = kernstart + kernsize;
1080 debugf(" updated data_end: 0x%08x\n", data_end);
1083 * Clear the structures - note we can only do it safely after the
1084 * possible additional TLB1 translations are in place (above) so that
1085 * all range up to the currently calculated 'data_end' is covered.
1087 dpcpu_init(dpcpu, 0);
1088 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1089 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1091 /*******************************************************/
1092 /* Set the start and end of kva. */
1093 /*******************************************************/
1094 virtual_avail = round_page(data_end);
1095 virtual_end = VM_MAX_KERNEL_ADDRESS;
1097 /* Allocate KVA space for page zero/copy operations. */
1098 zero_page_va = virtual_avail;
1099 virtual_avail += PAGE_SIZE;
1100 zero_page_idle_va = virtual_avail;
1101 virtual_avail += PAGE_SIZE;
1102 copy_page_src_va = virtual_avail;
1103 virtual_avail += PAGE_SIZE;
1104 copy_page_dst_va = virtual_avail;
1105 virtual_avail += PAGE_SIZE;
1106 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1107 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1108 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1109 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1111 /* Initialize page zero/copy mutexes. */
1112 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1113 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1115 /* Allocate KVA space for ptbl bufs. */
1116 ptbl_buf_pool_vabase = virtual_avail;
1117 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1118 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1119 ptbl_buf_pool_vabase, virtual_avail);
1121 /* Calculate corresponding physical addresses for the kernel region. */
1122 phys_kernelend = kernload + kernsize;
1123 debugf("kernel image and allocated data:\n");
1124 debugf(" kernload = 0x%08x\n", kernload);
1125 debugf(" kernstart = 0x%08x\n", kernstart);
1126 debugf(" kernsize = 0x%08x\n", kernsize);
1128 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1129 panic("mmu_booke_bootstrap: phys_avail too small");
1132 * Remove kernel physical address range from avail regions list. Page
1133 * align all regions. Non-page aligned memory isn't very interesting
1134 * to us. Also, sort the entries for ascending addresses.
1137 /* Retrieve phys/avail mem regions */
1138 mem_regions(&physmem_regions, &physmem_regions_sz,
1139 &availmem_regions, &availmem_regions_sz);
1141 cnt = availmem_regions_sz;
1142 debugf("processing avail regions:\n");
1143 for (mp = availmem_regions; mp->mr_size; mp++) {
1145 e = mp->mr_start + mp->mr_size;
1146 debugf(" %08x-%08x -> ", s, e);
1147 /* Check whether this region holds all of the kernel. */
1148 if (s < kernload && e > phys_kernelend) {
1149 availmem_regions[cnt].mr_start = phys_kernelend;
1150 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1153 /* Look whether this regions starts within the kernel. */
1154 if (s >= kernload && s < phys_kernelend) {
1155 if (e <= phys_kernelend)
1159 /* Now look whether this region ends within the kernel. */
1160 if (e > kernload && e <= phys_kernelend) {
1165 /* Now page align the start and size of the region. */
1171 debugf("%08x-%08x = %x\n", s, e, sz);
1173 /* Check whether some memory is left here. */
1177 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1183 /* Do an insertion sort. */
1184 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1185 if (s < mp1->mr_start)
1188 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1196 availmem_regions_sz = cnt;
1198 /*******************************************************/
1199 /* Steal physical memory for kernel stack from the end */
1200 /* of the first avail region */
1201 /*******************************************************/
1202 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1203 kstack0_phys = availmem_regions[0].mr_start +
1204 availmem_regions[0].mr_size;
1205 kstack0_phys -= kstack0_sz;
1206 availmem_regions[0].mr_size -= kstack0_sz;
1208 /*******************************************************/
1209 /* Fill in phys_avail table, based on availmem_regions */
1210 /*******************************************************/
1211 phys_avail_count = 0;
1214 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1216 debugf("fill in phys_avail:\n");
1217 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1219 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1220 availmem_regions[i].mr_start,
1221 availmem_regions[i].mr_start +
1222 availmem_regions[i].mr_size,
1223 availmem_regions[i].mr_size);
1225 if (hwphyssz != 0 &&
1226 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1227 debugf(" hw.physmem adjust\n");
1228 if (physsz < hwphyssz) {
1229 phys_avail[j] = availmem_regions[i].mr_start;
1231 availmem_regions[i].mr_start +
1239 phys_avail[j] = availmem_regions[i].mr_start;
1240 phys_avail[j + 1] = availmem_regions[i].mr_start +
1241 availmem_regions[i].mr_size;
1243 physsz += availmem_regions[i].mr_size;
1245 physmem = btoc(physsz);
1247 /* Calculate the last available physical address. */
1248 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1250 Maxmem = powerpc_btop(phys_avail[i + 1]);
1252 debugf("Maxmem = 0x%08lx\n", Maxmem);
1253 debugf("phys_avail_count = %d\n", phys_avail_count);
1254 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1257 /*******************************************************/
1258 /* Initialize (statically allocated) kernel pmap. */
1259 /*******************************************************/
1260 PMAP_LOCK_INIT(kernel_pmap);
1261 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1263 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1264 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1265 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1266 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1268 /* Initialize kernel pdir */
1269 for (i = 0; i < kernel_ptbls; i++)
1270 kernel_pmap->pm_pdir[kptbl_min + i] =
1271 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1273 for (i = 0; i < MAXCPU; i++) {
1274 kernel_pmap->pm_tid[i] = TID_KERNEL;
1276 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1277 tidbusy[i][0] = kernel_pmap;
1281 * Fill in PTEs covering kernel code and data. They are not required
1282 * for address translation, as this area is covered by static TLB1
1283 * entries, but for pte_vatopa() to work correctly with kernel area
1286 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1287 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1288 pte->rpn = kernload + (va - kernstart);
1289 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1292 /* Mark kernel_pmap active on all CPUs */
1293 CPU_FILL(&kernel_pmap->pm_active);
1296 * Initialize the global pv list lock.
1298 rw_init(&pvh_global_lock, "pmap pv global");
1300 /*******************************************************/
1302 /*******************************************************/
1304 /* Enter kstack0 into kernel map, provide guard page */
1305 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1306 thread0.td_kstack = kstack0;
1307 thread0.td_kstack_pages = KSTACK_PAGES;
1309 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1310 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1311 kstack0_phys, kstack0_phys + kstack0_sz);
1312 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1314 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1315 for (i = 0; i < KSTACK_PAGES; i++) {
1316 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1317 kstack0 += PAGE_SIZE;
1318 kstack0_phys += PAGE_SIZE;
1321 pmap_bootstrapped = 1;
1323 debugf("virtual_avail = %08x\n", virtual_avail);
1324 debugf("virtual_end = %08x\n", virtual_end);
1326 debugf("mmu_booke_bootstrap: exit\n");
1331 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1336 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1337 * have the snapshot of its contents in the s/w tlb1[] table, so use
1338 * these values directly to (re)program AP's TLB1 hardware.
1340 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1341 /* Skip invalid entries */
1342 if (!(tlb1[i].mas1 & MAS1_VALID))
1345 tlb1_write_entry(i);
1348 set_mas4_defaults();
1353 * Get the physical page address for the given pmap/virtual address.
1356 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1361 pa = pte_vatopa(mmu, pmap, va);
1368 * Extract the physical page address associated with the given
1369 * kernel virtual address.
1372 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1376 /* Check TLB1 mappings */
1377 for (i = 0; i < tlb1_idx; i++) {
1378 if (!(tlb1[i].mas1 & MAS1_VALID))
1380 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size)
1381 return (tlb1[i].phys + (va - tlb1[i].virt));
1384 return (pte_vatopa(mmu, kernel_pmap, va));
1388 * Initialize the pmap module.
1389 * Called by vm_init, to initialize any structures that the pmap
1390 * system needs to map virtual memory.
1393 mmu_booke_init(mmu_t mmu)
1395 int shpgperproc = PMAP_SHPGPERPROC;
1398 * Initialize the address space (zone) for the pv entries. Set a
1399 * high water mark so that the system can recover from excessive
1400 * numbers of pv entries.
1402 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1403 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1405 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1406 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1408 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1409 pv_entry_high_water = 9 * (pv_entry_max / 10);
1411 uma_zone_reserve_kva(pvzone, pv_entry_max);
1413 /* Pre-fill pvzone with initial number of pv entries. */
1414 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1416 /* Initialize ptbl allocation. */
1421 * Map a list of wired pages into kernel virtual address space. This is
1422 * intended for temporary mappings which do not need page modification or
1423 * references recorded. Existing mappings in the region are overwritten.
1426 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1431 while (count-- > 0) {
1432 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1439 * Remove page mappings from kernel virtual address space. Intended for
1440 * temporary mappings entered by mmu_booke_qenter.
1443 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1448 while (count-- > 0) {
1449 mmu_booke_kremove(mmu, va);
1455 * Map a wired page into kernel virtual address space.
1458 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1461 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1465 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1467 unsigned int pdir_idx = PDIR_IDX(va);
1468 unsigned int ptbl_idx = PTBL_IDX(va);
1472 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1473 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1475 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1476 flags |= tlb_calc_wimg(pa, ma);
1478 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1480 mtx_lock_spin(&tlbivax_mutex);
1483 if (PTE_ISVALID(pte)) {
1485 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1487 /* Flush entry from TLB0 */
1488 tlb0_flush_entry(va);
1491 pte->rpn = pa & ~PTE_PA_MASK;
1494 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1495 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1496 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1498 /* Flush the real memory from the instruction cache. */
1499 if ((flags & (PTE_I | PTE_G)) == 0) {
1500 __syncicache((void *)va, PAGE_SIZE);
1504 mtx_unlock_spin(&tlbivax_mutex);
1508 * Remove a page from kernel page table.
1511 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1513 unsigned int pdir_idx = PDIR_IDX(va);
1514 unsigned int ptbl_idx = PTBL_IDX(va);
1517 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1519 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1520 (va <= VM_MAX_KERNEL_ADDRESS)),
1521 ("mmu_booke_kremove: invalid va"));
1523 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1525 if (!PTE_ISVALID(pte)) {
1527 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1532 mtx_lock_spin(&tlbivax_mutex);
1535 /* Invalidate entry in TLB0, update PTE. */
1536 tlb0_flush_entry(va);
1541 mtx_unlock_spin(&tlbivax_mutex);
1545 * Initialize pmap associated with process 0.
1548 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1551 PMAP_LOCK_INIT(pmap);
1552 mmu_booke_pinit(mmu, pmap);
1553 PCPU_SET(curpmap, pmap);
1557 * Initialize a preallocated and zeroed pmap structure,
1558 * such as one in a vmspace structure.
1561 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1565 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1566 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1568 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1570 for (i = 0; i < MAXCPU; i++)
1571 pmap->pm_tid[i] = TID_NONE;
1572 CPU_ZERO(&kernel_pmap->pm_active);
1573 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1574 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1575 TAILQ_INIT(&pmap->pm_ptbl_list);
1579 * Release any resources held by the given physical map.
1580 * Called when a pmap initialized by mmu_booke_pinit is being released.
1581 * Should only be called if the map contains no valid mappings.
1584 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1587 KASSERT(pmap->pm_stats.resident_count == 0,
1588 ("pmap_release: pmap resident count %ld != 0",
1589 pmap->pm_stats.resident_count));
1593 * Insert the given physical page at the specified virtual address in the
1594 * target physical map with the protection requested. If specified the page
1595 * will be wired down.
1598 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1599 vm_prot_t prot, u_int flags, int8_t psind)
1603 rw_wlock(&pvh_global_lock);
1605 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
1606 rw_wunlock(&pvh_global_lock);
1612 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1613 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1618 int error, su, sync;
1620 pa = VM_PAGE_TO_PHYS(m);
1621 su = (pmap == kernel_pmap);
1624 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1625 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1626 // (u_int32_t)pmap, su, pmap->pm_tid,
1627 // (u_int32_t)m, va, pa, prot, flags);
1630 KASSERT(((va >= virtual_avail) &&
1631 (va <= VM_MAX_KERNEL_ADDRESS)),
1632 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1634 KASSERT((va <= VM_MAXUSER_ADDRESS),
1635 ("mmu_booke_enter_locked: user pmap, non user va"));
1637 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1638 VM_OBJECT_ASSERT_LOCKED(m->object);
1640 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1643 * If there is an existing mapping, and the physical address has not
1644 * changed, must be protection or wiring change.
1646 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1647 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1650 * Before actually updating pte->flags we calculate and
1651 * prepare its new value in a helper var.
1654 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1656 /* Wiring change, just update stats. */
1657 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1658 if (!PTE_ISWIRED(pte)) {
1660 pmap->pm_stats.wired_count++;
1663 if (PTE_ISWIRED(pte)) {
1664 flags &= ~PTE_WIRED;
1665 pmap->pm_stats.wired_count--;
1669 if (prot & VM_PROT_WRITE) {
1670 /* Add write permissions. */
1675 if ((flags & PTE_MANAGED) != 0)
1676 vm_page_aflag_set(m, PGA_WRITEABLE);
1678 /* Handle modified pages, sense modify status. */
1681 * The PTE_MODIFIED flag could be set by underlying
1682 * TLB misses since we last read it (above), possibly
1683 * other CPUs could update it so we check in the PTE
1684 * directly rather than rely on that saved local flags
1687 if (PTE_ISMODIFIED(pte))
1691 if (prot & VM_PROT_EXECUTE) {
1697 * Check existing flags for execute permissions: if we
1698 * are turning execute permissions on, icache should
1701 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1705 flags &= ~PTE_REFERENCED;
1708 * The new flags value is all calculated -- only now actually
1711 mtx_lock_spin(&tlbivax_mutex);
1714 tlb0_flush_entry(va);
1718 mtx_unlock_spin(&tlbivax_mutex);
1722 * If there is an existing mapping, but it's for a different
1723 * physical address, pte_enter() will delete the old mapping.
1725 //if ((pte != NULL) && PTE_ISVALID(pte))
1726 // debugf("mmu_booke_enter_locked: replace\n");
1728 // debugf("mmu_booke_enter_locked: new\n");
1730 /* Now set up the flags and install the new mapping. */
1731 flags = (PTE_SR | PTE_VALID);
1737 if (prot & VM_PROT_WRITE) {
1742 if ((m->oflags & VPO_UNMANAGED) == 0)
1743 vm_page_aflag_set(m, PGA_WRITEABLE);
1746 if (prot & VM_PROT_EXECUTE) {
1752 /* If its wired update stats. */
1753 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1756 error = pte_enter(mmu, pmap, m, va, flags,
1757 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1759 return (KERN_RESOURCE_SHORTAGE);
1761 if ((flags & PMAP_ENTER_WIRED) != 0)
1762 pmap->pm_stats.wired_count++;
1764 /* Flush the real memory from the instruction cache. */
1765 if (prot & VM_PROT_EXECUTE)
1769 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1770 __syncicache((void *)va, PAGE_SIZE);
1774 return (KERN_SUCCESS);
1778 * Maps a sequence of resident pages belonging to the same object.
1779 * The sequence begins with the given page m_start. This page is
1780 * mapped at the given virtual address start. Each subsequent page is
1781 * mapped at a virtual address that is offset from start by the same
1782 * amount as the page is offset from m_start within the object. The
1783 * last page in the sequence is the page with the largest offset from
1784 * m_start that can be mapped at a virtual address less than the given
1785 * virtual address end. Not every virtual page between start and end
1786 * is mapped; only those for which a resident page exists with the
1787 * corresponding offset from m_start are mapped.
1790 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1791 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1794 vm_pindex_t diff, psize;
1796 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1798 psize = atop(end - start);
1800 rw_wlock(&pvh_global_lock);
1802 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1803 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1804 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1805 PMAP_ENTER_NOSLEEP, 0);
1806 m = TAILQ_NEXT(m, listq);
1808 rw_wunlock(&pvh_global_lock);
1813 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1817 rw_wlock(&pvh_global_lock);
1819 mmu_booke_enter_locked(mmu, pmap, va, m,
1820 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP,
1822 rw_wunlock(&pvh_global_lock);
1827 * Remove the given range of addresses from the specified map.
1829 * It is assumed that the start and end are properly rounded to the page size.
1832 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1837 int su = (pmap == kernel_pmap);
1839 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1840 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1843 KASSERT(((va >= virtual_avail) &&
1844 (va <= VM_MAX_KERNEL_ADDRESS)),
1845 ("mmu_booke_remove: kernel pmap, non kernel va"));
1847 KASSERT((va <= VM_MAXUSER_ADDRESS),
1848 ("mmu_booke_remove: user pmap, non user va"));
1851 if (PMAP_REMOVE_DONE(pmap)) {
1852 //debugf("mmu_booke_remove: e (empty)\n");
1856 hold_flag = PTBL_HOLD_FLAG(pmap);
1857 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1859 rw_wlock(&pvh_global_lock);
1861 for (; va < endva; va += PAGE_SIZE) {
1862 pte = pte_find(mmu, pmap, va);
1863 if ((pte != NULL) && PTE_ISVALID(pte))
1864 pte_remove(mmu, pmap, va, hold_flag);
1867 rw_wunlock(&pvh_global_lock);
1869 //debugf("mmu_booke_remove: e\n");
1873 * Remove physical page from all pmaps in which it resides.
1876 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1881 rw_wlock(&pvh_global_lock);
1882 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1883 pvn = TAILQ_NEXT(pv, pv_link);
1885 PMAP_LOCK(pv->pv_pmap);
1886 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1887 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1888 PMAP_UNLOCK(pv->pv_pmap);
1890 vm_page_aflag_clear(m, PGA_WRITEABLE);
1891 rw_wunlock(&pvh_global_lock);
1895 * Map a range of physical addresses into kernel virtual address space.
1898 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1899 vm_paddr_t pa_end, int prot)
1901 vm_offset_t sva = *virt;
1902 vm_offset_t va = sva;
1904 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1905 // sva, pa_start, pa_end);
1907 while (pa_start < pa_end) {
1908 mmu_booke_kenter(mmu, va, pa_start);
1910 pa_start += PAGE_SIZE;
1914 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1919 * The pmap must be activated before it's address space can be accessed in any
1923 mmu_booke_activate(mmu_t mmu, struct thread *td)
1928 pmap = &td->td_proc->p_vmspace->vm_pmap;
1930 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1931 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1933 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1937 cpuid = PCPU_GET(cpuid);
1938 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1939 PCPU_SET(curpmap, pmap);
1941 if (pmap->pm_tid[cpuid] == TID_NONE)
1944 /* Load PID0 register with pmap tid value. */
1945 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1946 __asm __volatile("isync");
1948 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1952 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1953 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1957 * Deactivate the specified process's address space.
1960 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1964 pmap = &td->td_proc->p_vmspace->vm_pmap;
1966 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1967 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1969 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1971 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1972 PCPU_SET(curpmap, NULL);
1976 * Copy the range specified by src_addr/len
1977 * from the source map to the range dst_addr/len
1978 * in the destination map.
1980 * This routine is only advisory and need not do anything.
1983 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1984 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1990 * Set the physical protection on the specified range of this map as requested.
1993 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2000 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2001 mmu_booke_remove(mmu, pmap, sva, eva);
2005 if (prot & VM_PROT_WRITE)
2009 for (va = sva; va < eva; va += PAGE_SIZE) {
2010 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2011 if (PTE_ISVALID(pte)) {
2012 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2014 mtx_lock_spin(&tlbivax_mutex);
2017 /* Handle modified pages. */
2018 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2021 tlb0_flush_entry(va);
2022 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2025 mtx_unlock_spin(&tlbivax_mutex);
2033 * Clear the write and modified bits in each of the given page's mappings.
2036 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2041 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2042 ("mmu_booke_remove_write: page %p is not managed", m));
2045 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2046 * set by another thread while the object is locked. Thus,
2047 * if PGA_WRITEABLE is clear, no page table entries need updating.
2049 VM_OBJECT_ASSERT_WLOCKED(m->object);
2050 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2052 rw_wlock(&pvh_global_lock);
2053 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2054 PMAP_LOCK(pv->pv_pmap);
2055 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2056 if (PTE_ISVALID(pte)) {
2057 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2059 mtx_lock_spin(&tlbivax_mutex);
2062 /* Handle modified pages. */
2063 if (PTE_ISMODIFIED(pte))
2066 /* Flush mapping from TLB0. */
2067 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2070 mtx_unlock_spin(&tlbivax_mutex);
2073 PMAP_UNLOCK(pv->pv_pmap);
2075 vm_page_aflag_clear(m, PGA_WRITEABLE);
2076 rw_wunlock(&pvh_global_lock);
2080 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2089 va = trunc_page(va);
2090 sz = round_page(sz);
2092 rw_wlock(&pvh_global_lock);
2093 pmap = PCPU_GET(curpmap);
2094 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2097 pte = pte_find(mmu, pm, va);
2098 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2104 /* Create a mapping in the active pmap. */
2106 m = PHYS_TO_VM_PAGE(pa);
2108 pte_enter(mmu, pmap, m, addr,
2109 PTE_SR | PTE_VALID | PTE_UR, FALSE);
2110 __syncicache((void *)addr, PAGE_SIZE);
2111 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2114 __syncicache((void *)va, PAGE_SIZE);
2119 rw_wunlock(&pvh_global_lock);
2123 * Atomically extract and hold the physical page with the given
2124 * pmap and virtual address pair if that mapping permits the given
2128 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2140 pte = pte_find(mmu, pmap, va);
2141 if ((pte != NULL) && PTE_ISVALID(pte)) {
2142 if (pmap == kernel_pmap)
2147 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2148 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2150 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2161 * Initialize a vm_page's machine-dependent fields.
2164 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2167 TAILQ_INIT(&m->md.pv_list);
2171 * mmu_booke_zero_page_area zeros the specified hardware page by
2172 * mapping it into virtual memory and using bzero to clear
2175 * off and size must reside within a single page.
2178 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2182 /* XXX KASSERT off and size are within a single page? */
2184 mtx_lock(&zero_page_mutex);
2187 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2188 bzero((caddr_t)va + off, size);
2189 mmu_booke_kremove(mmu, va);
2191 mtx_unlock(&zero_page_mutex);
2195 * mmu_booke_zero_page zeros the specified hardware page.
2198 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2201 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2205 * mmu_booke_copy_page copies the specified (machine independent) page by
2206 * mapping the page into virtual memory and using memcopy to copy the page,
2207 * one machine dependent page at a time.
2210 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2212 vm_offset_t sva, dva;
2214 sva = copy_page_src_va;
2215 dva = copy_page_dst_va;
2217 mtx_lock(©_page_mutex);
2218 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2219 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2220 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2221 mmu_booke_kremove(mmu, dva);
2222 mmu_booke_kremove(mmu, sva);
2223 mtx_unlock(©_page_mutex);
2227 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2228 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2231 vm_offset_t a_pg_offset, b_pg_offset;
2234 mtx_lock(©_page_mutex);
2235 while (xfersize > 0) {
2236 a_pg_offset = a_offset & PAGE_MASK;
2237 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2238 mmu_booke_kenter(mmu, copy_page_src_va,
2239 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2240 a_cp = (char *)copy_page_src_va + a_pg_offset;
2241 b_pg_offset = b_offset & PAGE_MASK;
2242 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2243 mmu_booke_kenter(mmu, copy_page_dst_va,
2244 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2245 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2246 bcopy(a_cp, b_cp, cnt);
2247 mmu_booke_kremove(mmu, copy_page_dst_va);
2248 mmu_booke_kremove(mmu, copy_page_src_va);
2253 mtx_unlock(©_page_mutex);
2257 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2258 * into virtual memory and using bzero to clear its contents. This is intended
2259 * to be called from the vm_pagezero process only and outside of Giant. No
2263 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2267 va = zero_page_idle_va;
2268 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2269 bzero((caddr_t)va, PAGE_SIZE);
2270 mmu_booke_kremove(mmu, va);
2274 * Return whether or not the specified physical page was modified
2275 * in any of physical maps.
2278 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2284 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2285 ("mmu_booke_is_modified: page %p is not managed", m));
2289 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2290 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2291 * is clear, no PTEs can be modified.
2293 VM_OBJECT_ASSERT_WLOCKED(m->object);
2294 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2296 rw_wlock(&pvh_global_lock);
2297 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2298 PMAP_LOCK(pv->pv_pmap);
2299 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2301 if (PTE_ISMODIFIED(pte))
2304 PMAP_UNLOCK(pv->pv_pmap);
2308 rw_wunlock(&pvh_global_lock);
2313 * Return whether or not the specified virtual address is eligible
2317 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2324 * Return whether or not the specified physical page was referenced
2325 * in any physical maps.
2328 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2334 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2335 ("mmu_booke_is_referenced: page %p is not managed", m));
2337 rw_wlock(&pvh_global_lock);
2338 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2339 PMAP_LOCK(pv->pv_pmap);
2340 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2342 if (PTE_ISREFERENCED(pte))
2345 PMAP_UNLOCK(pv->pv_pmap);
2349 rw_wunlock(&pvh_global_lock);
2354 * Clear the modify bits on the specified physical page.
2357 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2362 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2363 ("mmu_booke_clear_modify: page %p is not managed", m));
2364 VM_OBJECT_ASSERT_WLOCKED(m->object);
2365 KASSERT(!vm_page_xbusied(m),
2366 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2369 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2370 * If the object containing the page is locked and the page is not
2371 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2373 if ((m->aflags & PGA_WRITEABLE) == 0)
2375 rw_wlock(&pvh_global_lock);
2376 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2377 PMAP_LOCK(pv->pv_pmap);
2378 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2380 mtx_lock_spin(&tlbivax_mutex);
2383 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2384 tlb0_flush_entry(pv->pv_va);
2385 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2390 mtx_unlock_spin(&tlbivax_mutex);
2392 PMAP_UNLOCK(pv->pv_pmap);
2394 rw_wunlock(&pvh_global_lock);
2398 * Return a count of reference bits for a page, clearing those bits.
2399 * It is not necessary for every reference bit to be cleared, but it
2400 * is necessary that 0 only be returned when there are truly no
2401 * reference bits set.
2403 * XXX: The exact number of bits to check and clear is a matter that
2404 * should be tested and standardized at some point in the future for
2405 * optimal aging of shared pages.
2408 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2414 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2415 ("mmu_booke_ts_referenced: page %p is not managed", m));
2417 rw_wlock(&pvh_global_lock);
2418 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2419 PMAP_LOCK(pv->pv_pmap);
2420 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2422 if (PTE_ISREFERENCED(pte)) {
2423 mtx_lock_spin(&tlbivax_mutex);
2426 tlb0_flush_entry(pv->pv_va);
2427 pte->flags &= ~PTE_REFERENCED;
2430 mtx_unlock_spin(&tlbivax_mutex);
2433 PMAP_UNLOCK(pv->pv_pmap);
2438 PMAP_UNLOCK(pv->pv_pmap);
2440 rw_wunlock(&pvh_global_lock);
2445 * Clear the wired attribute from the mappings for the specified range of
2446 * addresses in the given pmap. Every valid mapping within that range must
2447 * have the wired attribute set. In contrast, invalid mappings cannot have
2448 * the wired attribute set, so they are ignored.
2450 * The wired attribute of the page table entry is not a hardware feature, so
2451 * there is no need to invalidate any TLB entries.
2454 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2460 for (va = sva; va < eva; va += PAGE_SIZE) {
2461 if ((pte = pte_find(mmu, pmap, va)) != NULL &&
2463 if (!PTE_ISWIRED(pte))
2464 panic("mmu_booke_unwire: pte %p isn't wired",
2466 pte->flags &= ~PTE_WIRED;
2467 pmap->pm_stats.wired_count--;
2475 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2476 * page. This count may be changed upwards or downwards in the future; it is
2477 * only necessary that true be returned for a small subset of pmaps for proper
2481 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2487 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2488 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2491 rw_wlock(&pvh_global_lock);
2492 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2493 if (pv->pv_pmap == pmap) {
2500 rw_wunlock(&pvh_global_lock);
2505 * Return the number of managed mappings to the given physical page that are
2509 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2515 if ((m->oflags & VPO_UNMANAGED) != 0)
2517 rw_wlock(&pvh_global_lock);
2518 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2519 PMAP_LOCK(pv->pv_pmap);
2520 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2521 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2523 PMAP_UNLOCK(pv->pv_pmap);
2525 rw_wunlock(&pvh_global_lock);
2530 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2536 * This currently does not work for entries that
2537 * overlap TLB1 entries.
2539 for (i = 0; i < tlb1_idx; i ++) {
2540 if (tlb1_iomapped(i, pa, size, &va) == 0)
2548 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
2554 /* Minidumps are based on virtual memory addresses. */
2560 /* Raw physical memory dumps don't have a virtual address. */
2561 /* We always map a 256MB page at 256M. */
2562 gran = 256 * 1024 * 1024;
2563 ppa = pa & ~(gran - 1);
2566 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2568 if (sz > (gran - ofs))
2569 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2574 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va)
2580 /* Minidumps are based on virtual memory addresses. */
2581 /* Nothing to do... */
2585 /* Raw physical memory dumps don't have a virtual address. */
2587 tlb1[tlb1_idx].mas1 = 0;
2588 tlb1[tlb1_idx].mas2 = 0;
2589 tlb1[tlb1_idx].mas3 = 0;
2590 tlb1_write_entry(tlb1_idx);
2592 gran = 256 * 1024 * 1024;
2593 ppa = pa & ~(gran - 1);
2595 if (sz > (gran - ofs)) {
2597 tlb1[tlb1_idx].mas1 = 0;
2598 tlb1[tlb1_idx].mas2 = 0;
2599 tlb1[tlb1_idx].mas3 = 0;
2600 tlb1_write_entry(tlb1_idx);
2604 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2607 mmu_booke_scan_init(mmu_t mmu)
2614 /* Initialize phys. segments for dumpsys(). */
2615 memset(&dump_map, 0, sizeof(dump_map));
2616 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2617 &availmem_regions_sz);
2618 for (i = 0; i < physmem_regions_sz; i++) {
2619 dump_map[i].pa_start = physmem_regions[i].mr_start;
2620 dump_map[i].pa_size = physmem_regions[i].mr_size;
2625 /* Virtual segments for minidumps: */
2626 memset(&dump_map, 0, sizeof(dump_map));
2628 /* 1st: kernel .data and .bss. */
2629 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2630 dump_map[0].pa_size =
2631 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2633 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2634 dump_map[1].pa_start = data_start;
2635 dump_map[1].pa_size = data_end - data_start;
2637 /* 3rd: kernel VM. */
2638 va = dump_map[1].pa_start + dump_map[1].pa_size;
2639 /* Find start of next chunk (from va). */
2640 while (va < virtual_end) {
2641 /* Don't dump the buffer cache. */
2642 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2643 va = kmi.buffer_eva;
2646 pte = pte_find(mmu, kernel_pmap, va);
2647 if (pte != NULL && PTE_ISVALID(pte))
2651 if (va < virtual_end) {
2652 dump_map[2].pa_start = va;
2654 /* Find last page in chunk. */
2655 while (va < virtual_end) {
2656 /* Don't run into the buffer cache. */
2657 if (va == kmi.buffer_sva)
2659 pte = pte_find(mmu, kernel_pmap, va);
2660 if (pte == NULL || !PTE_ISVALID(pte))
2664 dump_map[2].pa_size = va - dump_map[2].pa_start;
2669 * Map a set of physical memory pages into the kernel virtual address space.
2670 * Return a pointer to where it is mapped. This routine is intended to be used
2671 * for mapping device memory, NOT real memory.
2674 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2677 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2681 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2689 * Check if this is premapped in TLB1. Note: this should probably also
2690 * check whether a sequence of TLB1 entries exist that match the
2691 * requirement, but now only checks the easy case.
2693 if (ma == VM_MEMATTR_DEFAULT) {
2694 for (i = 0; i < tlb1_idx; i++) {
2695 if (!(tlb1[i].mas1 & MAS1_VALID))
2697 if (pa >= tlb1[i].phys &&
2698 (pa + size) <= (tlb1[i].phys + tlb1[i].size))
2699 return (void *)(tlb1[i].virt +
2700 (pa - tlb1[i].phys));
2704 size = roundup(size, PAGE_SIZE);
2707 * We leave a hole for device direct mapping between the maximum user
2708 * address (0x8000000) and the minimum KVA address (0xc0000000). If
2709 * devices are in there, just map them 1:1. If not, map them to the
2710 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped
2711 * addresses should be pulled from an allocator, but since we do not
2712 * ever free TLB1 entries, it is safe just to increment a counter.
2713 * Note that there isn't a lot of address space here (128 MB) and it
2714 * is not at all difficult to imagine running out, since that is a 4:1
2715 * compression from the 0xc0000000 - 0xf0000000 address space that gets
2718 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) &&
2719 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS)
2722 va = atomic_fetchadd_int(&tlb1_map_base, size);
2726 sz = 1 << (ilog2(size) & ~1);
2728 printf("Wiring VA=%x to PA=%x (size=%x), "
2729 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2730 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma));
2740 * 'Unmap' a range mapped by mmu_booke_mapdev().
2743 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2745 #ifdef SUPPORTS_SHRINKING_TLB1
2746 vm_offset_t base, offset;
2749 * Unmap only if this is inside kernel virtual space.
2751 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2752 base = trunc_page(va);
2753 offset = va & PAGE_MASK;
2754 size = roundup(offset + size, PAGE_SIZE);
2755 kva_free(base, size);
2761 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2762 * specified pmap. This eliminates the blast of soft faults on process startup
2763 * and immediately after an mmap.
2766 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2767 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2770 VM_OBJECT_ASSERT_WLOCKED(object);
2771 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2772 ("mmu_booke_object_init_pt: non-device object"));
2776 * Perform the pmap work for mincore.
2779 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2780 vm_paddr_t *locked_pa)
2783 /* XXX: this should be implemented at some point */
2787 /**************************************************************************/
2789 /**************************************************************************/
2792 * Allocate a TID. If necessary, steal one from someone else.
2793 * The new TID is flushed from the TLB before returning.
2796 tid_alloc(pmap_t pmap)
2801 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2803 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2805 thiscpu = PCPU_GET(cpuid);
2807 tid = PCPU_GET(tid_next);
2810 PCPU_SET(tid_next, tid + 1);
2812 /* If we are stealing TID then clear the relevant pmap's field */
2813 if (tidbusy[thiscpu][tid] != NULL) {
2815 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2817 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2819 /* Flush all entries from TLB0 matching this TID. */
2820 tid_flush(tid, tlb0_ways, tlb0_entries_per_way);
2823 tidbusy[thiscpu][tid] = pmap;
2824 pmap->pm_tid[thiscpu] = tid;
2825 __asm __volatile("msync; isync");
2827 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2828 PCPU_GET(tid_next));
2833 /**************************************************************************/
2835 /**************************************************************************/
2838 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2848 if (mas1 & MAS1_VALID)
2853 if (mas1 & MAS1_IPROT)
2858 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2859 tid = MAS1_GETTID(mas1);
2861 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2864 size = tsize2size(tsize);
2866 debugf("%3d: (%s) [AS=%d] "
2867 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2868 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2869 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2872 /* Convert TLB0 va and way number to tlb0[] table index. */
2873 static inline unsigned int
2874 tlb0_tableidx(vm_offset_t va, unsigned int way)
2878 idx = (way * TLB0_ENTRIES_PER_WAY);
2879 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2884 * Invalidate TLB0 entry.
2887 tlb0_flush_entry(vm_offset_t va)
2890 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2892 mtx_assert(&tlbivax_mutex, MA_OWNED);
2894 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2895 __asm __volatile("isync; msync");
2896 __asm __volatile("tlbsync; msync");
2898 CTR1(KTR_PMAP, "%s: e", __func__);
2901 /* Print out contents of the MAS registers for each TLB0 entry */
2903 tlb0_print_tlbentries(void)
2905 uint32_t mas0, mas1, mas2, mas3, mas7;
2906 int entryidx, way, idx;
2908 debugf("TLB0 entries:\n");
2909 for (way = 0; way < TLB0_WAYS; way ++)
2910 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2912 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2913 mtspr(SPR_MAS0, mas0);
2914 __asm __volatile("isync");
2916 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2917 mtspr(SPR_MAS2, mas2);
2919 __asm __volatile("isync; tlbre");
2921 mas1 = mfspr(SPR_MAS1);
2922 mas2 = mfspr(SPR_MAS2);
2923 mas3 = mfspr(SPR_MAS3);
2924 mas7 = mfspr(SPR_MAS7);
2926 idx = tlb0_tableidx(mas2, way);
2927 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2931 /**************************************************************************/
2933 /**************************************************************************/
2936 * TLB1 mapping notes:
2938 * TLB1[0] Kernel text and data.
2939 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2940 * windows, other devices mappings.
2944 * Write given entry to TLB1 hardware.
2945 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2948 tlb1_write_entry(unsigned int idx)
2950 uint32_t mas0, mas7;
2952 //debugf("tlb1_write_entry: s\n");
2954 /* Clear high order RPN bits */
2958 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2959 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2961 mtspr(SPR_MAS0, mas0);
2962 __asm __volatile("isync");
2963 mtspr(SPR_MAS1, tlb1[idx].mas1);
2964 __asm __volatile("isync");
2965 mtspr(SPR_MAS2, tlb1[idx].mas2);
2966 __asm __volatile("isync");
2967 mtspr(SPR_MAS3, tlb1[idx].mas3);
2968 __asm __volatile("isync");
2969 mtspr(SPR_MAS7, mas7);
2970 __asm __volatile("isync; tlbwe; isync; msync");
2972 //debugf("tlb1_write_entry: e\n");
2976 * Return the largest uint value log such that 2^log <= num.
2979 ilog2(unsigned int num)
2983 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2988 * Convert TLB TSIZE value to mapped region size.
2991 tsize2size(unsigned int tsize)
2996 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2999 return ((1 << (2 * tsize)) * 1024);
3003 * Convert region size (must be power of 4) to TLB TSIZE value.
3006 size2tsize(vm_size_t size)
3009 return (ilog2(size) / 2 - 5);
3013 * Register permanent kernel mapping in TLB1.
3015 * Entries are created starting from index 0 (current free entry is
3016 * kept in tlb1_idx) and are not supposed to be invalidated.
3019 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
3025 index = atomic_fetchadd_int(&tlb1_idx, 1);
3026 if (index >= TLB1_ENTRIES) {
3027 printf("tlb1_set_entry: TLB1 full!\n");
3031 /* Convert size to TSIZE */
3032 tsize = size2tsize(size);
3034 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3035 /* XXX TS is hard coded to 0 for now as we only use single address space */
3036 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3039 * Atomicity is preserved by the atomic increment above since nothing
3040 * is ever removed from tlb1.
3043 tlb1[index].phys = pa;
3044 tlb1[index].virt = va;
3045 tlb1[index].size = size;
3046 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3047 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3048 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags;
3050 /* Set supervisor RWX permission bits */
3051 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3053 tlb1_write_entry(index);
3056 * XXX in general TLB1 updates should be propagated between CPUs,
3057 * since current design assumes to have the same TLB1 set-up on all
3064 * Map in contiguous RAM region into the TLB1 using maximum of
3065 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3067 * If necessary round up last entry size and return total size
3068 * used by all allocated entries.
3071 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3073 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3074 vm_size_t mapped, pgsz, base, mask;
3077 /* Round up to the next 1M */
3078 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
3083 pgsz = 64*1024*1024;
3084 while (mapped < size) {
3085 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3086 while (pgsz > (size - mapped))
3092 /* We under-map. Correct for this. */
3093 if (mapped < size) {
3094 while (pgs[idx - 1] == pgsz) {
3098 /* XXX We may increase beyond out starting point. */
3107 /* Align address to the boundary */
3109 va = (va + mask) & ~mask;
3110 pa = (pa + mask) & ~mask;
3113 for (idx = 0; idx < nents; idx++) {
3115 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3116 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3121 mapped = (va - base);
3122 printf("mapped size 0x%08x (wasted space 0x%08x)\n",
3123 mapped, mapped - size);
3128 * TLB1 initialization routine, to be called after the very first
3129 * assembler level setup done in locore.S.
3134 uint32_t mas0, mas1, mas2, mas3;
3138 if (bootinfo != NULL && bootinfo[0] != 1) {
3139 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3143 /* The first entry/entries are used to map the kernel. */
3144 for (i = 0; i < tlb1_idx; i++) {
3145 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3146 mtspr(SPR_MAS0, mas0);
3147 __asm __volatile("isync; tlbre");
3149 mas1 = mfspr(SPR_MAS1);
3150 if ((mas1 & MAS1_VALID) == 0)
3153 mas2 = mfspr(SPR_MAS2);
3154 mas3 = mfspr(SPR_MAS3);
3156 tlb1[i].mas1 = mas1;
3157 tlb1[i].mas2 = mfspr(SPR_MAS2);
3158 tlb1[i].mas3 = mas3;
3159 tlb1[i].virt = mas2 & MAS2_EPN_MASK;
3160 tlb1[i].phys = mas3 & MAS3_RPN;
3163 kernload = mas3 & MAS3_RPN;
3165 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3166 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0;
3167 kernsize += tlb1[i].size;
3171 bp_ntlb1s = tlb1_idx;
3174 /* Purge the remaining entries */
3175 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3176 tlb1_write_entry(i);
3178 /* Setup TLB miss defaults */
3179 set_mas4_defaults();
3183 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
3189 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
3191 for (i = 0; i < tlb1_idx; i++) {
3192 if (!(tlb1[i].mas1 & MAS1_VALID))
3194 if (pa >= tlb1[i].phys && (pa + size) <=
3195 (tlb1[i].phys + tlb1[i].size))
3196 return (tlb1[i].virt + (pa - tlb1[i].phys));
3199 pa_base = trunc_page(pa);
3200 size = roundup(size + (pa - pa_base), PAGE_SIZE);
3201 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
3202 va = tlb1_map_base + (pa - pa_base);
3205 sz = 1 << (ilog2(size) & ~1);
3206 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO);
3209 tlb1_map_base += sz;
3213 bp_ntlb1s = tlb1_idx;
3220 * Setup MAS4 defaults.
3221 * These values are loaded to MAS0-2 on a TLB miss.
3224 set_mas4_defaults(void)
3228 /* Defaults: TLB0, PID0, TSIZED=4K */
3229 mas4 = MAS4_TLBSELD0;
3230 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3234 mtspr(SPR_MAS4, mas4);
3235 __asm __volatile("isync");
3239 * Print out contents of the MAS registers for each TLB1 entry
3242 tlb1_print_tlbentries(void)
3244 uint32_t mas0, mas1, mas2, mas3, mas7;
3247 debugf("TLB1 entries:\n");
3248 for (i = 0; i < TLB1_ENTRIES; i++) {
3250 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3251 mtspr(SPR_MAS0, mas0);
3253 __asm __volatile("isync; tlbre");
3255 mas1 = mfspr(SPR_MAS1);
3256 mas2 = mfspr(SPR_MAS2);
3257 mas3 = mfspr(SPR_MAS3);
3258 mas7 = mfspr(SPR_MAS7);
3260 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3265 * Print out contents of the in-ram tlb1 table.
3268 tlb1_print_entries(void)
3272 debugf("tlb1[] table entries:\n");
3273 for (i = 0; i < TLB1_ENTRIES; i++)
3274 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3278 * Return 0 if the physical IO range is encompassed by one of the
3279 * the TLB1 entries, otherwise return related error code.
3282 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3285 vm_paddr_t pa_start;
3287 unsigned int entry_tsize;
3288 vm_size_t entry_size;
3290 *va = (vm_offset_t)NULL;
3292 /* Skip invalid entries */
3293 if (!(tlb1[i].mas1 & MAS1_VALID))
3297 * The entry must be cache-inhibited, guarded, and r/w
3298 * so it can function as an i/o page
3300 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3301 if (prot != (MAS2_I | MAS2_G))
3304 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3305 if (prot != (MAS3_SR | MAS3_SW))
3308 /* The address should be within the entry range. */
3309 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3310 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3312 entry_size = tsize2size(entry_tsize);
3313 pa_start = tlb1[i].mas3 & MAS3_RPN;
3314 pa_end = pa_start + entry_size - 1;
3316 if ((pa < pa_start) || ((pa + size) > pa_end))
3319 /* Return virtual address of this mapping. */
3320 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);