2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - ptbl_bufs-1 : message buffer
63 * ptbl_bufs - kernel_pdir-1 : kernel page tables
64 * kernel_pdir - kernel_pp2d-1 : kernel page directory
65 * kernel_pp2d - . : kernel pointers to page directory
66 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
67 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
68 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
69 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
70 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
71 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
72 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
73 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
74 * - 0xffff_ffff_ffff_ffff : device direct map
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD$");
81 #include "opt_kstack_pages.h"
83 #include <sys/param.h>
85 #include <sys/malloc.h>
89 #include <sys/queue.h>
90 #include <sys/systm.h>
91 #include <sys/kernel.h>
92 #include <sys/kerneldump.h>
93 #include <sys/linker.h>
94 #include <sys/msgbuf.h>
96 #include <sys/mutex.h>
97 #include <sys/rwlock.h>
98 #include <sys/sched.h>
100 #include <sys/vmmeter.h>
103 #include <vm/vm_page.h>
104 #include <vm/vm_kern.h>
105 #include <vm/vm_pageout.h>
106 #include <vm/vm_extern.h>
107 #include <vm/vm_object.h>
108 #include <vm/vm_param.h>
109 #include <vm/vm_map.h>
110 #include <vm/vm_pager.h>
111 #include <vm/vm_phys.h>
112 #include <vm/vm_pagequeue.h>
115 #include <machine/_inttypes.h>
116 #include <machine/cpu.h>
117 #include <machine/pcb.h>
118 #include <machine/platform.h>
120 #include <machine/tlb.h>
121 #include <machine/spr.h>
122 #include <machine/md_var.h>
123 #include <machine/mmuvar.h>
124 #include <machine/pmap.h>
125 #include <machine/pte.h>
131 #define SPARSE_MAPDEV
133 #define debugf(fmt, args...) printf(fmt, ##args)
135 #define debugf(fmt, args...)
139 #define PRI0ptrX "016lx"
141 #define PRI0ptrX "08x"
144 #define TODO panic("%s: not implemented", __func__);
146 extern unsigned char _etext[];
147 extern unsigned char _end[];
149 extern uint32_t *bootinfo;
152 vm_offset_t kernstart;
155 /* Message buffer and tables. */
156 static vm_offset_t data_start;
157 static vm_size_t data_end;
159 /* Phys/avail memory regions. */
160 static struct mem_region *availmem_regions;
161 static int availmem_regions_sz;
162 static struct mem_region *physmem_regions;
163 static int physmem_regions_sz;
165 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
166 static vm_offset_t zero_page_va;
167 static struct mtx zero_page_mutex;
169 static struct mtx tlbivax_mutex;
171 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
172 static vm_offset_t copy_page_src_va;
173 static vm_offset_t copy_page_dst_va;
174 static struct mtx copy_page_mutex;
176 /**************************************************************************/
178 /**************************************************************************/
180 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
181 vm_prot_t, u_int flags, int8_t psind);
183 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
184 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
186 unsigned int kernel_pdirs;
190 * If user pmap is processed with mmu_booke_remove and the resident count
191 * drops to 0, there are no more pages to remove, so we need not continue.
193 #define PMAP_REMOVE_DONE(pmap) \
194 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
196 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
197 extern int elf32_nxstack;
200 /**************************************************************************/
201 /* TLB and TID handling */
202 /**************************************************************************/
204 /* Translation ID busy table */
205 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
208 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
209 * core revisions and should be read from h/w registers during early config.
211 uint32_t tlb0_entries;
213 uint32_t tlb0_entries_per_way;
214 uint32_t tlb1_entries;
216 #define TLB0_ENTRIES (tlb0_entries)
217 #define TLB0_WAYS (tlb0_ways)
218 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
220 #define TLB1_ENTRIES (tlb1_entries)
222 static vm_offset_t tlb1_map_base = VM_MAXUSER_ADDRESS + PAGE_SIZE;
224 static tlbtid_t tid_alloc(struct pmap *);
225 static void tid_flush(tlbtid_t tid);
229 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
231 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
235 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
236 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
237 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
238 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
240 static vm_size_t tsize2size(unsigned int);
241 static unsigned int size2tsize(vm_size_t);
242 static unsigned int ilog2(unsigned long);
244 static void set_mas4_defaults(void);
246 static inline void tlb0_flush_entry(vm_offset_t);
247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
249 /**************************************************************************/
250 /* Page table management */
251 /**************************************************************************/
253 static struct rwlock_padalign pvh_global_lock;
255 /* Data for the pv entry allocation mechanism */
256 static uma_zone_t pvzone;
257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
261 #ifndef PMAP_SHPGPERPROC
262 #define PMAP_SHPGPERPROC 200
265 static void ptbl_init(void);
266 static struct ptbl_buf *ptbl_buf_alloc(void);
267 static void ptbl_buf_free(struct ptbl_buf *);
268 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
271 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **,
272 unsigned int, boolean_t);
273 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int);
274 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int);
275 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t);
277 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t);
278 static void ptbl_free(mmu_t, pmap_t, unsigned int);
279 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
280 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
283 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
284 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
285 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
286 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
287 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t);
289 static pv_entry_t pv_alloc(void);
290 static void pv_free(pv_entry_t);
291 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
292 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
294 static void booke_pmap_init_qpages(void);
296 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
298 #define PTBL_BUFS (16UL * 16 * 16)
300 #define PTBL_BUFS (128 * 16)
304 TAILQ_ENTRY(ptbl_buf) link; /* list link */
305 vm_offset_t kva; /* va of mapping */
308 /* ptbl free list and a lock used for access synchronization. */
309 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
310 static struct mtx ptbl_buf_freelist_lock;
312 /* Base address of kva space allocated fot ptbl bufs. */
313 static vm_offset_t ptbl_buf_pool_vabase;
315 /* Pointer to ptbl_buf structures. */
316 static struct ptbl_buf *ptbl_bufs;
319 extern tlb_entry_t __boot_tlb1[];
320 void pmap_bootstrap_ap(volatile uint32_t *);
324 * Kernel MMU interface
326 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
327 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
328 vm_size_t, vm_offset_t);
329 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
330 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
331 vm_offset_t, vm_page_t *, vm_offset_t, int);
332 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
333 vm_prot_t, u_int flags, int8_t psind);
334 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
335 vm_page_t, vm_prot_t);
336 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
338 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
339 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
341 static void mmu_booke_init(mmu_t);
342 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
343 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
344 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
345 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
346 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
348 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
350 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
351 vm_object_t, vm_pindex_t, vm_size_t);
352 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
353 static void mmu_booke_page_init(mmu_t, vm_page_t);
354 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
355 static void mmu_booke_pinit(mmu_t, pmap_t);
356 static void mmu_booke_pinit0(mmu_t, pmap_t);
357 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
359 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
360 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
361 static void mmu_booke_release(mmu_t, pmap_t);
362 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
363 static void mmu_booke_remove_all(mmu_t, vm_page_t);
364 static void mmu_booke_remove_write(mmu_t, vm_page_t);
365 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
366 static void mmu_booke_zero_page(mmu_t, vm_page_t);
367 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
368 static void mmu_booke_activate(mmu_t, struct thread *);
369 static void mmu_booke_deactivate(mmu_t, struct thread *);
370 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
371 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
372 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
373 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
374 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
375 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
376 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
377 static void mmu_booke_kremove(mmu_t, vm_offset_t);
378 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
379 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
381 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t,
383 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t,
385 static void mmu_booke_scan_init(mmu_t);
386 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m);
387 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr);
388 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr,
389 vm_size_t sz, vm_memattr_t mode);
390 static int mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm,
391 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
392 static int mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
393 int *is_user, vm_offset_t *decoded_addr);
396 static mmu_method_t mmu_booke_methods[] = {
397 /* pmap dispatcher interface */
398 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
399 MMUMETHOD(mmu_copy, mmu_booke_copy),
400 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
401 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
402 MMUMETHOD(mmu_enter, mmu_booke_enter),
403 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
404 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
405 MMUMETHOD(mmu_extract, mmu_booke_extract),
406 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
407 MMUMETHOD(mmu_init, mmu_booke_init),
408 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
409 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
410 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
411 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
412 MMUMETHOD(mmu_map, mmu_booke_map),
413 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
414 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
415 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
416 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
417 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
418 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
419 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
420 MMUMETHOD(mmu_protect, mmu_booke_protect),
421 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
422 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
423 MMUMETHOD(mmu_release, mmu_booke_release),
424 MMUMETHOD(mmu_remove, mmu_booke_remove),
425 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
426 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
427 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
428 MMUMETHOD(mmu_unwire, mmu_booke_unwire),
429 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
430 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
431 MMUMETHOD(mmu_activate, mmu_booke_activate),
432 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
433 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page),
434 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page),
436 /* Internal interfaces */
437 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
438 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
439 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
440 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
441 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
442 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
443 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
444 MMUMETHOD(mmu_kremove, mmu_booke_kremove),
445 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
446 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr),
447 MMUMETHOD(mmu_map_user_ptr, mmu_booke_map_user_ptr),
448 MMUMETHOD(mmu_decode_kernel_ptr, mmu_booke_decode_kernel_ptr),
450 /* dumpsys() support */
451 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
452 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
453 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init),
458 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
460 static __inline uint32_t
461 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
466 if (ma != VM_MEMATTR_DEFAULT) {
468 case VM_MEMATTR_UNCACHEABLE:
469 return (MAS2_I | MAS2_G);
470 case VM_MEMATTR_WRITE_COMBINING:
471 case VM_MEMATTR_WRITE_BACK:
472 case VM_MEMATTR_PREFETCHABLE:
474 case VM_MEMATTR_WRITE_THROUGH:
475 return (MAS2_W | MAS2_M);
476 case VM_MEMATTR_CACHEABLE:
482 * Assume the page is cache inhibited and access is guarded unless
483 * it's in our available memory array.
485 attrib = _TLB_ENTRY_IO;
486 for (i = 0; i < physmem_regions_sz; i++) {
487 if ((pa >= physmem_regions[i].mr_start) &&
488 (pa < (physmem_regions[i].mr_start +
489 physmem_regions[i].mr_size))) {
490 attrib = _TLB_ENTRY_MEM;
507 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
510 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
511 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
513 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
514 ("tlb_miss_lock: tried to lock self"));
516 tlb_lock(pc->pc_booke.tlb_lock);
518 CTR1(KTR_PMAP, "%s: locked", __func__);
525 tlb_miss_unlock(void)
533 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
535 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
536 __func__, pc->pc_cpuid);
538 tlb_unlock(pc->pc_booke.tlb_lock);
540 CTR1(KTR_PMAP, "%s: unlocked", __func__);
546 /* Return number of entries in TLB0. */
548 tlb0_get_tlbconf(void)
552 tlb0_cfg = mfspr(SPR_TLB0CFG);
553 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
554 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
555 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
558 /* Return number of entries in TLB1. */
560 tlb1_get_tlbconf(void)
564 tlb1_cfg = mfspr(SPR_TLB1CFG);
565 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
568 /**************************************************************************/
569 /* Page table related */
570 /**************************************************************************/
573 /* Initialize pool of kva ptbl buffers. */
579 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
580 TAILQ_INIT(&ptbl_buf_freelist);
582 for (i = 0; i < PTBL_BUFS; i++) {
583 ptbl_bufs[i].kva = ptbl_buf_pool_vabase +
584 i * MAX(PTBL_PAGES,PDIR_PAGES) * PAGE_SIZE;
585 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
589 /* Get an sf_buf from the freelist. */
590 static struct ptbl_buf *
593 struct ptbl_buf *buf;
595 mtx_lock(&ptbl_buf_freelist_lock);
596 buf = TAILQ_FIRST(&ptbl_buf_freelist);
598 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
599 mtx_unlock(&ptbl_buf_freelist_lock);
604 /* Return ptbl buff to free pool. */
606 ptbl_buf_free(struct ptbl_buf *buf)
608 mtx_lock(&ptbl_buf_freelist_lock);
609 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
610 mtx_unlock(&ptbl_buf_freelist_lock);
614 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
617 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t * ptbl)
619 struct ptbl_buf *pbuf;
621 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) {
622 if (pbuf->kva == (vm_offset_t) ptbl) {
623 /* Remove from pmap ptbl buf list. */
624 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
626 /* Free corresponding ptbl buf. */
634 /* Get a pointer to a PTE in a page table. */
635 static __inline pte_t *
636 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
641 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
643 pdir = pmap->pm_pp2d[PP2D_IDX(va)];
646 ptbl = pdir[PDIR_IDX(va)];
647 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL);
651 * Search the list of allocated pdir bufs and find on list of allocated pdirs
654 ptbl_free_pmap_pdir(mmu_t mmu, pmap_t pmap, pte_t ** pdir)
656 struct ptbl_buf *pbuf;
658 TAILQ_FOREACH(pbuf, &pmap->pm_pdir_list, link) {
659 if (pbuf->kva == (vm_offset_t) pdir) {
660 /* Remove from pmap ptbl buf list. */
661 TAILQ_REMOVE(&pmap->pm_pdir_list, pbuf, link);
663 /* Free corresponding pdir buf. */
670 /* Free pdir pages and invalidate pdir entry. */
672 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx)
680 pdir = pmap->pm_pp2d[pp2d_idx];
682 KASSERT((pdir != NULL), ("pdir_free: null pdir"));
684 pmap->pm_pp2d[pp2d_idx] = NULL;
686 for (i = 0; i < PDIR_PAGES; i++) {
687 va = ((vm_offset_t) pdir + (i * PAGE_SIZE));
688 pa = pte_vatopa(mmu, kernel_pmap, va);
689 m = PHYS_TO_VM_PAGE(pa);
690 vm_page_free_zero(m);
695 ptbl_free_pmap_pdir(mmu, pmap, pdir);
699 * Decrement pdir pages hold count and attempt to free pdir pages. Called
700 * when removing directory entry from pdir.
702 * Return 1 if pdir pages were freed.
705 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx)
712 KASSERT((pmap != kernel_pmap),
713 ("pdir_unhold: unholding kernel pdir!"));
715 pdir = pmap->pm_pp2d[pp2d_idx];
717 KASSERT(((vm_offset_t) pdir >= VM_MIN_KERNEL_ADDRESS),
718 ("pdir_unhold: non kva pdir"));
720 /* decrement hold count */
721 for (i = 0; i < PDIR_PAGES; i++) {
722 pa = pte_vatopa(mmu, kernel_pmap,
723 (vm_offset_t) pdir + (i * PAGE_SIZE));
724 m = PHYS_TO_VM_PAGE(pa);
729 * Free pdir pages if there are no dir entries in this pdir.
730 * wire_count has the same value for all ptbl pages, so check the
733 if (m->wire_count == 0) {
734 pdir_free(mmu, pmap, pp2d_idx);
741 * Increment hold count for pdir pages. This routine is used when new ptlb
742 * entry is being inserted into pdir.
745 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir)
751 KASSERT((pmap != kernel_pmap),
752 ("pdir_hold: holding kernel pdir!"));
754 KASSERT((pdir != NULL), ("pdir_hold: null pdir"));
756 for (i = 0; i < PDIR_PAGES; i++) {
757 pa = pte_vatopa(mmu, kernel_pmap,
758 (vm_offset_t) pdir + (i * PAGE_SIZE));
759 m = PHYS_TO_VM_PAGE(pa);
764 /* Allocate page table. */
766 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx,
769 vm_page_t mtbl [PTBL_PAGES];
771 struct ptbl_buf *pbuf;
777 KASSERT((pdir[pdir_idx] == NULL),
778 ("%s: valid ptbl entry exists!", __func__));
780 pbuf = ptbl_buf_alloc();
782 panic("%s: couldn't alloc kernel virtual memory", __func__);
784 ptbl = (pte_t *) pbuf->kva;
786 for (i = 0; i < PTBL_PAGES; i++) {
787 pidx = (PTBL_PAGES * pdir_idx) + i;
788 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
789 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) {
791 rw_wunlock(&pvh_global_lock);
793 ptbl_free_pmap_ptbl(pmap, ptbl);
794 for (j = 0; j < i; j++)
795 vm_page_free(mtbl[j]);
800 rw_wlock(&pvh_global_lock);
806 /* Mapin allocated pages into kernel_pmap. */
807 mmu_booke_qenter(mmu, (vm_offset_t) ptbl, mtbl, PTBL_PAGES);
808 /* Zero whole ptbl. */
809 bzero((caddr_t) ptbl, PTBL_PAGES * PAGE_SIZE);
811 /* Add pbuf to the pmap ptbl bufs list. */
812 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
817 /* Free ptbl pages and invalidate pdir entry. */
819 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx)
827 ptbl = pdir[pdir_idx];
829 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
831 pdir[pdir_idx] = NULL;
833 for (i = 0; i < PTBL_PAGES; i++) {
834 va = ((vm_offset_t) ptbl + (i * PAGE_SIZE));
835 pa = pte_vatopa(mmu, kernel_pmap, va);
836 m = PHYS_TO_VM_PAGE(pa);
837 vm_page_free_zero(m);
842 ptbl_free_pmap_ptbl(pmap, ptbl);
846 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called
847 * when removing pte entry from ptbl.
849 * Return 1 if ptbl pages were freed.
852 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va)
862 pp2d_idx = PP2D_IDX(va);
863 pdir_idx = PDIR_IDX(va);
865 KASSERT((pmap != kernel_pmap),
866 ("ptbl_unhold: unholding kernel ptbl!"));
868 pdir = pmap->pm_pp2d[pp2d_idx];
869 ptbl = pdir[pdir_idx];
871 KASSERT(((vm_offset_t) ptbl >= VM_MIN_KERNEL_ADDRESS),
872 ("ptbl_unhold: non kva ptbl"));
874 /* decrement hold count */
875 for (i = 0; i < PTBL_PAGES; i++) {
876 pa = pte_vatopa(mmu, kernel_pmap,
877 (vm_offset_t) ptbl + (i * PAGE_SIZE));
878 m = PHYS_TO_VM_PAGE(pa);
883 * Free ptbl pages if there are no pte entries in this ptbl.
884 * wire_count has the same value for all ptbl pages, so check the
887 if (m->wire_count == 0) {
888 /* A pair of indirect entries might point to this ptbl page */
890 tlb_flush_entry(pmap, va & ~((2UL * PAGE_SIZE_1M) - 1),
891 TLB_SIZE_1M, MAS6_SIND);
892 tlb_flush_entry(pmap, (va & ~((2UL * PAGE_SIZE_1M) - 1)) | PAGE_SIZE_1M,
893 TLB_SIZE_1M, MAS6_SIND);
895 ptbl_free(mmu, pmap, pdir, pdir_idx);
896 pdir_unhold(mmu, pmap, pp2d_idx);
903 * Increment hold count for ptbl pages. This routine is used when new pte
904 * entry is being inserted into ptbl.
907 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx)
914 KASSERT((pmap != kernel_pmap),
915 ("ptbl_hold: holding kernel ptbl!"));
917 ptbl = pdir[pdir_idx];
919 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
921 for (i = 0; i < PTBL_PAGES; i++) {
922 pa = pte_vatopa(mmu, kernel_pmap,
923 (vm_offset_t) ptbl + (i * PAGE_SIZE));
924 m = PHYS_TO_VM_PAGE(pa);
930 /* Initialize pool of kva ptbl buffers. */
936 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
937 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
938 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
939 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
941 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
942 TAILQ_INIT(&ptbl_buf_freelist);
944 for (i = 0; i < PTBL_BUFS; i++) {
946 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
947 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
951 /* Get a ptbl_buf from the freelist. */
952 static struct ptbl_buf *
955 struct ptbl_buf *buf;
957 mtx_lock(&ptbl_buf_freelist_lock);
958 buf = TAILQ_FIRST(&ptbl_buf_freelist);
960 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
961 mtx_unlock(&ptbl_buf_freelist_lock);
963 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
968 /* Return ptbl buff to free pool. */
970 ptbl_buf_free(struct ptbl_buf *buf)
973 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
975 mtx_lock(&ptbl_buf_freelist_lock);
976 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
977 mtx_unlock(&ptbl_buf_freelist_lock);
981 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
984 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
986 struct ptbl_buf *pbuf;
988 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
990 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
992 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
993 if (pbuf->kva == (vm_offset_t)ptbl) {
994 /* Remove from pmap ptbl buf list. */
995 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
997 /* Free corresponding ptbl buf. */
1003 /* Allocate page table. */
1005 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
1007 vm_page_t mtbl[PTBL_PAGES];
1009 struct ptbl_buf *pbuf;
1014 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
1015 (pmap == kernel_pmap), pdir_idx);
1017 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1018 ("ptbl_alloc: invalid pdir_idx"));
1019 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
1020 ("pte_alloc: valid ptbl entry exists!"));
1022 pbuf = ptbl_buf_alloc();
1024 panic("pte_alloc: couldn't alloc kernel virtual memory");
1026 ptbl = (pte_t *)pbuf->kva;
1028 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
1030 for (i = 0; i < PTBL_PAGES; i++) {
1031 pidx = (PTBL_PAGES * pdir_idx) + i;
1032 while ((m = vm_page_alloc(NULL, pidx,
1033 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
1035 rw_wunlock(&pvh_global_lock);
1037 ptbl_free_pmap_ptbl(pmap, ptbl);
1038 for (j = 0; j < i; j++)
1039 vm_page_free(mtbl[j]);
1044 rw_wlock(&pvh_global_lock);
1050 /* Map allocated pages into kernel_pmap. */
1051 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
1053 /* Zero whole ptbl. */
1054 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
1056 /* Add pbuf to the pmap ptbl bufs list. */
1057 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
1062 /* Free ptbl pages and invalidate pdir entry. */
1064 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1072 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
1073 (pmap == kernel_pmap), pdir_idx);
1075 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1076 ("ptbl_free: invalid pdir_idx"));
1078 ptbl = pmap->pm_pdir[pdir_idx];
1080 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
1082 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
1085 * Invalidate the pdir entry as soon as possible, so that other CPUs
1086 * don't attempt to look up the page tables we are releasing.
1088 mtx_lock_spin(&tlbivax_mutex);
1091 pmap->pm_pdir[pdir_idx] = NULL;
1094 mtx_unlock_spin(&tlbivax_mutex);
1096 for (i = 0; i < PTBL_PAGES; i++) {
1097 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
1098 pa = pte_vatopa(mmu, kernel_pmap, va);
1099 m = PHYS_TO_VM_PAGE(pa);
1100 vm_page_free_zero(m);
1102 mmu_booke_kremove(mmu, va);
1105 ptbl_free_pmap_ptbl(pmap, ptbl);
1109 * Decrement ptbl pages hold count and attempt to free ptbl pages.
1110 * Called when removing pte entry from ptbl.
1112 * Return 1 if ptbl pages were freed.
1115 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1122 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
1123 (pmap == kernel_pmap), pdir_idx);
1125 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1126 ("ptbl_unhold: invalid pdir_idx"));
1127 KASSERT((pmap != kernel_pmap),
1128 ("ptbl_unhold: unholding kernel ptbl!"));
1130 ptbl = pmap->pm_pdir[pdir_idx];
1132 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
1133 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
1134 ("ptbl_unhold: non kva ptbl"));
1136 /* decrement hold count */
1137 for (i = 0; i < PTBL_PAGES; i++) {
1138 pa = pte_vatopa(mmu, kernel_pmap,
1139 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1140 m = PHYS_TO_VM_PAGE(pa);
1145 * Free ptbl pages if there are no pte etries in this ptbl.
1146 * wire_count has the same value for all ptbl pages, so check the last
1149 if (m->wire_count == 0) {
1150 ptbl_free(mmu, pmap, pdir_idx);
1152 //debugf("ptbl_unhold: e (freed ptbl)\n");
1160 * Increment hold count for ptbl pages. This routine is used when a new pte
1161 * entry is being inserted into the ptbl.
1164 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1171 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
1174 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1175 ("ptbl_hold: invalid pdir_idx"));
1176 KASSERT((pmap != kernel_pmap),
1177 ("ptbl_hold: holding kernel ptbl!"));
1179 ptbl = pmap->pm_pdir[pdir_idx];
1181 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
1183 for (i = 0; i < PTBL_PAGES; i++) {
1184 pa = pte_vatopa(mmu, kernel_pmap,
1185 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1186 m = PHYS_TO_VM_PAGE(pa);
1192 /* Allocate pv_entry structure. */
1199 if (pv_entry_count > pv_entry_high_water)
1200 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
1201 pv = uma_zalloc(pvzone, M_NOWAIT);
1206 /* Free pv_entry structure. */
1207 static __inline void
1208 pv_free(pv_entry_t pve)
1212 uma_zfree(pvzone, pve);
1216 /* Allocate and initialize pv_entry structure. */
1218 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
1222 //int su = (pmap == kernel_pmap);
1223 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
1224 // (u_int32_t)pmap, va, (u_int32_t)m);
1228 panic("pv_insert: no pv entries!");
1230 pve->pv_pmap = pmap;
1233 /* add to pv_list */
1234 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1235 rw_assert(&pvh_global_lock, RA_WLOCKED);
1237 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
1239 //debugf("pv_insert: e\n");
1242 /* Destroy pv entry. */
1244 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
1248 //int su = (pmap == kernel_pmap);
1249 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
1251 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1252 rw_assert(&pvh_global_lock, RA_WLOCKED);
1255 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
1256 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
1257 /* remove from pv_list */
1258 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
1259 if (TAILQ_EMPTY(&m->md.pv_list))
1260 vm_page_aflag_clear(m, PGA_WRITEABLE);
1262 /* free pv entry struct */
1268 //debugf("pv_remove: e\n");
1271 #ifdef __powerpc64__
1273 * Clean pte entry, try to free page table page if requested.
1275 * Return 1 if ptbl pages were freed, otherwise return 0.
1278 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags)
1283 pte = pte_find(mmu, pmap, va);
1284 KASSERT(pte != NULL, ("%s: NULL pte", __func__));
1286 if (!PTE_ISVALID(pte))
1289 /* Get vm_page_t for mapped pte. */
1290 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1292 if (PTE_ISWIRED(pte))
1293 pmap->pm_stats.wired_count--;
1295 /* Handle managed entry. */
1296 if (PTE_ISMANAGED(pte)) {
1298 /* Handle modified pages. */
1299 if (PTE_ISMODIFIED(pte))
1302 /* Referenced pages. */
1303 if (PTE_ISREFERENCED(pte))
1304 vm_page_aflag_set(m, PGA_REFERENCED);
1306 /* Remove pv_entry from pv_list. */
1307 pv_remove(pmap, va, m);
1308 } else if (m->md.pv_tracked) {
1309 pv_remove(pmap, va, m);
1310 if (TAILQ_EMPTY(&m->md.pv_list))
1311 m->md.pv_tracked = false;
1313 mtx_lock_spin(&tlbivax_mutex);
1316 tlb0_flush_entry(va);
1320 mtx_unlock_spin(&tlbivax_mutex);
1322 pmap->pm_stats.resident_count--;
1324 if (flags & PTBL_UNHOLD) {
1325 return (ptbl_unhold(mmu, pmap, va));
1331 * allocate a page of pointers to page directories, do not preallocate the
1335 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep)
1337 vm_page_t mtbl [PDIR_PAGES];
1339 struct ptbl_buf *pbuf;
1345 pbuf = ptbl_buf_alloc();
1348 panic("%s: couldn't alloc kernel virtual memory", __func__);
1350 /* Allocate pdir pages, this will sleep! */
1351 for (i = 0; i < PDIR_PAGES; i++) {
1352 pidx = (PDIR_PAGES * pp2d_idx) + i;
1353 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
1354 while ((m = vm_page_alloc(NULL, pidx, req)) == NULL) {
1362 /* Mapin allocated pages into kernel_pmap. */
1363 pdir = (pte_t **) pbuf->kva;
1364 pmap_qenter((vm_offset_t) pdir, mtbl, PDIR_PAGES);
1366 /* Zero whole pdir. */
1367 bzero((caddr_t) pdir, PDIR_PAGES * PAGE_SIZE);
1369 /* Add pdir to the pmap pdir bufs list. */
1370 TAILQ_INSERT_TAIL(&pmap->pm_pdir_list, pbuf, link);
1376 * Insert PTE for a given page and virtual address.
1379 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1382 unsigned int pp2d_idx = PP2D_IDX(va);
1383 unsigned int pdir_idx = PDIR_IDX(va);
1384 unsigned int ptbl_idx = PTBL_IDX(va);
1385 pte_t *ptbl, *pte, pte_tmp;
1388 /* Get the page directory pointer. */
1389 pdir = pmap->pm_pp2d[pp2d_idx];
1391 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep);
1393 /* Get the page table pointer. */
1394 ptbl = pdir[pdir_idx];
1397 /* Allocate page table pages. */
1398 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep);
1400 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1403 pte = &ptbl[ptbl_idx];
1406 * Check if there is valid mapping for requested va, if there
1409 pte = &ptbl[ptbl_idx];
1410 if (PTE_ISVALID(pte)) {
1411 pte_remove(mmu, pmap, va, PTBL_HOLD);
1414 * pte is not used, increment hold count for ptbl
1417 if (pmap != kernel_pmap)
1418 ptbl_hold(mmu, pmap, pdir, pdir_idx);
1422 if (pdir[pdir_idx] == NULL) {
1423 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL)
1424 pdir_hold(mmu, pmap, pdir);
1425 pdir[pdir_idx] = ptbl;
1427 if (pmap->pm_pp2d[pp2d_idx] == NULL)
1428 pmap->pm_pp2d[pp2d_idx] = pdir;
1431 * Insert pv_entry into pv_list for mapped page if part of managed
1434 if ((m->oflags & VPO_UNMANAGED) == 0) {
1435 flags |= PTE_MANAGED;
1437 /* Create and insert pv entry. */
1438 pv_insert(pmap, va, m);
1441 pmap->pm_stats.resident_count++;
1443 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1444 pte_tmp |= (PTE_VALID | flags);
1446 mtx_lock_spin(&tlbivax_mutex);
1449 tlb0_flush_entry(va);
1453 mtx_unlock_spin(&tlbivax_mutex);
1458 /* Return the pa for the given pmap/va. */
1460 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1465 pte = pte_find(mmu, pmap, va);
1466 if ((pte != NULL) && PTE_ISVALID(pte))
1467 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1472 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */
1474 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1481 /* Initialize kernel pdir */
1482 for (i = 0; i < kernel_pdirs; i++) {
1483 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] =
1484 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES));
1485 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES));
1486 j < PDIR_NENTRIES; j++) {
1487 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] =
1488 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE * PDIR_PAGES) +
1489 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE * PTBL_PAGES));
1494 * Fill in PTEs covering kernel code and data. They are not required
1495 * for address translation, as this area is covered by static TLB1
1496 * entries, but for pte_vatopa() to work correctly with kernel area
1499 for (va = addr; va < data_end; va += PAGE_SIZE) {
1500 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]);
1501 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1502 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1503 PTE_VALID | PTE_PS_4KB;
1508 * Clean pte entry, try to free page table page if requested.
1510 * Return 1 if ptbl pages were freed, otherwise return 0.
1513 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
1515 unsigned int pdir_idx = PDIR_IDX(va);
1516 unsigned int ptbl_idx = PTBL_IDX(va);
1521 //int su = (pmap == kernel_pmap);
1522 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
1523 // su, (u_int32_t)pmap, va, flags);
1525 ptbl = pmap->pm_pdir[pdir_idx];
1526 KASSERT(ptbl, ("pte_remove: null ptbl"));
1528 pte = &ptbl[ptbl_idx];
1530 if (pte == NULL || !PTE_ISVALID(pte))
1533 if (PTE_ISWIRED(pte))
1534 pmap->pm_stats.wired_count--;
1536 /* Get vm_page_t for mapped pte. */
1537 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1539 /* Handle managed entry. */
1540 if (PTE_ISMANAGED(pte)) {
1542 if (PTE_ISMODIFIED(pte))
1545 if (PTE_ISREFERENCED(pte))
1546 vm_page_aflag_set(m, PGA_REFERENCED);
1548 pv_remove(pmap, va, m);
1549 } else if (m->md.pv_tracked) {
1551 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is
1552 * used. This is needed by the NCSW support code for fast
1553 * VA<->PA translation.
1555 pv_remove(pmap, va, m);
1556 if (TAILQ_EMPTY(&m->md.pv_list))
1557 m->md.pv_tracked = false;
1560 mtx_lock_spin(&tlbivax_mutex);
1563 tlb0_flush_entry(va);
1567 mtx_unlock_spin(&tlbivax_mutex);
1569 pmap->pm_stats.resident_count--;
1571 if (flags & PTBL_UNHOLD) {
1572 //debugf("pte_remove: e (unhold)\n");
1573 return (ptbl_unhold(mmu, pmap, pdir_idx));
1576 //debugf("pte_remove: e\n");
1581 * Insert PTE for a given page and virtual address.
1584 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1587 unsigned int pdir_idx = PDIR_IDX(va);
1588 unsigned int ptbl_idx = PTBL_IDX(va);
1589 pte_t *ptbl, *pte, pte_tmp;
1591 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
1592 pmap == kernel_pmap, pmap, va);
1594 /* Get the page table pointer. */
1595 ptbl = pmap->pm_pdir[pdir_idx];
1598 /* Allocate page table pages. */
1599 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
1601 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1604 pmap->pm_pdir[pdir_idx] = ptbl;
1605 pte = &ptbl[ptbl_idx];
1608 * Check if there is valid mapping for requested
1609 * va, if there is, remove it.
1611 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
1612 if (PTE_ISVALID(pte)) {
1613 pte_remove(mmu, pmap, va, PTBL_HOLD);
1616 * pte is not used, increment hold count
1619 if (pmap != kernel_pmap)
1620 ptbl_hold(mmu, pmap, pdir_idx);
1625 * Insert pv_entry into pv_list for mapped page if part of managed
1628 if ((m->oflags & VPO_UNMANAGED) == 0) {
1629 flags |= PTE_MANAGED;
1631 /* Create and insert pv entry. */
1632 pv_insert(pmap, va, m);
1635 pmap->pm_stats.resident_count++;
1637 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1638 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
1640 mtx_lock_spin(&tlbivax_mutex);
1643 tlb0_flush_entry(va);
1647 mtx_unlock_spin(&tlbivax_mutex);
1651 /* Return the pa for the given pmap/va. */
1653 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1658 pte = pte_find(mmu, pmap, va);
1659 if ((pte != NULL) && PTE_ISVALID(pte))
1660 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1664 /* Get a pointer to a PTE in a page table. */
1666 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1668 unsigned int pdir_idx = PDIR_IDX(va);
1669 unsigned int ptbl_idx = PTBL_IDX(va);
1671 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
1673 if (pmap->pm_pdir[pdir_idx])
1674 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
1679 /* Set up kernel page tables. */
1681 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1687 /* Initialize kernel pdir */
1688 for (i = 0; i < kernel_ptbls; i++)
1689 kernel_pmap->pm_pdir[kptbl_min + i] =
1690 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES));
1693 * Fill in PTEs covering kernel code and data. They are not required
1694 * for address translation, as this area is covered by static TLB1
1695 * entries, but for pte_vatopa() to work correctly with kernel area
1698 for (va = addr; va < data_end; va += PAGE_SIZE) {
1699 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1700 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1701 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1702 PTE_VALID | PTE_PS_4KB;
1707 /**************************************************************************/
1709 /**************************************************************************/
1712 * This is called during booke_init, before the system is really initialized.
1715 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1717 vm_paddr_t phys_kernelend;
1718 struct mem_region *mp, *mp1;
1720 vm_paddr_t s, e, sz;
1721 vm_paddr_t physsz, hwphyssz;
1722 u_int phys_avail_count;
1723 vm_size_t kstack0_sz;
1724 vm_offset_t kernel_pdir, kstack0;
1725 vm_paddr_t kstack0_phys;
1728 debugf("mmu_booke_bootstrap: entered\n");
1730 /* Set interesting system properties */
1731 #ifdef __powerpc64__
1736 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
1740 /* Initialize invalidation mutex */
1741 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1743 /* Read TLB0 size and associativity. */
1747 * Align kernel start and end address (kernel image).
1748 * Note that kernel end does not necessarily relate to kernsize.
1749 * kernsize is the size of the kernel that is actually mapped.
1751 kernstart = trunc_page(start);
1752 data_start = round_page(kernelend);
1753 data_end = data_start;
1755 /* Allocate the dynamic per-cpu area. */
1756 dpcpu = (void *)data_end;
1757 data_end += DPCPU_SIZE;
1759 /* Allocate space for the message buffer. */
1760 msgbufp = (struct msgbuf *)data_end;
1761 data_end += msgbufsize;
1762 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1763 (uintptr_t)msgbufp, data_end);
1765 data_end = round_page(data_end);
1767 /* Allocate space for ptbl_bufs. */
1768 ptbl_bufs = (struct ptbl_buf *)data_end;
1769 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1770 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1771 (uintptr_t)ptbl_bufs, data_end);
1773 data_end = round_page(data_end);
1775 /* Allocate PTE tables for kernel KVA. */
1776 kernel_pdir = data_end;
1777 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS,
1779 #ifdef __powerpc64__
1780 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES);
1781 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE;
1783 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1784 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1785 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1786 kernel_pdir, data_end);
1788 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
1789 if (data_end - kernstart > kernsize) {
1790 kernsize += tlb1_mapin_region(kernstart + kernsize,
1791 kernload + kernsize, (data_end - kernstart) - kernsize);
1793 data_end = kernstart + kernsize;
1794 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
1797 * Clear the structures - note we can only do it safely after the
1798 * possible additional TLB1 translations are in place (above) so that
1799 * all range up to the currently calculated 'data_end' is covered.
1801 dpcpu_init(dpcpu, 0);
1802 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1803 #ifdef __powerpc64__
1804 memset((void *)kernel_pdir, 0,
1805 kernel_pdirs * PDIR_PAGES * PAGE_SIZE +
1806 kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1808 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1811 /*******************************************************/
1812 /* Set the start and end of kva. */
1813 /*******************************************************/
1814 virtual_avail = round_page(data_end);
1815 virtual_end = VM_MAX_KERNEL_ADDRESS;
1817 /* Allocate KVA space for page zero/copy operations. */
1818 zero_page_va = virtual_avail;
1819 virtual_avail += PAGE_SIZE;
1820 copy_page_src_va = virtual_avail;
1821 virtual_avail += PAGE_SIZE;
1822 copy_page_dst_va = virtual_avail;
1823 virtual_avail += PAGE_SIZE;
1824 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
1825 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
1826 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
1828 /* Initialize page zero/copy mutexes. */
1829 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1830 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1832 /* Allocate KVA space for ptbl bufs. */
1833 ptbl_buf_pool_vabase = virtual_avail;
1834 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1835 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1836 ptbl_buf_pool_vabase, virtual_avail);
1838 /* Calculate corresponding physical addresses for the kernel region. */
1839 phys_kernelend = kernload + kernsize;
1840 debugf("kernel image and allocated data:\n");
1841 debugf(" kernload = 0x%09llx\n", (uint64_t)kernload);
1842 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
1843 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
1846 * Remove kernel physical address range from avail regions list. Page
1847 * align all regions. Non-page aligned memory isn't very interesting
1848 * to us. Also, sort the entries for ascending addresses.
1851 /* Retrieve phys/avail mem regions */
1852 mem_regions(&physmem_regions, &physmem_regions_sz,
1853 &availmem_regions, &availmem_regions_sz);
1855 if (nitems(phys_avail) < availmem_regions_sz)
1856 panic("mmu_booke_bootstrap: phys_avail too small");
1859 cnt = availmem_regions_sz;
1860 debugf("processing avail regions:\n");
1861 for (mp = availmem_regions; mp->mr_size; mp++) {
1863 e = mp->mr_start + mp->mr_size;
1864 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
1865 /* Check whether this region holds all of the kernel. */
1866 if (s < kernload && e > phys_kernelend) {
1867 availmem_regions[cnt].mr_start = phys_kernelend;
1868 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1871 /* Look whether this regions starts within the kernel. */
1872 if (s >= kernload && s < phys_kernelend) {
1873 if (e <= phys_kernelend)
1877 /* Now look whether this region ends within the kernel. */
1878 if (e > kernload && e <= phys_kernelend) {
1883 /* Now page align the start and size of the region. */
1889 debugf("%09jx-%09jx = %jx\n",
1890 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
1892 /* Check whether some memory is left here. */
1896 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1902 /* Do an insertion sort. */
1903 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1904 if (s < mp1->mr_start)
1907 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1915 availmem_regions_sz = cnt;
1917 /*******************************************************/
1918 /* Steal physical memory for kernel stack from the end */
1919 /* of the first avail region */
1920 /*******************************************************/
1921 kstack0_sz = kstack_pages * PAGE_SIZE;
1922 kstack0_phys = availmem_regions[0].mr_start +
1923 availmem_regions[0].mr_size;
1924 kstack0_phys -= kstack0_sz;
1925 availmem_regions[0].mr_size -= kstack0_sz;
1927 /*******************************************************/
1928 /* Fill in phys_avail table, based on availmem_regions */
1929 /*******************************************************/
1930 phys_avail_count = 0;
1933 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1935 debugf("fill in phys_avail:\n");
1936 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1938 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
1939 (uintmax_t)availmem_regions[i].mr_start,
1940 (uintmax_t)availmem_regions[i].mr_start +
1941 availmem_regions[i].mr_size,
1942 (uintmax_t)availmem_regions[i].mr_size);
1944 if (hwphyssz != 0 &&
1945 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1946 debugf(" hw.physmem adjust\n");
1947 if (physsz < hwphyssz) {
1948 phys_avail[j] = availmem_regions[i].mr_start;
1950 availmem_regions[i].mr_start +
1958 phys_avail[j] = availmem_regions[i].mr_start;
1959 phys_avail[j + 1] = availmem_regions[i].mr_start +
1960 availmem_regions[i].mr_size;
1962 physsz += availmem_regions[i].mr_size;
1964 physmem = btoc(physsz);
1966 /* Calculate the last available physical address. */
1967 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1969 Maxmem = powerpc_btop(phys_avail[i + 1]);
1971 debugf("Maxmem = 0x%08lx\n", Maxmem);
1972 debugf("phys_avail_count = %d\n", phys_avail_count);
1973 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
1974 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
1976 #ifdef __powerpc64__
1978 * Map the physical memory contiguously in TLB1.
1979 * Round so it fits into a single mapping.
1981 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
1985 /*******************************************************/
1986 /* Initialize (statically allocated) kernel pmap. */
1987 /*******************************************************/
1988 PMAP_LOCK_INIT(kernel_pmap);
1989 #ifndef __powerpc64__
1990 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1993 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
1994 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir);
1995 for (i = 0; i < MAXCPU; i++) {
1996 kernel_pmap->pm_tid[i] = TID_KERNEL;
1998 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1999 tidbusy[i][TID_KERNEL] = kernel_pmap;
2002 /* Mark kernel_pmap active on all CPUs */
2003 CPU_FILL(&kernel_pmap->pm_active);
2006 * Initialize the global pv list lock.
2008 rw_init(&pvh_global_lock, "pmap pv global");
2010 /*******************************************************/
2012 /*******************************************************/
2014 /* Enter kstack0 into kernel map, provide guard page */
2015 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
2016 thread0.td_kstack = kstack0;
2017 thread0.td_kstack_pages = kstack_pages;
2019 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
2020 debugf("kstack0_phys at 0x%09llx - 0x%09llx\n",
2021 kstack0_phys, kstack0_phys + kstack0_sz);
2022 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
2023 kstack0, kstack0 + kstack0_sz);
2025 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
2026 for (i = 0; i < kstack_pages; i++) {
2027 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
2028 kstack0 += PAGE_SIZE;
2029 kstack0_phys += PAGE_SIZE;
2032 pmap_bootstrapped = 1;
2034 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
2035 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
2037 debugf("mmu_booke_bootstrap: exit\n");
2044 tlb_entry_t *e, tmp;
2047 /* Prepare TLB1 image for AP processors */
2049 for (i = 0; i < TLB1_ENTRIES; i++) {
2050 tlb1_read_entry(&tmp, i);
2052 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
2053 memcpy(e++, &tmp, sizeof(tmp));
2058 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
2063 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
2064 * have the snapshot of its contents in the s/w __boot_tlb1[] table
2065 * created by tlb1_ap_prep(), so use these values directly to
2066 * (re)program AP's TLB1 hardware.
2068 * Start at index 1 because index 0 has the kernel map.
2070 for (i = 1; i < TLB1_ENTRIES; i++) {
2071 if (__boot_tlb1[i].mas1 & MAS1_VALID)
2072 tlb1_write_entry(&__boot_tlb1[i], i);
2075 set_mas4_defaults();
2080 booke_pmap_init_qpages(void)
2087 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
2088 if (pc->pc_qmap_addr == 0)
2089 panic("pmap_init_qpages: unable to allocate KVA");
2093 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
2096 * Get the physical page address for the given pmap/virtual address.
2099 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
2104 pa = pte_vatopa(mmu, pmap, va);
2111 * Extract the physical page address associated with the given
2112 * kernel virtual address.
2115 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
2121 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
2122 p = pte_vatopa(mmu, kernel_pmap, va);
2125 /* Check TLB1 mappings */
2126 for (i = 0; i < TLB1_ENTRIES; i++) {
2127 tlb1_read_entry(&e, i);
2128 if (!(e.mas1 & MAS1_VALID))
2130 if (va >= e.virt && va < e.virt + e.size)
2131 return (e.phys + (va - e.virt));
2139 * Initialize the pmap module.
2140 * Called by vm_init, to initialize any structures that the pmap
2141 * system needs to map virtual memory.
2144 mmu_booke_init(mmu_t mmu)
2146 int shpgperproc = PMAP_SHPGPERPROC;
2149 * Initialize the address space (zone) for the pv entries. Set a
2150 * high water mark so that the system can recover from excessive
2151 * numbers of pv entries.
2153 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
2154 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
2156 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
2157 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
2159 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
2160 pv_entry_high_water = 9 * (pv_entry_max / 10);
2162 uma_zone_reserve_kva(pvzone, pv_entry_max);
2164 /* Pre-fill pvzone with initial number of pv entries. */
2165 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
2167 /* Initialize ptbl allocation. */
2172 * Map a list of wired pages into kernel virtual address space. This is
2173 * intended for temporary mappings which do not need page modification or
2174 * references recorded. Existing mappings in the region are overwritten.
2177 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
2182 while (count-- > 0) {
2183 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2190 * Remove page mappings from kernel virtual address space. Intended for
2191 * temporary mappings entered by mmu_booke_qenter.
2194 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
2199 while (count-- > 0) {
2200 mmu_booke_kremove(mmu, va);
2206 * Map a wired page into kernel virtual address space.
2209 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
2212 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
2216 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
2221 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2222 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
2224 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
2225 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
2226 flags |= PTE_PS_4KB;
2228 pte = pte_find(mmu, kernel_pmap, va);
2229 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
2231 mtx_lock_spin(&tlbivax_mutex);
2234 if (PTE_ISVALID(pte)) {
2236 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
2238 /* Flush entry from TLB0 */
2239 tlb0_flush_entry(va);
2242 *pte = PTE_RPN_FROM_PA(pa) | flags;
2244 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
2245 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
2246 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
2248 /* Flush the real memory from the instruction cache. */
2249 if ((flags & (PTE_I | PTE_G)) == 0)
2250 __syncicache((void *)va, PAGE_SIZE);
2253 mtx_unlock_spin(&tlbivax_mutex);
2257 * Remove a page from kernel page table.
2260 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
2264 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
2266 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2267 (va <= VM_MAX_KERNEL_ADDRESS)),
2268 ("mmu_booke_kremove: invalid va"));
2270 pte = pte_find(mmu, kernel_pmap, va);
2272 if (!PTE_ISVALID(pte)) {
2274 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
2279 mtx_lock_spin(&tlbivax_mutex);
2282 /* Invalidate entry in TLB0, update PTE. */
2283 tlb0_flush_entry(va);
2287 mtx_unlock_spin(&tlbivax_mutex);
2291 * Provide a kernel pointer corresponding to a given userland pointer.
2292 * The returned pointer is valid until the next time this function is
2293 * called in this thread. This is used internally in copyin/copyout.
2296 mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
2297 void **kaddr, size_t ulen, size_t *klen)
2300 if ((uintptr_t)uaddr + ulen > VM_MAXUSER_ADDRESS + PAGE_SIZE)
2303 *kaddr = (void *)(uintptr_t)uaddr;
2311 * Figure out where a given kernel pointer (usually in a fault) points
2312 * to from the VM's perspective, potentially remapping into userland's
2316 mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
2317 vm_offset_t *decoded_addr)
2320 if (addr < VM_MAXUSER_ADDRESS)
2325 *decoded_addr = addr;
2330 * Initialize pmap associated with process 0.
2333 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
2336 PMAP_LOCK_INIT(pmap);
2337 mmu_booke_pinit(mmu, pmap);
2338 PCPU_SET(curpmap, pmap);
2342 * Initialize a preallocated and zeroed pmap structure,
2343 * such as one in a vmspace structure.
2346 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
2350 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
2351 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
2353 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
2355 for (i = 0; i < MAXCPU; i++)
2356 pmap->pm_tid[i] = TID_NONE;
2357 CPU_ZERO(&kernel_pmap->pm_active);
2358 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2359 #ifdef __powerpc64__
2360 bzero(&pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES);
2361 TAILQ_INIT(&pmap->pm_pdir_list);
2363 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
2365 TAILQ_INIT(&pmap->pm_ptbl_list);
2369 * Release any resources held by the given physical map.
2370 * Called when a pmap initialized by mmu_booke_pinit is being released.
2371 * Should only be called if the map contains no valid mappings.
2374 mmu_booke_release(mmu_t mmu, pmap_t pmap)
2377 KASSERT(pmap->pm_stats.resident_count == 0,
2378 ("pmap_release: pmap resident count %ld != 0",
2379 pmap->pm_stats.resident_count));
2383 * Insert the given physical page at the specified virtual address in the
2384 * target physical map with the protection requested. If specified the page
2385 * will be wired down.
2388 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2389 vm_prot_t prot, u_int flags, int8_t psind)
2393 rw_wlock(&pvh_global_lock);
2395 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
2397 rw_wunlock(&pvh_global_lock);
2402 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2403 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
2408 int error, su, sync;
2410 pa = VM_PAGE_TO_PHYS(m);
2411 su = (pmap == kernel_pmap);
2414 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
2415 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
2416 // (u_int32_t)pmap, su, pmap->pm_tid,
2417 // (u_int32_t)m, va, pa, prot, flags);
2420 KASSERT(((va >= virtual_avail) &&
2421 (va <= VM_MAX_KERNEL_ADDRESS)),
2422 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
2424 KASSERT((va <= VM_MAXUSER_ADDRESS),
2425 ("mmu_booke_enter_locked: user pmap, non user va"));
2427 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2428 VM_OBJECT_ASSERT_LOCKED(m->object);
2430 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2433 * If there is an existing mapping, and the physical address has not
2434 * changed, must be protection or wiring change.
2436 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
2437 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
2440 * Before actually updating pte->flags we calculate and
2441 * prepare its new value in a helper var.
2444 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
2446 /* Wiring change, just update stats. */
2447 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
2448 if (!PTE_ISWIRED(pte)) {
2450 pmap->pm_stats.wired_count++;
2453 if (PTE_ISWIRED(pte)) {
2454 flags &= ~PTE_WIRED;
2455 pmap->pm_stats.wired_count--;
2459 if (prot & VM_PROT_WRITE) {
2460 /* Add write permissions. */
2465 if ((flags & PTE_MANAGED) != 0)
2466 vm_page_aflag_set(m, PGA_WRITEABLE);
2468 /* Handle modified pages, sense modify status. */
2471 * The PTE_MODIFIED flag could be set by underlying
2472 * TLB misses since we last read it (above), possibly
2473 * other CPUs could update it so we check in the PTE
2474 * directly rather than rely on that saved local flags
2477 if (PTE_ISMODIFIED(pte))
2481 if (prot & VM_PROT_EXECUTE) {
2487 * Check existing flags for execute permissions: if we
2488 * are turning execute permissions on, icache should
2491 if ((*pte & (PTE_UX | PTE_SX)) == 0)
2495 flags &= ~PTE_REFERENCED;
2498 * The new flags value is all calculated -- only now actually
2501 mtx_lock_spin(&tlbivax_mutex);
2504 tlb0_flush_entry(va);
2505 *pte &= ~PTE_FLAGS_MASK;
2509 mtx_unlock_spin(&tlbivax_mutex);
2513 * If there is an existing mapping, but it's for a different
2514 * physical address, pte_enter() will delete the old mapping.
2516 //if ((pte != NULL) && PTE_ISVALID(pte))
2517 // debugf("mmu_booke_enter_locked: replace\n");
2519 // debugf("mmu_booke_enter_locked: new\n");
2521 /* Now set up the flags and install the new mapping. */
2522 flags = (PTE_SR | PTE_VALID);
2528 if (prot & VM_PROT_WRITE) {
2533 if ((m->oflags & VPO_UNMANAGED) == 0)
2534 vm_page_aflag_set(m, PGA_WRITEABLE);
2537 if (prot & VM_PROT_EXECUTE) {
2543 /* If its wired update stats. */
2544 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
2547 error = pte_enter(mmu, pmap, m, va, flags,
2548 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
2550 return (KERN_RESOURCE_SHORTAGE);
2552 if ((flags & PMAP_ENTER_WIRED) != 0)
2553 pmap->pm_stats.wired_count++;
2555 /* Flush the real memory from the instruction cache. */
2556 if (prot & VM_PROT_EXECUTE)
2560 if (sync && (su || pmap == PCPU_GET(curpmap))) {
2561 __syncicache((void *)va, PAGE_SIZE);
2565 return (KERN_SUCCESS);
2569 * Maps a sequence of resident pages belonging to the same object.
2570 * The sequence begins with the given page m_start. This page is
2571 * mapped at the given virtual address start. Each subsequent page is
2572 * mapped at a virtual address that is offset from start by the same
2573 * amount as the page is offset from m_start within the object. The
2574 * last page in the sequence is the page with the largest offset from
2575 * m_start that can be mapped at a virtual address less than the given
2576 * virtual address end. Not every virtual page between start and end
2577 * is mapped; only those for which a resident page exists with the
2578 * corresponding offset from m_start are mapped.
2581 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
2582 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
2585 vm_pindex_t diff, psize;
2587 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2589 psize = atop(end - start);
2591 rw_wlock(&pvh_global_lock);
2593 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2594 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
2595 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
2596 PMAP_ENTER_NOSLEEP, 0);
2597 m = TAILQ_NEXT(m, listq);
2599 rw_wunlock(&pvh_global_lock);
2604 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2608 rw_wlock(&pvh_global_lock);
2610 mmu_booke_enter_locked(mmu, pmap, va, m,
2611 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP,
2613 rw_wunlock(&pvh_global_lock);
2618 * Remove the given range of addresses from the specified map.
2620 * It is assumed that the start and end are properly rounded to the page size.
2623 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
2628 int su = (pmap == kernel_pmap);
2630 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
2631 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
2634 KASSERT(((va >= virtual_avail) &&
2635 (va <= VM_MAX_KERNEL_ADDRESS)),
2636 ("mmu_booke_remove: kernel pmap, non kernel va"));
2638 KASSERT((va <= VM_MAXUSER_ADDRESS),
2639 ("mmu_booke_remove: user pmap, non user va"));
2642 if (PMAP_REMOVE_DONE(pmap)) {
2643 //debugf("mmu_booke_remove: e (empty)\n");
2647 hold_flag = PTBL_HOLD_FLAG(pmap);
2648 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
2650 rw_wlock(&pvh_global_lock);
2652 for (; va < endva; va += PAGE_SIZE) {
2653 pte = pte_find(mmu, pmap, va);
2654 if ((pte != NULL) && PTE_ISVALID(pte))
2655 pte_remove(mmu, pmap, va, hold_flag);
2658 rw_wunlock(&pvh_global_lock);
2660 //debugf("mmu_booke_remove: e\n");
2664 * Remove physical page from all pmaps in which it resides.
2667 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
2672 rw_wlock(&pvh_global_lock);
2673 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
2674 pvn = TAILQ_NEXT(pv, pv_link);
2676 PMAP_LOCK(pv->pv_pmap);
2677 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
2678 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
2679 PMAP_UNLOCK(pv->pv_pmap);
2681 vm_page_aflag_clear(m, PGA_WRITEABLE);
2682 rw_wunlock(&pvh_global_lock);
2686 * Map a range of physical addresses into kernel virtual address space.
2689 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2690 vm_paddr_t pa_end, int prot)
2692 vm_offset_t sva = *virt;
2693 vm_offset_t va = sva;
2695 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
2696 // sva, pa_start, pa_end);
2698 while (pa_start < pa_end) {
2699 mmu_booke_kenter(mmu, va, pa_start);
2701 pa_start += PAGE_SIZE;
2705 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
2710 * The pmap must be activated before it's address space can be accessed in any
2714 mmu_booke_activate(mmu_t mmu, struct thread *td)
2719 pmap = &td->td_proc->p_vmspace->vm_pmap;
2721 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
2722 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2724 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
2728 cpuid = PCPU_GET(cpuid);
2729 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
2730 PCPU_SET(curpmap, pmap);
2732 if (pmap->pm_tid[cpuid] == TID_NONE)
2735 /* Load PID0 register with pmap tid value. */
2736 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
2737 __asm __volatile("isync");
2739 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
2743 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
2744 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
2748 * Deactivate the specified process's address space.
2751 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
2755 pmap = &td->td_proc->p_vmspace->vm_pmap;
2757 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
2758 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2760 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
2762 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
2763 PCPU_SET(curpmap, NULL);
2767 * Copy the range specified by src_addr/len
2768 * from the source map to the range dst_addr/len
2769 * in the destination map.
2771 * This routine is only advisory and need not do anything.
2774 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
2775 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
2781 * Set the physical protection on the specified range of this map as requested.
2784 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2791 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2792 mmu_booke_remove(mmu, pmap, sva, eva);
2796 if (prot & VM_PROT_WRITE)
2800 for (va = sva; va < eva; va += PAGE_SIZE) {
2801 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2802 if (PTE_ISVALID(pte)) {
2803 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2805 mtx_lock_spin(&tlbivax_mutex);
2808 /* Handle modified pages. */
2809 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2812 tlb0_flush_entry(va);
2813 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2816 mtx_unlock_spin(&tlbivax_mutex);
2824 * Clear the write and modified bits in each of the given page's mappings.
2827 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2832 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2833 ("mmu_booke_remove_write: page %p is not managed", m));
2836 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2837 * set by another thread while the object is locked. Thus,
2838 * if PGA_WRITEABLE is clear, no page table entries need updating.
2840 VM_OBJECT_ASSERT_WLOCKED(m->object);
2841 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2843 rw_wlock(&pvh_global_lock);
2844 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2845 PMAP_LOCK(pv->pv_pmap);
2846 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2847 if (PTE_ISVALID(pte)) {
2848 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2850 mtx_lock_spin(&tlbivax_mutex);
2853 /* Handle modified pages. */
2854 if (PTE_ISMODIFIED(pte))
2857 /* Flush mapping from TLB0. */
2858 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2861 mtx_unlock_spin(&tlbivax_mutex);
2864 PMAP_UNLOCK(pv->pv_pmap);
2866 vm_page_aflag_clear(m, PGA_WRITEABLE);
2867 rw_wunlock(&pvh_global_lock);
2871 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2880 va = trunc_page(va);
2881 sz = round_page(sz);
2883 rw_wlock(&pvh_global_lock);
2884 pmap = PCPU_GET(curpmap);
2885 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2888 pte = pte_find(mmu, pm, va);
2889 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2895 /* Create a mapping in the active pmap. */
2897 m = PHYS_TO_VM_PAGE(pa);
2899 pte_enter(mmu, pmap, m, addr,
2900 PTE_SR | PTE_VALID | PTE_UR, FALSE);
2901 __syncicache((void *)addr, PAGE_SIZE);
2902 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2905 __syncicache((void *)va, PAGE_SIZE);
2910 rw_wunlock(&pvh_global_lock);
2914 * Atomically extract and hold the physical page with the given
2915 * pmap and virtual address pair if that mapping permits the given
2919 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2931 pte = pte_find(mmu, pmap, va);
2932 if ((pte != NULL) && PTE_ISVALID(pte)) {
2933 if (pmap == kernel_pmap)
2938 if ((*pte & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2939 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2941 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2952 * Initialize a vm_page's machine-dependent fields.
2955 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2958 m->md.pv_tracked = 0;
2959 TAILQ_INIT(&m->md.pv_list);
2963 * mmu_booke_zero_page_area zeros the specified hardware page by
2964 * mapping it into virtual memory and using bzero to clear
2967 * off and size must reside within a single page.
2970 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2974 /* XXX KASSERT off and size are within a single page? */
2976 #ifdef __powerpc64__
2977 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2978 bzero((caddr_t)va + off, size);
2980 mtx_lock(&zero_page_mutex);
2983 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2984 bzero((caddr_t)va + off, size);
2985 mmu_booke_kremove(mmu, va);
2987 mtx_unlock(&zero_page_mutex);
2992 * mmu_booke_zero_page zeros the specified hardware page.
2995 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2997 vm_offset_t off, va;
2999 #ifdef __powerpc64__
3000 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
3002 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
3003 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
3006 mtx_lock(&zero_page_mutex);
3008 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
3010 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
3011 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
3013 mmu_booke_kremove(mmu, va);
3015 mtx_unlock(&zero_page_mutex);
3020 * mmu_booke_copy_page copies the specified (machine independent) page by
3021 * mapping the page into virtual memory and using memcopy to copy the page,
3022 * one machine dependent page at a time.
3025 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
3027 vm_offset_t sva, dva;
3029 #ifdef __powerpc64__
3030 sva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(sm));
3031 dva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dm));
3032 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
3034 mtx_lock(©_page_mutex);
3035 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
3036 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
3037 sva = copy_page_src_va;
3038 dva = copy_page_dst_va;
3040 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
3042 mmu_booke_kremove(mmu, dva);
3043 mmu_booke_kremove(mmu, sva);
3044 mtx_unlock(©_page_mutex);
3049 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
3050 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
3053 vm_offset_t a_pg_offset, b_pg_offset;
3056 #ifdef __powerpc64__
3059 while (xfersize > 0) {
3060 a_pg_offset = a_offset & PAGE_MASK;
3061 pa = ma[a_offset >> PAGE_SHIFT];
3062 b_pg_offset = b_offset & PAGE_MASK;
3063 pb = mb[b_offset >> PAGE_SHIFT];
3064 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3065 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3066 a_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pa)) +
3068 b_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pb)) +
3070 bcopy(a_cp, b_cp, cnt);
3076 mtx_lock(©_page_mutex);
3077 while (xfersize > 0) {
3078 a_pg_offset = a_offset & PAGE_MASK;
3079 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
3080 mmu_booke_kenter(mmu, copy_page_src_va,
3081 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
3082 a_cp = (char *)copy_page_src_va + a_pg_offset;
3083 b_pg_offset = b_offset & PAGE_MASK;
3084 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
3085 mmu_booke_kenter(mmu, copy_page_dst_va,
3086 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
3087 b_cp = (char *)copy_page_dst_va + b_pg_offset;
3088 bcopy(a_cp, b_cp, cnt);
3089 mmu_booke_kremove(mmu, copy_page_dst_va);
3090 mmu_booke_kremove(mmu, copy_page_src_va);
3095 mtx_unlock(©_page_mutex);
3100 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m)
3102 #ifdef __powerpc64__
3103 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
3110 paddr = VM_PAGE_TO_PHYS(m);
3112 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
3113 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
3114 flags |= PTE_PS_4KB;
3117 qaddr = PCPU_GET(qmap_addr);
3119 pte = pte_find(mmu, kernel_pmap, qaddr);
3121 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy"));
3124 * XXX: tlbivax is broadcast to other cores, but qaddr should
3125 * not be present in other TLBs. Is there a better instruction
3126 * sequence to use? Or just forget it & use mmu_booke_kenter()...
3128 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK));
3129 __asm __volatile("isync; msync");
3131 *pte = PTE_RPN_FROM_PA(paddr) | flags;
3133 /* Flush the real memory from the instruction cache. */
3134 if ((flags & (PTE_I | PTE_G)) == 0)
3135 __syncicache((void *)qaddr, PAGE_SIZE);
3142 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr)
3144 #ifndef __powerpc64__
3147 pte = pte_find(mmu, kernel_pmap, addr);
3149 KASSERT(PCPU_GET(qmap_addr) == addr,
3150 ("mmu_booke_quick_remove_page: invalid address"));
3152 ("mmu_booke_quick_remove_page: PTE not in use"));
3160 * Return whether or not the specified physical page was modified
3161 * in any of physical maps.
3164 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
3170 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3171 ("mmu_booke_is_modified: page %p is not managed", m));
3175 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3176 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3177 * is clear, no PTEs can be modified.
3179 VM_OBJECT_ASSERT_WLOCKED(m->object);
3180 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3182 rw_wlock(&pvh_global_lock);
3183 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3184 PMAP_LOCK(pv->pv_pmap);
3185 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3187 if (PTE_ISMODIFIED(pte))
3190 PMAP_UNLOCK(pv->pv_pmap);
3194 rw_wunlock(&pvh_global_lock);
3199 * Return whether or not the specified virtual address is eligible
3203 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
3210 * Return whether or not the specified physical page was referenced
3211 * in any physical maps.
3214 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
3220 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3221 ("mmu_booke_is_referenced: page %p is not managed", m));
3223 rw_wlock(&pvh_global_lock);
3224 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3225 PMAP_LOCK(pv->pv_pmap);
3226 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3228 if (PTE_ISREFERENCED(pte))
3231 PMAP_UNLOCK(pv->pv_pmap);
3235 rw_wunlock(&pvh_global_lock);
3240 * Clear the modify bits on the specified physical page.
3243 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
3248 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3249 ("mmu_booke_clear_modify: page %p is not managed", m));
3250 VM_OBJECT_ASSERT_WLOCKED(m->object);
3251 KASSERT(!vm_page_xbusied(m),
3252 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
3255 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
3256 * If the object containing the page is locked and the page is not
3257 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
3259 if ((m->aflags & PGA_WRITEABLE) == 0)
3261 rw_wlock(&pvh_global_lock);
3262 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3263 PMAP_LOCK(pv->pv_pmap);
3264 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3266 mtx_lock_spin(&tlbivax_mutex);
3269 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
3270 tlb0_flush_entry(pv->pv_va);
3271 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
3276 mtx_unlock_spin(&tlbivax_mutex);
3278 PMAP_UNLOCK(pv->pv_pmap);
3280 rw_wunlock(&pvh_global_lock);
3284 * Return a count of reference bits for a page, clearing those bits.
3285 * It is not necessary for every reference bit to be cleared, but it
3286 * is necessary that 0 only be returned when there are truly no
3287 * reference bits set.
3289 * As an optimization, update the page's dirty field if a modified bit is
3290 * found while counting reference bits. This opportunistic update can be
3291 * performed at low cost and can eliminate the need for some future calls
3292 * to pmap_is_modified(). However, since this function stops after
3293 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3294 * dirty pages. Those dirty pages will only be detected by a future call
3295 * to pmap_is_modified().
3298 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
3304 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3305 ("mmu_booke_ts_referenced: page %p is not managed", m));
3307 rw_wlock(&pvh_global_lock);
3308 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3309 PMAP_LOCK(pv->pv_pmap);
3310 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3312 if (PTE_ISMODIFIED(pte))
3314 if (PTE_ISREFERENCED(pte)) {
3315 mtx_lock_spin(&tlbivax_mutex);
3318 tlb0_flush_entry(pv->pv_va);
3319 *pte &= ~PTE_REFERENCED;
3322 mtx_unlock_spin(&tlbivax_mutex);
3324 if (++count >= PMAP_TS_REFERENCED_MAX) {
3325 PMAP_UNLOCK(pv->pv_pmap);
3330 PMAP_UNLOCK(pv->pv_pmap);
3332 rw_wunlock(&pvh_global_lock);
3337 * Clear the wired attribute from the mappings for the specified range of
3338 * addresses in the given pmap. Every valid mapping within that range must
3339 * have the wired attribute set. In contrast, invalid mappings cannot have
3340 * the wired attribute set, so they are ignored.
3342 * The wired attribute of the page table entry is not a hardware feature, so
3343 * there is no need to invalidate any TLB entries.
3346 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3352 for (va = sva; va < eva; va += PAGE_SIZE) {
3353 if ((pte = pte_find(mmu, pmap, va)) != NULL &&
3355 if (!PTE_ISWIRED(pte))
3356 panic("mmu_booke_unwire: pte %p isn't wired",
3359 pmap->pm_stats.wired_count--;
3367 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
3368 * page. This count may be changed upwards or downwards in the future; it is
3369 * only necessary that true be returned for a small subset of pmaps for proper
3373 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
3379 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3380 ("mmu_booke_page_exists_quick: page %p is not managed", m));
3383 rw_wlock(&pvh_global_lock);
3384 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3385 if (pv->pv_pmap == pmap) {
3392 rw_wunlock(&pvh_global_lock);
3397 * Return the number of managed mappings to the given physical page that are
3401 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
3407 if ((m->oflags & VPO_UNMANAGED) != 0)
3409 rw_wlock(&pvh_global_lock);
3410 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3411 PMAP_LOCK(pv->pv_pmap);
3412 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
3413 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
3415 PMAP_UNLOCK(pv->pv_pmap);
3417 rw_wunlock(&pvh_global_lock);
3422 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3428 * This currently does not work for entries that
3429 * overlap TLB1 entries.
3431 for (i = 0; i < TLB1_ENTRIES; i ++) {
3432 if (tlb1_iomapped(i, pa, size, &va) == 0)
3440 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
3446 /* Minidumps are based on virtual memory addresses. */
3448 *va = (void *)(vm_offset_t)pa;
3452 /* Raw physical memory dumps don't have a virtual address. */
3453 /* We always map a 256MB page at 256M. */
3454 gran = 256 * 1024 * 1024;
3455 ppa = rounddown2(pa, gran);
3458 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
3460 if (sz > (gran - ofs))
3461 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
3466 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va)
3474 /* Minidumps are based on virtual memory addresses. */
3475 /* Nothing to do... */
3479 for (i = 0; i < TLB1_ENTRIES; i++) {
3480 tlb1_read_entry(&e, i);
3481 if (!(e.mas1 & MAS1_VALID))
3485 /* Raw physical memory dumps don't have a virtual address. */
3490 tlb1_write_entry(&e, i);
3492 gran = 256 * 1024 * 1024;
3493 ppa = rounddown2(pa, gran);
3495 if (sz > (gran - ofs)) {
3500 tlb1_write_entry(&e, i);
3504 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
3507 mmu_booke_scan_init(mmu_t mmu)
3514 /* Initialize phys. segments for dumpsys(). */
3515 memset(&dump_map, 0, sizeof(dump_map));
3516 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
3517 &availmem_regions_sz);
3518 for (i = 0; i < physmem_regions_sz; i++) {
3519 dump_map[i].pa_start = physmem_regions[i].mr_start;
3520 dump_map[i].pa_size = physmem_regions[i].mr_size;
3525 /* Virtual segments for minidumps: */
3526 memset(&dump_map, 0, sizeof(dump_map));
3528 /* 1st: kernel .data and .bss. */
3529 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
3530 dump_map[0].pa_size =
3531 round_page((uintptr_t)_end) - dump_map[0].pa_start;
3533 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
3534 dump_map[1].pa_start = data_start;
3535 dump_map[1].pa_size = data_end - data_start;
3537 /* 3rd: kernel VM. */
3538 va = dump_map[1].pa_start + dump_map[1].pa_size;
3539 /* Find start of next chunk (from va). */
3540 while (va < virtual_end) {
3541 /* Don't dump the buffer cache. */
3542 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
3543 va = kmi.buffer_eva;
3546 pte = pte_find(mmu, kernel_pmap, va);
3547 if (pte != NULL && PTE_ISVALID(pte))
3551 if (va < virtual_end) {
3552 dump_map[2].pa_start = va;
3554 /* Find last page in chunk. */
3555 while (va < virtual_end) {
3556 /* Don't run into the buffer cache. */
3557 if (va == kmi.buffer_sva)
3559 pte = pte_find(mmu, kernel_pmap, va);
3560 if (pte == NULL || !PTE_ISVALID(pte))
3564 dump_map[2].pa_size = va - dump_map[2].pa_start;
3569 * Map a set of physical memory pages into the kernel virtual address space.
3570 * Return a pointer to where it is mapped. This routine is intended to be used
3571 * for mapping device memory, NOT real memory.
3574 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3577 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
3581 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3585 uintptr_t va, tmpva;
3590 * Check if this is premapped in TLB1. Note: this should probably also
3591 * check whether a sequence of TLB1 entries exist that match the
3592 * requirement, but now only checks the easy case.
3594 for (i = 0; i < TLB1_ENTRIES; i++) {
3595 tlb1_read_entry(&e, i);
3596 if (!(e.mas1 & MAS1_VALID))
3599 (pa + size) <= (e.phys + e.size) &&
3600 (ma == VM_MEMATTR_DEFAULT ||
3601 tlb_calc_wimg(pa, ma) ==
3602 (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED))))
3603 return (void *)(e.virt +
3604 (vm_offset_t)(pa - e.phys));
3607 size = roundup(size, PAGE_SIZE);
3610 * The device mapping area is between VM_MAXUSER_ADDRESS and
3611 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
3613 #ifdef SPARSE_MAPDEV
3615 * With a sparse mapdev, align to the largest starting region. This
3616 * could feasibly be optimized for a 'best-fit' alignment, but that
3617 * calculation could be very costly.
3618 * Align to the smaller of:
3619 * - first set bit in overlap of (pa & size mask)
3620 * - largest size envelope
3622 * It's possible the device mapping may start at a PA that's not larger
3623 * than the size mask, so we need to offset in to maximize the TLB entry
3624 * range and minimize the number of used TLB entries.
3627 tmpva = tlb1_map_base;
3628 sz = ffsl(((1 << flsl(size-1)) - 1) & pa);
3629 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
3630 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
3631 #ifdef __powerpc64__
3632 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size));
3634 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
3637 #ifdef __powerpc64__
3638 va = atomic_fetchadd_long(&tlb1_map_base, size);
3640 va = atomic_fetchadd_int(&tlb1_map_base, size);
3646 sz = 1 << (ilog2(size) & ~1);
3647 /* Align size to PA */
3651 } while (pa % sz != 0);
3653 /* Now align from there to VA */
3657 } while (va % sz != 0);
3660 printf("Wiring VA=%lx to PA=%jx (size=%lx)\n",
3661 va, (uintmax_t)pa, sz);
3662 if (tlb1_set_entry(va, pa, sz,
3663 _TLB_ENTRY_SHARED | tlb_calc_wimg(pa, ma)) < 0)
3674 * 'Unmap' a range mapped by mmu_booke_mapdev().
3677 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
3679 #ifdef SUPPORTS_SHRINKING_TLB1
3680 vm_offset_t base, offset;
3683 * Unmap only if this is inside kernel virtual space.
3685 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
3686 base = trunc_page(va);
3687 offset = va & PAGE_MASK;
3688 size = roundup(offset + size, PAGE_SIZE);
3689 kva_free(base, size);
3695 * mmu_booke_object_init_pt preloads the ptes for a given object into the
3696 * specified pmap. This eliminates the blast of soft faults on process startup
3697 * and immediately after an mmap.
3700 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3701 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
3704 VM_OBJECT_ASSERT_WLOCKED(object);
3705 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3706 ("mmu_booke_object_init_pt: non-device object"));
3710 * Perform the pmap work for mincore.
3713 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3714 vm_paddr_t *locked_pa)
3717 /* XXX: this should be implemented at some point */
3722 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz,
3730 /* Check TLB1 mappings */
3731 for (i = 0; i < TLB1_ENTRIES; i++) {
3732 tlb1_read_entry(&e, i);
3733 if (!(e.mas1 & MAS1_VALID))
3735 if (addr >= e.virt && addr < e.virt + e.size)
3738 if (i < TLB1_ENTRIES) {
3739 /* Only allow full mappings to be modified for now. */
3740 /* Validate the range. */
3741 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
3742 tlb1_read_entry(&e, j);
3743 if (va != e.virt || (sz - (va - addr) < e.size))
3746 for (va = addr; va < addr + sz; va += e.size, i++) {
3747 tlb1_read_entry(&e, i);
3748 e.mas2 &= ~MAS2_WIMGE_MASK;
3749 e.mas2 |= tlb_calc_wimg(e.phys, mode);
3752 * Write it out to the TLB. Should really re-sync with other
3755 tlb1_write_entry(&e, i);
3760 /* Not in TLB1, try through pmap */
3761 /* First validate the range. */
3762 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3763 pte = pte_find(mmu, kernel_pmap, va);
3764 if (pte == NULL || !PTE_ISVALID(pte))
3768 mtx_lock_spin(&tlbivax_mutex);
3770 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3771 pte = pte_find(mmu, kernel_pmap, va);
3772 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
3773 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
3774 tlb0_flush_entry(va);
3777 mtx_unlock_spin(&tlbivax_mutex);
3782 /**************************************************************************/
3784 /**************************************************************************/
3787 * Allocate a TID. If necessary, steal one from someone else.
3788 * The new TID is flushed from the TLB before returning.
3791 tid_alloc(pmap_t pmap)
3796 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
3798 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
3800 thiscpu = PCPU_GET(cpuid);
3802 tid = PCPU_GET(booke.tid_next);
3805 PCPU_SET(booke.tid_next, tid + 1);
3807 /* If we are stealing TID then clear the relevant pmap's field */
3808 if (tidbusy[thiscpu][tid] != NULL) {
3810 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
3812 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
3814 /* Flush all entries from TLB0 matching this TID. */
3818 tidbusy[thiscpu][tid] = pmap;
3819 pmap->pm_tid[thiscpu] = tid;
3820 __asm __volatile("msync; isync");
3822 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
3823 PCPU_GET(booke.tid_next));
3828 /**************************************************************************/
3830 /**************************************************************************/
3832 /* Convert TLB0 va and way number to tlb0[] table index. */
3833 static inline unsigned int
3834 tlb0_tableidx(vm_offset_t va, unsigned int way)
3838 idx = (way * TLB0_ENTRIES_PER_WAY);
3839 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
3844 * Invalidate TLB0 entry.
3847 tlb0_flush_entry(vm_offset_t va)
3850 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
3852 mtx_assert(&tlbivax_mutex, MA_OWNED);
3854 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
3855 __asm __volatile("isync; msync");
3856 __asm __volatile("tlbsync; msync");
3858 CTR1(KTR_PMAP, "%s: e", __func__);
3862 /**************************************************************************/
3864 /**************************************************************************/
3867 * TLB1 mapping notes:
3869 * TLB1[0] Kernel text and data.
3870 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
3871 * windows, other devices mappings.
3875 * Read an entry from given TLB1 slot.
3878 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
3883 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
3886 __asm __volatile("wrteei 0");
3888 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
3889 mtspr(SPR_MAS0, mas0);
3890 __asm __volatile("isync; tlbre");
3892 entry->mas1 = mfspr(SPR_MAS1);
3893 entry->mas2 = mfspr(SPR_MAS2);
3894 entry->mas3 = mfspr(SPR_MAS3);
3896 switch ((mfpvr() >> 16) & 0xFFFF) {
3901 entry->mas7 = mfspr(SPR_MAS7);
3909 entry->virt = entry->mas2 & MAS2_EPN_MASK;
3910 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
3911 (entry->mas3 & MAS3_RPN);
3913 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
3916 struct tlbwrite_args {
3922 tlb1_write_entry_int(void *arg)
3924 struct tlbwrite_args *args = arg;
3928 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(args->idx);
3930 mtspr(SPR_MAS0, mas0);
3931 mtspr(SPR_MAS1, args->e->mas1);
3932 mtspr(SPR_MAS2, args->e->mas2);
3933 mtspr(SPR_MAS3, args->e->mas3);
3934 switch ((mfpvr() >> 16) & 0xFFFF) {
3941 mtspr(SPR_MAS7, args->e->mas7);
3947 __asm __volatile("isync; tlbwe; isync; msync");
3952 tlb1_write_entry_sync(void *arg)
3954 /* Empty synchronization point for smp_rendezvous(). */
3958 * Write given entry to TLB1 hardware.
3961 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
3963 struct tlbwrite_args args;
3969 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
3971 smp_rendezvous(tlb1_write_entry_sync,
3972 tlb1_write_entry_int,
3973 tlb1_write_entry_sync, &args);
3980 __asm __volatile("wrteei 0");
3981 tlb1_write_entry_int(&args);
3987 * Return the largest uint value log such that 2^log <= num.
3990 ilog2(unsigned long num)
3994 #ifdef __powerpc64__
3995 __asm ("cntlzd %0, %1" : "=r" (lz) : "r" (num));
3998 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
4004 * Convert TLB TSIZE value to mapped region size.
4007 tsize2size(unsigned int tsize)
4012 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
4015 return ((1 << (2 * tsize)) * 1024);
4019 * Convert region size (must be power of 4) to TLB TSIZE value.
4022 size2tsize(vm_size_t size)
4025 return (ilog2(size) / 2 - 5);
4029 * Register permanent kernel mapping in TLB1.
4031 * Entries are created starting from index 0 (current free entry is
4032 * kept in tlb1_idx) and are not supposed to be invalidated.
4035 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
4042 for (index = 0; index < TLB1_ENTRIES; index++) {
4043 tlb1_read_entry(&e, index);
4044 if ((e.mas1 & MAS1_VALID) == 0)
4046 /* Check if we're just updating the flags, and update them. */
4047 if (e.phys == pa && e.virt == va && e.size == size) {
4048 e.mas2 = (va & MAS2_EPN_MASK) | flags;
4049 tlb1_write_entry(&e, index);
4053 if (index >= TLB1_ENTRIES) {
4054 printf("tlb1_set_entry: TLB1 full!\n");
4058 /* Convert size to TSIZE */
4059 tsize = size2tsize(size);
4061 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
4062 /* XXX TS is hard coded to 0 for now as we only use single address space */
4063 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
4068 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
4069 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
4070 e.mas2 = (va & MAS2_EPN_MASK) | flags;
4072 /* Set supervisor RWX permission bits */
4073 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
4074 e.mas7 = (pa >> 32) & MAS7_RPN;
4076 tlb1_write_entry(&e, index);
4079 * XXX in general TLB1 updates should be propagated between CPUs,
4080 * since current design assumes to have the same TLB1 set-up on all
4087 * Map in contiguous RAM region into the TLB1 using maximum of
4088 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
4090 * If necessary round up last entry size and return total size
4091 * used by all allocated entries.
4094 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
4096 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
4097 vm_size_t mapped, pgsz, base, mask;
4100 /* Round up to the next 1M */
4101 size = roundup2(size, 1 << 20);
4106 pgsz = 64*1024*1024;
4107 while (mapped < size) {
4108 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
4109 while (pgsz > (size - mapped))
4115 /* We under-map. Correct for this. */
4116 if (mapped < size) {
4117 while (pgs[idx - 1] == pgsz) {
4121 /* XXX We may increase beyond out starting point. */
4130 /* Align address to the boundary */
4132 va = (va + mask) & ~mask;
4133 pa = (pa + mask) & ~mask;
4136 for (idx = 0; idx < nents; idx++) {
4138 debugf("%u: %llx -> %jx, size=%jx\n", idx, pa,
4139 (uintmax_t)va, (uintmax_t)pgsz);
4140 tlb1_set_entry(va, pa, pgsz,
4141 _TLB_ENTRY_SHARED | _TLB_ENTRY_MEM);
4146 mapped = (va - base);
4148 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
4149 mapped, mapped - size);
4154 * TLB1 initialization routine, to be called after the very first
4155 * assembler level setup done in locore.S.
4160 uint32_t mas0, mas1, mas2, mas3, mas7;
4165 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
4166 mtspr(SPR_MAS0, mas0);
4167 __asm __volatile("isync; tlbre");
4169 mas1 = mfspr(SPR_MAS1);
4170 mas2 = mfspr(SPR_MAS2);
4171 mas3 = mfspr(SPR_MAS3);
4172 mas7 = mfspr(SPR_MAS7);
4174 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
4177 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4178 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
4180 /* Setup TLB miss defaults */
4181 set_mas4_defaults();
4185 * pmap_early_io_unmap() should be used in short conjunction with
4186 * pmap_early_io_map(), as in the following snippet:
4188 * x = pmap_early_io_map(...);
4189 * <do something with x>
4190 * pmap_early_io_unmap(x, size);
4192 * And avoiding more allocations between.
4195 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
4201 size = roundup(size, PAGE_SIZE);
4203 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
4204 tlb1_read_entry(&e, i);
4205 if (!(e.mas1 & MAS1_VALID))
4207 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
4209 e.mas1 &= ~MAS1_VALID;
4210 tlb1_write_entry(&e, i);
4213 if (tlb1_map_base == va + isize)
4214 tlb1_map_base -= isize;
4218 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
4225 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
4227 for (i = 0; i < TLB1_ENTRIES; i++) {
4228 tlb1_read_entry(&e, i);
4229 if (!(e.mas1 & MAS1_VALID))
4231 if (pa >= e.phys && (pa + size) <=
4233 return (e.virt + (pa - e.phys));
4236 pa_base = rounddown(pa, PAGE_SIZE);
4237 size = roundup(size + (pa - pa_base), PAGE_SIZE);
4238 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
4239 va = tlb1_map_base + (pa - pa_base);
4242 sz = 1 << (ilog2(size) & ~1);
4243 tlb1_set_entry(tlb1_map_base, pa_base, sz,
4244 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
4247 tlb1_map_base += sz;
4254 pmap_track_page(pmap_t pmap, vm_offset_t va)
4258 struct pv_entry *pve;
4260 va = trunc_page(va);
4261 pa = pmap_kextract(va);
4262 page = PHYS_TO_VM_PAGE(pa);
4264 rw_wlock(&pvh_global_lock);
4267 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
4268 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
4272 page->md.pv_tracked = true;
4273 pv_insert(pmap, va, page);
4276 rw_wunlock(&pvh_global_lock);
4281 * Setup MAS4 defaults.
4282 * These values are loaded to MAS0-2 on a TLB miss.
4285 set_mas4_defaults(void)
4289 /* Defaults: TLB0, PID0, TSIZED=4K */
4290 mas4 = MAS4_TLBSELD0;
4291 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
4295 mtspr(SPR_MAS4, mas4);
4296 __asm __volatile("isync");
4301 * Return 0 if the physical IO range is encompassed by one of the
4302 * the TLB1 entries, otherwise return related error code.
4305 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
4308 vm_paddr_t pa_start;
4310 unsigned int entry_tsize;
4311 vm_size_t entry_size;
4314 *va = (vm_offset_t)NULL;
4316 tlb1_read_entry(&e, i);
4317 /* Skip invalid entries */
4318 if (!(e.mas1 & MAS1_VALID))
4322 * The entry must be cache-inhibited, guarded, and r/w
4323 * so it can function as an i/o page
4325 prot = e.mas2 & (MAS2_I | MAS2_G);
4326 if (prot != (MAS2_I | MAS2_G))
4329 prot = e.mas3 & (MAS3_SR | MAS3_SW);
4330 if (prot != (MAS3_SR | MAS3_SW))
4333 /* The address should be within the entry range. */
4334 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4335 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
4337 entry_size = tsize2size(entry_tsize);
4338 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
4339 (e.mas3 & MAS3_RPN);
4340 pa_end = pa_start + entry_size;
4342 if ((pa < pa_start) || ((pa + size) > pa_end))
4345 /* Return virtual address of this mapping. */
4346 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
4351 * Invalidate all TLB0 entries which match the given TID. Note this is
4352 * dedicated for cases when invalidations should NOT be propagated to other
4356 tid_flush(tlbtid_t tid)
4359 uint32_t mas0, mas1, mas2;
4363 /* Don't evict kernel translations */
4364 if (tid == TID_KERNEL)
4368 __asm __volatile("wrteei 0");
4371 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use
4372 * it for PID invalidation.
4374 switch ((mfpvr() >> 16) & 0xffff) {
4378 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
4380 __asm __volatile("isync; .long 0x7c000024; isync; msync");
4385 for (way = 0; way < TLB0_WAYS; way++)
4386 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
4388 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4389 mtspr(SPR_MAS0, mas0);
4391 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
4392 mtspr(SPR_MAS2, mas2);
4394 __asm __volatile("isync; tlbre");
4396 mas1 = mfspr(SPR_MAS1);
4398 if (!(mas1 & MAS1_VALID))
4400 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
4402 mas1 &= ~MAS1_VALID;
4403 mtspr(SPR_MAS1, mas1);
4404 __asm __volatile("isync; tlbwe; isync; msync");
4410 /* Print out contents of the MAS registers for each TLB0 entry */
4412 #ifdef __powerpc64__
4413 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
4415 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
4426 if (mas1 & MAS1_VALID)
4431 if (mas1 & MAS1_IPROT)
4436 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
4437 tid = MAS1_GETTID(mas1);
4439 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4442 size = tsize2size(tsize);
4444 printf("%3d: (%s) [AS=%d] "
4445 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
4446 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
4447 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
4450 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
4452 uint32_t mas0, mas1, mas3, mas7;
4453 #ifdef __powerpc64__
4458 int entryidx, way, idx;
4460 printf("TLB0 entries:\n");
4461 for (way = 0; way < TLB0_WAYS; way ++)
4462 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
4464 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4465 mtspr(SPR_MAS0, mas0);
4467 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
4468 mtspr(SPR_MAS2, mas2);
4470 __asm __volatile("isync; tlbre");
4472 mas1 = mfspr(SPR_MAS1);
4473 mas2 = mfspr(SPR_MAS2);
4474 mas3 = mfspr(SPR_MAS3);
4475 mas7 = mfspr(SPR_MAS7);
4477 idx = tlb0_tableidx(mas2, way);
4478 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
4483 * Print out contents of the MAS registers for each TLB1 entry
4485 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
4487 uint32_t mas0, mas1, mas3, mas7;
4488 #ifdef __powerpc64__
4495 printf("TLB1 entries:\n");
4496 for (i = 0; i < TLB1_ENTRIES; i++) {
4498 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
4499 mtspr(SPR_MAS0, mas0);
4501 __asm __volatile("isync; tlbre");
4503 mas1 = mfspr(SPR_MAS1);
4504 mas2 = mfspr(SPR_MAS2);
4505 mas3 = mfspr(SPR_MAS3);
4506 mas7 = mfspr(SPR_MAS7);
4508 tlb_print_entry(i, mas1, mas2, mas3, mas7);