2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/types.h>
55 #include <sys/param.h>
56 #include <sys/malloc.h>
60 #include <sys/queue.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/linker.h>
64 #include <sys/msgbuf.h>
66 #include <sys/mutex.h>
67 #include <sys/sched.h>
69 #include <sys/vmmeter.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
82 #include <machine/cpu.h>
83 #include <machine/pcb.h>
84 #include <machine/platform.h>
86 #include <machine/tlb.h>
87 #include <machine/spr.h>
88 #include <machine/vmparam.h>
89 #include <machine/md_var.h>
90 #include <machine/mmuvar.h>
91 #include <machine/pmap.h>
92 #include <machine/pte.h>
97 #define debugf(fmt, args...) printf(fmt, ##args)
99 #define debugf(fmt, args...)
102 #define TODO panic("%s: not implemented", __func__);
104 extern struct mtx sched_lock;
106 extern int dumpsys_minidump;
108 extern unsigned char _etext[];
109 extern unsigned char _end[];
111 extern uint32_t *bootinfo;
114 extern uint32_t bp_kernload;
118 vm_offset_t kernstart;
121 /* Message buffer and tables. */
122 static vm_offset_t data_start;
123 static vm_size_t data_end;
125 /* Phys/avail memory regions. */
126 static struct mem_region *availmem_regions;
127 static int availmem_regions_sz;
128 static struct mem_region *physmem_regions;
129 static int physmem_regions_sz;
131 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
132 static vm_offset_t zero_page_va;
133 static struct mtx zero_page_mutex;
135 static struct mtx tlbivax_mutex;
138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
139 * by idle thred only, no lock required.
141 static vm_offset_t zero_page_idle_va;
143 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
144 static vm_offset_t copy_page_src_va;
145 static vm_offset_t copy_page_dst_va;
146 static struct mtx copy_page_mutex;
148 /**************************************************************************/
150 /**************************************************************************/
152 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
153 vm_prot_t, boolean_t);
155 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
156 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
159 * If user pmap is processed with mmu_booke_remove and the resident count
160 * drops to 0, there are no more pages to remove, so we need not continue.
162 #define PMAP_REMOVE_DONE(pmap) \
163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
165 extern void tid_flush(tlbtid_t);
167 /**************************************************************************/
168 /* TLB and TID handling */
169 /**************************************************************************/
171 /* Translation ID busy table */
172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
176 * core revisions and should be read from h/w registers during early config.
178 uint32_t tlb0_entries;
180 uint32_t tlb0_entries_per_way;
182 #define TLB0_ENTRIES (tlb0_entries)
183 #define TLB0_WAYS (tlb0_ways)
184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
186 #define TLB1_ENTRIES 16
188 /* In-ram copy of the TLB1 */
189 static tlb_entry_t tlb1[TLB1_ENTRIES];
191 /* Next free entry in the TLB1 */
192 static unsigned int tlb1_idx;
194 static tlbtid_t tid_alloc(struct pmap *);
196 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
198 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
199 static void tlb1_write_entry(unsigned int);
200 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
201 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
203 static vm_size_t tsize2size(unsigned int);
204 static unsigned int size2tsize(vm_size_t);
205 static unsigned int ilog2(unsigned int);
207 static void set_mas4_defaults(void);
209 static inline void tlb0_flush_entry(vm_offset_t);
210 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
212 /**************************************************************************/
213 /* Page table management */
214 /**************************************************************************/
216 /* Data for the pv entry allocation mechanism */
217 static uma_zone_t pvzone;
218 static struct vm_object pvzone_obj;
219 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
221 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
223 #ifndef PMAP_SHPGPERPROC
224 #define PMAP_SHPGPERPROC 200
227 static void ptbl_init(void);
228 static struct ptbl_buf *ptbl_buf_alloc(void);
229 static void ptbl_buf_free(struct ptbl_buf *);
230 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
232 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
233 static void ptbl_free(mmu_t, pmap_t, unsigned int);
234 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
235 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
237 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
238 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
239 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
240 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
242 static pv_entry_t pv_alloc(void);
243 static void pv_free(pv_entry_t);
244 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
245 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
247 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
248 #define PTBL_BUFS (128 * 16)
251 TAILQ_ENTRY(ptbl_buf) link; /* list link */
252 vm_offset_t kva; /* va of mapping */
255 /* ptbl free list and a lock used for access synchronization. */
256 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
257 static struct mtx ptbl_buf_freelist_lock;
259 /* Base address of kva space allocated fot ptbl bufs. */
260 static vm_offset_t ptbl_buf_pool_vabase;
262 /* Pointer to ptbl_buf structures. */
263 static struct ptbl_buf *ptbl_bufs;
265 void pmap_bootstrap_ap(volatile uint32_t *);
268 * Kernel MMU interface
270 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
271 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
272 static void mmu_booke_clear_reference(mmu_t, vm_page_t);
273 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
274 vm_size_t, vm_offset_t);
275 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
276 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
277 vm_prot_t, boolean_t);
278 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
279 vm_page_t, vm_prot_t);
280 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
282 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
283 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
285 static void mmu_booke_init(mmu_t);
286 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
287 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
288 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
289 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
290 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
292 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
294 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
295 vm_object_t, vm_pindex_t, vm_size_t);
296 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
297 static void mmu_booke_page_init(mmu_t, vm_page_t);
298 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
299 static void mmu_booke_pinit(mmu_t, pmap_t);
300 static void mmu_booke_pinit0(mmu_t, pmap_t);
301 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
303 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
304 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
305 static void mmu_booke_release(mmu_t, pmap_t);
306 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
307 static void mmu_booke_remove_all(mmu_t, vm_page_t);
308 static void mmu_booke_remove_write(mmu_t, vm_page_t);
309 static void mmu_booke_zero_page(mmu_t, vm_page_t);
310 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
311 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
312 static void mmu_booke_activate(mmu_t, struct thread *);
313 static void mmu_booke_deactivate(mmu_t, struct thread *);
314 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
315 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
316 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
317 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
318 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
319 static void mmu_booke_kremove(mmu_t, vm_offset_t);
320 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
321 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
323 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
324 vm_size_t, vm_size_t *);
325 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
326 vm_size_t, vm_offset_t);
327 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
329 static mmu_method_t mmu_booke_methods[] = {
330 /* pmap dispatcher interface */
331 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
332 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
333 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference),
334 MMUMETHOD(mmu_copy, mmu_booke_copy),
335 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
336 MMUMETHOD(mmu_enter, mmu_booke_enter),
337 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
338 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
339 MMUMETHOD(mmu_extract, mmu_booke_extract),
340 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
341 MMUMETHOD(mmu_init, mmu_booke_init),
342 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
343 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
344 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
345 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
346 MMUMETHOD(mmu_map, mmu_booke_map),
347 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
348 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
349 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
350 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
351 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
352 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
353 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
354 MMUMETHOD(mmu_protect, mmu_booke_protect),
355 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
356 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
357 MMUMETHOD(mmu_release, mmu_booke_release),
358 MMUMETHOD(mmu_remove, mmu_booke_remove),
359 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
360 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
361 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
362 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
363 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
364 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
365 MMUMETHOD(mmu_activate, mmu_booke_activate),
366 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
368 /* Internal interfaces */
369 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
370 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
371 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
372 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
373 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
374 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
375 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
377 /* dumpsys() support */
378 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
379 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
380 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
385 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
396 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
399 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
400 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
402 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
403 ("tlb_miss_lock: tried to lock self"));
405 tlb_lock(pc->pc_booke_tlb_lock);
407 CTR1(KTR_PMAP, "%s: locked", __func__);
414 tlb_miss_unlock(void)
422 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
424 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
425 __func__, pc->pc_cpuid);
427 tlb_unlock(pc->pc_booke_tlb_lock);
429 CTR1(KTR_PMAP, "%s: unlocked", __func__);
435 /* Return number of entries in TLB0. */
437 tlb0_get_tlbconf(void)
441 tlb0_cfg = mfspr(SPR_TLB0CFG);
442 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
443 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
444 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
447 /* Initialize pool of kva ptbl buffers. */
453 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
454 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
455 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
456 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
458 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
459 TAILQ_INIT(&ptbl_buf_freelist);
461 for (i = 0; i < PTBL_BUFS; i++) {
462 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
463 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
467 /* Get a ptbl_buf from the freelist. */
468 static struct ptbl_buf *
471 struct ptbl_buf *buf;
473 mtx_lock(&ptbl_buf_freelist_lock);
474 buf = TAILQ_FIRST(&ptbl_buf_freelist);
476 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
477 mtx_unlock(&ptbl_buf_freelist_lock);
479 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
484 /* Return ptbl buff to free pool. */
486 ptbl_buf_free(struct ptbl_buf *buf)
489 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
491 mtx_lock(&ptbl_buf_freelist_lock);
492 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
493 mtx_unlock(&ptbl_buf_freelist_lock);
497 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
500 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
502 struct ptbl_buf *pbuf;
504 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
508 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
509 if (pbuf->kva == (vm_offset_t)ptbl) {
510 /* Remove from pmap ptbl buf list. */
511 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
513 /* Free corresponding ptbl buf. */
519 /* Allocate page table. */
521 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
523 vm_page_t mtbl[PTBL_PAGES];
525 struct ptbl_buf *pbuf;
530 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
531 (pmap == kernel_pmap), pdir_idx);
533 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
534 ("ptbl_alloc: invalid pdir_idx"));
535 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
536 ("pte_alloc: valid ptbl entry exists!"));
538 pbuf = ptbl_buf_alloc();
540 panic("pte_alloc: couldn't alloc kernel virtual memory");
542 ptbl = (pte_t *)pbuf->kva;
544 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
546 /* Allocate ptbl pages, this will sleep! */
547 for (i = 0; i < PTBL_PAGES; i++) {
548 pidx = (PTBL_PAGES * pdir_idx) + i;
549 while ((m = vm_page_alloc(NULL, pidx,
550 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
553 vm_page_unlock_queues();
555 vm_page_lock_queues();
561 /* Map allocated pages into kernel_pmap. */
562 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
564 /* Zero whole ptbl. */
565 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
567 /* Add pbuf to the pmap ptbl bufs list. */
568 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
573 /* Free ptbl pages and invalidate pdir entry. */
575 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
583 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
584 (pmap == kernel_pmap), pdir_idx);
586 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
587 ("ptbl_free: invalid pdir_idx"));
589 ptbl = pmap->pm_pdir[pdir_idx];
591 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
593 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
596 * Invalidate the pdir entry as soon as possible, so that other CPUs
597 * don't attempt to look up the page tables we are releasing.
599 mtx_lock_spin(&tlbivax_mutex);
602 pmap->pm_pdir[pdir_idx] = NULL;
605 mtx_unlock_spin(&tlbivax_mutex);
607 for (i = 0; i < PTBL_PAGES; i++) {
608 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
609 pa = pte_vatopa(mmu, kernel_pmap, va);
610 m = PHYS_TO_VM_PAGE(pa);
611 vm_page_free_zero(m);
612 atomic_subtract_int(&cnt.v_wire_count, 1);
613 mmu_booke_kremove(mmu, va);
616 ptbl_free_pmap_ptbl(pmap, ptbl);
620 * Decrement ptbl pages hold count and attempt to free ptbl pages.
621 * Called when removing pte entry from ptbl.
623 * Return 1 if ptbl pages were freed.
626 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
633 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
634 (pmap == kernel_pmap), pdir_idx);
636 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
637 ("ptbl_unhold: invalid pdir_idx"));
638 KASSERT((pmap != kernel_pmap),
639 ("ptbl_unhold: unholding kernel ptbl!"));
641 ptbl = pmap->pm_pdir[pdir_idx];
643 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
644 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
645 ("ptbl_unhold: non kva ptbl"));
647 /* decrement hold count */
648 for (i = 0; i < PTBL_PAGES; i++) {
649 pa = pte_vatopa(mmu, kernel_pmap,
650 (vm_offset_t)ptbl + (i * PAGE_SIZE));
651 m = PHYS_TO_VM_PAGE(pa);
656 * Free ptbl pages if there are no pte etries in this ptbl.
657 * wire_count has the same value for all ptbl pages, so check the last
660 if (m->wire_count == 0) {
661 ptbl_free(mmu, pmap, pdir_idx);
663 //debugf("ptbl_unhold: e (freed ptbl)\n");
671 * Increment hold count for ptbl pages. This routine is used when a new pte
672 * entry is being inserted into the ptbl.
675 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
682 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
685 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
686 ("ptbl_hold: invalid pdir_idx"));
687 KASSERT((pmap != kernel_pmap),
688 ("ptbl_hold: holding kernel ptbl!"));
690 ptbl = pmap->pm_pdir[pdir_idx];
692 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
694 for (i = 0; i < PTBL_PAGES; i++) {
695 pa = pte_vatopa(mmu, kernel_pmap,
696 (vm_offset_t)ptbl + (i * PAGE_SIZE));
697 m = PHYS_TO_VM_PAGE(pa);
702 /* Allocate pv_entry structure. */
709 if (pv_entry_count > pv_entry_high_water)
711 pv = uma_zalloc(pvzone, M_NOWAIT);
716 /* Free pv_entry structure. */
718 pv_free(pv_entry_t pve)
722 uma_zfree(pvzone, pve);
726 /* Allocate and initialize pv_entry structure. */
728 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
732 //int su = (pmap == kernel_pmap);
733 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
734 // (u_int32_t)pmap, va, (u_int32_t)m);
738 panic("pv_insert: no pv entries!");
744 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
745 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
747 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
749 //debugf("pv_insert: e\n");
752 /* Destroy pv entry. */
754 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
758 //int su = (pmap == kernel_pmap);
759 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
761 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
762 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
765 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
766 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
767 /* remove from pv_list */
768 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
769 if (TAILQ_EMPTY(&m->md.pv_list))
770 vm_page_aflag_clear(m, PGA_WRITEABLE);
772 /* free pv entry struct */
778 //debugf("pv_remove: e\n");
782 * Clean pte entry, try to free page table page if requested.
784 * Return 1 if ptbl pages were freed, otherwise return 0.
787 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
789 unsigned int pdir_idx = PDIR_IDX(va);
790 unsigned int ptbl_idx = PTBL_IDX(va);
795 //int su = (pmap == kernel_pmap);
796 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
797 // su, (u_int32_t)pmap, va, flags);
799 ptbl = pmap->pm_pdir[pdir_idx];
800 KASSERT(ptbl, ("pte_remove: null ptbl"));
802 pte = &ptbl[ptbl_idx];
804 if (pte == NULL || !PTE_ISVALID(pte))
807 if (PTE_ISWIRED(pte))
808 pmap->pm_stats.wired_count--;
810 /* Handle managed entry. */
811 if (PTE_ISMANAGED(pte)) {
812 /* Get vm_page_t for mapped pte. */
813 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
815 if (PTE_ISMODIFIED(pte))
818 if (PTE_ISREFERENCED(pte))
819 vm_page_aflag_set(m, PGA_REFERENCED);
821 pv_remove(pmap, va, m);
824 mtx_lock_spin(&tlbivax_mutex);
827 tlb0_flush_entry(va);
832 mtx_unlock_spin(&tlbivax_mutex);
834 pmap->pm_stats.resident_count--;
836 if (flags & PTBL_UNHOLD) {
837 //debugf("pte_remove: e (unhold)\n");
838 return (ptbl_unhold(mmu, pmap, pdir_idx));
841 //debugf("pte_remove: e\n");
846 * Insert PTE for a given page and virtual address.
849 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
851 unsigned int pdir_idx = PDIR_IDX(va);
852 unsigned int ptbl_idx = PTBL_IDX(va);
855 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
856 pmap == kernel_pmap, pmap, va);
858 /* Get the page table pointer. */
859 ptbl = pmap->pm_pdir[pdir_idx];
862 /* Allocate page table pages. */
863 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
866 * Check if there is valid mapping for requested
867 * va, if there is, remove it.
869 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
870 if (PTE_ISVALID(pte)) {
871 pte_remove(mmu, pmap, va, PTBL_HOLD);
874 * pte is not used, increment hold count
877 if (pmap != kernel_pmap)
878 ptbl_hold(mmu, pmap, pdir_idx);
883 * Insert pv_entry into pv_list for mapped page if part of managed
886 if ((m->oflags & VPO_UNMANAGED) == 0) {
887 flags |= PTE_MANAGED;
889 /* Create and insert pv entry. */
890 pv_insert(pmap, va, m);
893 pmap->pm_stats.resident_count++;
895 mtx_lock_spin(&tlbivax_mutex);
898 tlb0_flush_entry(va);
899 if (pmap->pm_pdir[pdir_idx] == NULL) {
901 * If we just allocated a new page table, hook it in
904 pmap->pm_pdir[pdir_idx] = ptbl;
906 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
907 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
908 pte->flags |= (PTE_VALID | flags);
911 mtx_unlock_spin(&tlbivax_mutex);
914 /* Return the pa for the given pmap/va. */
916 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
921 pte = pte_find(mmu, pmap, va);
922 if ((pte != NULL) && PTE_ISVALID(pte))
923 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
927 /* Get a pointer to a PTE in a page table. */
929 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
931 unsigned int pdir_idx = PDIR_IDX(va);
932 unsigned int ptbl_idx = PTBL_IDX(va);
934 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
936 if (pmap->pm_pdir[pdir_idx])
937 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
942 /**************************************************************************/
944 /**************************************************************************/
947 * This is called during booke_init, before the system is really initialized.
950 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
952 vm_offset_t phys_kernelend;
953 struct mem_region *mp, *mp1;
956 u_int phys_avail_count;
957 vm_size_t physsz, hwphyssz, kstack0_sz;
958 vm_offset_t kernel_pdir, kstack0, va;
959 vm_paddr_t kstack0_phys;
963 debugf("mmu_booke_bootstrap: entered\n");
966 bp_kernload = kernload;
969 /* Initialize invalidation mutex */
970 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
972 /* Read TLB0 size and associativity. */
976 * Align kernel start and end address (kernel image).
977 * Note that kernel end does not necessarily relate to kernsize.
978 * kernsize is the size of the kernel that is actually mapped.
979 * Also note that "start - 1" is deliberate. With SMP, the
980 * entry point is exactly a page from the actual load address.
981 * As such, trunc_page() has no effect and we're off by a page.
982 * Since we always have the ELF header between the load address
983 * and the entry point, we can safely subtract 1 to compensate.
985 kernstart = trunc_page(start - 1);
986 data_start = round_page(kernelend);
987 data_end = data_start;
990 * Addresses of preloaded modules (like file systems) use
991 * physical addresses. Make sure we relocate those into
994 preload_addr_relocate = kernstart - kernload;
996 /* Allocate the dynamic per-cpu area. */
997 dpcpu = (void *)data_end;
998 data_end += DPCPU_SIZE;
1000 /* Allocate space for the message buffer. */
1001 msgbufp = (struct msgbuf *)data_end;
1002 data_end += msgbufsize;
1003 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1006 data_end = round_page(data_end);
1008 /* Allocate space for ptbl_bufs. */
1009 ptbl_bufs = (struct ptbl_buf *)data_end;
1010 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1011 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1014 data_end = round_page(data_end);
1016 /* Allocate PTE tables for kernel KVA. */
1017 kernel_pdir = data_end;
1018 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1019 PDIR_SIZE - 1) / PDIR_SIZE;
1020 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1021 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1022 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1024 debugf(" data_end: 0x%08x\n", data_end);
1025 if (data_end - kernstart > kernsize) {
1026 kernsize += tlb1_mapin_region(kernstart + kernsize,
1027 kernload + kernsize, (data_end - kernstart) - kernsize);
1029 data_end = kernstart + kernsize;
1030 debugf(" updated data_end: 0x%08x\n", data_end);
1033 * Clear the structures - note we can only do it safely after the
1034 * possible additional TLB1 translations are in place (above) so that
1035 * all range up to the currently calculated 'data_end' is covered.
1037 dpcpu_init(dpcpu, 0);
1038 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1039 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1041 /*******************************************************/
1042 /* Set the start and end of kva. */
1043 /*******************************************************/
1044 virtual_avail = round_page(data_end);
1045 virtual_end = VM_MAX_KERNEL_ADDRESS;
1047 /* Allocate KVA space for page zero/copy operations. */
1048 zero_page_va = virtual_avail;
1049 virtual_avail += PAGE_SIZE;
1050 zero_page_idle_va = virtual_avail;
1051 virtual_avail += PAGE_SIZE;
1052 copy_page_src_va = virtual_avail;
1053 virtual_avail += PAGE_SIZE;
1054 copy_page_dst_va = virtual_avail;
1055 virtual_avail += PAGE_SIZE;
1056 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1057 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1058 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1059 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1061 /* Initialize page zero/copy mutexes. */
1062 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1063 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1065 /* Allocate KVA space for ptbl bufs. */
1066 ptbl_buf_pool_vabase = virtual_avail;
1067 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1068 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1069 ptbl_buf_pool_vabase, virtual_avail);
1071 /* Calculate corresponding physical addresses for the kernel region. */
1072 phys_kernelend = kernload + kernsize;
1073 debugf("kernel image and allocated data:\n");
1074 debugf(" kernload = 0x%08x\n", kernload);
1075 debugf(" kernstart = 0x%08x\n", kernstart);
1076 debugf(" kernsize = 0x%08x\n", kernsize);
1078 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1079 panic("mmu_booke_bootstrap: phys_avail too small");
1082 * Remove kernel physical address range from avail regions list. Page
1083 * align all regions. Non-page aligned memory isn't very interesting
1084 * to us. Also, sort the entries for ascending addresses.
1087 /* Retrieve phys/avail mem regions */
1088 mem_regions(&physmem_regions, &physmem_regions_sz,
1089 &availmem_regions, &availmem_regions_sz);
1091 cnt = availmem_regions_sz;
1092 debugf("processing avail regions:\n");
1093 for (mp = availmem_regions; mp->mr_size; mp++) {
1095 e = mp->mr_start + mp->mr_size;
1096 debugf(" %08x-%08x -> ", s, e);
1097 /* Check whether this region holds all of the kernel. */
1098 if (s < kernload && e > phys_kernelend) {
1099 availmem_regions[cnt].mr_start = phys_kernelend;
1100 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1103 /* Look whether this regions starts within the kernel. */
1104 if (s >= kernload && s < phys_kernelend) {
1105 if (e <= phys_kernelend)
1109 /* Now look whether this region ends within the kernel. */
1110 if (e > kernload && e <= phys_kernelend) {
1115 /* Now page align the start and size of the region. */
1121 debugf("%08x-%08x = %x\n", s, e, sz);
1123 /* Check whether some memory is left here. */
1127 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1133 /* Do an insertion sort. */
1134 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1135 if (s < mp1->mr_start)
1138 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1146 availmem_regions_sz = cnt;
1148 /*******************************************************/
1149 /* Steal physical memory for kernel stack from the end */
1150 /* of the first avail region */
1151 /*******************************************************/
1152 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1153 kstack0_phys = availmem_regions[0].mr_start +
1154 availmem_regions[0].mr_size;
1155 kstack0_phys -= kstack0_sz;
1156 availmem_regions[0].mr_size -= kstack0_sz;
1158 /*******************************************************/
1159 /* Fill in phys_avail table, based on availmem_regions */
1160 /*******************************************************/
1161 phys_avail_count = 0;
1164 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1166 debugf("fill in phys_avail:\n");
1167 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1169 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1170 availmem_regions[i].mr_start,
1171 availmem_regions[i].mr_start +
1172 availmem_regions[i].mr_size,
1173 availmem_regions[i].mr_size);
1175 if (hwphyssz != 0 &&
1176 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1177 debugf(" hw.physmem adjust\n");
1178 if (physsz < hwphyssz) {
1179 phys_avail[j] = availmem_regions[i].mr_start;
1181 availmem_regions[i].mr_start +
1189 phys_avail[j] = availmem_regions[i].mr_start;
1190 phys_avail[j + 1] = availmem_regions[i].mr_start +
1191 availmem_regions[i].mr_size;
1193 physsz += availmem_regions[i].mr_size;
1195 physmem = btoc(physsz);
1197 /* Calculate the last available physical address. */
1198 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1200 Maxmem = powerpc_btop(phys_avail[i + 1]);
1202 debugf("Maxmem = 0x%08lx\n", Maxmem);
1203 debugf("phys_avail_count = %d\n", phys_avail_count);
1204 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1207 /*******************************************************/
1208 /* Initialize (statically allocated) kernel pmap. */
1209 /*******************************************************/
1210 PMAP_LOCK_INIT(kernel_pmap);
1211 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1213 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1214 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1215 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1216 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1218 /* Initialize kernel pdir */
1219 for (i = 0; i < kernel_ptbls; i++)
1220 kernel_pmap->pm_pdir[kptbl_min + i] =
1221 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1223 for (i = 0; i < MAXCPU; i++) {
1224 kernel_pmap->pm_tid[i] = TID_KERNEL;
1226 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1227 tidbusy[i][0] = kernel_pmap;
1231 * Fill in PTEs covering kernel code and data. They are not required
1232 * for address translation, as this area is covered by static TLB1
1233 * entries, but for pte_vatopa() to work correctly with kernel area
1236 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1237 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1238 pte->rpn = kernload + (va - kernstart);
1239 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1242 /* Mark kernel_pmap active on all CPUs */
1243 CPU_FILL(&kernel_pmap->pm_active);
1245 /*******************************************************/
1247 /*******************************************************/
1249 /* Enter kstack0 into kernel map, provide guard page */
1250 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1251 thread0.td_kstack = kstack0;
1252 thread0.td_kstack_pages = KSTACK_PAGES;
1254 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1255 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1256 kstack0_phys, kstack0_phys + kstack0_sz);
1257 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1259 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1260 for (i = 0; i < KSTACK_PAGES; i++) {
1261 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1262 kstack0 += PAGE_SIZE;
1263 kstack0_phys += PAGE_SIZE;
1266 debugf("virtual_avail = %08x\n", virtual_avail);
1267 debugf("virtual_end = %08x\n", virtual_end);
1269 debugf("mmu_booke_bootstrap: exit\n");
1273 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1278 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1279 * have the snapshot of its contents in the s/w tlb1[] table, so use
1280 * these values directly to (re)program AP's TLB1 hardware.
1282 for (i = 0; i < tlb1_idx; i ++) {
1283 /* Skip invalid entries */
1284 if (!(tlb1[i].mas1 & MAS1_VALID))
1287 tlb1_write_entry(i);
1290 set_mas4_defaults();
1294 * Get the physical page address for the given pmap/virtual address.
1297 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1302 pa = pte_vatopa(mmu, pmap, va);
1309 * Extract the physical page address associated with the given
1310 * kernel virtual address.
1313 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1316 return (pte_vatopa(mmu, kernel_pmap, va));
1320 * Initialize the pmap module.
1321 * Called by vm_init, to initialize any structures that the pmap
1322 * system needs to map virtual memory.
1325 mmu_booke_init(mmu_t mmu)
1327 int shpgperproc = PMAP_SHPGPERPROC;
1330 * Initialize the address space (zone) for the pv entries. Set a
1331 * high water mark so that the system can recover from excessive
1332 * numbers of pv entries.
1334 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1335 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1337 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1338 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1340 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1341 pv_entry_high_water = 9 * (pv_entry_max / 10);
1343 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1345 /* Pre-fill pvzone with initial number of pv entries. */
1346 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1348 /* Initialize ptbl allocation. */
1353 * Map a list of wired pages into kernel virtual address space. This is
1354 * intended for temporary mappings which do not need page modification or
1355 * references recorded. Existing mappings in the region are overwritten.
1358 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1363 while (count-- > 0) {
1364 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1371 * Remove page mappings from kernel virtual address space. Intended for
1372 * temporary mappings entered by mmu_booke_qenter.
1375 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1380 while (count-- > 0) {
1381 mmu_booke_kremove(mmu, va);
1387 * Map a wired page into kernel virtual address space.
1390 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1392 unsigned int pdir_idx = PDIR_IDX(va);
1393 unsigned int ptbl_idx = PTBL_IDX(va);
1397 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1398 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1400 flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1402 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1404 mtx_lock_spin(&tlbivax_mutex);
1407 if (PTE_ISVALID(pte)) {
1409 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1411 /* Flush entry from TLB0 */
1412 tlb0_flush_entry(va);
1415 pte->rpn = pa & ~PTE_PA_MASK;
1418 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1419 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1420 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1422 /* Flush the real memory from the instruction cache. */
1423 if ((flags & (PTE_I | PTE_G)) == 0) {
1424 __syncicache((void *)va, PAGE_SIZE);
1428 mtx_unlock_spin(&tlbivax_mutex);
1432 * Remove a page from kernel page table.
1435 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1437 unsigned int pdir_idx = PDIR_IDX(va);
1438 unsigned int ptbl_idx = PTBL_IDX(va);
1441 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1443 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1444 (va <= VM_MAX_KERNEL_ADDRESS)),
1445 ("mmu_booke_kremove: invalid va"));
1447 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1449 if (!PTE_ISVALID(pte)) {
1451 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1456 mtx_lock_spin(&tlbivax_mutex);
1459 /* Invalidate entry in TLB0, update PTE. */
1460 tlb0_flush_entry(va);
1465 mtx_unlock_spin(&tlbivax_mutex);
1469 * Initialize pmap associated with process 0.
1472 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1475 mmu_booke_pinit(mmu, pmap);
1476 PCPU_SET(curpmap, pmap);
1480 * Initialize a preallocated and zeroed pmap structure,
1481 * such as one in a vmspace structure.
1484 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1488 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1489 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1491 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1493 PMAP_LOCK_INIT(pmap);
1494 for (i = 0; i < MAXCPU; i++)
1495 pmap->pm_tid[i] = TID_NONE;
1496 CPU_ZERO(&kernel_pmap->pm_active);
1497 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1498 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1499 TAILQ_INIT(&pmap->pm_ptbl_list);
1503 * Release any resources held by the given physical map.
1504 * Called when a pmap initialized by mmu_booke_pinit is being released.
1505 * Should only be called if the map contains no valid mappings.
1508 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1511 KASSERT(pmap->pm_stats.resident_count == 0,
1512 ("pmap_release: pmap resident count %ld != 0",
1513 pmap->pm_stats.resident_count));
1515 PMAP_LOCK_DESTROY(pmap);
1519 * Insert the given physical page at the specified virtual address in the
1520 * target physical map with the protection requested. If specified the page
1521 * will be wired down.
1524 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1525 vm_prot_t prot, boolean_t wired)
1528 vm_page_lock_queues();
1530 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1531 vm_page_unlock_queues();
1536 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1537 vm_prot_t prot, boolean_t wired)
1544 pa = VM_PAGE_TO_PHYS(m);
1545 su = (pmap == kernel_pmap);
1548 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1549 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1550 // (u_int32_t)pmap, su, pmap->pm_tid,
1551 // (u_int32_t)m, va, pa, prot, wired);
1554 KASSERT(((va >= virtual_avail) &&
1555 (va <= VM_MAX_KERNEL_ADDRESS)),
1556 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1558 KASSERT((va <= VM_MAXUSER_ADDRESS),
1559 ("mmu_booke_enter_locked: user pmap, non user va"));
1561 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1562 VM_OBJECT_LOCKED(m->object),
1563 ("mmu_booke_enter_locked: page %p is not busy", m));
1565 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1568 * If there is an existing mapping, and the physical address has not
1569 * changed, must be protection or wiring change.
1571 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1572 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1575 * Before actually updating pte->flags we calculate and
1576 * prepare its new value in a helper var.
1579 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1581 /* Wiring change, just update stats. */
1583 if (!PTE_ISWIRED(pte)) {
1585 pmap->pm_stats.wired_count++;
1588 if (PTE_ISWIRED(pte)) {
1589 flags &= ~PTE_WIRED;
1590 pmap->pm_stats.wired_count--;
1594 if (prot & VM_PROT_WRITE) {
1595 /* Add write permissions. */
1600 if ((flags & PTE_MANAGED) != 0)
1601 vm_page_aflag_set(m, PGA_WRITEABLE);
1603 /* Handle modified pages, sense modify status. */
1606 * The PTE_MODIFIED flag could be set by underlying
1607 * TLB misses since we last read it (above), possibly
1608 * other CPUs could update it so we check in the PTE
1609 * directly rather than rely on that saved local flags
1612 if (PTE_ISMODIFIED(pte))
1616 if (prot & VM_PROT_EXECUTE) {
1622 * Check existing flags for execute permissions: if we
1623 * are turning execute permissions on, icache should
1626 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1630 flags &= ~PTE_REFERENCED;
1633 * The new flags value is all calculated -- only now actually
1636 mtx_lock_spin(&tlbivax_mutex);
1639 tlb0_flush_entry(va);
1643 mtx_unlock_spin(&tlbivax_mutex);
1647 * If there is an existing mapping, but it's for a different
1648 * physical address, pte_enter() will delete the old mapping.
1650 //if ((pte != NULL) && PTE_ISVALID(pte))
1651 // debugf("mmu_booke_enter_locked: replace\n");
1653 // debugf("mmu_booke_enter_locked: new\n");
1655 /* Now set up the flags and install the new mapping. */
1656 flags = (PTE_SR | PTE_VALID);
1662 if (prot & VM_PROT_WRITE) {
1667 if ((m->oflags & VPO_UNMANAGED) == 0)
1668 vm_page_aflag_set(m, PGA_WRITEABLE);
1671 if (prot & VM_PROT_EXECUTE) {
1677 /* If its wired update stats. */
1679 pmap->pm_stats.wired_count++;
1683 pte_enter(mmu, pmap, m, va, flags);
1685 /* Flush the real memory from the instruction cache. */
1686 if (prot & VM_PROT_EXECUTE)
1690 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1691 __syncicache((void *)va, PAGE_SIZE);
1697 * Maps a sequence of resident pages belonging to the same object.
1698 * The sequence begins with the given page m_start. This page is
1699 * mapped at the given virtual address start. Each subsequent page is
1700 * mapped at a virtual address that is offset from start by the same
1701 * amount as the page is offset from m_start within the object. The
1702 * last page in the sequence is the page with the largest offset from
1703 * m_start that can be mapped at a virtual address less than the given
1704 * virtual address end. Not every virtual page between start and end
1705 * is mapped; only those for which a resident page exists with the
1706 * corresponding offset from m_start are mapped.
1709 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1710 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1713 vm_pindex_t diff, psize;
1715 psize = atop(end - start);
1717 vm_page_lock_queues();
1719 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1720 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1721 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1722 m = TAILQ_NEXT(m, listq);
1724 vm_page_unlock_queues();
1729 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1733 vm_page_lock_queues();
1735 mmu_booke_enter_locked(mmu, pmap, va, m,
1736 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1737 vm_page_unlock_queues();
1742 * Remove the given range of addresses from the specified map.
1744 * It is assumed that the start and end are properly rounded to the page size.
1747 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1752 int su = (pmap == kernel_pmap);
1754 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1755 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1758 KASSERT(((va >= virtual_avail) &&
1759 (va <= VM_MAX_KERNEL_ADDRESS)),
1760 ("mmu_booke_remove: kernel pmap, non kernel va"));
1762 KASSERT((va <= VM_MAXUSER_ADDRESS),
1763 ("mmu_booke_remove: user pmap, non user va"));
1766 if (PMAP_REMOVE_DONE(pmap)) {
1767 //debugf("mmu_booke_remove: e (empty)\n");
1771 hold_flag = PTBL_HOLD_FLAG(pmap);
1772 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1774 vm_page_lock_queues();
1776 for (; va < endva; va += PAGE_SIZE) {
1777 pte = pte_find(mmu, pmap, va);
1778 if ((pte != NULL) && PTE_ISVALID(pte))
1779 pte_remove(mmu, pmap, va, hold_flag);
1782 vm_page_unlock_queues();
1784 //debugf("mmu_booke_remove: e\n");
1788 * Remove physical page from all pmaps in which it resides.
1791 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1796 vm_page_lock_queues();
1797 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1798 pvn = TAILQ_NEXT(pv, pv_link);
1800 PMAP_LOCK(pv->pv_pmap);
1801 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1802 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1803 PMAP_UNLOCK(pv->pv_pmap);
1805 vm_page_aflag_clear(m, PGA_WRITEABLE);
1806 vm_page_unlock_queues();
1810 * Map a range of physical addresses into kernel virtual address space.
1813 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1814 vm_paddr_t pa_end, int prot)
1816 vm_offset_t sva = *virt;
1817 vm_offset_t va = sva;
1819 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1820 // sva, pa_start, pa_end);
1822 while (pa_start < pa_end) {
1823 mmu_booke_kenter(mmu, va, pa_start);
1825 pa_start += PAGE_SIZE;
1829 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1834 * The pmap must be activated before it's address space can be accessed in any
1838 mmu_booke_activate(mmu_t mmu, struct thread *td)
1843 pmap = &td->td_proc->p_vmspace->vm_pmap;
1845 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1846 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1848 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1850 mtx_lock_spin(&sched_lock);
1852 cpuid = PCPU_GET(cpuid);
1853 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1854 PCPU_SET(curpmap, pmap);
1856 if (pmap->pm_tid[cpuid] == TID_NONE)
1859 /* Load PID0 register with pmap tid value. */
1860 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1861 __asm __volatile("isync");
1863 mtx_unlock_spin(&sched_lock);
1865 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1866 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1870 * Deactivate the specified process's address space.
1873 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1877 pmap = &td->td_proc->p_vmspace->vm_pmap;
1879 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1880 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1882 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1883 PCPU_SET(curpmap, NULL);
1887 * Copy the range specified by src_addr/len
1888 * from the source map to the range dst_addr/len
1889 * in the destination map.
1891 * This routine is only advisory and need not do anything.
1894 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1895 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1901 * Set the physical protection on the specified range of this map as requested.
1904 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1911 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1912 mmu_booke_remove(mmu, pmap, sva, eva);
1916 if (prot & VM_PROT_WRITE)
1920 for (va = sva; va < eva; va += PAGE_SIZE) {
1921 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1922 if (PTE_ISVALID(pte)) {
1923 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1925 mtx_lock_spin(&tlbivax_mutex);
1928 /* Handle modified pages. */
1929 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1932 tlb0_flush_entry(va);
1933 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1936 mtx_unlock_spin(&tlbivax_mutex);
1944 * Clear the write and modified bits in each of the given page's mappings.
1947 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
1952 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1953 ("mmu_booke_remove_write: page %p is not managed", m));
1956 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1957 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1958 * is clear, no page table entries need updating.
1960 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1961 if ((m->oflags & VPO_BUSY) == 0 &&
1962 (m->aflags & PGA_WRITEABLE) == 0)
1964 vm_page_lock_queues();
1965 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1966 PMAP_LOCK(pv->pv_pmap);
1967 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
1968 if (PTE_ISVALID(pte)) {
1969 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1971 mtx_lock_spin(&tlbivax_mutex);
1974 /* Handle modified pages. */
1975 if (PTE_ISMODIFIED(pte))
1978 /* Flush mapping from TLB0. */
1979 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1982 mtx_unlock_spin(&tlbivax_mutex);
1985 PMAP_UNLOCK(pv->pv_pmap);
1987 vm_page_aflag_clear(m, PGA_WRITEABLE);
1988 vm_page_unlock_queues();
1992 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2001 va = trunc_page(va);
2002 sz = round_page(sz);
2004 vm_page_lock_queues();
2005 pmap = PCPU_GET(curpmap);
2006 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2009 pte = pte_find(mmu, pm, va);
2010 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2016 /* Create a mapping in the active pmap. */
2018 m = PHYS_TO_VM_PAGE(pa);
2020 pte_enter(mmu, pmap, m, addr,
2021 PTE_SR | PTE_VALID | PTE_UR);
2022 __syncicache((void *)addr, PAGE_SIZE);
2023 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2026 __syncicache((void *)va, PAGE_SIZE);
2031 vm_page_unlock_queues();
2035 * Atomically extract and hold the physical page with the given
2036 * pmap and virtual address pair if that mapping permits the given
2040 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2052 pte = pte_find(mmu, pmap, va);
2053 if ((pte != NULL) && PTE_ISVALID(pte)) {
2054 if (pmap == kernel_pmap)
2059 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2060 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2062 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2073 * Initialize a vm_page's machine-dependent fields.
2076 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2079 TAILQ_INIT(&m->md.pv_list);
2083 * mmu_booke_zero_page_area zeros the specified hardware page by
2084 * mapping it into virtual memory and using bzero to clear
2087 * off and size must reside within a single page.
2090 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2094 /* XXX KASSERT off and size are within a single page? */
2096 mtx_lock(&zero_page_mutex);
2099 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2100 bzero((caddr_t)va + off, size);
2101 mmu_booke_kremove(mmu, va);
2103 mtx_unlock(&zero_page_mutex);
2107 * mmu_booke_zero_page zeros the specified hardware page.
2110 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2113 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2117 * mmu_booke_copy_page copies the specified (machine independent) page by
2118 * mapping the page into virtual memory and using memcopy to copy the page,
2119 * one machine dependent page at a time.
2122 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2124 vm_offset_t sva, dva;
2126 sva = copy_page_src_va;
2127 dva = copy_page_dst_va;
2129 mtx_lock(©_page_mutex);
2130 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2131 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2132 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2133 mmu_booke_kremove(mmu, dva);
2134 mmu_booke_kremove(mmu, sva);
2135 mtx_unlock(©_page_mutex);
2139 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2140 * into virtual memory and using bzero to clear its contents. This is intended
2141 * to be called from the vm_pagezero process only and outside of Giant. No
2145 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2149 va = zero_page_idle_va;
2150 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2151 bzero((caddr_t)va, PAGE_SIZE);
2152 mmu_booke_kremove(mmu, va);
2156 * Return whether or not the specified physical page was modified
2157 * in any of physical maps.
2160 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2166 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2167 ("mmu_booke_is_modified: page %p is not managed", m));
2171 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
2172 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2173 * is clear, no PTEs can be modified.
2175 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2176 if ((m->oflags & VPO_BUSY) == 0 &&
2177 (m->aflags & PGA_WRITEABLE) == 0)
2179 vm_page_lock_queues();
2180 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2181 PMAP_LOCK(pv->pv_pmap);
2182 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2184 if (PTE_ISMODIFIED(pte))
2187 PMAP_UNLOCK(pv->pv_pmap);
2191 vm_page_unlock_queues();
2196 * Return whether or not the specified virtual address is eligible
2200 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2207 * Return whether or not the specified physical page was referenced
2208 * in any physical maps.
2211 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2217 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2218 ("mmu_booke_is_referenced: page %p is not managed", m));
2220 vm_page_lock_queues();
2221 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2222 PMAP_LOCK(pv->pv_pmap);
2223 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2225 if (PTE_ISREFERENCED(pte))
2228 PMAP_UNLOCK(pv->pv_pmap);
2232 vm_page_unlock_queues();
2237 * Clear the modify bits on the specified physical page.
2240 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2245 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2246 ("mmu_booke_clear_modify: page %p is not managed", m));
2247 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2248 KASSERT((m->oflags & VPO_BUSY) == 0,
2249 ("mmu_booke_clear_modify: page %p is busy", m));
2252 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2253 * If the object containing the page is locked and the page is not
2254 * VPO_BUSY, then PG_AWRITEABLE cannot be concurrently set.
2256 if ((m->aflags & PGA_WRITEABLE) == 0)
2258 vm_page_lock_queues();
2259 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2260 PMAP_LOCK(pv->pv_pmap);
2261 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2263 mtx_lock_spin(&tlbivax_mutex);
2266 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2267 tlb0_flush_entry(pv->pv_va);
2268 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2273 mtx_unlock_spin(&tlbivax_mutex);
2275 PMAP_UNLOCK(pv->pv_pmap);
2277 vm_page_unlock_queues();
2281 * Return a count of reference bits for a page, clearing those bits.
2282 * It is not necessary for every reference bit to be cleared, but it
2283 * is necessary that 0 only be returned when there are truly no
2284 * reference bits set.
2286 * XXX: The exact number of bits to check and clear is a matter that
2287 * should be tested and standardized at some point in the future for
2288 * optimal aging of shared pages.
2291 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2297 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2298 ("mmu_booke_ts_referenced: page %p is not managed", m));
2300 vm_page_lock_queues();
2301 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2302 PMAP_LOCK(pv->pv_pmap);
2303 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2305 if (PTE_ISREFERENCED(pte)) {
2306 mtx_lock_spin(&tlbivax_mutex);
2309 tlb0_flush_entry(pv->pv_va);
2310 pte->flags &= ~PTE_REFERENCED;
2313 mtx_unlock_spin(&tlbivax_mutex);
2316 PMAP_UNLOCK(pv->pv_pmap);
2321 PMAP_UNLOCK(pv->pv_pmap);
2323 vm_page_unlock_queues();
2328 * Clear the reference bit on the specified physical page.
2331 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m)
2336 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2337 ("mmu_booke_clear_reference: page %p is not managed", m));
2338 vm_page_lock_queues();
2339 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2340 PMAP_LOCK(pv->pv_pmap);
2341 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2343 if (PTE_ISREFERENCED(pte)) {
2344 mtx_lock_spin(&tlbivax_mutex);
2347 tlb0_flush_entry(pv->pv_va);
2348 pte->flags &= ~PTE_REFERENCED;
2351 mtx_unlock_spin(&tlbivax_mutex);
2354 PMAP_UNLOCK(pv->pv_pmap);
2356 vm_page_unlock_queues();
2360 * Change wiring attribute for a map/virtual-address pair.
2363 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2368 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2370 if (!PTE_ISWIRED(pte)) {
2371 pte->flags |= PTE_WIRED;
2372 pmap->pm_stats.wired_count++;
2375 if (PTE_ISWIRED(pte)) {
2376 pte->flags &= ~PTE_WIRED;
2377 pmap->pm_stats.wired_count--;
2385 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2386 * page. This count may be changed upwards or downwards in the future; it is
2387 * only necessary that true be returned for a small subset of pmaps for proper
2391 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2397 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2398 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2401 vm_page_lock_queues();
2402 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2403 if (pv->pv_pmap == pmap) {
2410 vm_page_unlock_queues();
2415 * Return the number of managed mappings to the given physical page that are
2419 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2425 if ((m->oflags & VPO_UNMANAGED) != 0)
2427 vm_page_lock_queues();
2428 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2429 PMAP_LOCK(pv->pv_pmap);
2430 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2431 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2433 PMAP_UNLOCK(pv->pv_pmap);
2435 vm_page_unlock_queues();
2440 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2446 * This currently does not work for entries that
2447 * overlap TLB1 entries.
2449 for (i = 0; i < tlb1_idx; i ++) {
2450 if (tlb1_iomapped(i, pa, size, &va) == 0)
2458 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2465 /* Raw physical memory dumps don't have a virtual address. */
2466 if (md->md_vaddr == ~0UL) {
2467 /* We always map a 256MB page at 256M. */
2468 gran = 256 * 1024 * 1024;
2469 pa = md->md_paddr + ofs;
2470 ppa = pa & ~(gran - 1);
2473 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2474 if (*sz > (gran - ofs))
2479 /* Minidumps are based on virtual memory addresses. */
2480 va = md->md_vaddr + ofs;
2481 if (va >= kernstart + kernsize) {
2482 gran = PAGE_SIZE - (va & PAGE_MASK);
2490 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2494 /* Raw physical memory dumps don't have a virtual address. */
2495 if (md->md_vaddr == ~0UL) {
2497 tlb1[tlb1_idx].mas1 = 0;
2498 tlb1[tlb1_idx].mas2 = 0;
2499 tlb1[tlb1_idx].mas3 = 0;
2500 tlb1_write_entry(tlb1_idx);
2504 /* Minidumps are based on virtual memory addresses. */
2505 /* Nothing to do... */
2509 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2511 static struct pmap_md md;
2515 if (dumpsys_minidump) {
2516 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2518 /* 1st: kernel .data and .bss. */
2520 md.md_vaddr = trunc_page((uintptr_t)_etext);
2521 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2524 switch (prev->md_index) {
2526 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2528 md.md_vaddr = data_start;
2529 md.md_size = data_end - data_start;
2532 /* 3rd: kernel VM. */
2533 va = prev->md_vaddr + prev->md_size;
2534 /* Find start of next chunk (from va). */
2535 while (va < virtual_end) {
2536 /* Don't dump the buffer cache. */
2537 if (va >= kmi.buffer_sva &&
2538 va < kmi.buffer_eva) {
2539 va = kmi.buffer_eva;
2542 pte = pte_find(mmu, kernel_pmap, va);
2543 if (pte != NULL && PTE_ISVALID(pte))
2547 if (va < virtual_end) {
2550 /* Find last page in chunk. */
2551 while (va < virtual_end) {
2552 /* Don't run into the buffer cache. */
2553 if (va == kmi.buffer_sva)
2555 pte = pte_find(mmu, kernel_pmap, va);
2556 if (pte == NULL || !PTE_ISVALID(pte))
2560 md.md_size = va - md.md_vaddr;
2568 } else { /* minidumps */
2569 mem_regions(&physmem_regions, &physmem_regions_sz,
2570 &availmem_regions, &availmem_regions_sz);
2573 /* first physical chunk. */
2574 md.md_paddr = physmem_regions[0].mr_start;
2575 md.md_size = physmem_regions[0].mr_size;
2578 } else if (md.md_index < physmem_regions_sz) {
2579 md.md_paddr = physmem_regions[md.md_index].mr_start;
2580 md.md_size = physmem_regions[md.md_index].mr_size;
2584 /* There's no next physical chunk. */
2593 * Map a set of physical memory pages into the kernel virtual address space.
2594 * Return a pointer to where it is mapped. This routine is intended to be used
2595 * for mapping device memory, NOT real memory.
2598 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2604 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa);
2608 sz = 1 << (ilog2(size) & ~1);
2610 printf("Wiring VA=%x to PA=%x (size=%x), "
2611 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2612 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO);
2622 * 'Unmap' a range mapped by mmu_booke_mapdev().
2625 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2627 vm_offset_t base, offset;
2630 * Unmap only if this is inside kernel virtual space.
2632 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2633 base = trunc_page(va);
2634 offset = va & PAGE_MASK;
2635 size = roundup(offset + size, PAGE_SIZE);
2636 kmem_free(kernel_map, base, size);
2641 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2642 * specified pmap. This eliminates the blast of soft faults on process startup
2643 * and immediately after an mmap.
2646 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2647 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2650 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2651 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2652 ("mmu_booke_object_init_pt: non-device object"));
2656 * Perform the pmap work for mincore.
2659 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2660 vm_paddr_t *locked_pa)
2667 /**************************************************************************/
2669 /**************************************************************************/
2672 * Allocate a TID. If necessary, steal one from someone else.
2673 * The new TID is flushed from the TLB before returning.
2676 tid_alloc(pmap_t pmap)
2681 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2683 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2685 thiscpu = PCPU_GET(cpuid);
2687 tid = PCPU_GET(tid_next);
2690 PCPU_SET(tid_next, tid + 1);
2692 /* If we are stealing TID then clear the relevant pmap's field */
2693 if (tidbusy[thiscpu][tid] != NULL) {
2695 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2697 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2699 /* Flush all entries from TLB0 matching this TID. */
2703 tidbusy[thiscpu][tid] = pmap;
2704 pmap->pm_tid[thiscpu] = tid;
2705 __asm __volatile("msync; isync");
2707 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2708 PCPU_GET(tid_next));
2713 /**************************************************************************/
2715 /**************************************************************************/
2718 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2728 if (mas1 & MAS1_VALID)
2733 if (mas1 & MAS1_IPROT)
2738 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2739 tid = MAS1_GETTID(mas1);
2741 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2744 size = tsize2size(tsize);
2746 debugf("%3d: (%s) [AS=%d] "
2747 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2748 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2749 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2752 /* Convert TLB0 va and way number to tlb0[] table index. */
2753 static inline unsigned int
2754 tlb0_tableidx(vm_offset_t va, unsigned int way)
2758 idx = (way * TLB0_ENTRIES_PER_WAY);
2759 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2764 * Invalidate TLB0 entry.
2767 tlb0_flush_entry(vm_offset_t va)
2770 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2772 mtx_assert(&tlbivax_mutex, MA_OWNED);
2774 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2775 __asm __volatile("isync; msync");
2776 __asm __volatile("tlbsync; msync");
2778 CTR1(KTR_PMAP, "%s: e", __func__);
2781 /* Print out contents of the MAS registers for each TLB0 entry */
2783 tlb0_print_tlbentries(void)
2785 uint32_t mas0, mas1, mas2, mas3, mas7;
2786 int entryidx, way, idx;
2788 debugf("TLB0 entries:\n");
2789 for (way = 0; way < TLB0_WAYS; way ++)
2790 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2792 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2793 mtspr(SPR_MAS0, mas0);
2794 __asm __volatile("isync");
2796 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2797 mtspr(SPR_MAS2, mas2);
2799 __asm __volatile("isync; tlbre");
2801 mas1 = mfspr(SPR_MAS1);
2802 mas2 = mfspr(SPR_MAS2);
2803 mas3 = mfspr(SPR_MAS3);
2804 mas7 = mfspr(SPR_MAS7);
2806 idx = tlb0_tableidx(mas2, way);
2807 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2811 /**************************************************************************/
2813 /**************************************************************************/
2816 * TLB1 mapping notes:
2819 * TLB1[1] Kernel text and data.
2820 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI
2821 * windows, other devices mappings.
2825 * Write given entry to TLB1 hardware.
2826 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2829 tlb1_write_entry(unsigned int idx)
2831 uint32_t mas0, mas7;
2833 //debugf("tlb1_write_entry: s\n");
2835 /* Clear high order RPN bits */
2839 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2840 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2842 mtspr(SPR_MAS0, mas0);
2843 __asm __volatile("isync");
2844 mtspr(SPR_MAS1, tlb1[idx].mas1);
2845 __asm __volatile("isync");
2846 mtspr(SPR_MAS2, tlb1[idx].mas2);
2847 __asm __volatile("isync");
2848 mtspr(SPR_MAS3, tlb1[idx].mas3);
2849 __asm __volatile("isync");
2850 mtspr(SPR_MAS7, mas7);
2851 __asm __volatile("isync; tlbwe; isync; msync");
2853 //debugf("tlb1_write_entry: e\n");
2857 * Return the largest uint value log such that 2^log <= num.
2860 ilog2(unsigned int num)
2864 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2869 * Convert TLB TSIZE value to mapped region size.
2872 tsize2size(unsigned int tsize)
2877 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2880 return ((1 << (2 * tsize)) * 1024);
2884 * Convert region size (must be power of 4) to TLB TSIZE value.
2887 size2tsize(vm_size_t size)
2890 return (ilog2(size) / 2 - 5);
2894 * Register permanent kernel mapping in TLB1.
2896 * Entries are created starting from index 0 (current free entry is
2897 * kept in tlb1_idx) and are not supposed to be invalidated.
2900 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2906 if (tlb1_idx >= TLB1_ENTRIES) {
2907 printf("tlb1_set_entry: TLB1 full!\n");
2911 /* Convert size to TSIZE */
2912 tsize = size2tsize(size);
2914 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2915 /* XXX TS is hard coded to 0 for now as we only use single address space */
2916 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2918 /* XXX LOCK tlb1[] */
2920 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2921 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2922 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags;
2924 /* Set supervisor RWX permission bits */
2925 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2927 tlb1_write_entry(tlb1_idx++);
2929 /* XXX UNLOCK tlb1[] */
2932 * XXX in general TLB1 updates should be propagated between CPUs,
2933 * since current design assumes to have the same TLB1 set-up on all
2940 * Map in contiguous RAM region into the TLB1 using maximum of
2941 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
2943 * If necessary round up last entry size and return total size
2944 * used by all allocated entries.
2947 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
2949 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
2950 vm_size_t mapped, pgsz, base, mask;
2953 /* Round up to the next 1M */
2954 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
2959 pgsz = 64*1024*1024;
2960 while (mapped < size) {
2961 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
2962 while (pgsz > (size - mapped))
2968 /* We under-map. Correct for this. */
2969 if (mapped < size) {
2970 while (pgs[idx - 1] == pgsz) {
2974 /* XXX We may increase beyond out starting point. */
2983 /* Align address to the boundary */
2985 va = (va + mask) & ~mask;
2986 pa = (pa + mask) & ~mask;
2989 for (idx = 0; idx < nents; idx++) {
2991 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
2992 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
2997 mapped = (va - base);
2998 debugf("mapped size 0x%08x (wasted space 0x%08x)\n",
2999 mapped, mapped - size);
3004 * TLB1 initialization routine, to be called after the very first
3005 * assembler level setup done in locore.S.
3008 tlb1_init(vm_offset_t ccsrbar)
3010 uint32_t mas0, mas1, mas3;
3014 if (bootinfo != NULL && bootinfo[0] != 1) {
3015 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3019 /* The first entry/entries are used to map the kernel. */
3020 for (i = 0; i < tlb1_idx; i++) {
3021 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3022 mtspr(SPR_MAS0, mas0);
3023 __asm __volatile("isync; tlbre");
3025 mas1 = mfspr(SPR_MAS1);
3026 if ((mas1 & MAS1_VALID) == 0)
3029 mas3 = mfspr(SPR_MAS3);
3031 tlb1[i].mas1 = mas1;
3032 tlb1[i].mas2 = mfspr(SPR_MAS2);
3033 tlb1[i].mas3 = mas3;
3036 kernload = mas3 & MAS3_RPN;
3038 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3039 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
3042 /* Map in CCSRBAR. */
3043 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
3045 /* Purge the remaining entries */
3046 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3047 tlb1_write_entry(i);
3049 /* Setup TLB miss defaults */
3050 set_mas4_defaults();
3054 * Setup MAS4 defaults.
3055 * These values are loaded to MAS0-2 on a TLB miss.
3058 set_mas4_defaults(void)
3062 /* Defaults: TLB0, PID0, TSIZED=4K */
3063 mas4 = MAS4_TLBSELD0;
3064 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3068 mtspr(SPR_MAS4, mas4);
3069 __asm __volatile("isync");
3073 * Print out contents of the MAS registers for each TLB1 entry
3076 tlb1_print_tlbentries(void)
3078 uint32_t mas0, mas1, mas2, mas3, mas7;
3081 debugf("TLB1 entries:\n");
3082 for (i = 0; i < TLB1_ENTRIES; i++) {
3084 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3085 mtspr(SPR_MAS0, mas0);
3087 __asm __volatile("isync; tlbre");
3089 mas1 = mfspr(SPR_MAS1);
3090 mas2 = mfspr(SPR_MAS2);
3091 mas3 = mfspr(SPR_MAS3);
3092 mas7 = mfspr(SPR_MAS7);
3094 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3099 * Print out contents of the in-ram tlb1 table.
3102 tlb1_print_entries(void)
3106 debugf("tlb1[] table entries:\n");
3107 for (i = 0; i < TLB1_ENTRIES; i++)
3108 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3112 * Return 0 if the physical IO range is encompassed by one of the
3113 * the TLB1 entries, otherwise return related error code.
3116 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3119 vm_paddr_t pa_start;
3121 unsigned int entry_tsize;
3122 vm_size_t entry_size;
3124 *va = (vm_offset_t)NULL;
3126 /* Skip invalid entries */
3127 if (!(tlb1[i].mas1 & MAS1_VALID))
3131 * The entry must be cache-inhibited, guarded, and r/w
3132 * so it can function as an i/o page
3134 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3135 if (prot != (MAS2_I | MAS2_G))
3138 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3139 if (prot != (MAS3_SR | MAS3_SW))
3142 /* The address should be within the entry range. */
3143 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3144 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3146 entry_size = tsize2size(entry_tsize);
3147 pa_start = tlb1[i].mas3 & MAS3_RPN;
3148 pa_end = pa_start + entry_size - 1;
3150 if ((pa < pa_start) || ((pa + size) > pa_end))
3153 /* Return virtual address of this mapping. */
3154 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);