2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_kern.h>
104 #include <vm/vm_pageout.h>
105 #include <vm/vm_extern.h>
106 #include <vm/vm_object.h>
107 #include <vm/vm_param.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
114 #include <machine/_inttypes.h>
115 #include <machine/cpu.h>
116 #include <machine/pcb.h>
117 #include <machine/platform.h>
119 #include <machine/tlb.h>
120 #include <machine/spr.h>
121 #include <machine/md_var.h>
122 #include <machine/mmuvar.h>
123 #include <machine/pmap.h>
124 #include <machine/pte.h>
128 #define SPARSE_MAPDEV
130 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
131 #define POW2_MAPPINGS
134 #define debugf(fmt, args...) printf(fmt, ##args)
136 #define debugf(fmt, args...)
140 #define PRI0ptrX "016lx"
142 #define PRI0ptrX "08x"
145 #define TODO panic("%s: not implemented", __func__);
147 extern unsigned char _etext[];
148 extern unsigned char _end[];
150 extern uint32_t *bootinfo;
153 vm_offset_t kernstart;
156 /* Message buffer and tables. */
157 static vm_offset_t data_start;
158 static vm_size_t data_end;
160 /* Phys/avail memory regions. */
161 static struct mem_region *availmem_regions;
162 static int availmem_regions_sz;
163 static struct mem_region *physmem_regions;
164 static int physmem_regions_sz;
166 #ifndef __powerpc64__
167 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
168 static vm_offset_t zero_page_va;
169 static struct mtx zero_page_mutex;
171 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
172 static vm_offset_t copy_page_src_va;
173 static vm_offset_t copy_page_dst_va;
174 static struct mtx copy_page_mutex;
177 static struct mtx tlbivax_mutex;
179 /**************************************************************************/
181 /**************************************************************************/
183 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
184 vm_prot_t, u_int flags, int8_t psind);
186 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
187 static uma_zone_t ptbl_root_zone;
190 * If user pmap is processed with mmu_booke_remove and the resident count
191 * drops to 0, there are no more pages to remove, so we need not continue.
193 #define PMAP_REMOVE_DONE(pmap) \
194 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
196 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
197 extern int elf32_nxstack;
200 /**************************************************************************/
201 /* TLB and TID handling */
202 /**************************************************************************/
204 /* Translation ID busy table */
205 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
208 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
209 * core revisions and should be read from h/w registers during early config.
211 uint32_t tlb0_entries;
213 uint32_t tlb0_entries_per_way;
214 uint32_t tlb1_entries;
216 #define TLB0_ENTRIES (tlb0_entries)
217 #define TLB0_WAYS (tlb0_ways)
218 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
220 #define TLB1_ENTRIES (tlb1_entries)
222 static tlbtid_t tid_alloc(struct pmap *);
226 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
228 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
232 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
233 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
234 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
235 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
237 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
239 static vm_size_t tsize2size(unsigned int);
240 static unsigned int size2tsize(vm_size_t);
241 static unsigned long ilog2(unsigned long);
243 static void set_mas4_defaults(void);
245 static inline void tlb0_flush_entry(vm_offset_t);
246 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
248 /**************************************************************************/
249 /* Page table management */
250 /**************************************************************************/
252 static struct rwlock_padalign pvh_global_lock;
254 /* Data for the pv entry allocation mechanism */
255 static uma_zone_t pvzone;
256 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
258 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
260 #ifndef PMAP_SHPGPERPROC
261 #define PMAP_SHPGPERPROC 200
264 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
265 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
266 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
267 static pte_t *pte_find(pmap_t, vm_offset_t);
268 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
270 static pv_entry_t pv_alloc(void);
271 static void pv_free(pv_entry_t);
272 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
273 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
275 static void booke_pmap_init_qpages(void);
277 static inline void tlb_miss_lock(void);
278 static inline void tlb_miss_unlock(void);
281 extern tlb_entry_t __boot_tlb1[];
282 void pmap_bootstrap_ap(volatile uint32_t *);
286 * Kernel MMU interface
288 static void mmu_booke_clear_modify(vm_page_t);
289 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
290 vm_size_t, vm_offset_t);
291 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
292 static void mmu_booke_copy_pages(vm_page_t *,
293 vm_offset_t, vm_page_t *, vm_offset_t, int);
294 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
295 vm_prot_t, u_int flags, int8_t psind);
296 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
297 vm_page_t, vm_prot_t);
298 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
300 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
301 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
303 static void mmu_booke_init(void);
304 static boolean_t mmu_booke_is_modified(vm_page_t);
305 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
306 static boolean_t mmu_booke_is_referenced(vm_page_t);
307 static int mmu_booke_ts_referenced(vm_page_t);
308 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
310 static int mmu_booke_mincore(pmap_t, vm_offset_t,
312 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
313 vm_object_t, vm_pindex_t, vm_size_t);
314 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t);
315 static void mmu_booke_page_init(vm_page_t);
316 static int mmu_booke_page_wired_mappings(vm_page_t);
317 static int mmu_booke_pinit(pmap_t);
318 static void mmu_booke_pinit0(pmap_t);
319 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
321 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int);
322 static void mmu_booke_qremove(vm_offset_t, int);
323 static void mmu_booke_release(pmap_t);
324 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
325 static void mmu_booke_remove_all(vm_page_t);
326 static void mmu_booke_remove_write(vm_page_t);
327 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
328 static void mmu_booke_zero_page(vm_page_t);
329 static void mmu_booke_zero_page_area(vm_page_t, int, int);
330 static void mmu_booke_activate(struct thread *);
331 static void mmu_booke_deactivate(struct thread *);
332 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
333 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
334 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
335 static void mmu_booke_unmapdev(vm_offset_t, vm_size_t);
336 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
337 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
338 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
339 static void mmu_booke_kremove(vm_offset_t);
340 static boolean_t mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
341 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
343 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
345 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
347 static void mmu_booke_scan_init(void);
348 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m);
349 static void mmu_booke_quick_remove_page(vm_offset_t addr);
350 static int mmu_booke_change_attr(vm_offset_t addr,
351 vm_size_t sz, vm_memattr_t mode);
352 static int mmu_booke_map_user_ptr(pmap_t pm,
353 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
354 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
355 int *is_user, vm_offset_t *decoded_addr);
356 static void mmu_booke_page_array_startup(long);
357 static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
360 static struct pmap_funcs mmu_booke_methods = {
361 /* pmap dispatcher interface */
362 .clear_modify = mmu_booke_clear_modify,
363 .copy = mmu_booke_copy,
364 .copy_page = mmu_booke_copy_page,
365 .copy_pages = mmu_booke_copy_pages,
366 .enter = mmu_booke_enter,
367 .enter_object = mmu_booke_enter_object,
368 .enter_quick = mmu_booke_enter_quick,
369 .extract = mmu_booke_extract,
370 .extract_and_hold = mmu_booke_extract_and_hold,
371 .init = mmu_booke_init,
372 .is_modified = mmu_booke_is_modified,
373 .is_prefaultable = mmu_booke_is_prefaultable,
374 .is_referenced = mmu_booke_is_referenced,
375 .ts_referenced = mmu_booke_ts_referenced,
376 .map = mmu_booke_map,
377 .mincore = mmu_booke_mincore,
378 .object_init_pt = mmu_booke_object_init_pt,
379 .page_exists_quick = mmu_booke_page_exists_quick,
380 .page_init = mmu_booke_page_init,
381 .page_wired_mappings = mmu_booke_page_wired_mappings,
382 .pinit = mmu_booke_pinit,
383 .pinit0 = mmu_booke_pinit0,
384 .protect = mmu_booke_protect,
385 .qenter = mmu_booke_qenter,
386 .qremove = mmu_booke_qremove,
387 .release = mmu_booke_release,
388 .remove = mmu_booke_remove,
389 .remove_all = mmu_booke_remove_all,
390 .remove_write = mmu_booke_remove_write,
391 .sync_icache = mmu_booke_sync_icache,
392 .unwire = mmu_booke_unwire,
393 .zero_page = mmu_booke_zero_page,
394 .zero_page_area = mmu_booke_zero_page_area,
395 .activate = mmu_booke_activate,
396 .deactivate = mmu_booke_deactivate,
397 .quick_enter_page = mmu_booke_quick_enter_page,
398 .quick_remove_page = mmu_booke_quick_remove_page,
399 .page_array_startup = mmu_booke_page_array_startup,
400 .page_is_mapped = mmu_booke_page_is_mapped,
402 /* Internal interfaces */
403 .bootstrap = mmu_booke_bootstrap,
404 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
405 .mapdev = mmu_booke_mapdev,
406 .mapdev_attr = mmu_booke_mapdev_attr,
407 .kenter = mmu_booke_kenter,
408 .kenter_attr = mmu_booke_kenter_attr,
409 .kextract = mmu_booke_kextract,
410 .kremove = mmu_booke_kremove,
411 .unmapdev = mmu_booke_unmapdev,
412 .change_attr = mmu_booke_change_attr,
413 .map_user_ptr = mmu_booke_map_user_ptr,
414 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
416 /* dumpsys() support */
417 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
418 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
419 .dumpsys_pa_init = mmu_booke_scan_init,
422 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
430 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
432 static __inline uint32_t
433 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
438 if (ma != VM_MEMATTR_DEFAULT) {
440 case VM_MEMATTR_UNCACHEABLE:
441 return (MAS2_I | MAS2_G);
442 case VM_MEMATTR_WRITE_COMBINING:
443 case VM_MEMATTR_WRITE_BACK:
444 case VM_MEMATTR_PREFETCHABLE:
446 case VM_MEMATTR_WRITE_THROUGH:
447 return (MAS2_W | MAS2_M);
448 case VM_MEMATTR_CACHEABLE:
454 * Assume the page is cache inhibited and access is guarded unless
455 * it's in our available memory array.
457 attrib = _TLB_ENTRY_IO;
458 for (i = 0; i < physmem_regions_sz; i++) {
459 if ((pa >= physmem_regions[i].mr_start) &&
460 (pa < (physmem_regions[i].mr_start +
461 physmem_regions[i].mr_size))) {
462 attrib = _TLB_ENTRY_MEM;
479 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
482 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
483 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
485 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
486 ("tlb_miss_lock: tried to lock self"));
488 tlb_lock(pc->pc_booke.tlb_lock);
490 CTR1(KTR_PMAP, "%s: locked", __func__);
497 tlb_miss_unlock(void)
505 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
507 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
508 __func__, pc->pc_cpuid);
510 tlb_unlock(pc->pc_booke.tlb_lock);
512 CTR1(KTR_PMAP, "%s: unlocked", __func__);
518 /* Return number of entries in TLB0. */
520 tlb0_get_tlbconf(void)
524 tlb0_cfg = mfspr(SPR_TLB0CFG);
525 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
526 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
527 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
530 /* Return number of entries in TLB1. */
532 tlb1_get_tlbconf(void)
536 tlb1_cfg = mfspr(SPR_TLB1CFG);
537 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
540 /**************************************************************************/
541 /* Page table related */
542 /**************************************************************************/
544 /* Allocate pv_entry structure. */
551 if (pv_entry_count > pv_entry_high_water)
552 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
553 pv = uma_zalloc(pvzone, M_NOWAIT);
558 /* Free pv_entry structure. */
560 pv_free(pv_entry_t pve)
564 uma_zfree(pvzone, pve);
568 /* Allocate and initialize pv_entry structure. */
570 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
574 //int su = (pmap == kernel_pmap);
575 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
576 // (u_int32_t)pmap, va, (u_int32_t)m);
580 panic("pv_insert: no pv entries!");
586 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
587 rw_assert(&pvh_global_lock, RA_WLOCKED);
589 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
591 //debugf("pv_insert: e\n");
594 /* Destroy pv entry. */
596 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
600 //int su = (pmap == kernel_pmap);
601 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
603 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
604 rw_assert(&pvh_global_lock, RA_WLOCKED);
607 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
608 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
609 /* remove from pv_list */
610 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
611 if (TAILQ_EMPTY(&m->md.pv_list))
612 vm_page_aflag_clear(m, PGA_WRITEABLE);
614 /* free pv entry struct */
620 //debugf("pv_remove: e\n");
623 /**************************************************************************/
625 /**************************************************************************/
628 * This is called during booke_init, before the system is really initialized.
631 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
633 vm_paddr_t phys_kernelend;
634 struct mem_region *mp, *mp1;
637 vm_paddr_t physsz, hwphyssz;
638 u_int phys_avail_count;
639 vm_size_t kstack0_sz;
640 vm_paddr_t kstack0_phys;
644 debugf("mmu_booke_bootstrap: entered\n");
646 /* Set interesting system properties */
652 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
656 /* Initialize invalidation mutex */
657 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
659 /* Read TLB0 size and associativity. */
663 * Align kernel start and end address (kernel image).
664 * Note that kernel end does not necessarily relate to kernsize.
665 * kernsize is the size of the kernel that is actually mapped.
667 data_start = round_page(kernelend);
668 data_end = data_start;
670 /* Allocate the dynamic per-cpu area. */
671 dpcpu = (void *)data_end;
672 data_end += DPCPU_SIZE;
674 /* Allocate space for the message buffer. */
675 msgbufp = (struct msgbuf *)data_end;
676 data_end += msgbufsize;
677 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
678 (uintptr_t)msgbufp, data_end);
680 data_end = round_page(data_end);
681 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
683 /* Retrieve phys/avail mem regions */
684 mem_regions(&physmem_regions, &physmem_regions_sz,
685 &availmem_regions, &availmem_regions_sz);
687 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
688 panic("mmu_booke_bootstrap: phys_avail too small");
690 data_end = round_page(data_end);
691 vm_page_array = (vm_page_t)data_end;
693 * Get a rough idea (upper bound) on the size of the page array. The
694 * vm_page_array will not handle any more pages than we have in the
695 * avail_regions array, and most likely much less.
698 for (mp = availmem_regions; mp->mr_size; mp++) {
701 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
702 data_end += round_page(sz * sizeof(struct vm_page));
704 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
705 data_end = roundup2(data_end, 1 << 20);
707 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
708 debugf(" kernstart: %#zx\n", kernstart);
709 debugf(" kernsize: %#zx\n", kernsize);
711 if (data_end - kernstart > kernsize) {
712 kernsize += tlb1_mapin_region(kernstart + kernsize,
713 kernload + kernsize, (data_end - kernstart) - kernsize,
716 data_end = kernstart + kernsize;
717 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
720 * Clear the structures - note we can only do it safely after the
721 * possible additional TLB1 translations are in place (above) so that
722 * all range up to the currently calculated 'data_end' is covered.
724 bzero((void *)data_start, data_end - data_start);
725 dpcpu_init(dpcpu, 0);
727 /*******************************************************/
728 /* Set the start and end of kva. */
729 /*******************************************************/
730 virtual_avail = round_page(data_end);
731 virtual_end = VM_MAX_KERNEL_ADDRESS;
733 #ifndef __powerpc64__
734 /* Allocate KVA space for page zero/copy operations. */
735 zero_page_va = virtual_avail;
736 virtual_avail += PAGE_SIZE;
737 copy_page_src_va = virtual_avail;
738 virtual_avail += PAGE_SIZE;
739 copy_page_dst_va = virtual_avail;
740 virtual_avail += PAGE_SIZE;
741 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
742 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
743 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
745 /* Initialize page zero/copy mutexes. */
746 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
747 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
749 /* Allocate KVA space for ptbl bufs. */
750 ptbl_buf_pool_vabase = virtual_avail;
751 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
752 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
753 ptbl_buf_pool_vabase, virtual_avail);
756 /* Calculate corresponding physical addresses for the kernel region. */
757 phys_kernelend = kernload + kernsize;
758 debugf("kernel image and allocated data:\n");
759 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
760 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
761 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
764 * Remove kernel physical address range from avail regions list. Page
765 * align all regions. Non-page aligned memory isn't very interesting
766 * to us. Also, sort the entries for ascending addresses.
770 cnt = availmem_regions_sz;
771 debugf("processing avail regions:\n");
772 for (mp = availmem_regions; mp->mr_size; mp++) {
774 e = mp->mr_start + mp->mr_size;
775 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
776 /* Check whether this region holds all of the kernel. */
777 if (s < kernload && e > phys_kernelend) {
778 availmem_regions[cnt].mr_start = phys_kernelend;
779 availmem_regions[cnt++].mr_size = e - phys_kernelend;
782 /* Look whether this regions starts within the kernel. */
783 if (s >= kernload && s < phys_kernelend) {
784 if (e <= phys_kernelend)
788 /* Now look whether this region ends within the kernel. */
789 if (e > kernload && e <= phys_kernelend) {
794 /* Now page align the start and size of the region. */
800 debugf("%09jx-%09jx = %jx\n",
801 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
803 /* Check whether some memory is left here. */
807 (cnt - (mp - availmem_regions)) * sizeof(*mp));
813 /* Do an insertion sort. */
814 for (mp1 = availmem_regions; mp1 < mp; mp1++)
815 if (s < mp1->mr_start)
818 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
826 availmem_regions_sz = cnt;
828 /*******************************************************/
829 /* Steal physical memory for kernel stack from the end */
830 /* of the first avail region */
831 /*******************************************************/
832 kstack0_sz = kstack_pages * PAGE_SIZE;
833 kstack0_phys = availmem_regions[0].mr_start +
834 availmem_regions[0].mr_size;
835 kstack0_phys -= kstack0_sz;
836 availmem_regions[0].mr_size -= kstack0_sz;
838 /*******************************************************/
839 /* Fill in phys_avail table, based on availmem_regions */
840 /*******************************************************/
841 phys_avail_count = 0;
844 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
846 debugf("fill in phys_avail:\n");
847 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
849 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
850 (uintmax_t)availmem_regions[i].mr_start,
851 (uintmax_t)availmem_regions[i].mr_start +
852 availmem_regions[i].mr_size,
853 (uintmax_t)availmem_regions[i].mr_size);
856 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
857 debugf(" hw.physmem adjust\n");
858 if (physsz < hwphyssz) {
859 phys_avail[j] = availmem_regions[i].mr_start;
861 availmem_regions[i].mr_start +
865 dump_avail[j] = phys_avail[j];
866 dump_avail[j + 1] = phys_avail[j + 1];
871 phys_avail[j] = availmem_regions[i].mr_start;
872 phys_avail[j + 1] = availmem_regions[i].mr_start +
873 availmem_regions[i].mr_size;
875 physsz += availmem_regions[i].mr_size;
876 dump_avail[j] = phys_avail[j];
877 dump_avail[j + 1] = phys_avail[j + 1];
879 physmem = btoc(physsz);
881 /* Calculate the last available physical address. */
882 for (i = 0; phys_avail[i + 2] != 0; i += 2)
884 Maxmem = powerpc_btop(phys_avail[i + 1]);
886 debugf("Maxmem = 0x%08lx\n", Maxmem);
887 debugf("phys_avail_count = %d\n", phys_avail_count);
888 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
889 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
893 * Map the physical memory contiguously in TLB1.
894 * Round so it fits into a single mapping.
896 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
897 phys_avail[i + 1], _TLB_ENTRY_MEM);
900 /*******************************************************/
901 /* Initialize (statically allocated) kernel pmap. */
902 /*******************************************************/
903 PMAP_LOCK_INIT(kernel_pmap);
905 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
906 kernel_pte_alloc(virtual_avail, kernstart);
907 for (i = 0; i < MAXCPU; i++) {
908 kernel_pmap->pm_tid[i] = TID_KERNEL;
910 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
911 tidbusy[i][TID_KERNEL] = kernel_pmap;
914 /* Mark kernel_pmap active on all CPUs */
915 CPU_FILL(&kernel_pmap->pm_active);
918 * Initialize the global pv list lock.
920 rw_init(&pvh_global_lock, "pmap pv global");
922 /*******************************************************/
924 /*******************************************************/
926 /* Enter kstack0 into kernel map, provide guard page */
927 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
928 thread0.td_kstack = kstack0;
929 thread0.td_kstack_pages = kstack_pages;
931 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
932 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
933 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
934 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
935 kstack0, kstack0 + kstack0_sz);
937 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
938 for (i = 0; i < kstack_pages; i++) {
939 mmu_booke_kenter(kstack0, kstack0_phys);
940 kstack0 += PAGE_SIZE;
941 kstack0_phys += PAGE_SIZE;
944 pmap_bootstrapped = 1;
946 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
947 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
949 debugf("mmu_booke_bootstrap: exit\n");
959 /* Prepare TLB1 image for AP processors */
961 for (i = 0; i < TLB1_ENTRIES; i++) {
962 tlb1_read_entry(&tmp, i);
964 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
965 memcpy(e++, &tmp, sizeof(tmp));
970 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
975 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
976 * have the snapshot of its contents in the s/w __boot_tlb1[] table
977 * created by tlb1_ap_prep(), so use these values directly to
978 * (re)program AP's TLB1 hardware.
980 * Start at index 1 because index 0 has the kernel map.
982 for (i = 1; i < TLB1_ENTRIES; i++) {
983 if (__boot_tlb1[i].mas1 & MAS1_VALID)
984 tlb1_write_entry(&__boot_tlb1[i], i);
992 booke_pmap_init_qpages(void)
999 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1000 if (pc->pc_qmap_addr == 0)
1001 panic("pmap_init_qpages: unable to allocate KVA");
1005 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1008 * Get the physical page address for the given pmap/virtual address.
1011 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1016 pa = pte_vatopa(pmap, va);
1023 * Extract the physical page address associated with the given
1024 * kernel virtual address.
1027 mmu_booke_kextract(vm_offset_t va)
1033 #ifdef __powerpc64__
1034 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1035 return (DMAP_TO_PHYS(va));
1038 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1039 p = pte_vatopa(kernel_pmap, va);
1042 /* Check TLB1 mappings */
1043 for (i = 0; i < TLB1_ENTRIES; i++) {
1044 tlb1_read_entry(&e, i);
1045 if (!(e.mas1 & MAS1_VALID))
1047 if (va >= e.virt && va < e.virt + e.size)
1048 return (e.phys + (va - e.virt));
1056 * Initialize the pmap module.
1057 * Called by vm_init, to initialize any structures that the pmap
1058 * system needs to map virtual memory.
1063 int shpgperproc = PMAP_SHPGPERPROC;
1066 * Initialize the address space (zone) for the pv entries. Set a
1067 * high water mark so that the system can recover from excessive
1068 * numbers of pv entries.
1070 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1071 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1073 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1074 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1076 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1077 pv_entry_high_water = 9 * (pv_entry_max / 10);
1079 uma_zone_reserve_kva(pvzone, pv_entry_max);
1081 /* Pre-fill pvzone with initial number of pv entries. */
1082 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1084 /* Create a UMA zone for page table roots. */
1085 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1086 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1088 /* Initialize ptbl allocation. */
1093 * Map a list of wired pages into kernel virtual address space. This is
1094 * intended for temporary mappings which do not need page modification or
1095 * references recorded. Existing mappings in the region are overwritten.
1098 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count)
1103 while (count-- > 0) {
1104 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1111 * Remove page mappings from kernel virtual address space. Intended for
1112 * temporary mappings entered by mmu_booke_qenter.
1115 mmu_booke_qremove(vm_offset_t sva, int count)
1120 while (count-- > 0) {
1121 mmu_booke_kremove(va);
1127 * Map a wired page into kernel virtual address space.
1130 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1133 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1137 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1142 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1143 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1145 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1146 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1147 flags |= PTE_PS_4KB;
1149 pte = pte_find(kernel_pmap, va);
1150 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1152 mtx_lock_spin(&tlbivax_mutex);
1155 if (PTE_ISVALID(pte)) {
1157 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1159 /* Flush entry from TLB0 */
1160 tlb0_flush_entry(va);
1163 *pte = PTE_RPN_FROM_PA(pa) | flags;
1165 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1166 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1167 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1169 /* Flush the real memory from the instruction cache. */
1170 if ((flags & (PTE_I | PTE_G)) == 0)
1171 __syncicache((void *)va, PAGE_SIZE);
1174 mtx_unlock_spin(&tlbivax_mutex);
1178 * Remove a page from kernel page table.
1181 mmu_booke_kremove(vm_offset_t va)
1185 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1187 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1188 (va <= VM_MAX_KERNEL_ADDRESS)),
1189 ("mmu_booke_kremove: invalid va"));
1191 pte = pte_find(kernel_pmap, va);
1193 if (!PTE_ISVALID(pte)) {
1195 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1200 mtx_lock_spin(&tlbivax_mutex);
1203 /* Invalidate entry in TLB0, update PTE. */
1204 tlb0_flush_entry(va);
1208 mtx_unlock_spin(&tlbivax_mutex);
1212 * Provide a kernel pointer corresponding to a given userland pointer.
1213 * The returned pointer is valid until the next time this function is
1214 * called in this thread. This is used internally in copyin/copyout.
1217 mmu_booke_map_user_ptr(pmap_t pm, volatile const void *uaddr,
1218 void **kaddr, size_t ulen, size_t *klen)
1221 if (trunc_page((uintptr_t)uaddr + ulen) > VM_MAXUSER_ADDRESS)
1224 *kaddr = (void *)(uintptr_t)uaddr;
1232 * Figure out where a given kernel pointer (usually in a fault) points
1233 * to from the VM's perspective, potentially remapping into userland's
1237 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1238 vm_offset_t *decoded_addr)
1241 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1246 *decoded_addr = addr;
1251 mmu_booke_page_is_mapped(vm_page_t m)
1254 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1258 * Initialize pmap associated with process 0.
1261 mmu_booke_pinit0(pmap_t pmap)
1264 PMAP_LOCK_INIT(pmap);
1265 mmu_booke_pinit(pmap);
1266 PCPU_SET(curpmap, pmap);
1270 * Insert the given physical page at the specified virtual address in the
1271 * target physical map with the protection requested. If specified the page
1272 * will be wired down.
1275 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1276 vm_prot_t prot, u_int flags, int8_t psind)
1280 rw_wlock(&pvh_global_lock);
1282 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1284 rw_wunlock(&pvh_global_lock);
1289 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1290 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1295 int error, su, sync;
1297 pa = VM_PAGE_TO_PHYS(m);
1298 su = (pmap == kernel_pmap);
1301 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1302 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1303 // (u_int32_t)pmap, su, pmap->pm_tid,
1304 // (u_int32_t)m, va, pa, prot, flags);
1307 KASSERT(((va >= virtual_avail) &&
1308 (va <= VM_MAX_KERNEL_ADDRESS)),
1309 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1311 KASSERT((va <= VM_MAXUSER_ADDRESS),
1312 ("mmu_booke_enter_locked: user pmap, non user va"));
1314 if ((m->oflags & VPO_UNMANAGED) == 0) {
1315 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1316 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1318 VM_OBJECT_ASSERT_LOCKED(m->object);
1321 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1324 * If there is an existing mapping, and the physical address has not
1325 * changed, must be protection or wiring change.
1327 if (((pte = pte_find(pmap, va)) != NULL) &&
1328 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1331 * Before actually updating pte->flags we calculate and
1332 * prepare its new value in a helper var.
1335 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1337 /* Wiring change, just update stats. */
1338 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1339 if (!PTE_ISWIRED(pte)) {
1341 pmap->pm_stats.wired_count++;
1344 if (PTE_ISWIRED(pte)) {
1345 flags &= ~PTE_WIRED;
1346 pmap->pm_stats.wired_count--;
1350 if (prot & VM_PROT_WRITE) {
1351 /* Add write permissions. */
1356 if ((flags & PTE_MANAGED) != 0)
1357 vm_page_aflag_set(m, PGA_WRITEABLE);
1359 /* Handle modified pages, sense modify status. */
1362 * The PTE_MODIFIED flag could be set by underlying
1363 * TLB misses since we last read it (above), possibly
1364 * other CPUs could update it so we check in the PTE
1365 * directly rather than rely on that saved local flags
1368 if (PTE_ISMODIFIED(pte))
1372 if (prot & VM_PROT_EXECUTE) {
1378 * Check existing flags for execute permissions: if we
1379 * are turning execute permissions on, icache should
1382 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1386 flags &= ~PTE_REFERENCED;
1389 * The new flags value is all calculated -- only now actually
1392 mtx_lock_spin(&tlbivax_mutex);
1395 tlb0_flush_entry(va);
1396 *pte &= ~PTE_FLAGS_MASK;
1400 mtx_unlock_spin(&tlbivax_mutex);
1404 * If there is an existing mapping, but it's for a different
1405 * physical address, pte_enter() will delete the old mapping.
1407 //if ((pte != NULL) && PTE_ISVALID(pte))
1408 // debugf("mmu_booke_enter_locked: replace\n");
1410 // debugf("mmu_booke_enter_locked: new\n");
1412 /* Now set up the flags and install the new mapping. */
1413 flags = (PTE_SR | PTE_VALID);
1419 if (prot & VM_PROT_WRITE) {
1424 if ((m->oflags & VPO_UNMANAGED) == 0)
1425 vm_page_aflag_set(m, PGA_WRITEABLE);
1428 if (prot & VM_PROT_EXECUTE) {
1434 /* If its wired update stats. */
1435 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1438 error = pte_enter(pmap, m, va, flags,
1439 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1441 return (KERN_RESOURCE_SHORTAGE);
1443 if ((flags & PMAP_ENTER_WIRED) != 0)
1444 pmap->pm_stats.wired_count++;
1446 /* Flush the real memory from the instruction cache. */
1447 if (prot & VM_PROT_EXECUTE)
1451 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1452 __syncicache((void *)va, PAGE_SIZE);
1456 return (KERN_SUCCESS);
1460 * Maps a sequence of resident pages belonging to the same object.
1461 * The sequence begins with the given page m_start. This page is
1462 * mapped at the given virtual address start. Each subsequent page is
1463 * mapped at a virtual address that is offset from start by the same
1464 * amount as the page is offset from m_start within the object. The
1465 * last page in the sequence is the page with the largest offset from
1466 * m_start that can be mapped at a virtual address less than the given
1467 * virtual address end. Not every virtual page between start and end
1468 * is mapped; only those for which a resident page exists with the
1469 * corresponding offset from m_start are mapped.
1472 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1473 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1476 vm_pindex_t diff, psize;
1478 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1480 psize = atop(end - start);
1482 rw_wlock(&pvh_global_lock);
1484 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1485 mmu_booke_enter_locked(pmap, start + ptoa(diff), m,
1486 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1487 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1488 m = TAILQ_NEXT(m, listq);
1491 rw_wunlock(&pvh_global_lock);
1495 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1499 rw_wlock(&pvh_global_lock);
1501 mmu_booke_enter_locked(pmap, va, m,
1502 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1503 PMAP_ENTER_QUICK_LOCKED, 0);
1505 rw_wunlock(&pvh_global_lock);
1509 * Remove the given range of addresses from the specified map.
1511 * It is assumed that the start and end are properly rounded to the page size.
1514 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1519 int su = (pmap == kernel_pmap);
1521 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1522 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1525 KASSERT(((va >= virtual_avail) &&
1526 (va <= VM_MAX_KERNEL_ADDRESS)),
1527 ("mmu_booke_remove: kernel pmap, non kernel va"));
1529 KASSERT((va <= VM_MAXUSER_ADDRESS),
1530 ("mmu_booke_remove: user pmap, non user va"));
1533 if (PMAP_REMOVE_DONE(pmap)) {
1534 //debugf("mmu_booke_remove: e (empty)\n");
1538 hold_flag = PTBL_HOLD_FLAG(pmap);
1539 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1541 rw_wlock(&pvh_global_lock);
1543 for (; va < endva; va += PAGE_SIZE) {
1544 pte = pte_find_next(pmap, &va);
1545 if ((pte == NULL) || !PTE_ISVALID(pte))
1549 pte_remove(pmap, va, hold_flag);
1552 rw_wunlock(&pvh_global_lock);
1554 //debugf("mmu_booke_remove: e\n");
1558 * Remove physical page from all pmaps in which it resides.
1561 mmu_booke_remove_all(vm_page_t m)
1566 rw_wlock(&pvh_global_lock);
1567 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1568 PMAP_LOCK(pv->pv_pmap);
1569 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1570 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1571 PMAP_UNLOCK(pv->pv_pmap);
1573 vm_page_aflag_clear(m, PGA_WRITEABLE);
1574 rw_wunlock(&pvh_global_lock);
1578 * Map a range of physical addresses into kernel virtual address space.
1581 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1582 vm_paddr_t pa_end, int prot)
1584 vm_offset_t sva = *virt;
1585 vm_offset_t va = sva;
1587 #ifdef __powerpc64__
1588 /* XXX: Handle memory not starting at 0x0. */
1589 if (pa_end < ctob(Maxmem))
1590 return (PHYS_TO_DMAP(pa_start));
1593 while (pa_start < pa_end) {
1594 mmu_booke_kenter(va, pa_start);
1596 pa_start += PAGE_SIZE;
1604 * The pmap must be activated before it's address space can be accessed in any
1608 mmu_booke_activate(struct thread *td)
1613 pmap = &td->td_proc->p_vmspace->vm_pmap;
1615 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1616 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1618 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1622 cpuid = PCPU_GET(cpuid);
1623 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1624 PCPU_SET(curpmap, pmap);
1626 if (pmap->pm_tid[cpuid] == TID_NONE)
1629 /* Load PID0 register with pmap tid value. */
1630 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1631 __asm __volatile("isync");
1633 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1637 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1638 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1642 * Deactivate the specified process's address space.
1645 mmu_booke_deactivate(struct thread *td)
1649 pmap = &td->td_proc->p_vmspace->vm_pmap;
1651 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1652 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1654 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1656 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1657 PCPU_SET(curpmap, NULL);
1661 * Copy the range specified by src_addr/len
1662 * from the source map to the range dst_addr/len
1663 * in the destination map.
1665 * This routine is only advisory and need not do anything.
1668 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1669 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1675 * Set the physical protection on the specified range of this map as requested.
1678 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1685 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1686 mmu_booke_remove(pmap, sva, eva);
1690 if (prot & VM_PROT_WRITE)
1694 for (va = sva; va < eva; va += PAGE_SIZE) {
1695 if ((pte = pte_find(pmap, va)) != NULL) {
1696 if (PTE_ISVALID(pte)) {
1697 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1699 mtx_lock_spin(&tlbivax_mutex);
1702 /* Handle modified pages. */
1703 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1706 tlb0_flush_entry(va);
1707 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1710 mtx_unlock_spin(&tlbivax_mutex);
1718 * Clear the write and modified bits in each of the given page's mappings.
1721 mmu_booke_remove_write(vm_page_t m)
1726 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1727 ("mmu_booke_remove_write: page %p is not managed", m));
1728 vm_page_assert_busied(m);
1730 if (!pmap_page_is_write_mapped(m))
1732 rw_wlock(&pvh_global_lock);
1733 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1734 PMAP_LOCK(pv->pv_pmap);
1735 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1736 if (PTE_ISVALID(pte)) {
1737 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1739 mtx_lock_spin(&tlbivax_mutex);
1742 /* Handle modified pages. */
1743 if (PTE_ISMODIFIED(pte))
1746 /* Flush mapping from TLB0. */
1747 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1750 mtx_unlock_spin(&tlbivax_mutex);
1753 PMAP_UNLOCK(pv->pv_pmap);
1755 vm_page_aflag_clear(m, PGA_WRITEABLE);
1756 rw_wunlock(&pvh_global_lock);
1760 * Atomically extract and hold the physical page with the given
1761 * pmap and virtual address pair if that mapping permits the given
1765 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1774 pte = pte_find(pmap, va);
1775 if ((pte != NULL) && PTE_ISVALID(pte)) {
1776 if (pmap == kernel_pmap)
1781 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1782 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1783 if (!vm_page_wire_mapped(m))
1792 * Initialize a vm_page's machine-dependent fields.
1795 mmu_booke_page_init(vm_page_t m)
1798 m->md.pv_tracked = 0;
1799 TAILQ_INIT(&m->md.pv_list);
1803 * Return whether or not the specified physical page was modified
1804 * in any of physical maps.
1807 mmu_booke_is_modified(vm_page_t m)
1813 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1814 ("mmu_booke_is_modified: page %p is not managed", m));
1818 * If the page is not busied then this check is racy.
1820 if (!pmap_page_is_write_mapped(m))
1823 rw_wlock(&pvh_global_lock);
1824 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1825 PMAP_LOCK(pv->pv_pmap);
1826 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1828 if (PTE_ISMODIFIED(pte))
1831 PMAP_UNLOCK(pv->pv_pmap);
1835 rw_wunlock(&pvh_global_lock);
1840 * Return whether or not the specified virtual address is eligible
1844 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1851 * Return whether or not the specified physical page was referenced
1852 * in any physical maps.
1855 mmu_booke_is_referenced(vm_page_t m)
1861 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1862 ("mmu_booke_is_referenced: page %p is not managed", m));
1864 rw_wlock(&pvh_global_lock);
1865 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1866 PMAP_LOCK(pv->pv_pmap);
1867 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1869 if (PTE_ISREFERENCED(pte))
1872 PMAP_UNLOCK(pv->pv_pmap);
1876 rw_wunlock(&pvh_global_lock);
1881 * Clear the modify bits on the specified physical page.
1884 mmu_booke_clear_modify(vm_page_t m)
1889 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1890 ("mmu_booke_clear_modify: page %p is not managed", m));
1891 vm_page_assert_busied(m);
1893 if (!pmap_page_is_write_mapped(m))
1896 rw_wlock(&pvh_global_lock);
1897 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1898 PMAP_LOCK(pv->pv_pmap);
1899 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1901 mtx_lock_spin(&tlbivax_mutex);
1904 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1905 tlb0_flush_entry(pv->pv_va);
1906 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1911 mtx_unlock_spin(&tlbivax_mutex);
1913 PMAP_UNLOCK(pv->pv_pmap);
1915 rw_wunlock(&pvh_global_lock);
1919 * Return a count of reference bits for a page, clearing those bits.
1920 * It is not necessary for every reference bit to be cleared, but it
1921 * is necessary that 0 only be returned when there are truly no
1922 * reference bits set.
1924 * As an optimization, update the page's dirty field if a modified bit is
1925 * found while counting reference bits. This opportunistic update can be
1926 * performed at low cost and can eliminate the need for some future calls
1927 * to pmap_is_modified(). However, since this function stops after
1928 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1929 * dirty pages. Those dirty pages will only be detected by a future call
1930 * to pmap_is_modified().
1933 mmu_booke_ts_referenced(vm_page_t m)
1939 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1940 ("mmu_booke_ts_referenced: page %p is not managed", m));
1942 rw_wlock(&pvh_global_lock);
1943 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1944 PMAP_LOCK(pv->pv_pmap);
1945 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1947 if (PTE_ISMODIFIED(pte))
1949 if (PTE_ISREFERENCED(pte)) {
1950 mtx_lock_spin(&tlbivax_mutex);
1953 tlb0_flush_entry(pv->pv_va);
1954 *pte &= ~PTE_REFERENCED;
1957 mtx_unlock_spin(&tlbivax_mutex);
1959 if (++count >= PMAP_TS_REFERENCED_MAX) {
1960 PMAP_UNLOCK(pv->pv_pmap);
1965 PMAP_UNLOCK(pv->pv_pmap);
1967 rw_wunlock(&pvh_global_lock);
1972 * Clear the wired attribute from the mappings for the specified range of
1973 * addresses in the given pmap. Every valid mapping within that range must
1974 * have the wired attribute set. In contrast, invalid mappings cannot have
1975 * the wired attribute set, so they are ignored.
1977 * The wired attribute of the page table entry is not a hardware feature, so
1978 * there is no need to invalidate any TLB entries.
1981 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1987 for (va = sva; va < eva; va += PAGE_SIZE) {
1988 if ((pte = pte_find(pmap, va)) != NULL &&
1990 if (!PTE_ISWIRED(pte))
1991 panic("mmu_booke_unwire: pte %p isn't wired",
1994 pmap->pm_stats.wired_count--;
2002 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2003 * page. This count may be changed upwards or downwards in the future; it is
2004 * only necessary that true be returned for a small subset of pmaps for proper
2008 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
2014 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2015 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2018 rw_wlock(&pvh_global_lock);
2019 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2020 if (pv->pv_pmap == pmap) {
2027 rw_wunlock(&pvh_global_lock);
2032 * Return the number of managed mappings to the given physical page that are
2036 mmu_booke_page_wired_mappings(vm_page_t m)
2042 if ((m->oflags & VPO_UNMANAGED) != 0)
2044 rw_wlock(&pvh_global_lock);
2045 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2046 PMAP_LOCK(pv->pv_pmap);
2047 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2048 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2050 PMAP_UNLOCK(pv->pv_pmap);
2052 rw_wunlock(&pvh_global_lock);
2057 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2063 * This currently does not work for entries that
2064 * overlap TLB1 entries.
2066 for (i = 0; i < TLB1_ENTRIES; i ++) {
2067 if (tlb1_iomapped(i, pa, size, &va) == 0)
2075 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2081 /* Minidumps are based on virtual memory addresses. */
2083 *va = (void *)(vm_offset_t)pa;
2087 /* Raw physical memory dumps don't have a virtual address. */
2088 /* We always map a 256MB page at 256M. */
2089 gran = 256 * 1024 * 1024;
2090 ppa = rounddown2(pa, gran);
2093 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2095 if (sz > (gran - ofs))
2096 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2101 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2109 /* Minidumps are based on virtual memory addresses. */
2110 /* Nothing to do... */
2114 for (i = 0; i < TLB1_ENTRIES; i++) {
2115 tlb1_read_entry(&e, i);
2116 if (!(e.mas1 & MAS1_VALID))
2120 /* Raw physical memory dumps don't have a virtual address. */
2125 tlb1_write_entry(&e, i);
2127 gran = 256 * 1024 * 1024;
2128 ppa = rounddown2(pa, gran);
2130 if (sz > (gran - ofs)) {
2135 tlb1_write_entry(&e, i);
2139 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2142 mmu_booke_scan_init()
2149 /* Initialize phys. segments for dumpsys(). */
2150 memset(&dump_map, 0, sizeof(dump_map));
2151 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2152 &availmem_regions_sz);
2153 for (i = 0; i < physmem_regions_sz; i++) {
2154 dump_map[i].pa_start = physmem_regions[i].mr_start;
2155 dump_map[i].pa_size = physmem_regions[i].mr_size;
2160 /* Virtual segments for minidumps: */
2161 memset(&dump_map, 0, sizeof(dump_map));
2163 /* 1st: kernel .data and .bss. */
2164 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2165 dump_map[0].pa_size =
2166 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2168 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2169 dump_map[1].pa_start = data_start;
2170 dump_map[1].pa_size = data_end - data_start;
2172 /* 3rd: kernel VM. */
2173 va = dump_map[1].pa_start + dump_map[1].pa_size;
2174 /* Find start of next chunk (from va). */
2175 while (va < virtual_end) {
2176 /* Don't dump the buffer cache. */
2177 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2178 va = kmi.buffer_eva;
2181 pte = pte_find(kernel_pmap, va);
2182 if (pte != NULL && PTE_ISVALID(pte))
2186 if (va < virtual_end) {
2187 dump_map[2].pa_start = va;
2189 /* Find last page in chunk. */
2190 while (va < virtual_end) {
2191 /* Don't run into the buffer cache. */
2192 if (va == kmi.buffer_sva)
2194 pte = pte_find(kernel_pmap, va);
2195 if (pte == NULL || !PTE_ISVALID(pte))
2199 dump_map[2].pa_size = va - dump_map[2].pa_start;
2204 * Map a set of physical memory pages into the kernel virtual address space.
2205 * Return a pointer to where it is mapped. This routine is intended to be used
2206 * for mapping device memory, NOT real memory.
2209 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2212 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2216 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2220 for (i = 0; i < TLB1_ENTRIES; i++) {
2221 tlb1_read_entry(e, i);
2222 if ((e->mas1 & MAS1_VALID) == 0)
2231 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2235 #ifndef __powerpc64__
2238 uintptr_t va, retva;
2244 * Check if this is premapped in TLB1.
2249 wimge = tlb_calc_wimg(pa, ma);
2250 for (i = 0; i < TLB1_ENTRIES; i++) {
2251 tlb1_read_entry(&e, i);
2252 if (!(e.mas1 & MAS1_VALID))
2254 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2256 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2257 va = e.virt + (pa - e.phys);
2258 tmppa = e.phys + e.size;
2259 sz -= MIN(sz, e.size - (pa - e.phys));
2260 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2261 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2263 sz -= MIN(sz, e.size);
2264 tmppa = e.phys + e.size;
2268 return ((void *)va);
2272 size = roundup(size, PAGE_SIZE);
2274 #ifdef __powerpc64__
2275 KASSERT(pa < VM_MAPDEV_PA_MAX,
2276 ("Unsupported physical address! %lx", pa));
2277 va = VM_MAPDEV_BASE + pa;
2279 #ifdef POW2_MAPPINGS
2281 * Align the mapping to a power of 2 size, taking into account that we
2282 * may need to increase the size multiple times to satisfy the size and
2283 * alignment requirements.
2285 * This works in the general case because it's very rare (near never?)
2286 * to have different access properties (WIMG) within a single
2287 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2288 * can be undefined, and exact mappings will be used instead.
2291 size = roundup2(size, 1 << ilog2(size));
2292 while (rounddown2(va, size) + size < va + sz)
2294 va = rounddown2(va, size);
2295 pa = rounddown2(pa, size);
2299 * The device mapping area is between VM_MAXUSER_ADDRESS and
2300 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2302 #ifdef SPARSE_MAPDEV
2304 * With a sparse mapdev, align to the largest starting region. This
2305 * could feasibly be optimized for a 'best-fit' alignment, but that
2306 * calculation could be very costly.
2307 * Align to the smaller of:
2308 * - first set bit in overlap of (pa & size mask)
2309 * - largest size envelope
2311 * It's possible the device mapping may start at a PA that's not larger
2312 * than the size mask, so we need to offset in to maximize the TLB entry
2313 * range and minimize the number of used TLB entries.
2316 tmpva = tlb1_map_base;
2317 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2318 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2319 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2320 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2322 va = atomic_fetchadd_int(&tlb1_map_base, size);
2326 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2329 return ((void *)retva);
2333 * 'Unmap' a range mapped by mmu_booke_mapdev().
2336 mmu_booke_unmapdev(vm_offset_t va, vm_size_t size)
2338 #ifdef SUPPORTS_SHRINKING_TLB1
2339 vm_offset_t base, offset;
2342 * Unmap only if this is inside kernel virtual space.
2344 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2345 base = trunc_page(va);
2346 offset = va & PAGE_MASK;
2347 size = roundup(offset + size, PAGE_SIZE);
2348 kva_free(base, size);
2354 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2355 * specified pmap. This eliminates the blast of soft faults on process startup
2356 * and immediately after an mmap.
2359 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2360 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2363 VM_OBJECT_ASSERT_WLOCKED(object);
2364 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2365 ("mmu_booke_object_init_pt: non-device object"));
2369 * Perform the pmap work for mincore.
2372 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2375 /* XXX: this should be implemented at some point */
2380 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode)
2387 addr = trunc_page(addr);
2389 /* Only allow changes to mapped kernel addresses. This includes:
2391 * - DMAP (powerpc64)
2394 if (addr <= VM_MAXUSER_ADDRESS ||
2395 #ifdef __powerpc64__
2396 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2397 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2399 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2401 (addr > VM_MAX_KERNEL_ADDRESS))
2404 /* Check TLB1 mappings */
2405 for (i = 0; i < TLB1_ENTRIES; i++) {
2406 tlb1_read_entry(&e, i);
2407 if (!(e.mas1 & MAS1_VALID))
2409 if (addr >= e.virt && addr < e.virt + e.size)
2412 if (i < TLB1_ENTRIES) {
2413 /* Only allow full mappings to be modified for now. */
2414 /* Validate the range. */
2415 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2416 tlb1_read_entry(&e, j);
2417 if (va != e.virt || (sz - (va - addr) < e.size))
2420 for (va = addr; va < addr + sz; va += e.size, i++) {
2421 tlb1_read_entry(&e, i);
2422 e.mas2 &= ~MAS2_WIMGE_MASK;
2423 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2426 * Write it out to the TLB. Should really re-sync with other
2429 tlb1_write_entry(&e, i);
2434 /* Not in TLB1, try through pmap */
2435 /* First validate the range. */
2436 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2437 pte = pte_find(kernel_pmap, va);
2438 if (pte == NULL || !PTE_ISVALID(pte))
2442 mtx_lock_spin(&tlbivax_mutex);
2444 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2445 pte = pte_find(kernel_pmap, va);
2446 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2447 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2448 tlb0_flush_entry(va);
2451 mtx_unlock_spin(&tlbivax_mutex);
2457 mmu_booke_page_array_startup(long pages)
2459 vm_page_array_size = pages;
2462 /**************************************************************************/
2464 /**************************************************************************/
2467 * Allocate a TID. If necessary, steal one from someone else.
2468 * The new TID is flushed from the TLB before returning.
2471 tid_alloc(pmap_t pmap)
2476 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2478 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2480 thiscpu = PCPU_GET(cpuid);
2482 tid = PCPU_GET(booke.tid_next);
2485 PCPU_SET(booke.tid_next, tid + 1);
2487 /* If we are stealing TID then clear the relevant pmap's field */
2488 if (tidbusy[thiscpu][tid] != NULL) {
2490 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2492 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2494 /* Flush all entries from TLB0 matching this TID. */
2498 tidbusy[thiscpu][tid] = pmap;
2499 pmap->pm_tid[thiscpu] = tid;
2500 __asm __volatile("msync; isync");
2502 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2503 PCPU_GET(booke.tid_next));
2508 /**************************************************************************/
2510 /**************************************************************************/
2512 /* Convert TLB0 va and way number to tlb0[] table index. */
2513 static inline unsigned int
2514 tlb0_tableidx(vm_offset_t va, unsigned int way)
2518 idx = (way * TLB0_ENTRIES_PER_WAY);
2519 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2524 * Invalidate TLB0 entry.
2527 tlb0_flush_entry(vm_offset_t va)
2530 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2532 mtx_assert(&tlbivax_mutex, MA_OWNED);
2534 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2535 __asm __volatile("isync; msync");
2536 __asm __volatile("tlbsync; msync");
2538 CTR1(KTR_PMAP, "%s: e", __func__);
2542 /**************************************************************************/
2544 /**************************************************************************/
2547 * TLB1 mapping notes:
2549 * TLB1[0] Kernel text and data.
2550 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2551 * windows, other devices mappings.
2555 * Read an entry from given TLB1 slot.
2558 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2563 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2566 __asm __volatile("wrteei 0");
2568 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2569 mtspr(SPR_MAS0, mas0);
2570 __asm __volatile("isync; tlbre");
2572 entry->mas1 = mfspr(SPR_MAS1);
2573 entry->mas2 = mfspr(SPR_MAS2);
2574 entry->mas3 = mfspr(SPR_MAS3);
2576 switch ((mfpvr() >> 16) & 0xFFFF) {
2581 entry->mas7 = mfspr(SPR_MAS7);
2587 __asm __volatile("wrtee %0" :: "r"(msr));
2589 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2590 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2591 (entry->mas3 & MAS3_RPN);
2593 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2596 struct tlbwrite_args {
2602 tlb1_find_free(void)
2607 for (i = 0; i < TLB1_ENTRIES; i++) {
2608 tlb1_read_entry(&e, i);
2609 if ((e.mas1 & MAS1_VALID) == 0)
2616 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2621 for (i = 0; i < TLB1_ENTRIES; i++) {
2622 tlb1_read_entry(&e, i);
2623 if ((e.mas1 & MAS1_VALID) == 0)
2625 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2626 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2627 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2628 __asm __volatile("isync; tlbwe; isync; msync");
2634 tlb1_write_entry_int(void *arg)
2636 struct tlbwrite_args *args = arg;
2641 tlb1_purge_va_range(args->e->virt, args->e->size);
2642 idx = tlb1_find_free();
2644 panic("No free TLB1 entries!\n");
2647 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2649 mtspr(SPR_MAS0, mas0);
2650 mtspr(SPR_MAS1, args->e->mas1);
2651 mtspr(SPR_MAS2, args->e->mas2);
2652 mtspr(SPR_MAS3, args->e->mas3);
2653 switch ((mfpvr() >> 16) & 0xFFFF) {
2660 mtspr(SPR_MAS7, args->e->mas7);
2666 __asm __volatile("isync; tlbwe; isync; msync");
2671 tlb1_write_entry_sync(void *arg)
2673 /* Empty synchronization point for smp_rendezvous(). */
2677 * Write given entry to TLB1 hardware.
2680 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2682 struct tlbwrite_args args;
2688 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2690 smp_rendezvous(tlb1_write_entry_sync,
2691 tlb1_write_entry_int,
2692 tlb1_write_entry_sync, &args);
2699 __asm __volatile("wrteei 0");
2700 tlb1_write_entry_int(&args);
2701 __asm __volatile("wrtee %0" :: "r"(msr));
2706 * Convert TLB TSIZE value to mapped region size.
2709 tsize2size(unsigned int tsize)
2714 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2717 return ((1 << (2 * tsize)) * 1024);
2721 * Convert region size (must be power of 4) to TLB TSIZE value.
2724 size2tsize(vm_size_t size)
2727 return (ilog2(size) / 2 - 5);
2731 * Register permanent kernel mapping in TLB1.
2733 * Entries are created starting from index 0 (current free entry is
2734 * kept in tlb1_idx) and are not supposed to be invalidated.
2737 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2744 /* First try to update an existing entry. */
2745 for (index = 0; index < TLB1_ENTRIES; index++) {
2746 tlb1_read_entry(&e, index);
2747 /* Check if we're just updating the flags, and update them. */
2748 if (e.phys == pa && e.virt == va && e.size == size) {
2749 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2750 tlb1_write_entry(&e, index);
2755 /* Convert size to TSIZE */
2756 tsize = size2tsize(size);
2758 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2759 /* XXX TS is hard coded to 0 for now as we only use single address space */
2760 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2765 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2766 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2767 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2769 /* Set supervisor RWX permission bits */
2770 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2771 e.mas7 = (pa >> 32) & MAS7_RPN;
2773 tlb1_write_entry(&e, -1);
2779 * Map in contiguous RAM region into the TLB1.
2782 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2785 vm_size_t mapped, sz, ssize;
2792 sz = 1UL << (ilog2(size) & ~1);
2793 /* Align size to PA */
2797 } while (pa % sz != 0);
2799 /* Now align from there to VA */
2803 } while (va % sz != 0);
2805 #ifdef __powerpc64__
2807 * Clamp TLB1 entries to 4G.
2809 * While the e6500 supports up to 1TB mappings, the e5500
2810 * only supports up to 4G mappings. (0b1011)
2812 * If any e6500 machines capable of supporting a very
2813 * large amount of memory appear in the future, we can
2816 * For now, though, since we have plenty of space in TLB1,
2817 * always avoid creating entries larger than 4GB.
2819 sz = MIN(sz, 1UL << 32);
2822 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2823 (void *)va, (uintmax_t)pa, (long)sz);
2824 if (tlb1_set_entry(va, pa, sz,
2825 _TLB_ENTRY_SHARED | wimge) < 0)
2832 mapped = (va - base);
2834 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2835 mapped, mapped - ssize);
2841 * TLB1 initialization routine, to be called after the very first
2842 * assembler level setup done in locore.S.
2848 uint32_t mas0, mas1, mas3, mas7;
2853 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2854 mtspr(SPR_MAS0, mas0);
2855 __asm __volatile("isync; tlbre");
2857 mas1 = mfspr(SPR_MAS1);
2858 mas2 = mfspr(SPR_MAS2);
2859 mas3 = mfspr(SPR_MAS3);
2860 mas7 = mfspr(SPR_MAS7);
2862 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2865 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2866 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2867 kernstart = trunc_page(mas2);
2869 /* Setup TLB miss defaults */
2870 set_mas4_defaults();
2874 * pmap_early_io_unmap() should be used in short conjunction with
2875 * pmap_early_io_map(), as in the following snippet:
2877 * x = pmap_early_io_map(...);
2878 * <do something with x>
2879 * pmap_early_io_unmap(x, size);
2881 * And avoiding more allocations between.
2884 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2890 size = roundup(size, PAGE_SIZE);
2892 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2893 tlb1_read_entry(&e, i);
2894 if (!(e.mas1 & MAS1_VALID))
2896 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2898 e.mas1 &= ~MAS1_VALID;
2899 tlb1_write_entry(&e, i);
2902 if (tlb1_map_base == va + isize)
2903 tlb1_map_base -= isize;
2907 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2914 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2916 for (i = 0; i < TLB1_ENTRIES; i++) {
2917 tlb1_read_entry(&e, i);
2918 if (!(e.mas1 & MAS1_VALID))
2920 if (pa >= e.phys && (pa + size) <=
2922 return (e.virt + (pa - e.phys));
2925 pa_base = rounddown(pa, PAGE_SIZE);
2926 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2927 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2928 va = tlb1_map_base + (pa - pa_base);
2931 sz = 1 << (ilog2(size) & ~1);
2932 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2933 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2936 tlb1_map_base += sz;
2943 pmap_track_page(pmap_t pmap, vm_offset_t va)
2947 struct pv_entry *pve;
2949 va = trunc_page(va);
2950 pa = pmap_kextract(va);
2951 page = PHYS_TO_VM_PAGE(pa);
2953 rw_wlock(&pvh_global_lock);
2956 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
2957 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
2961 page->md.pv_tracked = true;
2962 pv_insert(pmap, va, page);
2965 rw_wunlock(&pvh_global_lock);
2970 * Setup MAS4 defaults.
2971 * These values are loaded to MAS0-2 on a TLB miss.
2974 set_mas4_defaults(void)
2978 /* Defaults: TLB0, PID0, TSIZED=4K */
2979 mas4 = MAS4_TLBSELD0;
2980 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
2984 mtspr(SPR_MAS4, mas4);
2985 __asm __volatile("isync");
2990 * Return 0 if the physical IO range is encompassed by one of the
2991 * the TLB1 entries, otherwise return related error code.
2994 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
2997 vm_paddr_t pa_start;
2999 unsigned int entry_tsize;
3000 vm_size_t entry_size;
3003 *va = (vm_offset_t)NULL;
3005 tlb1_read_entry(&e, i);
3006 /* Skip invalid entries */
3007 if (!(e.mas1 & MAS1_VALID))
3011 * The entry must be cache-inhibited, guarded, and r/w
3012 * so it can function as an i/o page
3014 prot = e.mas2 & (MAS2_I | MAS2_G);
3015 if (prot != (MAS2_I | MAS2_G))
3018 prot = e.mas3 & (MAS3_SR | MAS3_SW);
3019 if (prot != (MAS3_SR | MAS3_SW))
3022 /* The address should be within the entry range. */
3023 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3024 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3026 entry_size = tsize2size(entry_tsize);
3027 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
3028 (e.mas3 & MAS3_RPN);
3029 pa_end = pa_start + entry_size;
3031 if ((pa < pa_start) || ((pa + size) > pa_end))
3034 /* Return virtual address of this mapping. */
3035 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3040 /* Print out contents of the MAS registers for each TLB0 entry */
3042 #ifdef __powerpc64__
3043 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3045 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3056 if (mas1 & MAS1_VALID)
3061 if (mas1 & MAS1_IPROT)
3066 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3067 tid = MAS1_GETTID(mas1);
3069 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3072 size = tsize2size(tsize);
3074 printf("%3d: (%s) [AS=%d] "
3075 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3076 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3077 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3080 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3082 uint32_t mas0, mas1, mas3, mas7;
3083 #ifdef __powerpc64__
3088 int entryidx, way, idx;
3090 printf("TLB0 entries:\n");
3091 for (way = 0; way < TLB0_WAYS; way ++)
3092 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3094 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3095 mtspr(SPR_MAS0, mas0);
3097 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3098 mtspr(SPR_MAS2, mas2);
3100 __asm __volatile("isync; tlbre");
3102 mas1 = mfspr(SPR_MAS1);
3103 mas2 = mfspr(SPR_MAS2);
3104 mas3 = mfspr(SPR_MAS3);
3105 mas7 = mfspr(SPR_MAS7);
3107 idx = tlb0_tableidx(mas2, way);
3108 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3113 * Print out contents of the MAS registers for each TLB1 entry
3115 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3117 uint32_t mas0, mas1, mas3, mas7;
3118 #ifdef __powerpc64__
3125 printf("TLB1 entries:\n");
3126 for (i = 0; i < TLB1_ENTRIES; i++) {
3128 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3129 mtspr(SPR_MAS0, mas0);
3131 __asm __volatile("isync; tlbre");
3133 mas1 = mfspr(SPR_MAS1);
3134 mas2 = mfspr(SPR_MAS2);
3135 mas3 = mfspr(SPR_MAS3);
3136 mas7 = mfspr(SPR_MAS7);
3138 tlb_print_entry(i, mas1, mas2, mas3, mas7);