2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/param.h>
55 #include <sys/malloc.h>
59 #include <sys/queue.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/linker.h>
63 #include <sys/msgbuf.h>
65 #include <sys/mutex.h>
66 #include <sys/rwlock.h>
67 #include <sys/sched.h>
69 #include <sys/vmmeter.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
82 #include <machine/cpu.h>
83 #include <machine/pcb.h>
84 #include <machine/platform.h>
86 #include <machine/tlb.h>
87 #include <machine/spr.h>
88 #include <machine/md_var.h>
89 #include <machine/mmuvar.h>
90 #include <machine/pmap.h>
91 #include <machine/pte.h>
96 #define debugf(fmt, args...) printf(fmt, ##args)
98 #define debugf(fmt, args...)
101 #define TODO panic("%s: not implemented", __func__);
103 extern struct mtx sched_lock;
105 extern int dumpsys_minidump;
107 extern unsigned char _etext[];
108 extern unsigned char _end[];
110 extern uint32_t *bootinfo;
113 extern uint32_t bp_ntlb1s;
116 vm_paddr_t ccsrbar_pa;
118 vm_offset_t kernstart;
121 /* Message buffer and tables. */
122 static vm_offset_t data_start;
123 static vm_size_t data_end;
125 /* Phys/avail memory regions. */
126 static struct mem_region *availmem_regions;
127 static int availmem_regions_sz;
128 static struct mem_region *physmem_regions;
129 static int physmem_regions_sz;
131 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
132 static vm_offset_t zero_page_va;
133 static struct mtx zero_page_mutex;
135 static struct mtx tlbivax_mutex;
138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
139 * by idle thred only, no lock required.
141 static vm_offset_t zero_page_idle_va;
143 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
144 static vm_offset_t copy_page_src_va;
145 static vm_offset_t copy_page_dst_va;
146 static struct mtx copy_page_mutex;
148 /**************************************************************************/
150 /**************************************************************************/
152 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
153 vm_prot_t, boolean_t);
155 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
156 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
159 * If user pmap is processed with mmu_booke_remove and the resident count
160 * drops to 0, there are no more pages to remove, so we need not continue.
162 #define PMAP_REMOVE_DONE(pmap) \
163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
165 extern void tid_flush(tlbtid_t);
167 /**************************************************************************/
168 /* TLB and TID handling */
169 /**************************************************************************/
171 /* Translation ID busy table */
172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
176 * core revisions and should be read from h/w registers during early config.
178 uint32_t tlb0_entries;
180 uint32_t tlb0_entries_per_way;
182 #define TLB0_ENTRIES (tlb0_entries)
183 #define TLB0_WAYS (tlb0_ways)
184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
186 #define TLB1_ENTRIES 16
188 /* In-ram copy of the TLB1 */
189 static tlb_entry_t tlb1[TLB1_ENTRIES];
191 /* Next free entry in the TLB1 */
192 static unsigned int tlb1_idx;
194 static tlbtid_t tid_alloc(struct pmap *);
196 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
198 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
199 static void tlb1_write_entry(unsigned int);
200 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
201 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
203 static vm_size_t tsize2size(unsigned int);
204 static unsigned int size2tsize(vm_size_t);
205 static unsigned int ilog2(unsigned int);
207 static void set_mas4_defaults(void);
209 static inline void tlb0_flush_entry(vm_offset_t);
210 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
212 /**************************************************************************/
213 /* Page table management */
214 /**************************************************************************/
216 static struct rwlock_padalign pvh_global_lock;
218 /* Data for the pv entry allocation mechanism */
219 static uma_zone_t pvzone;
220 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
222 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
224 #ifndef PMAP_SHPGPERPROC
225 #define PMAP_SHPGPERPROC 200
228 static void ptbl_init(void);
229 static struct ptbl_buf *ptbl_buf_alloc(void);
230 static void ptbl_buf_free(struct ptbl_buf *);
231 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
233 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
234 static void ptbl_free(mmu_t, pmap_t, unsigned int);
235 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
236 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
238 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
239 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
240 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
241 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
243 static pv_entry_t pv_alloc(void);
244 static void pv_free(pv_entry_t);
245 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
246 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
248 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
249 #define PTBL_BUFS (128 * 16)
252 TAILQ_ENTRY(ptbl_buf) link; /* list link */
253 vm_offset_t kva; /* va of mapping */
256 /* ptbl free list and a lock used for access synchronization. */
257 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
258 static struct mtx ptbl_buf_freelist_lock;
260 /* Base address of kva space allocated fot ptbl bufs. */
261 static vm_offset_t ptbl_buf_pool_vabase;
263 /* Pointer to ptbl_buf structures. */
264 static struct ptbl_buf *ptbl_bufs;
266 void pmap_bootstrap_ap(volatile uint32_t *);
269 * Kernel MMU interface
271 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
272 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
273 static void mmu_booke_clear_reference(mmu_t, vm_page_t);
274 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
275 vm_size_t, vm_offset_t);
276 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
277 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
278 vm_offset_t, vm_page_t *, vm_offset_t, int);
279 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
280 vm_prot_t, boolean_t);
281 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
282 vm_page_t, vm_prot_t);
283 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
285 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
286 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
288 static void mmu_booke_init(mmu_t);
289 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
290 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
291 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
292 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
293 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
295 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
297 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
298 vm_object_t, vm_pindex_t, vm_size_t);
299 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
300 static void mmu_booke_page_init(mmu_t, vm_page_t);
301 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
302 static void mmu_booke_pinit(mmu_t, pmap_t);
303 static void mmu_booke_pinit0(mmu_t, pmap_t);
304 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
306 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
307 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
308 static void mmu_booke_release(mmu_t, pmap_t);
309 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
310 static void mmu_booke_remove_all(mmu_t, vm_page_t);
311 static void mmu_booke_remove_write(mmu_t, vm_page_t);
312 static void mmu_booke_zero_page(mmu_t, vm_page_t);
313 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
314 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
315 static void mmu_booke_activate(mmu_t, struct thread *);
316 static void mmu_booke_deactivate(mmu_t, struct thread *);
317 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
318 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
319 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
320 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
321 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
322 static void mmu_booke_kremove(mmu_t, vm_offset_t);
323 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
324 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
326 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
327 vm_size_t, vm_size_t *);
328 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
329 vm_size_t, vm_offset_t);
330 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
332 static mmu_method_t mmu_booke_methods[] = {
333 /* pmap dispatcher interface */
334 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
335 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
336 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference),
337 MMUMETHOD(mmu_copy, mmu_booke_copy),
338 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
339 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
340 MMUMETHOD(mmu_enter, mmu_booke_enter),
341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
343 MMUMETHOD(mmu_extract, mmu_booke_extract),
344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
345 MMUMETHOD(mmu_init, mmu_booke_init),
346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
350 MMUMETHOD(mmu_map, mmu_booke_map),
351 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
354 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
356 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
358 MMUMETHOD(mmu_protect, mmu_booke_protect),
359 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
360 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
361 MMUMETHOD(mmu_release, mmu_booke_release),
362 MMUMETHOD(mmu_remove, mmu_booke_remove),
363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
369 MMUMETHOD(mmu_activate, mmu_booke_activate),
370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
372 /* Internal interfaces */
373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
376 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
377 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
378 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
381 /* dumpsys() support */
382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
389 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
400 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
403 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
404 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
406 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
407 ("tlb_miss_lock: tried to lock self"));
409 tlb_lock(pc->pc_booke_tlb_lock);
411 CTR1(KTR_PMAP, "%s: locked", __func__);
418 tlb_miss_unlock(void)
426 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
428 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
429 __func__, pc->pc_cpuid);
431 tlb_unlock(pc->pc_booke_tlb_lock);
433 CTR1(KTR_PMAP, "%s: unlocked", __func__);
439 /* Return number of entries in TLB0. */
441 tlb0_get_tlbconf(void)
445 tlb0_cfg = mfspr(SPR_TLB0CFG);
446 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
447 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
448 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
451 /* Initialize pool of kva ptbl buffers. */
457 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
458 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
459 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
460 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
462 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
463 TAILQ_INIT(&ptbl_buf_freelist);
465 for (i = 0; i < PTBL_BUFS; i++) {
466 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
467 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
471 /* Get a ptbl_buf from the freelist. */
472 static struct ptbl_buf *
475 struct ptbl_buf *buf;
477 mtx_lock(&ptbl_buf_freelist_lock);
478 buf = TAILQ_FIRST(&ptbl_buf_freelist);
480 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
481 mtx_unlock(&ptbl_buf_freelist_lock);
483 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
488 /* Return ptbl buff to free pool. */
490 ptbl_buf_free(struct ptbl_buf *buf)
493 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
495 mtx_lock(&ptbl_buf_freelist_lock);
496 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
497 mtx_unlock(&ptbl_buf_freelist_lock);
501 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
504 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
506 struct ptbl_buf *pbuf;
508 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
510 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
512 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
513 if (pbuf->kva == (vm_offset_t)ptbl) {
514 /* Remove from pmap ptbl buf list. */
515 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
517 /* Free corresponding ptbl buf. */
523 /* Allocate page table. */
525 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
527 vm_page_t mtbl[PTBL_PAGES];
529 struct ptbl_buf *pbuf;
534 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
535 (pmap == kernel_pmap), pdir_idx);
537 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
538 ("ptbl_alloc: invalid pdir_idx"));
539 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
540 ("pte_alloc: valid ptbl entry exists!"));
542 pbuf = ptbl_buf_alloc();
544 panic("pte_alloc: couldn't alloc kernel virtual memory");
546 ptbl = (pte_t *)pbuf->kva;
548 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
550 /* Allocate ptbl pages, this will sleep! */
551 for (i = 0; i < PTBL_PAGES; i++) {
552 pidx = (PTBL_PAGES * pdir_idx) + i;
553 while ((m = vm_page_alloc(NULL, pidx,
554 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
557 rw_wunlock(&pvh_global_lock);
559 rw_wlock(&pvh_global_lock);
565 /* Map allocated pages into kernel_pmap. */
566 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
568 /* Zero whole ptbl. */
569 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
571 /* Add pbuf to the pmap ptbl bufs list. */
572 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
577 /* Free ptbl pages and invalidate pdir entry. */
579 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
587 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
588 (pmap == kernel_pmap), pdir_idx);
590 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
591 ("ptbl_free: invalid pdir_idx"));
593 ptbl = pmap->pm_pdir[pdir_idx];
595 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
597 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
600 * Invalidate the pdir entry as soon as possible, so that other CPUs
601 * don't attempt to look up the page tables we are releasing.
603 mtx_lock_spin(&tlbivax_mutex);
606 pmap->pm_pdir[pdir_idx] = NULL;
609 mtx_unlock_spin(&tlbivax_mutex);
611 for (i = 0; i < PTBL_PAGES; i++) {
612 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
613 pa = pte_vatopa(mmu, kernel_pmap, va);
614 m = PHYS_TO_VM_PAGE(pa);
615 vm_page_free_zero(m);
616 atomic_subtract_int(&cnt.v_wire_count, 1);
617 mmu_booke_kremove(mmu, va);
620 ptbl_free_pmap_ptbl(pmap, ptbl);
624 * Decrement ptbl pages hold count and attempt to free ptbl pages.
625 * Called when removing pte entry from ptbl.
627 * Return 1 if ptbl pages were freed.
630 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
637 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
638 (pmap == kernel_pmap), pdir_idx);
640 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
641 ("ptbl_unhold: invalid pdir_idx"));
642 KASSERT((pmap != kernel_pmap),
643 ("ptbl_unhold: unholding kernel ptbl!"));
645 ptbl = pmap->pm_pdir[pdir_idx];
647 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
648 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
649 ("ptbl_unhold: non kva ptbl"));
651 /* decrement hold count */
652 for (i = 0; i < PTBL_PAGES; i++) {
653 pa = pte_vatopa(mmu, kernel_pmap,
654 (vm_offset_t)ptbl + (i * PAGE_SIZE));
655 m = PHYS_TO_VM_PAGE(pa);
660 * Free ptbl pages if there are no pte etries in this ptbl.
661 * wire_count has the same value for all ptbl pages, so check the last
664 if (m->wire_count == 0) {
665 ptbl_free(mmu, pmap, pdir_idx);
667 //debugf("ptbl_unhold: e (freed ptbl)\n");
675 * Increment hold count for ptbl pages. This routine is used when a new pte
676 * entry is being inserted into the ptbl.
679 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
686 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
689 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
690 ("ptbl_hold: invalid pdir_idx"));
691 KASSERT((pmap != kernel_pmap),
692 ("ptbl_hold: holding kernel ptbl!"));
694 ptbl = pmap->pm_pdir[pdir_idx];
696 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
698 for (i = 0; i < PTBL_PAGES; i++) {
699 pa = pte_vatopa(mmu, kernel_pmap,
700 (vm_offset_t)ptbl + (i * PAGE_SIZE));
701 m = PHYS_TO_VM_PAGE(pa);
706 /* Allocate pv_entry structure. */
713 if (pv_entry_count > pv_entry_high_water)
715 pv = uma_zalloc(pvzone, M_NOWAIT);
720 /* Free pv_entry structure. */
722 pv_free(pv_entry_t pve)
726 uma_zfree(pvzone, pve);
730 /* Allocate and initialize pv_entry structure. */
732 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
736 //int su = (pmap == kernel_pmap);
737 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
738 // (u_int32_t)pmap, va, (u_int32_t)m);
742 panic("pv_insert: no pv entries!");
748 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
749 rw_assert(&pvh_global_lock, RA_WLOCKED);
751 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
753 //debugf("pv_insert: e\n");
756 /* Destroy pv entry. */
758 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
762 //int su = (pmap == kernel_pmap);
763 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
765 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
766 rw_assert(&pvh_global_lock, RA_WLOCKED);
769 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
770 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
771 /* remove from pv_list */
772 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
773 if (TAILQ_EMPTY(&m->md.pv_list))
774 vm_page_aflag_clear(m, PGA_WRITEABLE);
776 /* free pv entry struct */
782 //debugf("pv_remove: e\n");
786 * Clean pte entry, try to free page table page if requested.
788 * Return 1 if ptbl pages were freed, otherwise return 0.
791 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
793 unsigned int pdir_idx = PDIR_IDX(va);
794 unsigned int ptbl_idx = PTBL_IDX(va);
799 //int su = (pmap == kernel_pmap);
800 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
801 // su, (u_int32_t)pmap, va, flags);
803 ptbl = pmap->pm_pdir[pdir_idx];
804 KASSERT(ptbl, ("pte_remove: null ptbl"));
806 pte = &ptbl[ptbl_idx];
808 if (pte == NULL || !PTE_ISVALID(pte))
811 if (PTE_ISWIRED(pte))
812 pmap->pm_stats.wired_count--;
814 /* Handle managed entry. */
815 if (PTE_ISMANAGED(pte)) {
816 /* Get vm_page_t for mapped pte. */
817 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
819 if (PTE_ISMODIFIED(pte))
822 if (PTE_ISREFERENCED(pte))
823 vm_page_aflag_set(m, PGA_REFERENCED);
825 pv_remove(pmap, va, m);
828 mtx_lock_spin(&tlbivax_mutex);
831 tlb0_flush_entry(va);
836 mtx_unlock_spin(&tlbivax_mutex);
838 pmap->pm_stats.resident_count--;
840 if (flags & PTBL_UNHOLD) {
841 //debugf("pte_remove: e (unhold)\n");
842 return (ptbl_unhold(mmu, pmap, pdir_idx));
845 //debugf("pte_remove: e\n");
850 * Insert PTE for a given page and virtual address.
853 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
855 unsigned int pdir_idx = PDIR_IDX(va);
856 unsigned int ptbl_idx = PTBL_IDX(va);
859 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
860 pmap == kernel_pmap, pmap, va);
862 /* Get the page table pointer. */
863 ptbl = pmap->pm_pdir[pdir_idx];
866 /* Allocate page table pages. */
867 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
870 * Check if there is valid mapping for requested
871 * va, if there is, remove it.
873 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
874 if (PTE_ISVALID(pte)) {
875 pte_remove(mmu, pmap, va, PTBL_HOLD);
878 * pte is not used, increment hold count
881 if (pmap != kernel_pmap)
882 ptbl_hold(mmu, pmap, pdir_idx);
887 * Insert pv_entry into pv_list for mapped page if part of managed
890 if ((m->oflags & VPO_UNMANAGED) == 0) {
891 flags |= PTE_MANAGED;
893 /* Create and insert pv entry. */
894 pv_insert(pmap, va, m);
897 pmap->pm_stats.resident_count++;
899 mtx_lock_spin(&tlbivax_mutex);
902 tlb0_flush_entry(va);
903 if (pmap->pm_pdir[pdir_idx] == NULL) {
905 * If we just allocated a new page table, hook it in
908 pmap->pm_pdir[pdir_idx] = ptbl;
910 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
911 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
912 pte->flags |= (PTE_VALID | flags);
915 mtx_unlock_spin(&tlbivax_mutex);
918 /* Return the pa for the given pmap/va. */
920 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
925 pte = pte_find(mmu, pmap, va);
926 if ((pte != NULL) && PTE_ISVALID(pte))
927 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
931 /* Get a pointer to a PTE in a page table. */
933 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
935 unsigned int pdir_idx = PDIR_IDX(va);
936 unsigned int ptbl_idx = PTBL_IDX(va);
938 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
940 if (pmap->pm_pdir[pdir_idx])
941 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
946 /**************************************************************************/
948 /**************************************************************************/
951 * This is called during booke_init, before the system is really initialized.
954 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
956 vm_offset_t phys_kernelend;
957 struct mem_region *mp, *mp1;
960 u_int phys_avail_count;
961 vm_size_t physsz, hwphyssz, kstack0_sz;
962 vm_offset_t kernel_pdir, kstack0, va;
963 vm_paddr_t kstack0_phys;
967 debugf("mmu_booke_bootstrap: entered\n");
969 /* Initialize invalidation mutex */
970 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
972 /* Read TLB0 size and associativity. */
976 * Align kernel start and end address (kernel image).
977 * Note that kernel end does not necessarily relate to kernsize.
978 * kernsize is the size of the kernel that is actually mapped.
979 * Also note that "start - 1" is deliberate. With SMP, the
980 * entry point is exactly a page from the actual load address.
981 * As such, trunc_page() has no effect and we're off by a page.
982 * Since we always have the ELF header between the load address
983 * and the entry point, we can safely subtract 1 to compensate.
985 kernstart = trunc_page(start - 1);
986 data_start = round_page(kernelend);
987 data_end = data_start;
990 * Addresses of preloaded modules (like file systems) use
991 * physical addresses. Make sure we relocate those into
994 preload_addr_relocate = kernstart - kernload;
996 /* Allocate the dynamic per-cpu area. */
997 dpcpu = (void *)data_end;
998 data_end += DPCPU_SIZE;
1000 /* Allocate space for the message buffer. */
1001 msgbufp = (struct msgbuf *)data_end;
1002 data_end += msgbufsize;
1003 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1006 data_end = round_page(data_end);
1008 /* Allocate space for ptbl_bufs. */
1009 ptbl_bufs = (struct ptbl_buf *)data_end;
1010 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1011 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1014 data_end = round_page(data_end);
1016 /* Allocate PTE tables for kernel KVA. */
1017 kernel_pdir = data_end;
1018 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1019 PDIR_SIZE - 1) / PDIR_SIZE;
1020 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1021 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1022 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1024 debugf(" data_end: 0x%08x\n", data_end);
1025 if (data_end - kernstart > kernsize) {
1026 kernsize += tlb1_mapin_region(kernstart + kernsize,
1027 kernload + kernsize, (data_end - kernstart) - kernsize);
1029 data_end = kernstart + kernsize;
1030 debugf(" updated data_end: 0x%08x\n", data_end);
1033 * Clear the structures - note we can only do it safely after the
1034 * possible additional TLB1 translations are in place (above) so that
1035 * all range up to the currently calculated 'data_end' is covered.
1037 dpcpu_init(dpcpu, 0);
1038 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1039 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1041 /*******************************************************/
1042 /* Set the start and end of kva. */
1043 /*******************************************************/
1044 virtual_avail = round_page(data_end);
1045 virtual_end = VM_MAX_KERNEL_ADDRESS;
1047 /* Allocate KVA space for page zero/copy operations. */
1048 zero_page_va = virtual_avail;
1049 virtual_avail += PAGE_SIZE;
1050 zero_page_idle_va = virtual_avail;
1051 virtual_avail += PAGE_SIZE;
1052 copy_page_src_va = virtual_avail;
1053 virtual_avail += PAGE_SIZE;
1054 copy_page_dst_va = virtual_avail;
1055 virtual_avail += PAGE_SIZE;
1056 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1057 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1058 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1059 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1061 /* Initialize page zero/copy mutexes. */
1062 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1063 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1065 /* Allocate KVA space for ptbl bufs. */
1066 ptbl_buf_pool_vabase = virtual_avail;
1067 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1068 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1069 ptbl_buf_pool_vabase, virtual_avail);
1071 /* Calculate corresponding physical addresses for the kernel region. */
1072 phys_kernelend = kernload + kernsize;
1073 debugf("kernel image and allocated data:\n");
1074 debugf(" kernload = 0x%08x\n", kernload);
1075 debugf(" kernstart = 0x%08x\n", kernstart);
1076 debugf(" kernsize = 0x%08x\n", kernsize);
1078 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1079 panic("mmu_booke_bootstrap: phys_avail too small");
1082 * Remove kernel physical address range from avail regions list. Page
1083 * align all regions. Non-page aligned memory isn't very interesting
1084 * to us. Also, sort the entries for ascending addresses.
1087 /* Retrieve phys/avail mem regions */
1088 mem_regions(&physmem_regions, &physmem_regions_sz,
1089 &availmem_regions, &availmem_regions_sz);
1091 cnt = availmem_regions_sz;
1092 debugf("processing avail regions:\n");
1093 for (mp = availmem_regions; mp->mr_size; mp++) {
1095 e = mp->mr_start + mp->mr_size;
1096 debugf(" %08x-%08x -> ", s, e);
1097 /* Check whether this region holds all of the kernel. */
1098 if (s < kernload && e > phys_kernelend) {
1099 availmem_regions[cnt].mr_start = phys_kernelend;
1100 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1103 /* Look whether this regions starts within the kernel. */
1104 if (s >= kernload && s < phys_kernelend) {
1105 if (e <= phys_kernelend)
1109 /* Now look whether this region ends within the kernel. */
1110 if (e > kernload && e <= phys_kernelend) {
1115 /* Now page align the start and size of the region. */
1121 debugf("%08x-%08x = %x\n", s, e, sz);
1123 /* Check whether some memory is left here. */
1127 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1133 /* Do an insertion sort. */
1134 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1135 if (s < mp1->mr_start)
1138 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1146 availmem_regions_sz = cnt;
1148 /*******************************************************/
1149 /* Steal physical memory for kernel stack from the end */
1150 /* of the first avail region */
1151 /*******************************************************/
1152 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1153 kstack0_phys = availmem_regions[0].mr_start +
1154 availmem_regions[0].mr_size;
1155 kstack0_phys -= kstack0_sz;
1156 availmem_regions[0].mr_size -= kstack0_sz;
1158 /*******************************************************/
1159 /* Fill in phys_avail table, based on availmem_regions */
1160 /*******************************************************/
1161 phys_avail_count = 0;
1164 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1166 debugf("fill in phys_avail:\n");
1167 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1169 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1170 availmem_regions[i].mr_start,
1171 availmem_regions[i].mr_start +
1172 availmem_regions[i].mr_size,
1173 availmem_regions[i].mr_size);
1175 if (hwphyssz != 0 &&
1176 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1177 debugf(" hw.physmem adjust\n");
1178 if (physsz < hwphyssz) {
1179 phys_avail[j] = availmem_regions[i].mr_start;
1181 availmem_regions[i].mr_start +
1189 phys_avail[j] = availmem_regions[i].mr_start;
1190 phys_avail[j + 1] = availmem_regions[i].mr_start +
1191 availmem_regions[i].mr_size;
1193 physsz += availmem_regions[i].mr_size;
1195 physmem = btoc(physsz);
1197 /* Calculate the last available physical address. */
1198 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1200 Maxmem = powerpc_btop(phys_avail[i + 1]);
1202 debugf("Maxmem = 0x%08lx\n", Maxmem);
1203 debugf("phys_avail_count = %d\n", phys_avail_count);
1204 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1207 /*******************************************************/
1208 /* Initialize (statically allocated) kernel pmap. */
1209 /*******************************************************/
1210 PMAP_LOCK_INIT(kernel_pmap);
1211 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1213 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1214 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1215 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1216 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1218 /* Initialize kernel pdir */
1219 for (i = 0; i < kernel_ptbls; i++)
1220 kernel_pmap->pm_pdir[kptbl_min + i] =
1221 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1223 for (i = 0; i < MAXCPU; i++) {
1224 kernel_pmap->pm_tid[i] = TID_KERNEL;
1226 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1227 tidbusy[i][0] = kernel_pmap;
1231 * Fill in PTEs covering kernel code and data. They are not required
1232 * for address translation, as this area is covered by static TLB1
1233 * entries, but for pte_vatopa() to work correctly with kernel area
1236 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1237 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1238 pte->rpn = kernload + (va - kernstart);
1239 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1242 /* Mark kernel_pmap active on all CPUs */
1243 CPU_FILL(&kernel_pmap->pm_active);
1246 * Initialize the global pv list lock.
1248 rw_init(&pvh_global_lock, "pmap pv global");
1250 /*******************************************************/
1252 /*******************************************************/
1254 /* Enter kstack0 into kernel map, provide guard page */
1255 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1256 thread0.td_kstack = kstack0;
1257 thread0.td_kstack_pages = KSTACK_PAGES;
1259 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1260 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1261 kstack0_phys, kstack0_phys + kstack0_sz);
1262 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1264 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1265 for (i = 0; i < KSTACK_PAGES; i++) {
1266 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1267 kstack0 += PAGE_SIZE;
1268 kstack0_phys += PAGE_SIZE;
1271 debugf("virtual_avail = %08x\n", virtual_avail);
1272 debugf("virtual_end = %08x\n", virtual_end);
1274 debugf("mmu_booke_bootstrap: exit\n");
1278 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1283 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1284 * have the snapshot of its contents in the s/w tlb1[] table, so use
1285 * these values directly to (re)program AP's TLB1 hardware.
1287 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1288 /* Skip invalid entries */
1289 if (!(tlb1[i].mas1 & MAS1_VALID))
1292 tlb1_write_entry(i);
1295 set_mas4_defaults();
1299 * Get the physical page address for the given pmap/virtual address.
1302 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1307 pa = pte_vatopa(mmu, pmap, va);
1314 * Extract the physical page address associated with the given
1315 * kernel virtual address.
1318 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1321 return (pte_vatopa(mmu, kernel_pmap, va));
1325 * Initialize the pmap module.
1326 * Called by vm_init, to initialize any structures that the pmap
1327 * system needs to map virtual memory.
1330 mmu_booke_init(mmu_t mmu)
1332 int shpgperproc = PMAP_SHPGPERPROC;
1335 * Initialize the address space (zone) for the pv entries. Set a
1336 * high water mark so that the system can recover from excessive
1337 * numbers of pv entries.
1339 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1340 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1342 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1343 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1345 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1346 pv_entry_high_water = 9 * (pv_entry_max / 10);
1348 uma_zone_reserve_kva(pvzone, pv_entry_max);
1350 /* Pre-fill pvzone with initial number of pv entries. */
1351 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1353 /* Initialize ptbl allocation. */
1358 * Map a list of wired pages into kernel virtual address space. This is
1359 * intended for temporary mappings which do not need page modification or
1360 * references recorded. Existing mappings in the region are overwritten.
1363 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1368 while (count-- > 0) {
1369 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1376 * Remove page mappings from kernel virtual address space. Intended for
1377 * temporary mappings entered by mmu_booke_qenter.
1380 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1385 while (count-- > 0) {
1386 mmu_booke_kremove(mmu, va);
1392 * Map a wired page into kernel virtual address space.
1395 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1397 unsigned int pdir_idx = PDIR_IDX(va);
1398 unsigned int ptbl_idx = PTBL_IDX(va);
1402 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1403 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1405 flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1407 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1409 mtx_lock_spin(&tlbivax_mutex);
1412 if (PTE_ISVALID(pte)) {
1414 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1416 /* Flush entry from TLB0 */
1417 tlb0_flush_entry(va);
1420 pte->rpn = pa & ~PTE_PA_MASK;
1423 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1424 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1425 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1427 /* Flush the real memory from the instruction cache. */
1428 if ((flags & (PTE_I | PTE_G)) == 0) {
1429 __syncicache((void *)va, PAGE_SIZE);
1433 mtx_unlock_spin(&tlbivax_mutex);
1437 * Remove a page from kernel page table.
1440 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1442 unsigned int pdir_idx = PDIR_IDX(va);
1443 unsigned int ptbl_idx = PTBL_IDX(va);
1446 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1448 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1449 (va <= VM_MAX_KERNEL_ADDRESS)),
1450 ("mmu_booke_kremove: invalid va"));
1452 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1454 if (!PTE_ISVALID(pte)) {
1456 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1461 mtx_lock_spin(&tlbivax_mutex);
1464 /* Invalidate entry in TLB0, update PTE. */
1465 tlb0_flush_entry(va);
1470 mtx_unlock_spin(&tlbivax_mutex);
1474 * Initialize pmap associated with process 0.
1477 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1480 mmu_booke_pinit(mmu, pmap);
1481 PCPU_SET(curpmap, pmap);
1485 * Initialize a preallocated and zeroed pmap structure,
1486 * such as one in a vmspace structure.
1489 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1493 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1494 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1496 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1498 PMAP_LOCK_INIT(pmap);
1499 for (i = 0; i < MAXCPU; i++)
1500 pmap->pm_tid[i] = TID_NONE;
1501 CPU_ZERO(&kernel_pmap->pm_active);
1502 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1503 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1504 TAILQ_INIT(&pmap->pm_ptbl_list);
1508 * Release any resources held by the given physical map.
1509 * Called when a pmap initialized by mmu_booke_pinit is being released.
1510 * Should only be called if the map contains no valid mappings.
1513 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1516 KASSERT(pmap->pm_stats.resident_count == 0,
1517 ("pmap_release: pmap resident count %ld != 0",
1518 pmap->pm_stats.resident_count));
1520 PMAP_LOCK_DESTROY(pmap);
1524 * Insert the given physical page at the specified virtual address in the
1525 * target physical map with the protection requested. If specified the page
1526 * will be wired down.
1529 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1530 vm_prot_t prot, boolean_t wired)
1533 rw_wlock(&pvh_global_lock);
1535 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1536 rw_wunlock(&pvh_global_lock);
1541 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1542 vm_prot_t prot, boolean_t wired)
1549 pa = VM_PAGE_TO_PHYS(m);
1550 su = (pmap == kernel_pmap);
1553 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1554 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1555 // (u_int32_t)pmap, su, pmap->pm_tid,
1556 // (u_int32_t)m, va, pa, prot, wired);
1559 KASSERT(((va >= virtual_avail) &&
1560 (va <= VM_MAX_KERNEL_ADDRESS)),
1561 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1563 KASSERT((va <= VM_MAXUSER_ADDRESS),
1564 ("mmu_booke_enter_locked: user pmap, non user va"));
1566 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1567 VM_OBJECT_ASSERT_LOCKED(m->object);
1569 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1572 * If there is an existing mapping, and the physical address has not
1573 * changed, must be protection or wiring change.
1575 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1576 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1579 * Before actually updating pte->flags we calculate and
1580 * prepare its new value in a helper var.
1583 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1585 /* Wiring change, just update stats. */
1587 if (!PTE_ISWIRED(pte)) {
1589 pmap->pm_stats.wired_count++;
1592 if (PTE_ISWIRED(pte)) {
1593 flags &= ~PTE_WIRED;
1594 pmap->pm_stats.wired_count--;
1598 if (prot & VM_PROT_WRITE) {
1599 /* Add write permissions. */
1604 if ((flags & PTE_MANAGED) != 0)
1605 vm_page_aflag_set(m, PGA_WRITEABLE);
1607 /* Handle modified pages, sense modify status. */
1610 * The PTE_MODIFIED flag could be set by underlying
1611 * TLB misses since we last read it (above), possibly
1612 * other CPUs could update it so we check in the PTE
1613 * directly rather than rely on that saved local flags
1616 if (PTE_ISMODIFIED(pte))
1620 if (prot & VM_PROT_EXECUTE) {
1626 * Check existing flags for execute permissions: if we
1627 * are turning execute permissions on, icache should
1630 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1634 flags &= ~PTE_REFERENCED;
1637 * The new flags value is all calculated -- only now actually
1640 mtx_lock_spin(&tlbivax_mutex);
1643 tlb0_flush_entry(va);
1647 mtx_unlock_spin(&tlbivax_mutex);
1651 * If there is an existing mapping, but it's for a different
1652 * physical address, pte_enter() will delete the old mapping.
1654 //if ((pte != NULL) && PTE_ISVALID(pte))
1655 // debugf("mmu_booke_enter_locked: replace\n");
1657 // debugf("mmu_booke_enter_locked: new\n");
1659 /* Now set up the flags and install the new mapping. */
1660 flags = (PTE_SR | PTE_VALID);
1666 if (prot & VM_PROT_WRITE) {
1671 if ((m->oflags & VPO_UNMANAGED) == 0)
1672 vm_page_aflag_set(m, PGA_WRITEABLE);
1675 if (prot & VM_PROT_EXECUTE) {
1681 /* If its wired update stats. */
1683 pmap->pm_stats.wired_count++;
1687 pte_enter(mmu, pmap, m, va, flags);
1689 /* Flush the real memory from the instruction cache. */
1690 if (prot & VM_PROT_EXECUTE)
1694 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1695 __syncicache((void *)va, PAGE_SIZE);
1701 * Maps a sequence of resident pages belonging to the same object.
1702 * The sequence begins with the given page m_start. This page is
1703 * mapped at the given virtual address start. Each subsequent page is
1704 * mapped at a virtual address that is offset from start by the same
1705 * amount as the page is offset from m_start within the object. The
1706 * last page in the sequence is the page with the largest offset from
1707 * m_start that can be mapped at a virtual address less than the given
1708 * virtual address end. Not every virtual page between start and end
1709 * is mapped; only those for which a resident page exists with the
1710 * corresponding offset from m_start are mapped.
1713 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1714 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1717 vm_pindex_t diff, psize;
1719 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1721 psize = atop(end - start);
1723 rw_wlock(&pvh_global_lock);
1725 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1726 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1727 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1728 m = TAILQ_NEXT(m, listq);
1730 rw_wunlock(&pvh_global_lock);
1735 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1739 rw_wlock(&pvh_global_lock);
1741 mmu_booke_enter_locked(mmu, pmap, va, m,
1742 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1743 rw_wunlock(&pvh_global_lock);
1748 * Remove the given range of addresses from the specified map.
1750 * It is assumed that the start and end are properly rounded to the page size.
1753 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1758 int su = (pmap == kernel_pmap);
1760 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1761 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1764 KASSERT(((va >= virtual_avail) &&
1765 (va <= VM_MAX_KERNEL_ADDRESS)),
1766 ("mmu_booke_remove: kernel pmap, non kernel va"));
1768 KASSERT((va <= VM_MAXUSER_ADDRESS),
1769 ("mmu_booke_remove: user pmap, non user va"));
1772 if (PMAP_REMOVE_DONE(pmap)) {
1773 //debugf("mmu_booke_remove: e (empty)\n");
1777 hold_flag = PTBL_HOLD_FLAG(pmap);
1778 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1780 rw_wlock(&pvh_global_lock);
1782 for (; va < endva; va += PAGE_SIZE) {
1783 pte = pte_find(mmu, pmap, va);
1784 if ((pte != NULL) && PTE_ISVALID(pte))
1785 pte_remove(mmu, pmap, va, hold_flag);
1788 rw_wunlock(&pvh_global_lock);
1790 //debugf("mmu_booke_remove: e\n");
1794 * Remove physical page from all pmaps in which it resides.
1797 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1802 rw_wlock(&pvh_global_lock);
1803 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1804 pvn = TAILQ_NEXT(pv, pv_link);
1806 PMAP_LOCK(pv->pv_pmap);
1807 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1808 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1809 PMAP_UNLOCK(pv->pv_pmap);
1811 vm_page_aflag_clear(m, PGA_WRITEABLE);
1812 rw_wunlock(&pvh_global_lock);
1816 * Map a range of physical addresses into kernel virtual address space.
1819 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1820 vm_paddr_t pa_end, int prot)
1822 vm_offset_t sva = *virt;
1823 vm_offset_t va = sva;
1825 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1826 // sva, pa_start, pa_end);
1828 while (pa_start < pa_end) {
1829 mmu_booke_kenter(mmu, va, pa_start);
1831 pa_start += PAGE_SIZE;
1835 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1840 * The pmap must be activated before it's address space can be accessed in any
1844 mmu_booke_activate(mmu_t mmu, struct thread *td)
1849 pmap = &td->td_proc->p_vmspace->vm_pmap;
1851 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1852 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1854 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1856 mtx_lock_spin(&sched_lock);
1858 cpuid = PCPU_GET(cpuid);
1859 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1860 PCPU_SET(curpmap, pmap);
1862 if (pmap->pm_tid[cpuid] == TID_NONE)
1865 /* Load PID0 register with pmap tid value. */
1866 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1867 __asm __volatile("isync");
1869 mtx_unlock_spin(&sched_lock);
1871 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1872 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1876 * Deactivate the specified process's address space.
1879 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1883 pmap = &td->td_proc->p_vmspace->vm_pmap;
1885 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1886 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1888 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1889 PCPU_SET(curpmap, NULL);
1893 * Copy the range specified by src_addr/len
1894 * from the source map to the range dst_addr/len
1895 * in the destination map.
1897 * This routine is only advisory and need not do anything.
1900 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1901 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1907 * Set the physical protection on the specified range of this map as requested.
1910 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1917 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1918 mmu_booke_remove(mmu, pmap, sva, eva);
1922 if (prot & VM_PROT_WRITE)
1926 for (va = sva; va < eva; va += PAGE_SIZE) {
1927 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1928 if (PTE_ISVALID(pte)) {
1929 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1931 mtx_lock_spin(&tlbivax_mutex);
1934 /* Handle modified pages. */
1935 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1938 tlb0_flush_entry(va);
1939 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1942 mtx_unlock_spin(&tlbivax_mutex);
1950 * Clear the write and modified bits in each of the given page's mappings.
1953 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
1958 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1959 ("mmu_booke_remove_write: page %p is not managed", m));
1962 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1963 * set by another thread while the object is locked. Thus,
1964 * if PGA_WRITEABLE is clear, no page table entries need updating.
1966 VM_OBJECT_ASSERT_WLOCKED(m->object);
1967 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1969 rw_wlock(&pvh_global_lock);
1970 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1971 PMAP_LOCK(pv->pv_pmap);
1972 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
1973 if (PTE_ISVALID(pte)) {
1974 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1976 mtx_lock_spin(&tlbivax_mutex);
1979 /* Handle modified pages. */
1980 if (PTE_ISMODIFIED(pte))
1983 /* Flush mapping from TLB0. */
1984 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1987 mtx_unlock_spin(&tlbivax_mutex);
1990 PMAP_UNLOCK(pv->pv_pmap);
1992 vm_page_aflag_clear(m, PGA_WRITEABLE);
1993 rw_wunlock(&pvh_global_lock);
1997 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2006 va = trunc_page(va);
2007 sz = round_page(sz);
2009 rw_wlock(&pvh_global_lock);
2010 pmap = PCPU_GET(curpmap);
2011 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2014 pte = pte_find(mmu, pm, va);
2015 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2021 /* Create a mapping in the active pmap. */
2023 m = PHYS_TO_VM_PAGE(pa);
2025 pte_enter(mmu, pmap, m, addr,
2026 PTE_SR | PTE_VALID | PTE_UR);
2027 __syncicache((void *)addr, PAGE_SIZE);
2028 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2031 __syncicache((void *)va, PAGE_SIZE);
2036 rw_wunlock(&pvh_global_lock);
2040 * Atomically extract and hold the physical page with the given
2041 * pmap and virtual address pair if that mapping permits the given
2045 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2057 pte = pte_find(mmu, pmap, va);
2058 if ((pte != NULL) && PTE_ISVALID(pte)) {
2059 if (pmap == kernel_pmap)
2064 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2065 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2067 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2078 * Initialize a vm_page's machine-dependent fields.
2081 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2084 TAILQ_INIT(&m->md.pv_list);
2088 * mmu_booke_zero_page_area zeros the specified hardware page by
2089 * mapping it into virtual memory and using bzero to clear
2092 * off and size must reside within a single page.
2095 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2099 /* XXX KASSERT off and size are within a single page? */
2101 mtx_lock(&zero_page_mutex);
2104 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2105 bzero((caddr_t)va + off, size);
2106 mmu_booke_kremove(mmu, va);
2108 mtx_unlock(&zero_page_mutex);
2112 * mmu_booke_zero_page zeros the specified hardware page.
2115 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2118 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2122 * mmu_booke_copy_page copies the specified (machine independent) page by
2123 * mapping the page into virtual memory and using memcopy to copy the page,
2124 * one machine dependent page at a time.
2127 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2129 vm_offset_t sva, dva;
2131 sva = copy_page_src_va;
2132 dva = copy_page_dst_va;
2134 mtx_lock(©_page_mutex);
2135 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2136 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2137 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2138 mmu_booke_kremove(mmu, dva);
2139 mmu_booke_kremove(mmu, sva);
2140 mtx_unlock(©_page_mutex);
2144 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2145 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2148 vm_offset_t a_pg_offset, b_pg_offset;
2151 mtx_lock(©_page_mutex);
2152 while (xfersize > 0) {
2153 a_pg_offset = a_offset & PAGE_MASK;
2154 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2155 mmu_booke_kenter(mmu, copy_page_src_va,
2156 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2157 a_cp = (char *)copy_page_src_va + a_pg_offset;
2158 b_pg_offset = b_offset & PAGE_MASK;
2159 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2160 mmu_booke_kenter(mmu, copy_page_dst_va,
2161 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2162 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2163 bcopy(a_cp, b_cp, cnt);
2164 mmu_booke_kremove(mmu, copy_page_dst_va);
2165 mmu_booke_kremove(mmu, copy_page_src_va);
2170 mtx_unlock(©_page_mutex);
2174 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2175 * into virtual memory and using bzero to clear its contents. This is intended
2176 * to be called from the vm_pagezero process only and outside of Giant. No
2180 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2184 va = zero_page_idle_va;
2185 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2186 bzero((caddr_t)va, PAGE_SIZE);
2187 mmu_booke_kremove(mmu, va);
2191 * Return whether or not the specified physical page was modified
2192 * in any of physical maps.
2195 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2201 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2202 ("mmu_booke_is_modified: page %p is not managed", m));
2206 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2207 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2208 * is clear, no PTEs can be modified.
2210 VM_OBJECT_ASSERT_WLOCKED(m->object);
2211 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2213 rw_wlock(&pvh_global_lock);
2214 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2215 PMAP_LOCK(pv->pv_pmap);
2216 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2218 if (PTE_ISMODIFIED(pte))
2221 PMAP_UNLOCK(pv->pv_pmap);
2225 rw_wunlock(&pvh_global_lock);
2230 * Return whether or not the specified virtual address is eligible
2234 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2241 * Return whether or not the specified physical page was referenced
2242 * in any physical maps.
2245 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2251 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2252 ("mmu_booke_is_referenced: page %p is not managed", m));
2254 rw_wlock(&pvh_global_lock);
2255 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2256 PMAP_LOCK(pv->pv_pmap);
2257 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2259 if (PTE_ISREFERENCED(pte))
2262 PMAP_UNLOCK(pv->pv_pmap);
2266 rw_wunlock(&pvh_global_lock);
2271 * Clear the modify bits on the specified physical page.
2274 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2279 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2280 ("mmu_booke_clear_modify: page %p is not managed", m));
2281 VM_OBJECT_ASSERT_WLOCKED(m->object);
2282 KASSERT(!vm_page_xbusied(m),
2283 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2286 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2287 * If the object containing the page is locked and the page is not
2288 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2290 if ((m->aflags & PGA_WRITEABLE) == 0)
2292 rw_wlock(&pvh_global_lock);
2293 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2294 PMAP_LOCK(pv->pv_pmap);
2295 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2297 mtx_lock_spin(&tlbivax_mutex);
2300 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2301 tlb0_flush_entry(pv->pv_va);
2302 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2307 mtx_unlock_spin(&tlbivax_mutex);
2309 PMAP_UNLOCK(pv->pv_pmap);
2311 rw_wunlock(&pvh_global_lock);
2315 * Return a count of reference bits for a page, clearing those bits.
2316 * It is not necessary for every reference bit to be cleared, but it
2317 * is necessary that 0 only be returned when there are truly no
2318 * reference bits set.
2320 * XXX: The exact number of bits to check and clear is a matter that
2321 * should be tested and standardized at some point in the future for
2322 * optimal aging of shared pages.
2325 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2331 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2332 ("mmu_booke_ts_referenced: page %p is not managed", m));
2334 rw_wlock(&pvh_global_lock);
2335 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2336 PMAP_LOCK(pv->pv_pmap);
2337 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2339 if (PTE_ISREFERENCED(pte)) {
2340 mtx_lock_spin(&tlbivax_mutex);
2343 tlb0_flush_entry(pv->pv_va);
2344 pte->flags &= ~PTE_REFERENCED;
2347 mtx_unlock_spin(&tlbivax_mutex);
2350 PMAP_UNLOCK(pv->pv_pmap);
2355 PMAP_UNLOCK(pv->pv_pmap);
2357 rw_wunlock(&pvh_global_lock);
2362 * Clear the reference bit on the specified physical page.
2365 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m)
2370 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2371 ("mmu_booke_clear_reference: page %p is not managed", m));
2372 rw_wlock(&pvh_global_lock);
2373 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2374 PMAP_LOCK(pv->pv_pmap);
2375 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2377 if (PTE_ISREFERENCED(pte)) {
2378 mtx_lock_spin(&tlbivax_mutex);
2381 tlb0_flush_entry(pv->pv_va);
2382 pte->flags &= ~PTE_REFERENCED;
2385 mtx_unlock_spin(&tlbivax_mutex);
2388 PMAP_UNLOCK(pv->pv_pmap);
2390 rw_wunlock(&pvh_global_lock);
2394 * Change wiring attribute for a map/virtual-address pair.
2397 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2402 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2404 if (!PTE_ISWIRED(pte)) {
2405 pte->flags |= PTE_WIRED;
2406 pmap->pm_stats.wired_count++;
2409 if (PTE_ISWIRED(pte)) {
2410 pte->flags &= ~PTE_WIRED;
2411 pmap->pm_stats.wired_count--;
2419 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2420 * page. This count may be changed upwards or downwards in the future; it is
2421 * only necessary that true be returned for a small subset of pmaps for proper
2425 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2431 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2432 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2435 rw_wlock(&pvh_global_lock);
2436 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2437 if (pv->pv_pmap == pmap) {
2444 rw_wunlock(&pvh_global_lock);
2449 * Return the number of managed mappings to the given physical page that are
2453 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2459 if ((m->oflags & VPO_UNMANAGED) != 0)
2461 rw_wlock(&pvh_global_lock);
2462 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2463 PMAP_LOCK(pv->pv_pmap);
2464 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2465 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2467 PMAP_UNLOCK(pv->pv_pmap);
2469 rw_wunlock(&pvh_global_lock);
2474 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2480 * This currently does not work for entries that
2481 * overlap TLB1 entries.
2483 for (i = 0; i < tlb1_idx; i ++) {
2484 if (tlb1_iomapped(i, pa, size, &va) == 0)
2492 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2499 /* Raw physical memory dumps don't have a virtual address. */
2500 if (md->md_vaddr == ~0UL) {
2501 /* We always map a 256MB page at 256M. */
2502 gran = 256 * 1024 * 1024;
2503 pa = md->md_paddr + ofs;
2504 ppa = pa & ~(gran - 1);
2507 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2508 if (*sz > (gran - ofs))
2513 /* Minidumps are based on virtual memory addresses. */
2514 va = md->md_vaddr + ofs;
2515 if (va >= kernstart + kernsize) {
2516 gran = PAGE_SIZE - (va & PAGE_MASK);
2524 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2528 /* Raw physical memory dumps don't have a virtual address. */
2529 if (md->md_vaddr == ~0UL) {
2531 tlb1[tlb1_idx].mas1 = 0;
2532 tlb1[tlb1_idx].mas2 = 0;
2533 tlb1[tlb1_idx].mas3 = 0;
2534 tlb1_write_entry(tlb1_idx);
2538 /* Minidumps are based on virtual memory addresses. */
2539 /* Nothing to do... */
2543 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2545 static struct pmap_md md;
2549 if (dumpsys_minidump) {
2550 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2552 /* 1st: kernel .data and .bss. */
2554 md.md_vaddr = trunc_page((uintptr_t)_etext);
2555 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2558 switch (prev->md_index) {
2560 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2562 md.md_vaddr = data_start;
2563 md.md_size = data_end - data_start;
2566 /* 3rd: kernel VM. */
2567 va = prev->md_vaddr + prev->md_size;
2568 /* Find start of next chunk (from va). */
2569 while (va < virtual_end) {
2570 /* Don't dump the buffer cache. */
2571 if (va >= kmi.buffer_sva &&
2572 va < kmi.buffer_eva) {
2573 va = kmi.buffer_eva;
2576 pte = pte_find(mmu, kernel_pmap, va);
2577 if (pte != NULL && PTE_ISVALID(pte))
2581 if (va < virtual_end) {
2584 /* Find last page in chunk. */
2585 while (va < virtual_end) {
2586 /* Don't run into the buffer cache. */
2587 if (va == kmi.buffer_sva)
2589 pte = pte_find(mmu, kernel_pmap, va);
2590 if (pte == NULL || !PTE_ISVALID(pte))
2594 md.md_size = va - md.md_vaddr;
2602 } else { /* minidumps */
2603 mem_regions(&physmem_regions, &physmem_regions_sz,
2604 &availmem_regions, &availmem_regions_sz);
2607 /* first physical chunk. */
2608 md.md_paddr = physmem_regions[0].mr_start;
2609 md.md_size = physmem_regions[0].mr_size;
2612 } else if (md.md_index < physmem_regions_sz) {
2613 md.md_paddr = physmem_regions[md.md_index].mr_start;
2614 md.md_size = physmem_regions[md.md_index].mr_size;
2618 /* There's no next physical chunk. */
2627 * Map a set of physical memory pages into the kernel virtual address space.
2628 * Return a pointer to where it is mapped. This routine is intended to be used
2629 * for mapping device memory, NOT real memory.
2632 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2639 * CCSR is premapped. Note that (pa + size - 1) is there to make sure
2640 * we don't wrap around. Devices on the local bus typically extend all
2641 * the way up to and including 0xffffffff. In that case (pa + size)
2642 * would be 0. This creates a false positive (i.e. we think it's
2643 * within the CCSR) and not create a mapping.
2645 if (pa >= ccsrbar_pa && (pa + size - 1) < (ccsrbar_pa + CCSRBAR_SIZE)) {
2646 va = CCSRBAR_VA + (pa - ccsrbar_pa);
2647 return ((void *)va);
2650 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa);
2654 sz = 1 << (ilog2(size) & ~1);
2656 printf("Wiring VA=%x to PA=%x (size=%x), "
2657 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2658 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO);
2668 * 'Unmap' a range mapped by mmu_booke_mapdev().
2671 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2673 vm_offset_t base, offset;
2676 * Unmap only if this is inside kernel virtual space.
2678 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2679 base = trunc_page(va);
2680 offset = va & PAGE_MASK;
2681 size = roundup(offset + size, PAGE_SIZE);
2682 kva_free(base, size);
2687 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2688 * specified pmap. This eliminates the blast of soft faults on process startup
2689 * and immediately after an mmap.
2692 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2693 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2696 VM_OBJECT_ASSERT_WLOCKED(object);
2697 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2698 ("mmu_booke_object_init_pt: non-device object"));
2702 * Perform the pmap work for mincore.
2705 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2706 vm_paddr_t *locked_pa)
2713 /**************************************************************************/
2715 /**************************************************************************/
2718 * Allocate a TID. If necessary, steal one from someone else.
2719 * The new TID is flushed from the TLB before returning.
2722 tid_alloc(pmap_t pmap)
2727 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2729 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2731 thiscpu = PCPU_GET(cpuid);
2733 tid = PCPU_GET(tid_next);
2736 PCPU_SET(tid_next, tid + 1);
2738 /* If we are stealing TID then clear the relevant pmap's field */
2739 if (tidbusy[thiscpu][tid] != NULL) {
2741 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2743 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2745 /* Flush all entries from TLB0 matching this TID. */
2749 tidbusy[thiscpu][tid] = pmap;
2750 pmap->pm_tid[thiscpu] = tid;
2751 __asm __volatile("msync; isync");
2753 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2754 PCPU_GET(tid_next));
2759 /**************************************************************************/
2761 /**************************************************************************/
2764 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2774 if (mas1 & MAS1_VALID)
2779 if (mas1 & MAS1_IPROT)
2784 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2785 tid = MAS1_GETTID(mas1);
2787 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2790 size = tsize2size(tsize);
2792 debugf("%3d: (%s) [AS=%d] "
2793 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2794 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2795 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2798 /* Convert TLB0 va and way number to tlb0[] table index. */
2799 static inline unsigned int
2800 tlb0_tableidx(vm_offset_t va, unsigned int way)
2804 idx = (way * TLB0_ENTRIES_PER_WAY);
2805 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2810 * Invalidate TLB0 entry.
2813 tlb0_flush_entry(vm_offset_t va)
2816 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2818 mtx_assert(&tlbivax_mutex, MA_OWNED);
2820 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2821 __asm __volatile("isync; msync");
2822 __asm __volatile("tlbsync; msync");
2824 CTR1(KTR_PMAP, "%s: e", __func__);
2827 /* Print out contents of the MAS registers for each TLB0 entry */
2829 tlb0_print_tlbentries(void)
2831 uint32_t mas0, mas1, mas2, mas3, mas7;
2832 int entryidx, way, idx;
2834 debugf("TLB0 entries:\n");
2835 for (way = 0; way < TLB0_WAYS; way ++)
2836 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2838 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2839 mtspr(SPR_MAS0, mas0);
2840 __asm __volatile("isync");
2842 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2843 mtspr(SPR_MAS2, mas2);
2845 __asm __volatile("isync; tlbre");
2847 mas1 = mfspr(SPR_MAS1);
2848 mas2 = mfspr(SPR_MAS2);
2849 mas3 = mfspr(SPR_MAS3);
2850 mas7 = mfspr(SPR_MAS7);
2852 idx = tlb0_tableidx(mas2, way);
2853 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2857 /**************************************************************************/
2859 /**************************************************************************/
2862 * TLB1 mapping notes:
2865 * TLB1[1] Kernel text and data.
2866 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI
2867 * windows, other devices mappings.
2871 * Write given entry to TLB1 hardware.
2872 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2875 tlb1_write_entry(unsigned int idx)
2877 uint32_t mas0, mas7;
2879 //debugf("tlb1_write_entry: s\n");
2881 /* Clear high order RPN bits */
2885 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2886 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2888 mtspr(SPR_MAS0, mas0);
2889 __asm __volatile("isync");
2890 mtspr(SPR_MAS1, tlb1[idx].mas1);
2891 __asm __volatile("isync");
2892 mtspr(SPR_MAS2, tlb1[idx].mas2);
2893 __asm __volatile("isync");
2894 mtspr(SPR_MAS3, tlb1[idx].mas3);
2895 __asm __volatile("isync");
2896 mtspr(SPR_MAS7, mas7);
2897 __asm __volatile("isync; tlbwe; isync; msync");
2899 //debugf("tlb1_write_entry: e\n");
2903 * Return the largest uint value log such that 2^log <= num.
2906 ilog2(unsigned int num)
2910 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2915 * Convert TLB TSIZE value to mapped region size.
2918 tsize2size(unsigned int tsize)
2923 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2926 return ((1 << (2 * tsize)) * 1024);
2930 * Convert region size (must be power of 4) to TLB TSIZE value.
2933 size2tsize(vm_size_t size)
2936 return (ilog2(size) / 2 - 5);
2940 * Register permanent kernel mapping in TLB1.
2942 * Entries are created starting from index 0 (current free entry is
2943 * kept in tlb1_idx) and are not supposed to be invalidated.
2946 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2952 if (tlb1_idx >= TLB1_ENTRIES) {
2953 printf("tlb1_set_entry: TLB1 full!\n");
2957 /* Convert size to TSIZE */
2958 tsize = size2tsize(size);
2960 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2961 /* XXX TS is hard coded to 0 for now as we only use single address space */
2962 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2964 /* XXX LOCK tlb1[] */
2966 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2967 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2968 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags;
2970 /* Set supervisor RWX permission bits */
2971 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2973 tlb1_write_entry(tlb1_idx++);
2975 /* XXX UNLOCK tlb1[] */
2978 * XXX in general TLB1 updates should be propagated between CPUs,
2979 * since current design assumes to have the same TLB1 set-up on all
2986 * Map in contiguous RAM region into the TLB1 using maximum of
2987 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
2989 * If necessary round up last entry size and return total size
2990 * used by all allocated entries.
2993 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
2995 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
2996 vm_size_t mapped, pgsz, base, mask;
2999 /* Round up to the next 1M */
3000 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
3005 pgsz = 64*1024*1024;
3006 while (mapped < size) {
3007 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3008 while (pgsz > (size - mapped))
3014 /* We under-map. Correct for this. */
3015 if (mapped < size) {
3016 while (pgs[idx - 1] == pgsz) {
3020 /* XXX We may increase beyond out starting point. */
3029 /* Align address to the boundary */
3031 va = (va + mask) & ~mask;
3032 pa = (pa + mask) & ~mask;
3035 for (idx = 0; idx < nents; idx++) {
3037 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3038 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3043 mapped = (va - base);
3044 debugf("mapped size 0x%08x (wasted space 0x%08x)\n",
3045 mapped, mapped - size);
3050 * TLB1 initialization routine, to be called after the very first
3051 * assembler level setup done in locore.S.
3054 tlb1_init(vm_offset_t ccsrbar)
3056 uint32_t mas0, mas1, mas3;
3060 ccsrbar_pa = ccsrbar;
3062 if (bootinfo != NULL && bootinfo[0] != 1) {
3063 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3067 /* The first entry/entries are used to map the kernel. */
3068 for (i = 0; i < tlb1_idx; i++) {
3069 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3070 mtspr(SPR_MAS0, mas0);
3071 __asm __volatile("isync; tlbre");
3073 mas1 = mfspr(SPR_MAS1);
3074 if ((mas1 & MAS1_VALID) == 0)
3077 mas3 = mfspr(SPR_MAS3);
3079 tlb1[i].mas1 = mas1;
3080 tlb1[i].mas2 = mfspr(SPR_MAS2);
3081 tlb1[i].mas3 = mas3;
3084 kernload = mas3 & MAS3_RPN;
3086 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3087 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
3090 /* Map in CCSRBAR. */
3091 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
3094 bp_ntlb1s = tlb1_idx;
3097 /* Purge the remaining entries */
3098 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3099 tlb1_write_entry(i);
3101 /* Setup TLB miss defaults */
3102 set_mas4_defaults();
3106 * Setup MAS4 defaults.
3107 * These values are loaded to MAS0-2 on a TLB miss.
3110 set_mas4_defaults(void)
3114 /* Defaults: TLB0, PID0, TSIZED=4K */
3115 mas4 = MAS4_TLBSELD0;
3116 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3120 mtspr(SPR_MAS4, mas4);
3121 __asm __volatile("isync");
3125 * Print out contents of the MAS registers for each TLB1 entry
3128 tlb1_print_tlbentries(void)
3130 uint32_t mas0, mas1, mas2, mas3, mas7;
3133 debugf("TLB1 entries:\n");
3134 for (i = 0; i < TLB1_ENTRIES; i++) {
3136 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3137 mtspr(SPR_MAS0, mas0);
3139 __asm __volatile("isync; tlbre");
3141 mas1 = mfspr(SPR_MAS1);
3142 mas2 = mfspr(SPR_MAS2);
3143 mas3 = mfspr(SPR_MAS3);
3144 mas7 = mfspr(SPR_MAS7);
3146 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3151 * Print out contents of the in-ram tlb1 table.
3154 tlb1_print_entries(void)
3158 debugf("tlb1[] table entries:\n");
3159 for (i = 0; i < TLB1_ENTRIES; i++)
3160 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3164 * Return 0 if the physical IO range is encompassed by one of the
3165 * the TLB1 entries, otherwise return related error code.
3168 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3171 vm_paddr_t pa_start;
3173 unsigned int entry_tsize;
3174 vm_size_t entry_size;
3176 *va = (vm_offset_t)NULL;
3178 /* Skip invalid entries */
3179 if (!(tlb1[i].mas1 & MAS1_VALID))
3183 * The entry must be cache-inhibited, guarded, and r/w
3184 * so it can function as an i/o page
3186 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3187 if (prot != (MAS2_I | MAS2_G))
3190 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3191 if (prot != (MAS3_SR | MAS3_SW))
3194 /* The address should be within the entry range. */
3195 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3196 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3198 entry_size = tsize2size(entry_tsize);
3199 pa_start = tlb1[i].mas3 & MAS3_RPN;
3200 pa_end = pa_start + entry_size - 1;
3202 if ((pa < pa_start) || ((pa + size) > pa_end))
3205 /* Return virtual address of this mapping. */
3206 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);