2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_kern.h>
104 #include <vm/vm_pageout.h>
105 #include <vm/vm_extern.h>
106 #include <vm/vm_object.h>
107 #include <vm/vm_param.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
114 #include <machine/_inttypes.h>
115 #include <machine/cpu.h>
116 #include <machine/pcb.h>
117 #include <machine/platform.h>
119 #include <machine/tlb.h>
120 #include <machine/spr.h>
121 #include <machine/md_var.h>
122 #include <machine/mmuvar.h>
123 #include <machine/pmap.h>
124 #include <machine/pte.h>
130 #define SPARSE_MAPDEV
132 #define debugf(fmt, args...) printf(fmt, ##args)
134 #define debugf(fmt, args...)
138 #define PRI0ptrX "016lx"
140 #define PRI0ptrX "08x"
143 #define TODO panic("%s: not implemented", __func__);
145 extern unsigned char _etext[];
146 extern unsigned char _end[];
148 extern uint32_t *bootinfo;
151 vm_offset_t kernstart;
154 /* Message buffer and tables. */
155 static vm_offset_t data_start;
156 static vm_size_t data_end;
158 /* Phys/avail memory regions. */
159 static struct mem_region *availmem_regions;
160 static int availmem_regions_sz;
161 static struct mem_region *physmem_regions;
162 static int physmem_regions_sz;
164 #ifndef __powerpc64__
165 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
166 static vm_offset_t zero_page_va;
167 static struct mtx zero_page_mutex;
169 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
170 static vm_offset_t copy_page_src_va;
171 static vm_offset_t copy_page_dst_va;
172 static struct mtx copy_page_mutex;
175 static struct mtx tlbivax_mutex;
177 /**************************************************************************/
179 /**************************************************************************/
181 static int mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
182 vm_prot_t, u_int flags, int8_t psind);
184 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
185 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
187 unsigned int kernel_pdirs;
189 static uma_zone_t ptbl_root_zone;
192 * If user pmap is processed with mmu_booke_remove and the resident count
193 * drops to 0, there are no more pages to remove, so we need not continue.
195 #define PMAP_REMOVE_DONE(pmap) \
196 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
198 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
199 extern int elf32_nxstack;
202 /**************************************************************************/
203 /* TLB and TID handling */
204 /**************************************************************************/
206 /* Translation ID busy table */
207 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
210 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
211 * core revisions and should be read from h/w registers during early config.
213 uint32_t tlb0_entries;
215 uint32_t tlb0_entries_per_way;
216 uint32_t tlb1_entries;
218 #define TLB0_ENTRIES (tlb0_entries)
219 #define TLB0_WAYS (tlb0_ways)
220 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
222 #define TLB1_ENTRIES (tlb1_entries)
224 static vm_offset_t tlb1_map_base = (vm_offset_t)VM_MAXUSER_ADDRESS + PAGE_SIZE;
226 static tlbtid_t tid_alloc(struct pmap *);
227 static void tid_flush(tlbtid_t tid);
231 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
233 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
237 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
238 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
239 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
240 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
242 static vm_size_t tsize2size(unsigned int);
243 static unsigned int size2tsize(vm_size_t);
244 static unsigned long ilog2(unsigned long);
246 static void set_mas4_defaults(void);
248 static inline void tlb0_flush_entry(vm_offset_t);
249 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
251 /**************************************************************************/
252 /* Page table management */
253 /**************************************************************************/
255 static struct rwlock_padalign pvh_global_lock;
257 /* Data for the pv entry allocation mechanism */
258 static uma_zone_t pvzone;
259 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
261 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
263 #ifndef PMAP_SHPGPERPROC
264 #define PMAP_SHPGPERPROC 200
268 #define PMAP_ROOT_SIZE (sizeof(pte_t***) * PP2D_NENTRIES)
269 static pte_t *ptbl_alloc(mmu_t, pmap_t, pte_t **,
270 unsigned int, boolean_t);
271 static void ptbl_free(mmu_t, pmap_t, pte_t **, unsigned int, vm_page_t);
272 static void ptbl_hold(mmu_t, pmap_t, pte_t **, unsigned int);
273 static int ptbl_unhold(mmu_t, pmap_t, vm_offset_t);
275 #define PMAP_ROOT_SIZE (sizeof(pte_t**) * PDIR_NENTRIES)
276 static void ptbl_init(void);
277 static struct ptbl_buf *ptbl_buf_alloc(void);
278 static void ptbl_buf_free(struct ptbl_buf *);
279 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
281 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int, boolean_t);
282 static void ptbl_free(mmu_t, pmap_t, unsigned int);
283 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
284 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
287 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
288 static int pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
289 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
290 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
291 static void kernel_pte_alloc(vm_offset_t, vm_offset_t, vm_offset_t);
293 static pv_entry_t pv_alloc(void);
294 static void pv_free(pv_entry_t);
295 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
296 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
298 static void booke_pmap_init_qpages(void);
301 TAILQ_ENTRY(ptbl_buf) link; /* list link */
302 vm_offset_t kva; /* va of mapping */
305 #ifndef __powerpc64__
306 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
307 #define PTBL_BUFS (128 * 16)
309 /* ptbl free list and a lock used for access synchronization. */
310 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
311 static struct mtx ptbl_buf_freelist_lock;
313 /* Base address of kva space allocated fot ptbl bufs. */
314 static vm_offset_t ptbl_buf_pool_vabase;
316 /* Pointer to ptbl_buf structures. */
317 static struct ptbl_buf *ptbl_bufs;
321 extern tlb_entry_t __boot_tlb1[];
322 void pmap_bootstrap_ap(volatile uint32_t *);
326 * Kernel MMU interface
328 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
329 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
330 vm_size_t, vm_offset_t);
331 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
332 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
333 vm_offset_t, vm_page_t *, vm_offset_t, int);
334 static int mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
335 vm_prot_t, u_int flags, int8_t psind);
336 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
337 vm_page_t, vm_prot_t);
338 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
340 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
341 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
343 static void mmu_booke_init(mmu_t);
344 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
345 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
346 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
347 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
348 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
350 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
352 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
353 vm_object_t, vm_pindex_t, vm_size_t);
354 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
355 static void mmu_booke_page_init(mmu_t, vm_page_t);
356 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
357 static void mmu_booke_pinit(mmu_t, pmap_t);
358 static void mmu_booke_pinit0(mmu_t, pmap_t);
359 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
361 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
362 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
363 static void mmu_booke_release(mmu_t, pmap_t);
364 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
365 static void mmu_booke_remove_all(mmu_t, vm_page_t);
366 static void mmu_booke_remove_write(mmu_t, vm_page_t);
367 static void mmu_booke_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
368 static void mmu_booke_zero_page(mmu_t, vm_page_t);
369 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
370 static void mmu_booke_activate(mmu_t, struct thread *);
371 static void mmu_booke_deactivate(mmu_t, struct thread *);
372 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
373 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
374 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
375 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
376 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
377 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
378 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
379 static void mmu_booke_kremove(mmu_t, vm_offset_t);
380 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
381 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
383 static void mmu_booke_dumpsys_map(mmu_t, vm_paddr_t pa, size_t,
385 static void mmu_booke_dumpsys_unmap(mmu_t, vm_paddr_t pa, size_t,
387 static void mmu_booke_scan_init(mmu_t);
388 static vm_offset_t mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m);
389 static void mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr);
390 static int mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr,
391 vm_size_t sz, vm_memattr_t mode);
392 static int mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm,
393 volatile const void *uaddr, void **kaddr, size_t ulen, size_t *klen);
394 static int mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr,
395 int *is_user, vm_offset_t *decoded_addr);
396 static void mmu_booke_page_array_startup(mmu_t , long);
399 static mmu_method_t mmu_booke_methods[] = {
400 /* pmap dispatcher interface */
401 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
402 MMUMETHOD(mmu_copy, mmu_booke_copy),
403 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
404 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
405 MMUMETHOD(mmu_enter, mmu_booke_enter),
406 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
407 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
408 MMUMETHOD(mmu_extract, mmu_booke_extract),
409 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
410 MMUMETHOD(mmu_init, mmu_booke_init),
411 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
412 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
413 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
414 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
415 MMUMETHOD(mmu_map, mmu_booke_map),
416 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
417 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
418 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
419 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
420 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
421 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
422 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
423 MMUMETHOD(mmu_protect, mmu_booke_protect),
424 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
425 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
426 MMUMETHOD(mmu_release, mmu_booke_release),
427 MMUMETHOD(mmu_remove, mmu_booke_remove),
428 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
429 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
430 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
431 MMUMETHOD(mmu_unwire, mmu_booke_unwire),
432 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
433 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
434 MMUMETHOD(mmu_activate, mmu_booke_activate),
435 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
436 MMUMETHOD(mmu_quick_enter_page, mmu_booke_quick_enter_page),
437 MMUMETHOD(mmu_quick_remove_page, mmu_booke_quick_remove_page),
438 MMUMETHOD(mmu_page_array_startup, mmu_booke_page_array_startup),
440 /* Internal interfaces */
441 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
442 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
443 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
444 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
445 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
446 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
447 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
448 MMUMETHOD(mmu_kremove, mmu_booke_kremove),
449 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
450 MMUMETHOD(mmu_change_attr, mmu_booke_change_attr),
451 MMUMETHOD(mmu_map_user_ptr, mmu_booke_map_user_ptr),
452 MMUMETHOD(mmu_decode_kernel_ptr, mmu_booke_decode_kernel_ptr),
454 /* dumpsys() support */
455 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
456 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
457 MMUMETHOD(mmu_scan_init, mmu_booke_scan_init),
462 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
464 static __inline uint32_t
465 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
470 if (ma != VM_MEMATTR_DEFAULT) {
472 case VM_MEMATTR_UNCACHEABLE:
473 return (MAS2_I | MAS2_G);
474 case VM_MEMATTR_WRITE_COMBINING:
475 case VM_MEMATTR_WRITE_BACK:
476 case VM_MEMATTR_PREFETCHABLE:
478 case VM_MEMATTR_WRITE_THROUGH:
479 return (MAS2_W | MAS2_M);
480 case VM_MEMATTR_CACHEABLE:
486 * Assume the page is cache inhibited and access is guarded unless
487 * it's in our available memory array.
489 attrib = _TLB_ENTRY_IO;
490 for (i = 0; i < physmem_regions_sz; i++) {
491 if ((pa >= physmem_regions[i].mr_start) &&
492 (pa < (physmem_regions[i].mr_start +
493 physmem_regions[i].mr_size))) {
494 attrib = _TLB_ENTRY_MEM;
511 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
514 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
515 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
517 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
518 ("tlb_miss_lock: tried to lock self"));
520 tlb_lock(pc->pc_booke.tlb_lock);
522 CTR1(KTR_PMAP, "%s: locked", __func__);
529 tlb_miss_unlock(void)
537 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
539 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
540 __func__, pc->pc_cpuid);
542 tlb_unlock(pc->pc_booke.tlb_lock);
544 CTR1(KTR_PMAP, "%s: unlocked", __func__);
550 /* Return number of entries in TLB0. */
552 tlb0_get_tlbconf(void)
556 tlb0_cfg = mfspr(SPR_TLB0CFG);
557 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
558 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
559 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
562 /* Return number of entries in TLB1. */
564 tlb1_get_tlbconf(void)
568 tlb1_cfg = mfspr(SPR_TLB1CFG);
569 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
572 /**************************************************************************/
573 /* Page table related */
574 /**************************************************************************/
577 /* Initialize pool of kva ptbl buffers. */
583 /* Get a pointer to a PTE in a page table. */
584 static __inline pte_t *
585 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
590 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
592 pdir = pmap->pm_pp2d[PP2D_IDX(va)];
595 ptbl = pdir[PDIR_IDX(va)];
596 return ((ptbl != NULL) ? &ptbl[PTBL_IDX(va)] : NULL);
600 * allocate a page of pointers to page directories, do not preallocate the
604 pdir_alloc(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, bool nosleep)
610 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
611 while ((m = vm_page_alloc(NULL, pp2d_idx, req)) == NULL) {
620 /* Zero whole ptbl. */
621 pdir = (pte_t **)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
622 mmu_booke_zero_page(mmu, m);
627 /* Free pdir pages and invalidate pdir entry. */
629 pdir_free(mmu_t mmu, pmap_t pmap, unsigned int pp2d_idx, vm_page_t m)
633 pdir = pmap->pm_pp2d[pp2d_idx];
635 KASSERT((pdir != NULL), ("pdir_free: null pdir"));
637 pmap->pm_pp2d[pp2d_idx] = NULL;
640 vm_page_free_zero(m);
644 * Decrement pdir pages hold count and attempt to free pdir pages. Called
645 * when removing directory entry from pdir.
647 * Return 1 if pdir pages were freed.
650 pdir_unhold(mmu_t mmu, pmap_t pmap, u_int pp2d_idx)
656 KASSERT((pmap != kernel_pmap),
657 ("pdir_unhold: unholding kernel pdir!"));
659 pdir = pmap->pm_pp2d[pp2d_idx];
661 /* decrement hold count */
662 pa = DMAP_TO_PHYS((vm_offset_t) pdir);
663 m = PHYS_TO_VM_PAGE(pa);
666 * Free pdir page if there are no dir entries in this pdir.
669 if (m->ref_count == 0) {
670 pdir_free(mmu, pmap, pp2d_idx, m);
677 * Increment hold count for pdir pages. This routine is used when new ptlb
678 * entry is being inserted into pdir.
681 pdir_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir)
685 KASSERT((pmap != kernel_pmap),
686 ("pdir_hold: holding kernel pdir!"));
688 KASSERT((pdir != NULL), ("pdir_hold: null pdir"));
690 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pdir));
694 /* Allocate page table. */
696 ptbl_alloc(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx,
703 KASSERT((pdir[pdir_idx] == NULL),
704 ("%s: valid ptbl entry exists!", __func__));
706 req = VM_ALLOC_NOOBJ | VM_ALLOC_WIRED;
707 while ((m = vm_page_alloc(NULL, pdir_idx, req)) == NULL) {
709 rw_wunlock(&pvh_global_lock);
714 rw_wlock(&pvh_global_lock);
718 /* Zero whole ptbl. */
719 ptbl = (pte_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
720 mmu_booke_zero_page(mmu, m);
725 /* Free ptbl pages and invalidate pdir entry. */
727 ptbl_free(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx, vm_page_t m)
731 ptbl = pdir[pdir_idx];
733 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
735 pdir[pdir_idx] = NULL;
738 vm_page_free_zero(m);
742 * Decrement ptbl pages hold count and attempt to free ptbl pages. Called
743 * when removing pte entry from ptbl.
745 * Return 1 if ptbl pages were freed.
748 ptbl_unhold(mmu_t mmu, pmap_t pmap, vm_offset_t va)
756 pp2d_idx = PP2D_IDX(va);
757 pdir_idx = PDIR_IDX(va);
759 KASSERT((pmap != kernel_pmap),
760 ("ptbl_unhold: unholding kernel ptbl!"));
762 pdir = pmap->pm_pp2d[pp2d_idx];
763 ptbl = pdir[pdir_idx];
765 /* decrement hold count */
766 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t) ptbl));
769 * Free ptbl pages if there are no pte entries in this ptbl.
770 * ref_count has the same value for all ptbl pages, so check the
774 if (m->ref_count == 0) {
775 ptbl_free(mmu, pmap, pdir, pdir_idx, m);
776 pdir_unhold(mmu, pmap, pp2d_idx);
783 * Increment hold count for ptbl pages. This routine is used when new pte
784 * entry is being inserted into ptbl.
787 ptbl_hold(mmu_t mmu, pmap_t pmap, pte_t ** pdir, unsigned int pdir_idx)
792 KASSERT((pmap != kernel_pmap),
793 ("ptbl_hold: holding kernel ptbl!"));
795 ptbl = pdir[pdir_idx];
797 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
799 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t) ptbl));
804 /* Initialize pool of kva ptbl buffers. */
810 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
811 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
812 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
813 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
815 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
816 TAILQ_INIT(&ptbl_buf_freelist);
818 for (i = 0; i < PTBL_BUFS; i++) {
820 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
821 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
825 /* Get a ptbl_buf from the freelist. */
826 static struct ptbl_buf *
829 struct ptbl_buf *buf;
831 mtx_lock(&ptbl_buf_freelist_lock);
832 buf = TAILQ_FIRST(&ptbl_buf_freelist);
834 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
835 mtx_unlock(&ptbl_buf_freelist_lock);
837 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
842 /* Return ptbl buff to free pool. */
844 ptbl_buf_free(struct ptbl_buf *buf)
847 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
849 mtx_lock(&ptbl_buf_freelist_lock);
850 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
851 mtx_unlock(&ptbl_buf_freelist_lock);
855 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
858 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
860 struct ptbl_buf *pbuf;
862 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
864 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
866 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
867 if (pbuf->kva == (vm_offset_t)ptbl) {
868 /* Remove from pmap ptbl buf list. */
869 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
871 /* Free corresponding ptbl buf. */
877 /* Allocate page table. */
879 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
881 vm_page_t mtbl[PTBL_PAGES];
883 struct ptbl_buf *pbuf;
888 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
889 (pmap == kernel_pmap), pdir_idx);
891 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
892 ("ptbl_alloc: invalid pdir_idx"));
893 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
894 ("pte_alloc: valid ptbl entry exists!"));
896 pbuf = ptbl_buf_alloc();
898 panic("pte_alloc: couldn't alloc kernel virtual memory");
900 ptbl = (pte_t *)pbuf->kva;
902 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
904 for (i = 0; i < PTBL_PAGES; i++) {
905 pidx = (PTBL_PAGES * pdir_idx) + i;
906 while ((m = vm_page_alloc(NULL, pidx,
907 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
909 rw_wunlock(&pvh_global_lock);
911 ptbl_free_pmap_ptbl(pmap, ptbl);
912 for (j = 0; j < i; j++)
913 vm_page_free(mtbl[j]);
918 rw_wlock(&pvh_global_lock);
924 /* Map allocated pages into kernel_pmap. */
925 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
927 /* Zero whole ptbl. */
928 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
930 /* Add pbuf to the pmap ptbl bufs list. */
931 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
936 /* Free ptbl pages and invalidate pdir entry. */
938 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
946 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
947 (pmap == kernel_pmap), pdir_idx);
949 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
950 ("ptbl_free: invalid pdir_idx"));
952 ptbl = pmap->pm_pdir[pdir_idx];
954 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
956 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
959 * Invalidate the pdir entry as soon as possible, so that other CPUs
960 * don't attempt to look up the page tables we are releasing.
962 mtx_lock_spin(&tlbivax_mutex);
965 pmap->pm_pdir[pdir_idx] = NULL;
968 mtx_unlock_spin(&tlbivax_mutex);
970 for (i = 0; i < PTBL_PAGES; i++) {
971 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
972 pa = pte_vatopa(mmu, kernel_pmap, va);
973 m = PHYS_TO_VM_PAGE(pa);
974 vm_page_free_zero(m);
976 mmu_booke_kremove(mmu, va);
979 ptbl_free_pmap_ptbl(pmap, ptbl);
983 * Decrement ptbl pages hold count and attempt to free ptbl pages.
984 * Called when removing pte entry from ptbl.
986 * Return 1 if ptbl pages were freed.
989 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
996 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
997 (pmap == kernel_pmap), pdir_idx);
999 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1000 ("ptbl_unhold: invalid pdir_idx"));
1001 KASSERT((pmap != kernel_pmap),
1002 ("ptbl_unhold: unholding kernel ptbl!"));
1004 ptbl = pmap->pm_pdir[pdir_idx];
1006 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
1007 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
1008 ("ptbl_unhold: non kva ptbl"));
1010 /* decrement hold count */
1011 for (i = 0; i < PTBL_PAGES; i++) {
1012 pa = pte_vatopa(mmu, kernel_pmap,
1013 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1014 m = PHYS_TO_VM_PAGE(pa);
1019 * Free ptbl pages if there are no pte etries in this ptbl.
1020 * ref_count has the same value for all ptbl pages, so check the last
1023 if (m->ref_count == 0) {
1024 ptbl_free(mmu, pmap, pdir_idx);
1026 //debugf("ptbl_unhold: e (freed ptbl)\n");
1034 * Increment hold count for ptbl pages. This routine is used when a new pte
1035 * entry is being inserted into the ptbl.
1038 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
1045 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
1048 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
1049 ("ptbl_hold: invalid pdir_idx"));
1050 KASSERT((pmap != kernel_pmap),
1051 ("ptbl_hold: holding kernel ptbl!"));
1053 ptbl = pmap->pm_pdir[pdir_idx];
1055 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
1057 for (i = 0; i < PTBL_PAGES; i++) {
1058 pa = pte_vatopa(mmu, kernel_pmap,
1059 (vm_offset_t)ptbl + (i * PAGE_SIZE));
1060 m = PHYS_TO_VM_PAGE(pa);
1066 /* Allocate pv_entry structure. */
1073 if (pv_entry_count > pv_entry_high_water)
1074 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
1075 pv = uma_zalloc(pvzone, M_NOWAIT);
1080 /* Free pv_entry structure. */
1081 static __inline void
1082 pv_free(pv_entry_t pve)
1086 uma_zfree(pvzone, pve);
1090 /* Allocate and initialize pv_entry structure. */
1092 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
1096 //int su = (pmap == kernel_pmap);
1097 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
1098 // (u_int32_t)pmap, va, (u_int32_t)m);
1102 panic("pv_insert: no pv entries!");
1104 pve->pv_pmap = pmap;
1107 /* add to pv_list */
1108 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1109 rw_assert(&pvh_global_lock, RA_WLOCKED);
1111 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
1113 //debugf("pv_insert: e\n");
1116 /* Destroy pv entry. */
1118 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
1122 //int su = (pmap == kernel_pmap);
1123 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
1125 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1126 rw_assert(&pvh_global_lock, RA_WLOCKED);
1129 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
1130 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
1131 /* remove from pv_list */
1132 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
1133 if (TAILQ_EMPTY(&m->md.pv_list))
1134 vm_page_aflag_clear(m, PGA_WRITEABLE);
1136 /* free pv entry struct */
1142 //debugf("pv_remove: e\n");
1145 #ifdef __powerpc64__
1147 * Clean pte entry, try to free page table page if requested.
1149 * Return 1 if ptbl pages were freed, otherwise return 0.
1152 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, u_int8_t flags)
1157 pte = pte_find(mmu, pmap, va);
1158 KASSERT(pte != NULL, ("%s: NULL pte", __func__));
1160 if (!PTE_ISVALID(pte))
1163 /* Get vm_page_t for mapped pte. */
1164 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1166 if (PTE_ISWIRED(pte))
1167 pmap->pm_stats.wired_count--;
1169 /* Handle managed entry. */
1170 if (PTE_ISMANAGED(pte)) {
1172 /* Handle modified pages. */
1173 if (PTE_ISMODIFIED(pte))
1176 /* Referenced pages. */
1177 if (PTE_ISREFERENCED(pte))
1178 vm_page_aflag_set(m, PGA_REFERENCED);
1180 /* Remove pv_entry from pv_list. */
1181 pv_remove(pmap, va, m);
1182 } else if (pmap == kernel_pmap && m && m->md.pv_tracked) {
1183 pv_remove(pmap, va, m);
1184 if (TAILQ_EMPTY(&m->md.pv_list))
1185 m->md.pv_tracked = false;
1187 mtx_lock_spin(&tlbivax_mutex);
1190 tlb0_flush_entry(va);
1194 mtx_unlock_spin(&tlbivax_mutex);
1196 pmap->pm_stats.resident_count--;
1198 if (flags & PTBL_UNHOLD) {
1199 return (ptbl_unhold(mmu, pmap, va));
1205 * Insert PTE for a given page and virtual address.
1208 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1211 unsigned int pp2d_idx = PP2D_IDX(va);
1212 unsigned int pdir_idx = PDIR_IDX(va);
1213 unsigned int ptbl_idx = PTBL_IDX(va);
1214 pte_t *ptbl, *pte, pte_tmp;
1217 /* Get the page directory pointer. */
1218 pdir = pmap->pm_pp2d[pp2d_idx];
1220 pdir = pdir_alloc(mmu, pmap, pp2d_idx, nosleep);
1222 /* Get the page table pointer. */
1223 ptbl = pdir[pdir_idx];
1226 /* Allocate page table pages. */
1227 ptbl = ptbl_alloc(mmu, pmap, pdir, pdir_idx, nosleep);
1229 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1232 pte = &ptbl[ptbl_idx];
1235 * Check if there is valid mapping for requested va, if there
1238 pte = &ptbl[ptbl_idx];
1239 if (PTE_ISVALID(pte)) {
1240 pte_remove(mmu, pmap, va, PTBL_HOLD);
1243 * pte is not used, increment hold count for ptbl
1246 if (pmap != kernel_pmap)
1247 ptbl_hold(mmu, pmap, pdir, pdir_idx);
1251 if (pdir[pdir_idx] == NULL) {
1252 if (pmap != kernel_pmap && pmap->pm_pp2d[pp2d_idx] != NULL)
1253 pdir_hold(mmu, pmap, pdir);
1254 pdir[pdir_idx] = ptbl;
1256 if (pmap->pm_pp2d[pp2d_idx] == NULL)
1257 pmap->pm_pp2d[pp2d_idx] = pdir;
1260 * Insert pv_entry into pv_list for mapped page if part of managed
1263 if ((m->oflags & VPO_UNMANAGED) == 0) {
1264 flags |= PTE_MANAGED;
1266 /* Create and insert pv entry. */
1267 pv_insert(pmap, va, m);
1270 pmap->pm_stats.resident_count++;
1272 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1273 pte_tmp |= (PTE_VALID | flags);
1275 mtx_lock_spin(&tlbivax_mutex);
1278 tlb0_flush_entry(va);
1282 mtx_unlock_spin(&tlbivax_mutex);
1287 /* Return the pa for the given pmap/va. */
1289 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1294 pte = pte_find(mmu, pmap, va);
1295 if ((pte != NULL) && PTE_ISVALID(pte))
1296 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1301 /* allocate pte entries to manage (addr & mask) to (addr & mask) + size */
1303 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1310 /* Initialize kernel pdir */
1311 for (i = 0; i < kernel_pdirs; i++) {
1312 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)] =
1313 (pte_t **)(pdir + (i * PAGE_SIZE * PDIR_PAGES));
1314 for (j = PDIR_IDX(va + (i * PAGE_SIZE * PDIR_NENTRIES * PTBL_NENTRIES));
1315 j < PDIR_NENTRIES; j++) {
1316 kernel_pmap->pm_pp2d[i + PP2D_IDX(va)][j] =
1317 (pte_t *)(pdir + (kernel_pdirs * PAGE_SIZE) +
1318 (((i * PDIR_NENTRIES) + j) * PAGE_SIZE));
1323 * Fill in PTEs covering kernel code and data. They are not required
1324 * for address translation, as this area is covered by static TLB1
1325 * entries, but for pte_vatopa() to work correctly with kernel area
1328 for (va = addr; va < data_end; va += PAGE_SIZE) {
1329 pte = &(kernel_pmap->pm_pp2d[PP2D_IDX(va)][PDIR_IDX(va)][PTBL_IDX(va)]);
1330 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1331 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1332 PTE_VALID | PTE_PS_4KB;
1337 * Clean pte entry, try to free page table page if requested.
1339 * Return 1 if ptbl pages were freed, otherwise return 0.
1342 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
1344 unsigned int pdir_idx = PDIR_IDX(va);
1345 unsigned int ptbl_idx = PTBL_IDX(va);
1350 //int su = (pmap == kernel_pmap);
1351 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
1352 // su, (u_int32_t)pmap, va, flags);
1354 ptbl = pmap->pm_pdir[pdir_idx];
1355 KASSERT(ptbl, ("pte_remove: null ptbl"));
1357 pte = &ptbl[ptbl_idx];
1359 if (pte == NULL || !PTE_ISVALID(pte))
1362 if (PTE_ISWIRED(pte))
1363 pmap->pm_stats.wired_count--;
1365 /* Get vm_page_t for mapped pte. */
1366 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1368 /* Handle managed entry. */
1369 if (PTE_ISMANAGED(pte)) {
1371 if (PTE_ISMODIFIED(pte))
1374 if (PTE_ISREFERENCED(pte))
1375 vm_page_aflag_set(m, PGA_REFERENCED);
1377 pv_remove(pmap, va, m);
1378 } else if (pmap == kernel_pmap && m && m->md.pv_tracked) {
1380 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is
1381 * used. This is needed by the NCSW support code for fast
1382 * VA<->PA translation.
1384 pv_remove(pmap, va, m);
1385 if (TAILQ_EMPTY(&m->md.pv_list))
1386 m->md.pv_tracked = false;
1389 mtx_lock_spin(&tlbivax_mutex);
1392 tlb0_flush_entry(va);
1396 mtx_unlock_spin(&tlbivax_mutex);
1398 pmap->pm_stats.resident_count--;
1400 if (flags & PTBL_UNHOLD) {
1401 //debugf("pte_remove: e (unhold)\n");
1402 return (ptbl_unhold(mmu, pmap, pdir_idx));
1405 //debugf("pte_remove: e\n");
1410 * Insert PTE for a given page and virtual address.
1413 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
1416 unsigned int pdir_idx = PDIR_IDX(va);
1417 unsigned int ptbl_idx = PTBL_IDX(va);
1418 pte_t *ptbl, *pte, pte_tmp;
1420 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
1421 pmap == kernel_pmap, pmap, va);
1423 /* Get the page table pointer. */
1424 ptbl = pmap->pm_pdir[pdir_idx];
1427 /* Allocate page table pages. */
1428 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
1430 KASSERT(nosleep, ("nosleep and NULL ptbl"));
1433 pmap->pm_pdir[pdir_idx] = ptbl;
1434 pte = &ptbl[ptbl_idx];
1437 * Check if there is valid mapping for requested
1438 * va, if there is, remove it.
1440 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
1441 if (PTE_ISVALID(pte)) {
1442 pte_remove(mmu, pmap, va, PTBL_HOLD);
1445 * pte is not used, increment hold count
1448 if (pmap != kernel_pmap)
1449 ptbl_hold(mmu, pmap, pdir_idx);
1454 * Insert pv_entry into pv_list for mapped page if part of managed
1457 if ((m->oflags & VPO_UNMANAGED) == 0) {
1458 flags |= PTE_MANAGED;
1460 /* Create and insert pv entry. */
1461 pv_insert(pmap, va, m);
1464 pmap->pm_stats.resident_count++;
1466 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
1467 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
1469 mtx_lock_spin(&tlbivax_mutex);
1472 tlb0_flush_entry(va);
1476 mtx_unlock_spin(&tlbivax_mutex);
1480 /* Return the pa for the given pmap/va. */
1482 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1487 pte = pte_find(mmu, pmap, va);
1488 if ((pte != NULL) && PTE_ISVALID(pte))
1489 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
1493 /* Get a pointer to a PTE in a page table. */
1495 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1497 unsigned int pdir_idx = PDIR_IDX(va);
1498 unsigned int ptbl_idx = PTBL_IDX(va);
1500 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
1502 if (pmap->pm_pdir[pdir_idx])
1503 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
1508 /* Set up kernel page tables. */
1510 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr, vm_offset_t pdir)
1516 /* Initialize kernel pdir */
1517 for (i = 0; i < kernel_ptbls; i++)
1518 kernel_pmap->pm_pdir[kptbl_min + i] =
1519 (pte_t *)(pdir + (i * PAGE_SIZE * PTBL_PAGES));
1522 * Fill in PTEs covering kernel code and data. They are not required
1523 * for address translation, as this area is covered by static TLB1
1524 * entries, but for pte_vatopa() to work correctly with kernel area
1527 for (va = addr; va < data_end; va += PAGE_SIZE) {
1528 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1529 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
1530 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1531 PTE_VALID | PTE_PS_4KB;
1536 /**************************************************************************/
1538 /**************************************************************************/
1541 * This is called during booke_init, before the system is really initialized.
1544 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1546 vm_paddr_t phys_kernelend;
1547 struct mem_region *mp, *mp1;
1549 vm_paddr_t s, e, sz;
1550 vm_paddr_t physsz, hwphyssz;
1551 u_int phys_avail_count;
1552 vm_size_t kstack0_sz;
1553 vm_offset_t kernel_pdir, kstack0;
1554 vm_paddr_t kstack0_phys;
1556 vm_offset_t kernel_ptbl_root;
1558 debugf("mmu_booke_bootstrap: entered\n");
1560 /* Set interesting system properties */
1561 #ifdef __powerpc64__
1566 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
1570 /* Initialize invalidation mutex */
1571 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1573 /* Read TLB0 size and associativity. */
1577 * Align kernel start and end address (kernel image).
1578 * Note that kernel end does not necessarily relate to kernsize.
1579 * kernsize is the size of the kernel that is actually mapped.
1581 data_start = round_page(kernelend);
1582 data_end = data_start;
1584 /* Allocate the dynamic per-cpu area. */
1585 dpcpu = (void *)data_end;
1586 data_end += DPCPU_SIZE;
1588 /* Allocate space for the message buffer. */
1589 msgbufp = (struct msgbuf *)data_end;
1590 data_end += msgbufsize;
1591 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1592 (uintptr_t)msgbufp, data_end);
1594 data_end = round_page(data_end);
1596 #ifdef __powerpc64__
1597 kernel_ptbl_root = data_end;
1598 data_end += PP2D_NENTRIES * sizeof(pte_t**);
1600 /* Allocate space for ptbl_bufs. */
1601 ptbl_bufs = (struct ptbl_buf *)data_end;
1602 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1603 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1604 (uintptr_t)ptbl_bufs, data_end);
1606 data_end = round_page(data_end);
1607 kernel_ptbl_root = data_end;
1608 data_end += PDIR_NENTRIES * sizeof(pte_t*);
1611 /* Allocate PTE tables for kernel KVA. */
1612 kernel_pdir = data_end;
1613 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS,
1615 #ifdef __powerpc64__
1616 kernel_pdirs = howmany(kernel_ptbls, PDIR_NENTRIES);
1617 data_end += kernel_pdirs * PDIR_PAGES * PAGE_SIZE;
1619 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1620 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1621 debugf(" kernel pdir at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1622 kernel_pdir, data_end);
1624 /* Retrieve phys/avail mem regions */
1625 mem_regions(&physmem_regions, &physmem_regions_sz,
1626 &availmem_regions, &availmem_regions_sz);
1628 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
1629 panic("mmu_booke_bootstrap: phys_avail too small");
1631 data_end = round_page(data_end);
1632 vm_page_array = (vm_page_t)data_end;
1634 * Get a rough idea (upper bound) on the size of the page array. The
1635 * vm_page_array will not handle any more pages than we have in the
1636 * avail_regions array, and most likely much less.
1639 for (mp = availmem_regions; mp->mr_size; mp++) {
1642 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
1643 data_end += round_page(sz * sizeof(struct vm_page));
1645 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
1646 data_end = roundup2(data_end, 1 << 20);
1648 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
1649 debugf(" kernstart: %#zx\n", kernstart);
1650 debugf(" kernsize: %#zx\n", kernsize);
1652 if (data_end - kernstart > kernsize) {
1653 kernsize += tlb1_mapin_region(kernstart + kernsize,
1654 kernload + kernsize, (data_end - kernstart) - kernsize,
1657 data_end = kernstart + kernsize;
1658 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
1661 * Clear the structures - note we can only do it safely after the
1662 * possible additional TLB1 translations are in place (above) so that
1663 * all range up to the currently calculated 'data_end' is covered.
1665 dpcpu_init(dpcpu, 0);
1666 #ifdef __powerpc64__
1667 memset((void *)kernel_pdir, 0,
1668 kernel_pdirs * PDIR_PAGES * PAGE_SIZE +
1669 kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1671 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1672 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1675 /*******************************************************/
1676 /* Set the start and end of kva. */
1677 /*******************************************************/
1678 virtual_avail = round_page(data_end);
1679 virtual_end = VM_MAX_KERNEL_ADDRESS;
1681 #ifndef __powerpc64__
1682 /* Allocate KVA space for page zero/copy operations. */
1683 zero_page_va = virtual_avail;
1684 virtual_avail += PAGE_SIZE;
1685 copy_page_src_va = virtual_avail;
1686 virtual_avail += PAGE_SIZE;
1687 copy_page_dst_va = virtual_avail;
1688 virtual_avail += PAGE_SIZE;
1689 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
1690 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
1691 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
1693 /* Initialize page zero/copy mutexes. */
1694 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1695 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1697 /* Allocate KVA space for ptbl bufs. */
1698 ptbl_buf_pool_vabase = virtual_avail;
1699 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1700 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
1701 ptbl_buf_pool_vabase, virtual_avail);
1704 /* Calculate corresponding physical addresses for the kernel region. */
1705 phys_kernelend = kernload + kernsize;
1706 debugf("kernel image and allocated data:\n");
1707 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
1708 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
1709 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
1712 * Remove kernel physical address range from avail regions list. Page
1713 * align all regions. Non-page aligned memory isn't very interesting
1714 * to us. Also, sort the entries for ascending addresses.
1718 cnt = availmem_regions_sz;
1719 debugf("processing avail regions:\n");
1720 for (mp = availmem_regions; mp->mr_size; mp++) {
1722 e = mp->mr_start + mp->mr_size;
1723 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
1724 /* Check whether this region holds all of the kernel. */
1725 if (s < kernload && e > phys_kernelend) {
1726 availmem_regions[cnt].mr_start = phys_kernelend;
1727 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1730 /* Look whether this regions starts within the kernel. */
1731 if (s >= kernload && s < phys_kernelend) {
1732 if (e <= phys_kernelend)
1736 /* Now look whether this region ends within the kernel. */
1737 if (e > kernload && e <= phys_kernelend) {
1742 /* Now page align the start and size of the region. */
1748 debugf("%09jx-%09jx = %jx\n",
1749 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
1751 /* Check whether some memory is left here. */
1755 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1761 /* Do an insertion sort. */
1762 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1763 if (s < mp1->mr_start)
1766 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1774 availmem_regions_sz = cnt;
1776 /*******************************************************/
1777 /* Steal physical memory for kernel stack from the end */
1778 /* of the first avail region */
1779 /*******************************************************/
1780 kstack0_sz = kstack_pages * PAGE_SIZE;
1781 kstack0_phys = availmem_regions[0].mr_start +
1782 availmem_regions[0].mr_size;
1783 kstack0_phys -= kstack0_sz;
1784 availmem_regions[0].mr_size -= kstack0_sz;
1786 /*******************************************************/
1787 /* Fill in phys_avail table, based on availmem_regions */
1788 /*******************************************************/
1789 phys_avail_count = 0;
1792 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1794 debugf("fill in phys_avail:\n");
1795 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1797 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
1798 (uintmax_t)availmem_regions[i].mr_start,
1799 (uintmax_t)availmem_regions[i].mr_start +
1800 availmem_regions[i].mr_size,
1801 (uintmax_t)availmem_regions[i].mr_size);
1803 if (hwphyssz != 0 &&
1804 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1805 debugf(" hw.physmem adjust\n");
1806 if (physsz < hwphyssz) {
1807 phys_avail[j] = availmem_regions[i].mr_start;
1809 availmem_regions[i].mr_start +
1813 dump_avail[j] = phys_avail[j];
1814 dump_avail[j + 1] = phys_avail[j + 1];
1819 phys_avail[j] = availmem_regions[i].mr_start;
1820 phys_avail[j + 1] = availmem_regions[i].mr_start +
1821 availmem_regions[i].mr_size;
1823 physsz += availmem_regions[i].mr_size;
1824 dump_avail[j] = phys_avail[j];
1825 dump_avail[j + 1] = phys_avail[j + 1];
1827 physmem = btoc(physsz);
1829 /* Calculate the last available physical address. */
1830 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1832 Maxmem = powerpc_btop(phys_avail[i + 1]);
1834 debugf("Maxmem = 0x%08lx\n", Maxmem);
1835 debugf("phys_avail_count = %d\n", phys_avail_count);
1836 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
1837 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
1839 #ifdef __powerpc64__
1841 * Map the physical memory contiguously in TLB1.
1842 * Round so it fits into a single mapping.
1844 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
1845 phys_avail[i + 1], _TLB_ENTRY_MEM);
1848 /*******************************************************/
1849 /* Initialize (statically allocated) kernel pmap. */
1850 /*******************************************************/
1851 PMAP_LOCK_INIT(kernel_pmap);
1852 #ifdef __powerpc64__
1853 kernel_pmap->pm_pp2d = (pte_t ***)kernel_ptbl_root;
1855 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1856 kernel_pmap->pm_pdir = (pte_t **)kernel_ptbl_root;
1859 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
1860 kernel_pte_alloc(virtual_avail, kernstart, kernel_pdir);
1861 for (i = 0; i < MAXCPU; i++) {
1862 kernel_pmap->pm_tid[i] = TID_KERNEL;
1864 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1865 tidbusy[i][TID_KERNEL] = kernel_pmap;
1868 /* Mark kernel_pmap active on all CPUs */
1869 CPU_FILL(&kernel_pmap->pm_active);
1872 * Initialize the global pv list lock.
1874 rw_init(&pvh_global_lock, "pmap pv global");
1876 /*******************************************************/
1878 /*******************************************************/
1880 /* Enter kstack0 into kernel map, provide guard page */
1881 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1882 thread0.td_kstack = kstack0;
1883 thread0.td_kstack_pages = kstack_pages;
1885 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
1886 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
1887 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
1888 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
1889 kstack0, kstack0 + kstack0_sz);
1891 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1892 for (i = 0; i < kstack_pages; i++) {
1893 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1894 kstack0 += PAGE_SIZE;
1895 kstack0_phys += PAGE_SIZE;
1898 pmap_bootstrapped = 1;
1900 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
1901 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
1903 debugf("mmu_booke_bootstrap: exit\n");
1910 tlb_entry_t *e, tmp;
1913 /* Prepare TLB1 image for AP processors */
1915 for (i = 0; i < TLB1_ENTRIES; i++) {
1916 tlb1_read_entry(&tmp, i);
1918 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
1919 memcpy(e++, &tmp, sizeof(tmp));
1924 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1929 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1930 * have the snapshot of its contents in the s/w __boot_tlb1[] table
1931 * created by tlb1_ap_prep(), so use these values directly to
1932 * (re)program AP's TLB1 hardware.
1934 * Start at index 1 because index 0 has the kernel map.
1936 for (i = 1; i < TLB1_ENTRIES; i++) {
1937 if (__boot_tlb1[i].mas1 & MAS1_VALID)
1938 tlb1_write_entry(&__boot_tlb1[i], i);
1941 set_mas4_defaults();
1946 booke_pmap_init_qpages(void)
1953 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1954 if (pc->pc_qmap_addr == 0)
1955 panic("pmap_init_qpages: unable to allocate KVA");
1959 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1962 * Get the physical page address for the given pmap/virtual address.
1965 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1970 pa = pte_vatopa(mmu, pmap, va);
1977 * Extract the physical page address associated with the given
1978 * kernel virtual address.
1981 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1987 #ifdef __powerpc64__
1988 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1989 return (DMAP_TO_PHYS(va));
1992 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1993 p = pte_vatopa(mmu, kernel_pmap, va);
1996 /* Check TLB1 mappings */
1997 for (i = 0; i < TLB1_ENTRIES; i++) {
1998 tlb1_read_entry(&e, i);
1999 if (!(e.mas1 & MAS1_VALID))
2001 if (va >= e.virt && va < e.virt + e.size)
2002 return (e.phys + (va - e.virt));
2010 * Initialize the pmap module.
2011 * Called by vm_init, to initialize any structures that the pmap
2012 * system needs to map virtual memory.
2015 mmu_booke_init(mmu_t mmu)
2017 int shpgperproc = PMAP_SHPGPERPROC;
2020 * Initialize the address space (zone) for the pv entries. Set a
2021 * high water mark so that the system can recover from excessive
2022 * numbers of pv entries.
2024 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
2025 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
2027 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
2028 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
2030 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
2031 pv_entry_high_water = 9 * (pv_entry_max / 10);
2033 uma_zone_reserve_kva(pvzone, pv_entry_max);
2035 /* Pre-fill pvzone with initial number of pv entries. */
2036 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
2038 /* Create a UMA zone for page table roots. */
2039 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
2040 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
2042 /* Initialize ptbl allocation. */
2047 * Map a list of wired pages into kernel virtual address space. This is
2048 * intended for temporary mappings which do not need page modification or
2049 * references recorded. Existing mappings in the region are overwritten.
2052 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
2057 while (count-- > 0) {
2058 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
2065 * Remove page mappings from kernel virtual address space. Intended for
2066 * temporary mappings entered by mmu_booke_qenter.
2069 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
2074 while (count-- > 0) {
2075 mmu_booke_kremove(mmu, va);
2081 * Map a wired page into kernel virtual address space.
2084 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
2087 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
2091 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
2096 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2097 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
2099 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
2100 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
2101 flags |= PTE_PS_4KB;
2103 pte = pte_find(mmu, kernel_pmap, va);
2104 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
2106 mtx_lock_spin(&tlbivax_mutex);
2109 if (PTE_ISVALID(pte)) {
2111 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
2113 /* Flush entry from TLB0 */
2114 tlb0_flush_entry(va);
2117 *pte = PTE_RPN_FROM_PA(pa) | flags;
2119 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
2120 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
2121 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
2123 /* Flush the real memory from the instruction cache. */
2124 if ((flags & (PTE_I | PTE_G)) == 0)
2125 __syncicache((void *)va, PAGE_SIZE);
2128 mtx_unlock_spin(&tlbivax_mutex);
2132 * Remove a page from kernel page table.
2135 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
2139 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
2141 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
2142 (va <= VM_MAX_KERNEL_ADDRESS)),
2143 ("mmu_booke_kremove: invalid va"));
2145 pte = pte_find(mmu, kernel_pmap, va);
2147 if (!PTE_ISVALID(pte)) {
2149 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
2154 mtx_lock_spin(&tlbivax_mutex);
2157 /* Invalidate entry in TLB0, update PTE. */
2158 tlb0_flush_entry(va);
2162 mtx_unlock_spin(&tlbivax_mutex);
2166 * Provide a kernel pointer corresponding to a given userland pointer.
2167 * The returned pointer is valid until the next time this function is
2168 * called in this thread. This is used internally in copyin/copyout.
2171 mmu_booke_map_user_ptr(mmu_t mmu, pmap_t pm, volatile const void *uaddr,
2172 void **kaddr, size_t ulen, size_t *klen)
2175 if (trunc_page((uintptr_t)uaddr + ulen) > VM_MAXUSER_ADDRESS)
2178 *kaddr = (void *)(uintptr_t)uaddr;
2186 * Figure out where a given kernel pointer (usually in a fault) points
2187 * to from the VM's perspective, potentially remapping into userland's
2191 mmu_booke_decode_kernel_ptr(mmu_t mmu, vm_offset_t addr, int *is_user,
2192 vm_offset_t *decoded_addr)
2195 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
2200 *decoded_addr = addr;
2205 * Initialize pmap associated with process 0.
2208 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
2211 PMAP_LOCK_INIT(pmap);
2212 mmu_booke_pinit(mmu, pmap);
2213 PCPU_SET(curpmap, pmap);
2217 * Initialize a preallocated and zeroed pmap structure,
2218 * such as one in a vmspace structure.
2221 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
2225 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
2226 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
2228 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
2230 for (i = 0; i < MAXCPU; i++)
2231 pmap->pm_tid[i] = TID_NONE;
2232 CPU_ZERO(&kernel_pmap->pm_active);
2233 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
2234 #ifdef __powerpc64__
2235 pmap->pm_pp2d = uma_zalloc(ptbl_root_zone, M_WAITOK);
2236 bzero(pmap->pm_pp2d, sizeof(pte_t **) * PP2D_NENTRIES);
2238 pmap->pm_pdir = uma_zalloc(ptbl_root_zone, M_WAITOK);
2239 bzero(pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
2240 TAILQ_INIT(&pmap->pm_ptbl_list);
2245 * Release any resources held by the given physical map.
2246 * Called when a pmap initialized by mmu_booke_pinit is being released.
2247 * Should only be called if the map contains no valid mappings.
2250 mmu_booke_release(mmu_t mmu, pmap_t pmap)
2253 KASSERT(pmap->pm_stats.resident_count == 0,
2254 ("pmap_release: pmap resident count %ld != 0",
2255 pmap->pm_stats.resident_count));
2256 #ifdef __powerpc64__
2257 uma_zfree(ptbl_root_zone, pmap->pm_pp2d);
2259 uma_zfree(ptbl_root_zone, pmap->pm_pdir);
2264 * Insert the given physical page at the specified virtual address in the
2265 * target physical map with the protection requested. If specified the page
2266 * will be wired down.
2269 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2270 vm_prot_t prot, u_int flags, int8_t psind)
2274 rw_wlock(&pvh_global_lock);
2276 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
2278 rw_wunlock(&pvh_global_lock);
2283 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2284 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
2289 int error, su, sync;
2291 pa = VM_PAGE_TO_PHYS(m);
2292 su = (pmap == kernel_pmap);
2295 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
2296 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
2297 // (u_int32_t)pmap, su, pmap->pm_tid,
2298 // (u_int32_t)m, va, pa, prot, flags);
2301 KASSERT(((va >= virtual_avail) &&
2302 (va <= VM_MAX_KERNEL_ADDRESS)),
2303 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
2305 KASSERT((va <= VM_MAXUSER_ADDRESS),
2306 ("mmu_booke_enter_locked: user pmap, non user va"));
2308 if ((m->oflags & VPO_UNMANAGED) == 0) {
2309 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
2310 VM_PAGE_OBJECT_BUSY_ASSERT(m);
2312 VM_OBJECT_ASSERT_LOCKED(m->object);
2315 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2318 * If there is an existing mapping, and the physical address has not
2319 * changed, must be protection or wiring change.
2321 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
2322 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
2325 * Before actually updating pte->flags we calculate and
2326 * prepare its new value in a helper var.
2329 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
2331 /* Wiring change, just update stats. */
2332 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
2333 if (!PTE_ISWIRED(pte)) {
2335 pmap->pm_stats.wired_count++;
2338 if (PTE_ISWIRED(pte)) {
2339 flags &= ~PTE_WIRED;
2340 pmap->pm_stats.wired_count--;
2344 if (prot & VM_PROT_WRITE) {
2345 /* Add write permissions. */
2350 if ((flags & PTE_MANAGED) != 0)
2351 vm_page_aflag_set(m, PGA_WRITEABLE);
2353 /* Handle modified pages, sense modify status. */
2356 * The PTE_MODIFIED flag could be set by underlying
2357 * TLB misses since we last read it (above), possibly
2358 * other CPUs could update it so we check in the PTE
2359 * directly rather than rely on that saved local flags
2362 if (PTE_ISMODIFIED(pte))
2366 if (prot & VM_PROT_EXECUTE) {
2372 * Check existing flags for execute permissions: if we
2373 * are turning execute permissions on, icache should
2376 if ((*pte & (PTE_UX | PTE_SX)) == 0)
2380 flags &= ~PTE_REFERENCED;
2383 * The new flags value is all calculated -- only now actually
2386 mtx_lock_spin(&tlbivax_mutex);
2389 tlb0_flush_entry(va);
2390 *pte &= ~PTE_FLAGS_MASK;
2394 mtx_unlock_spin(&tlbivax_mutex);
2398 * If there is an existing mapping, but it's for a different
2399 * physical address, pte_enter() will delete the old mapping.
2401 //if ((pte != NULL) && PTE_ISVALID(pte))
2402 // debugf("mmu_booke_enter_locked: replace\n");
2404 // debugf("mmu_booke_enter_locked: new\n");
2406 /* Now set up the flags and install the new mapping. */
2407 flags = (PTE_SR | PTE_VALID);
2413 if (prot & VM_PROT_WRITE) {
2418 if ((m->oflags & VPO_UNMANAGED) == 0)
2419 vm_page_aflag_set(m, PGA_WRITEABLE);
2422 if (prot & VM_PROT_EXECUTE) {
2428 /* If its wired update stats. */
2429 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
2432 error = pte_enter(mmu, pmap, m, va, flags,
2433 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
2435 return (KERN_RESOURCE_SHORTAGE);
2437 if ((flags & PMAP_ENTER_WIRED) != 0)
2438 pmap->pm_stats.wired_count++;
2440 /* Flush the real memory from the instruction cache. */
2441 if (prot & VM_PROT_EXECUTE)
2445 if (sync && (su || pmap == PCPU_GET(curpmap))) {
2446 __syncicache((void *)va, PAGE_SIZE);
2450 return (KERN_SUCCESS);
2454 * Maps a sequence of resident pages belonging to the same object.
2455 * The sequence begins with the given page m_start. This page is
2456 * mapped at the given virtual address start. Each subsequent page is
2457 * mapped at a virtual address that is offset from start by the same
2458 * amount as the page is offset from m_start within the object. The
2459 * last page in the sequence is the page with the largest offset from
2460 * m_start that can be mapped at a virtual address less than the given
2461 * virtual address end. Not every virtual page between start and end
2462 * is mapped; only those for which a resident page exists with the
2463 * corresponding offset from m_start are mapped.
2466 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
2467 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
2470 vm_pindex_t diff, psize;
2472 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2474 psize = atop(end - start);
2476 rw_wlock(&pvh_global_lock);
2478 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2479 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
2480 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
2481 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
2482 m = TAILQ_NEXT(m, listq);
2484 rw_wunlock(&pvh_global_lock);
2489 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
2493 rw_wlock(&pvh_global_lock);
2495 mmu_booke_enter_locked(mmu, pmap, va, m,
2496 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
2497 PMAP_ENTER_QUICK_LOCKED, 0);
2498 rw_wunlock(&pvh_global_lock);
2503 * Remove the given range of addresses from the specified map.
2505 * It is assumed that the start and end are properly rounded to the page size.
2508 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
2513 int su = (pmap == kernel_pmap);
2515 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
2516 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
2519 KASSERT(((va >= virtual_avail) &&
2520 (va <= VM_MAX_KERNEL_ADDRESS)),
2521 ("mmu_booke_remove: kernel pmap, non kernel va"));
2523 KASSERT((va <= VM_MAXUSER_ADDRESS),
2524 ("mmu_booke_remove: user pmap, non user va"));
2527 if (PMAP_REMOVE_DONE(pmap)) {
2528 //debugf("mmu_booke_remove: e (empty)\n");
2532 hold_flag = PTBL_HOLD_FLAG(pmap);
2533 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
2535 rw_wlock(&pvh_global_lock);
2537 for (; va < endva; va += PAGE_SIZE) {
2538 pte = pte_find(mmu, pmap, va);
2539 if ((pte != NULL) && PTE_ISVALID(pte))
2540 pte_remove(mmu, pmap, va, hold_flag);
2543 rw_wunlock(&pvh_global_lock);
2545 //debugf("mmu_booke_remove: e\n");
2549 * Remove physical page from all pmaps in which it resides.
2552 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
2557 rw_wlock(&pvh_global_lock);
2558 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
2559 pvn = TAILQ_NEXT(pv, pv_link);
2561 PMAP_LOCK(pv->pv_pmap);
2562 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
2563 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
2564 PMAP_UNLOCK(pv->pv_pmap);
2566 vm_page_aflag_clear(m, PGA_WRITEABLE);
2567 rw_wunlock(&pvh_global_lock);
2571 * Map a range of physical addresses into kernel virtual address space.
2574 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
2575 vm_paddr_t pa_end, int prot)
2577 vm_offset_t sva = *virt;
2578 vm_offset_t va = sva;
2580 #ifdef __powerpc64__
2581 /* XXX: Handle memory not starting at 0x0. */
2582 if (pa_end < ctob(Maxmem))
2583 return (PHYS_TO_DMAP(pa_start));
2586 while (pa_start < pa_end) {
2587 mmu_booke_kenter(mmu, va, pa_start);
2589 pa_start += PAGE_SIZE;
2597 * The pmap must be activated before it's address space can be accessed in any
2601 mmu_booke_activate(mmu_t mmu, struct thread *td)
2606 pmap = &td->td_proc->p_vmspace->vm_pmap;
2608 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
2609 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2611 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
2615 cpuid = PCPU_GET(cpuid);
2616 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
2617 PCPU_SET(curpmap, pmap);
2619 if (pmap->pm_tid[cpuid] == TID_NONE)
2622 /* Load PID0 register with pmap tid value. */
2623 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
2624 __asm __volatile("isync");
2626 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
2630 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
2631 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
2635 * Deactivate the specified process's address space.
2638 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
2642 pmap = &td->td_proc->p_vmspace->vm_pmap;
2644 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
2645 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
2647 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
2649 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
2650 PCPU_SET(curpmap, NULL);
2654 * Copy the range specified by src_addr/len
2655 * from the source map to the range dst_addr/len
2656 * in the destination map.
2658 * This routine is only advisory and need not do anything.
2661 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
2662 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
2668 * Set the physical protection on the specified range of this map as requested.
2671 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2678 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2679 mmu_booke_remove(mmu, pmap, sva, eva);
2683 if (prot & VM_PROT_WRITE)
2687 for (va = sva; va < eva; va += PAGE_SIZE) {
2688 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2689 if (PTE_ISVALID(pte)) {
2690 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2692 mtx_lock_spin(&tlbivax_mutex);
2695 /* Handle modified pages. */
2696 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2699 tlb0_flush_entry(va);
2700 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2703 mtx_unlock_spin(&tlbivax_mutex);
2711 * Clear the write and modified bits in each of the given page's mappings.
2714 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2719 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2720 ("mmu_booke_remove_write: page %p is not managed", m));
2721 vm_page_assert_busied(m);
2723 if (!pmap_page_is_write_mapped(m))
2725 rw_wlock(&pvh_global_lock);
2726 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2727 PMAP_LOCK(pv->pv_pmap);
2728 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2729 if (PTE_ISVALID(pte)) {
2730 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2732 mtx_lock_spin(&tlbivax_mutex);
2735 /* Handle modified pages. */
2736 if (PTE_ISMODIFIED(pte))
2739 /* Flush mapping from TLB0. */
2740 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2743 mtx_unlock_spin(&tlbivax_mutex);
2746 PMAP_UNLOCK(pv->pv_pmap);
2748 vm_page_aflag_clear(m, PGA_WRITEABLE);
2749 rw_wunlock(&pvh_global_lock);
2753 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2758 #ifndef __powerpc64__
2765 #ifndef __powerpc64__
2766 rw_wlock(&pvh_global_lock);
2767 pmap = PCPU_GET(curpmap);
2768 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2772 pte = pte_find(mmu, pm, va);
2773 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2777 sync_sz = PAGE_SIZE - (va & PAGE_MASK);
2778 sync_sz = min(sync_sz, sz);
2780 #ifdef __powerpc64__
2781 pa += (va & PAGE_MASK);
2782 __syncicache((void *)PHYS_TO_DMAP(pa), sync_sz);
2785 /* Create a mapping in the active pmap. */
2787 m = PHYS_TO_VM_PAGE(pa);
2789 pte_enter(mmu, pmap, m, addr,
2790 PTE_SR | PTE_VALID, FALSE);
2791 addr += (va & PAGE_MASK);
2792 __syncicache((void *)addr, sync_sz);
2793 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2796 __syncicache((void *)va, sync_sz);
2802 #ifndef __powerpc64__
2803 rw_wunlock(&pvh_global_lock);
2808 * Atomically extract and hold the physical page with the given
2809 * pmap and virtual address pair if that mapping permits the given
2813 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2822 pte = pte_find(mmu, pmap, va);
2823 if ((pte != NULL) && PTE_ISVALID(pte)) {
2824 if (pmap == kernel_pmap)
2829 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
2830 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2831 if (!vm_page_wire_mapped(m))
2840 * Initialize a vm_page's machine-dependent fields.
2843 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2846 m->md.pv_tracked = 0;
2847 TAILQ_INIT(&m->md.pv_list);
2851 * mmu_booke_zero_page_area zeros the specified hardware page by
2852 * mapping it into virtual memory and using bzero to clear
2855 * off and size must reside within a single page.
2858 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2862 /* XXX KASSERT off and size are within a single page? */
2864 #ifdef __powerpc64__
2865 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2866 bzero((caddr_t)va + off, size);
2868 mtx_lock(&zero_page_mutex);
2871 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2872 bzero((caddr_t)va + off, size);
2873 mmu_booke_kremove(mmu, va);
2875 mtx_unlock(&zero_page_mutex);
2880 * mmu_booke_zero_page zeros the specified hardware page.
2883 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2885 vm_offset_t off, va;
2887 #ifdef __powerpc64__
2888 va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
2890 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
2891 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
2894 mtx_lock(&zero_page_mutex);
2896 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2898 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
2899 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
2901 mmu_booke_kremove(mmu, va);
2903 mtx_unlock(&zero_page_mutex);
2908 * mmu_booke_copy_page copies the specified (machine independent) page by
2909 * mapping the page into virtual memory and using memcopy to copy the page,
2910 * one machine dependent page at a time.
2913 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2915 vm_offset_t sva, dva;
2917 #ifdef __powerpc64__
2918 sva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(sm));
2919 dva = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dm));
2920 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2922 sva = copy_page_src_va;
2923 dva = copy_page_dst_va;
2925 mtx_lock(©_page_mutex);
2926 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2927 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2929 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2931 mmu_booke_kremove(mmu, dva);
2932 mmu_booke_kremove(mmu, sva);
2933 mtx_unlock(©_page_mutex);
2938 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2939 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2942 vm_offset_t a_pg_offset, b_pg_offset;
2945 #ifdef __powerpc64__
2948 while (xfersize > 0) {
2949 a_pg_offset = a_offset & PAGE_MASK;
2950 pa = ma[a_offset >> PAGE_SHIFT];
2951 b_pg_offset = b_offset & PAGE_MASK;
2952 pb = mb[b_offset >> PAGE_SHIFT];
2953 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2954 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2955 a_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pa)) +
2957 b_cp = (caddr_t)((uintptr_t)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pb)) +
2959 bcopy(a_cp, b_cp, cnt);
2965 mtx_lock(©_page_mutex);
2966 while (xfersize > 0) {
2967 a_pg_offset = a_offset & PAGE_MASK;
2968 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2969 mmu_booke_kenter(mmu, copy_page_src_va,
2970 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2971 a_cp = (char *)copy_page_src_va + a_pg_offset;
2972 b_pg_offset = b_offset & PAGE_MASK;
2973 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2974 mmu_booke_kenter(mmu, copy_page_dst_va,
2975 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2976 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2977 bcopy(a_cp, b_cp, cnt);
2978 mmu_booke_kremove(mmu, copy_page_dst_va);
2979 mmu_booke_kremove(mmu, copy_page_src_va);
2984 mtx_unlock(©_page_mutex);
2989 mmu_booke_quick_enter_page(mmu_t mmu, vm_page_t m)
2991 #ifdef __powerpc64__
2992 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)));
2999 paddr = VM_PAGE_TO_PHYS(m);
3001 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
3002 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
3003 flags |= PTE_PS_4KB;
3006 qaddr = PCPU_GET(qmap_addr);
3008 pte = pte_find(mmu, kernel_pmap, qaddr);
3010 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy"));
3013 * XXX: tlbivax is broadcast to other cores, but qaddr should
3014 * not be present in other TLBs. Is there a better instruction
3015 * sequence to use? Or just forget it & use mmu_booke_kenter()...
3017 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK));
3018 __asm __volatile("isync; msync");
3020 *pte = PTE_RPN_FROM_PA(paddr) | flags;
3022 /* Flush the real memory from the instruction cache. */
3023 if ((flags & (PTE_I | PTE_G)) == 0)
3024 __syncicache((void *)qaddr, PAGE_SIZE);
3031 mmu_booke_quick_remove_page(mmu_t mmu, vm_offset_t addr)
3033 #ifndef __powerpc64__
3036 pte = pte_find(mmu, kernel_pmap, addr);
3038 KASSERT(PCPU_GET(qmap_addr) == addr,
3039 ("mmu_booke_quick_remove_page: invalid address"));
3041 ("mmu_booke_quick_remove_page: PTE not in use"));
3049 * Return whether or not the specified physical page was modified
3050 * in any of physical maps.
3053 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
3059 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3060 ("mmu_booke_is_modified: page %p is not managed", m));
3064 * If the page is not busied then this check is racy.
3066 if (!pmap_page_is_write_mapped(m))
3069 rw_wlock(&pvh_global_lock);
3070 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3071 PMAP_LOCK(pv->pv_pmap);
3072 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3074 if (PTE_ISMODIFIED(pte))
3077 PMAP_UNLOCK(pv->pv_pmap);
3081 rw_wunlock(&pvh_global_lock);
3086 * Return whether or not the specified virtual address is eligible
3090 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
3097 * Return whether or not the specified physical page was referenced
3098 * in any physical maps.
3101 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
3107 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3108 ("mmu_booke_is_referenced: page %p is not managed", m));
3110 rw_wlock(&pvh_global_lock);
3111 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3112 PMAP_LOCK(pv->pv_pmap);
3113 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3115 if (PTE_ISREFERENCED(pte))
3118 PMAP_UNLOCK(pv->pv_pmap);
3122 rw_wunlock(&pvh_global_lock);
3127 * Clear the modify bits on the specified physical page.
3130 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
3135 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3136 ("mmu_booke_clear_modify: page %p is not managed", m));
3137 vm_page_assert_busied(m);
3139 if (!pmap_page_is_write_mapped(m))
3142 rw_wlock(&pvh_global_lock);
3143 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3144 PMAP_LOCK(pv->pv_pmap);
3145 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3147 mtx_lock_spin(&tlbivax_mutex);
3150 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
3151 tlb0_flush_entry(pv->pv_va);
3152 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
3157 mtx_unlock_spin(&tlbivax_mutex);
3159 PMAP_UNLOCK(pv->pv_pmap);
3161 rw_wunlock(&pvh_global_lock);
3165 * Return a count of reference bits for a page, clearing those bits.
3166 * It is not necessary for every reference bit to be cleared, but it
3167 * is necessary that 0 only be returned when there are truly no
3168 * reference bits set.
3170 * As an optimization, update the page's dirty field if a modified bit is
3171 * found while counting reference bits. This opportunistic update can be
3172 * performed at low cost and can eliminate the need for some future calls
3173 * to pmap_is_modified(). However, since this function stops after
3174 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
3175 * dirty pages. Those dirty pages will only be detected by a future call
3176 * to pmap_is_modified().
3179 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
3185 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3186 ("mmu_booke_ts_referenced: page %p is not managed", m));
3188 rw_wlock(&pvh_global_lock);
3189 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3190 PMAP_LOCK(pv->pv_pmap);
3191 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
3193 if (PTE_ISMODIFIED(pte))
3195 if (PTE_ISREFERENCED(pte)) {
3196 mtx_lock_spin(&tlbivax_mutex);
3199 tlb0_flush_entry(pv->pv_va);
3200 *pte &= ~PTE_REFERENCED;
3203 mtx_unlock_spin(&tlbivax_mutex);
3205 if (++count >= PMAP_TS_REFERENCED_MAX) {
3206 PMAP_UNLOCK(pv->pv_pmap);
3211 PMAP_UNLOCK(pv->pv_pmap);
3213 rw_wunlock(&pvh_global_lock);
3218 * Clear the wired attribute from the mappings for the specified range of
3219 * addresses in the given pmap. Every valid mapping within that range must
3220 * have the wired attribute set. In contrast, invalid mappings cannot have
3221 * the wired attribute set, so they are ignored.
3223 * The wired attribute of the page table entry is not a hardware feature, so
3224 * there is no need to invalidate any TLB entries.
3227 mmu_booke_unwire(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3233 for (va = sva; va < eva; va += PAGE_SIZE) {
3234 if ((pte = pte_find(mmu, pmap, va)) != NULL &&
3236 if (!PTE_ISWIRED(pte))
3237 panic("mmu_booke_unwire: pte %p isn't wired",
3240 pmap->pm_stats.wired_count--;
3248 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
3249 * page. This count may be changed upwards or downwards in the future; it is
3250 * only necessary that true be returned for a small subset of pmaps for proper
3254 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
3260 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3261 ("mmu_booke_page_exists_quick: page %p is not managed", m));
3264 rw_wlock(&pvh_global_lock);
3265 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3266 if (pv->pv_pmap == pmap) {
3273 rw_wunlock(&pvh_global_lock);
3278 * Return the number of managed mappings to the given physical page that are
3282 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
3288 if ((m->oflags & VPO_UNMANAGED) != 0)
3290 rw_wlock(&pvh_global_lock);
3291 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
3292 PMAP_LOCK(pv->pv_pmap);
3293 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
3294 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
3296 PMAP_UNLOCK(pv->pv_pmap);
3298 rw_wunlock(&pvh_global_lock);
3303 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3309 * This currently does not work for entries that
3310 * overlap TLB1 entries.
3312 for (i = 0; i < TLB1_ENTRIES; i ++) {
3313 if (tlb1_iomapped(i, pa, size, &va) == 0)
3321 mmu_booke_dumpsys_map(mmu_t mmu, vm_paddr_t pa, size_t sz, void **va)
3327 /* Minidumps are based on virtual memory addresses. */
3329 *va = (void *)(vm_offset_t)pa;
3333 /* Raw physical memory dumps don't have a virtual address. */
3334 /* We always map a 256MB page at 256M. */
3335 gran = 256 * 1024 * 1024;
3336 ppa = rounddown2(pa, gran);
3339 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
3341 if (sz > (gran - ofs))
3342 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
3347 mmu_booke_dumpsys_unmap(mmu_t mmu, vm_paddr_t pa, size_t sz, void *va)
3355 /* Minidumps are based on virtual memory addresses. */
3356 /* Nothing to do... */
3360 for (i = 0; i < TLB1_ENTRIES; i++) {
3361 tlb1_read_entry(&e, i);
3362 if (!(e.mas1 & MAS1_VALID))
3366 /* Raw physical memory dumps don't have a virtual address. */
3371 tlb1_write_entry(&e, i);
3373 gran = 256 * 1024 * 1024;
3374 ppa = rounddown2(pa, gran);
3376 if (sz > (gran - ofs)) {
3381 tlb1_write_entry(&e, i);
3385 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
3388 mmu_booke_scan_init(mmu_t mmu)
3395 /* Initialize phys. segments for dumpsys(). */
3396 memset(&dump_map, 0, sizeof(dump_map));
3397 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
3398 &availmem_regions_sz);
3399 for (i = 0; i < physmem_regions_sz; i++) {
3400 dump_map[i].pa_start = physmem_regions[i].mr_start;
3401 dump_map[i].pa_size = physmem_regions[i].mr_size;
3406 /* Virtual segments for minidumps: */
3407 memset(&dump_map, 0, sizeof(dump_map));
3409 /* 1st: kernel .data and .bss. */
3410 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
3411 dump_map[0].pa_size =
3412 round_page((uintptr_t)_end) - dump_map[0].pa_start;
3414 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
3415 dump_map[1].pa_start = data_start;
3416 dump_map[1].pa_size = data_end - data_start;
3418 /* 3rd: kernel VM. */
3419 va = dump_map[1].pa_start + dump_map[1].pa_size;
3420 /* Find start of next chunk (from va). */
3421 while (va < virtual_end) {
3422 /* Don't dump the buffer cache. */
3423 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
3424 va = kmi.buffer_eva;
3427 pte = pte_find(mmu, kernel_pmap, va);
3428 if (pte != NULL && PTE_ISVALID(pte))
3432 if (va < virtual_end) {
3433 dump_map[2].pa_start = va;
3435 /* Find last page in chunk. */
3436 while (va < virtual_end) {
3437 /* Don't run into the buffer cache. */
3438 if (va == kmi.buffer_sva)
3440 pte = pte_find(mmu, kernel_pmap, va);
3441 if (pte == NULL || !PTE_ISVALID(pte))
3445 dump_map[2].pa_size = va - dump_map[2].pa_start;
3450 * Map a set of physical memory pages into the kernel virtual address space.
3451 * Return a pointer to where it is mapped. This routine is intended to be used
3452 * for mapping device memory, NOT real memory.
3455 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
3458 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
3462 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
3466 for (i = 0; i < TLB1_ENTRIES; i++) {
3467 tlb1_read_entry(e, i);
3468 if ((e->mas1 & MAS1_VALID) == 0)
3475 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3480 uintptr_t va, tmpva;
3486 * Check if this is premapped in TLB1.
3491 wimge = tlb_calc_wimg(pa, ma);
3492 for (i = 0; i < TLB1_ENTRIES; i++) {
3493 tlb1_read_entry(&e, i);
3494 if (!(e.mas1 & MAS1_VALID))
3496 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
3498 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
3499 va = e.virt + (pa - e.phys);
3500 tmppa = e.phys + e.size;
3501 sz -= MIN(sz, e.size);
3502 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
3503 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
3505 sz -= MIN(sz, e.size);
3506 tmppa = e.phys + e.size;
3510 return ((void *)va);
3514 size = roundup(size, PAGE_SIZE);
3517 * The device mapping area is between VM_MAXUSER_ADDRESS and
3518 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
3520 #ifdef SPARSE_MAPDEV
3522 * With a sparse mapdev, align to the largest starting region. This
3523 * could feasibly be optimized for a 'best-fit' alignment, but that
3524 * calculation could be very costly.
3525 * Align to the smaller of:
3526 * - first set bit in overlap of (pa & size mask)
3527 * - largest size envelope
3529 * It's possible the device mapping may start at a PA that's not larger
3530 * than the size mask, so we need to offset in to maximize the TLB entry
3531 * range and minimize the number of used TLB entries.
3534 tmpva = tlb1_map_base;
3535 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
3536 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
3537 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
3538 #ifdef __powerpc64__
3539 } while (!atomic_cmpset_long(&tlb1_map_base, tmpva, va + size));
3541 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
3544 #ifdef __powerpc64__
3545 va = atomic_fetchadd_long(&tlb1_map_base, size);
3547 va = atomic_fetchadd_int(&tlb1_map_base, size);
3552 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
3559 * 'Unmap' a range mapped by mmu_booke_mapdev().
3562 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
3564 #ifdef SUPPORTS_SHRINKING_TLB1
3565 vm_offset_t base, offset;
3568 * Unmap only if this is inside kernel virtual space.
3570 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
3571 base = trunc_page(va);
3572 offset = va & PAGE_MASK;
3573 size = roundup(offset + size, PAGE_SIZE);
3574 kva_free(base, size);
3580 * mmu_booke_object_init_pt preloads the ptes for a given object into the
3581 * specified pmap. This eliminates the blast of soft faults on process startup
3582 * and immediately after an mmap.
3585 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3586 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
3589 VM_OBJECT_ASSERT_WLOCKED(object);
3590 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3591 ("mmu_booke_object_init_pt: non-device object"));
3595 * Perform the pmap work for mincore.
3598 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
3602 /* XXX: this should be implemented at some point */
3607 mmu_booke_change_attr(mmu_t mmu, vm_offset_t addr, vm_size_t sz,
3615 addr = trunc_page(addr);
3617 /* Only allow changes to mapped kernel addresses. This includes:
3619 * - DMAP (powerpc64)
3622 if (addr <= VM_MAXUSER_ADDRESS ||
3623 #ifdef __powerpc64__
3624 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
3625 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
3627 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
3629 (addr > VM_MAX_KERNEL_ADDRESS))
3632 /* Check TLB1 mappings */
3633 for (i = 0; i < TLB1_ENTRIES; i++) {
3634 tlb1_read_entry(&e, i);
3635 if (!(e.mas1 & MAS1_VALID))
3637 if (addr >= e.virt && addr < e.virt + e.size)
3640 if (i < TLB1_ENTRIES) {
3641 /* Only allow full mappings to be modified for now. */
3642 /* Validate the range. */
3643 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
3644 tlb1_read_entry(&e, j);
3645 if (va != e.virt || (sz - (va - addr) < e.size))
3648 for (va = addr; va < addr + sz; va += e.size, i++) {
3649 tlb1_read_entry(&e, i);
3650 e.mas2 &= ~MAS2_WIMGE_MASK;
3651 e.mas2 |= tlb_calc_wimg(e.phys, mode);
3654 * Write it out to the TLB. Should really re-sync with other
3657 tlb1_write_entry(&e, i);
3662 /* Not in TLB1, try through pmap */
3663 /* First validate the range. */
3664 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3665 pte = pte_find(mmu, kernel_pmap, va);
3666 if (pte == NULL || !PTE_ISVALID(pte))
3670 mtx_lock_spin(&tlbivax_mutex);
3672 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
3673 pte = pte_find(mmu, kernel_pmap, va);
3674 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
3675 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
3676 tlb0_flush_entry(va);
3679 mtx_unlock_spin(&tlbivax_mutex);
3685 mmu_booke_page_array_startup(mmu_t mmu, long pages)
3687 vm_page_array_size = pages;
3690 /**************************************************************************/
3692 /**************************************************************************/
3695 * Allocate a TID. If necessary, steal one from someone else.
3696 * The new TID is flushed from the TLB before returning.
3699 tid_alloc(pmap_t pmap)
3704 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
3706 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
3708 thiscpu = PCPU_GET(cpuid);
3710 tid = PCPU_GET(booke.tid_next);
3713 PCPU_SET(booke.tid_next, tid + 1);
3715 /* If we are stealing TID then clear the relevant pmap's field */
3716 if (tidbusy[thiscpu][tid] != NULL) {
3718 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
3720 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
3722 /* Flush all entries from TLB0 matching this TID. */
3726 tidbusy[thiscpu][tid] = pmap;
3727 pmap->pm_tid[thiscpu] = tid;
3728 __asm __volatile("msync; isync");
3730 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
3731 PCPU_GET(booke.tid_next));
3736 /**************************************************************************/
3738 /**************************************************************************/
3740 /* Convert TLB0 va and way number to tlb0[] table index. */
3741 static inline unsigned int
3742 tlb0_tableidx(vm_offset_t va, unsigned int way)
3746 idx = (way * TLB0_ENTRIES_PER_WAY);
3747 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
3752 * Invalidate TLB0 entry.
3755 tlb0_flush_entry(vm_offset_t va)
3758 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
3760 mtx_assert(&tlbivax_mutex, MA_OWNED);
3762 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
3763 __asm __volatile("isync; msync");
3764 __asm __volatile("tlbsync; msync");
3766 CTR1(KTR_PMAP, "%s: e", __func__);
3770 /**************************************************************************/
3772 /**************************************************************************/
3775 * TLB1 mapping notes:
3777 * TLB1[0] Kernel text and data.
3778 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
3779 * windows, other devices mappings.
3783 * Read an entry from given TLB1 slot.
3786 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
3791 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
3794 __asm __volatile("wrteei 0");
3796 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
3797 mtspr(SPR_MAS0, mas0);
3798 __asm __volatile("isync; tlbre");
3800 entry->mas1 = mfspr(SPR_MAS1);
3801 entry->mas2 = mfspr(SPR_MAS2);
3802 entry->mas3 = mfspr(SPR_MAS3);
3804 switch ((mfpvr() >> 16) & 0xFFFF) {
3809 entry->mas7 = mfspr(SPR_MAS7);
3815 __asm __volatile("wrtee %0" :: "r"(msr));
3817 entry->virt = entry->mas2 & MAS2_EPN_MASK;
3818 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
3819 (entry->mas3 & MAS3_RPN);
3821 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
3824 struct tlbwrite_args {
3830 tlb1_find_free(void)
3835 for (i = 0; i < TLB1_ENTRIES; i++) {
3836 tlb1_read_entry(&e, i);
3837 if ((e.mas1 & MAS1_VALID) == 0)
3844 tlb1_write_entry_int(void *arg)
3846 struct tlbwrite_args *args = arg;
3851 idx = tlb1_find_free();
3853 panic("No free TLB1 entries!\n");
3856 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
3858 mtspr(SPR_MAS0, mas0);
3859 mtspr(SPR_MAS1, args->e->mas1);
3860 mtspr(SPR_MAS2, args->e->mas2);
3861 mtspr(SPR_MAS3, args->e->mas3);
3862 switch ((mfpvr() >> 16) & 0xFFFF) {
3869 mtspr(SPR_MAS7, args->e->mas7);
3875 __asm __volatile("isync; tlbwe; isync; msync");
3880 tlb1_write_entry_sync(void *arg)
3882 /* Empty synchronization point for smp_rendezvous(). */
3886 * Write given entry to TLB1 hardware.
3889 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
3891 struct tlbwrite_args args;
3897 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
3899 smp_rendezvous(tlb1_write_entry_sync,
3900 tlb1_write_entry_int,
3901 tlb1_write_entry_sync, &args);
3908 __asm __volatile("wrteei 0");
3909 tlb1_write_entry_int(&args);
3910 __asm __volatile("wrtee %0" :: "r"(msr));
3915 * Return the largest uint value log such that 2^log <= num.
3917 static unsigned long
3918 ilog2(unsigned long num)
3922 #ifdef __powerpc64__
3923 __asm ("cntlzd %0, %1" : "=r" (lz) : "r" (num));
3926 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
3932 * Convert TLB TSIZE value to mapped region size.
3935 tsize2size(unsigned int tsize)
3940 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
3943 return ((1 << (2 * tsize)) * 1024);
3947 * Convert region size (must be power of 4) to TLB TSIZE value.
3950 size2tsize(vm_size_t size)
3953 return (ilog2(size) / 2 - 5);
3957 * Register permanent kernel mapping in TLB1.
3959 * Entries are created starting from index 0 (current free entry is
3960 * kept in tlb1_idx) and are not supposed to be invalidated.
3963 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
3970 /* First try to update an existing entry. */
3971 for (index = 0; index < TLB1_ENTRIES; index++) {
3972 tlb1_read_entry(&e, index);
3973 /* Check if we're just updating the flags, and update them. */
3974 if (e.phys == pa && e.virt == va && e.size == size) {
3975 e.mas2 = (va & MAS2_EPN_MASK) | flags;
3976 tlb1_write_entry(&e, index);
3981 /* Convert size to TSIZE */
3982 tsize = size2tsize(size);
3984 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3985 /* XXX TS is hard coded to 0 for now as we only use single address space */
3986 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3991 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3992 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3993 e.mas2 = (va & MAS2_EPN_MASK) | flags;
3995 /* Set supervisor RWX permission bits */
3996 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3997 e.mas7 = (pa >> 32) & MAS7_RPN;
3999 tlb1_write_entry(&e, -1);
4005 * Map in contiguous RAM region into the TLB1.
4008 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
4011 vm_size_t mapped, sz, ssize;
4018 sz = 1UL << (ilog2(size) & ~1);
4019 /* Align size to PA */
4023 } while (pa % sz != 0);
4025 /* Now align from there to VA */
4029 } while (va % sz != 0);
4031 /* Now align from there to VA */
4033 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
4034 (void *)va, (uintmax_t)pa, (long)sz);
4035 if (tlb1_set_entry(va, pa, sz,
4036 _TLB_ENTRY_SHARED | wimge) < 0)
4043 mapped = (va - base);
4045 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
4046 mapped, mapped - ssize);
4052 * TLB1 initialization routine, to be called after the very first
4053 * assembler level setup done in locore.S.
4059 uint32_t mas0, mas1, mas3, mas7;
4064 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
4065 mtspr(SPR_MAS0, mas0);
4066 __asm __volatile("isync; tlbre");
4068 mas1 = mfspr(SPR_MAS1);
4069 mas2 = mfspr(SPR_MAS2);
4070 mas3 = mfspr(SPR_MAS3);
4071 mas7 = mfspr(SPR_MAS7);
4073 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
4076 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4077 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
4078 kernstart = trunc_page(mas2);
4080 /* Setup TLB miss defaults */
4081 set_mas4_defaults();
4085 * pmap_early_io_unmap() should be used in short conjunction with
4086 * pmap_early_io_map(), as in the following snippet:
4088 * x = pmap_early_io_map(...);
4089 * <do something with x>
4090 * pmap_early_io_unmap(x, size);
4092 * And avoiding more allocations between.
4095 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
4101 size = roundup(size, PAGE_SIZE);
4103 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
4104 tlb1_read_entry(&e, i);
4105 if (!(e.mas1 & MAS1_VALID))
4107 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
4109 e.mas1 &= ~MAS1_VALID;
4110 tlb1_write_entry(&e, i);
4113 if (tlb1_map_base == va + isize)
4114 tlb1_map_base -= isize;
4118 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
4125 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
4127 for (i = 0; i < TLB1_ENTRIES; i++) {
4128 tlb1_read_entry(&e, i);
4129 if (!(e.mas1 & MAS1_VALID))
4131 if (pa >= e.phys && (pa + size) <=
4133 return (e.virt + (pa - e.phys));
4136 pa_base = rounddown(pa, PAGE_SIZE);
4137 size = roundup(size + (pa - pa_base), PAGE_SIZE);
4138 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
4139 va = tlb1_map_base + (pa - pa_base);
4142 sz = 1 << (ilog2(size) & ~1);
4143 tlb1_set_entry(tlb1_map_base, pa_base, sz,
4144 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
4147 tlb1_map_base += sz;
4154 pmap_track_page(pmap_t pmap, vm_offset_t va)
4158 struct pv_entry *pve;
4160 va = trunc_page(va);
4161 pa = pmap_kextract(va);
4162 page = PHYS_TO_VM_PAGE(pa);
4164 rw_wlock(&pvh_global_lock);
4167 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
4168 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
4172 page->md.pv_tracked = true;
4173 pv_insert(pmap, va, page);
4176 rw_wunlock(&pvh_global_lock);
4181 * Setup MAS4 defaults.
4182 * These values are loaded to MAS0-2 on a TLB miss.
4185 set_mas4_defaults(void)
4189 /* Defaults: TLB0, PID0, TSIZED=4K */
4190 mas4 = MAS4_TLBSELD0;
4191 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
4195 mtspr(SPR_MAS4, mas4);
4196 __asm __volatile("isync");
4201 * Return 0 if the physical IO range is encompassed by one of the
4202 * the TLB1 entries, otherwise return related error code.
4205 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
4208 vm_paddr_t pa_start;
4210 unsigned int entry_tsize;
4211 vm_size_t entry_size;
4214 *va = (vm_offset_t)NULL;
4216 tlb1_read_entry(&e, i);
4217 /* Skip invalid entries */
4218 if (!(e.mas1 & MAS1_VALID))
4222 * The entry must be cache-inhibited, guarded, and r/w
4223 * so it can function as an i/o page
4225 prot = e.mas2 & (MAS2_I | MAS2_G);
4226 if (prot != (MAS2_I | MAS2_G))
4229 prot = e.mas3 & (MAS3_SR | MAS3_SW);
4230 if (prot != (MAS3_SR | MAS3_SW))
4233 /* The address should be within the entry range. */
4234 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4235 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
4237 entry_size = tsize2size(entry_tsize);
4238 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
4239 (e.mas3 & MAS3_RPN);
4240 pa_end = pa_start + entry_size;
4242 if ((pa < pa_start) || ((pa + size) > pa_end))
4245 /* Return virtual address of this mapping. */
4246 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
4251 * Invalidate all TLB0 entries which match the given TID. Note this is
4252 * dedicated for cases when invalidations should NOT be propagated to other
4256 tid_flush(tlbtid_t tid)
4259 uint32_t mas0, mas1, mas2;
4263 /* Don't evict kernel translations */
4264 if (tid == TID_KERNEL)
4268 __asm __volatile("wrteei 0");
4271 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use
4272 * it for PID invalidation.
4274 switch ((mfpvr() >> 16) & 0xffff) {
4278 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
4280 __asm __volatile("isync; .long 0x7c200024; isync; msync");
4281 __asm __volatile("wrtee %0" :: "r"(msr));
4285 for (way = 0; way < TLB0_WAYS; way++)
4286 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
4288 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4289 mtspr(SPR_MAS0, mas0);
4291 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
4292 mtspr(SPR_MAS2, mas2);
4294 __asm __volatile("isync; tlbre");
4296 mas1 = mfspr(SPR_MAS1);
4298 if (!(mas1 & MAS1_VALID))
4300 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
4302 mas1 &= ~MAS1_VALID;
4303 mtspr(SPR_MAS1, mas1);
4304 __asm __volatile("isync; tlbwe; isync; msync");
4306 __asm __volatile("wrtee %0" :: "r"(msr));
4310 /* Print out contents of the MAS registers for each TLB0 entry */
4312 #ifdef __powerpc64__
4313 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
4315 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
4326 if (mas1 & MAS1_VALID)
4331 if (mas1 & MAS1_IPROT)
4336 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
4337 tid = MAS1_GETTID(mas1);
4339 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
4342 size = tsize2size(tsize);
4344 printf("%3d: (%s) [AS=%d] "
4345 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
4346 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
4347 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
4350 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
4352 uint32_t mas0, mas1, mas3, mas7;
4353 #ifdef __powerpc64__
4358 int entryidx, way, idx;
4360 printf("TLB0 entries:\n");
4361 for (way = 0; way < TLB0_WAYS; way ++)
4362 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
4364 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
4365 mtspr(SPR_MAS0, mas0);
4367 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
4368 mtspr(SPR_MAS2, mas2);
4370 __asm __volatile("isync; tlbre");
4372 mas1 = mfspr(SPR_MAS1);
4373 mas2 = mfspr(SPR_MAS2);
4374 mas3 = mfspr(SPR_MAS3);
4375 mas7 = mfspr(SPR_MAS7);
4377 idx = tlb0_tableidx(mas2, way);
4378 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
4383 * Print out contents of the MAS registers for each TLB1 entry
4385 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
4387 uint32_t mas0, mas1, mas3, mas7;
4388 #ifdef __powerpc64__
4395 printf("TLB1 entries:\n");
4396 for (i = 0; i < TLB1_ENTRIES; i++) {
4398 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
4399 mtspr(SPR_MAS0, mas0);
4401 __asm __volatile("isync; tlbre");
4403 mas1 = mfspr(SPR_MAS1);
4404 mas2 = mfspr(SPR_MAS2);
4405 mas3 = mfspr(SPR_MAS3);
4406 mas7 = mfspr(SPR_MAS7);
4408 tlb_print_entry(i, mas1, mas2, mas3, mas7);