2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/types.h>
55 #include <sys/param.h>
56 #include <sys/malloc.h>
60 #include <sys/queue.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/msgbuf.h>
65 #include <sys/mutex.h>
66 #include <sys/sched.h>
68 #include <sys/vmmeter.h>
71 #include <vm/vm_page.h>
72 #include <vm/vm_kern.h>
73 #include <vm/vm_pageout.h>
74 #include <vm/vm_extern.h>
75 #include <vm/vm_object.h>
76 #include <vm/vm_param.h>
77 #include <vm/vm_map.h>
78 #include <vm/vm_pager.h>
81 #include <machine/cpu.h>
82 #include <machine/pcb.h>
83 #include <machine/platform.h>
85 #include <machine/tlb.h>
86 #include <machine/spr.h>
87 #include <machine/vmparam.h>
88 #include <machine/md_var.h>
89 #include <machine/mmuvar.h>
90 #include <machine/pmap.h>
91 #include <machine/pte.h>
96 #define debugf(fmt, args...) printf(fmt, ##args)
98 #define debugf(fmt, args...)
101 #define TODO panic("%s: not implemented", __func__);
103 #include "opt_sched.h"
105 #error "e500 only works with SCHED_4BSD which uses a global scheduler lock."
107 extern struct mtx sched_lock;
109 extern int dumpsys_minidump;
111 extern unsigned char _etext[];
112 extern unsigned char _end[];
114 /* Kernel physical load address. */
115 extern uint32_t kernload;
116 vm_offset_t kernstart;
119 /* Message buffer and tables. */
120 static vm_offset_t data_start;
121 static vm_size_t data_end;
123 /* Phys/avail memory regions. */
124 static struct mem_region *availmem_regions;
125 static int availmem_regions_sz;
126 static struct mem_region *physmem_regions;
127 static int physmem_regions_sz;
129 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
130 static vm_offset_t zero_page_va;
131 static struct mtx zero_page_mutex;
133 static struct mtx tlbivax_mutex;
136 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
137 * by idle thred only, no lock required.
139 static vm_offset_t zero_page_idle_va;
141 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
142 static vm_offset_t copy_page_src_va;
143 static vm_offset_t copy_page_dst_va;
144 static struct mtx copy_page_mutex;
146 /**************************************************************************/
148 /**************************************************************************/
150 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
151 vm_prot_t, boolean_t);
153 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
154 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
157 * If user pmap is processed with mmu_booke_remove and the resident count
158 * drops to 0, there are no more pages to remove, so we need not continue.
160 #define PMAP_REMOVE_DONE(pmap) \
161 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
163 extern void tid_flush(tlbtid_t);
165 /**************************************************************************/
166 /* TLB and TID handling */
167 /**************************************************************************/
169 /* Translation ID busy table */
170 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
173 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
174 * core revisions and should be read from h/w registers during early config.
176 uint32_t tlb0_entries;
178 uint32_t tlb0_entries_per_way;
180 #define TLB0_ENTRIES (tlb0_entries)
181 #define TLB0_WAYS (tlb0_ways)
182 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
184 #define TLB1_ENTRIES 16
186 /* In-ram copy of the TLB1 */
187 static tlb_entry_t tlb1[TLB1_ENTRIES];
189 /* Next free entry in the TLB1 */
190 static unsigned int tlb1_idx;
192 static tlbtid_t tid_alloc(struct pmap *);
194 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
196 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
197 static void tlb1_write_entry(unsigned int);
198 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
199 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t);
201 static vm_size_t tsize2size(unsigned int);
202 static unsigned int size2tsize(vm_size_t);
203 static unsigned int ilog2(unsigned int);
205 static void set_mas4_defaults(void);
207 static inline void tlb0_flush_entry(vm_offset_t);
208 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
210 /**************************************************************************/
211 /* Page table management */
212 /**************************************************************************/
214 /* Data for the pv entry allocation mechanism */
215 static uma_zone_t pvzone;
216 static struct vm_object pvzone_obj;
217 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
219 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
221 #ifndef PMAP_SHPGPERPROC
222 #define PMAP_SHPGPERPROC 200
225 static void ptbl_init(void);
226 static struct ptbl_buf *ptbl_buf_alloc(void);
227 static void ptbl_buf_free(struct ptbl_buf *);
228 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
230 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
231 static void ptbl_free(mmu_t, pmap_t, unsigned int);
232 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
233 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
235 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
236 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
237 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
238 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
240 static pv_entry_t pv_alloc(void);
241 static void pv_free(pv_entry_t);
242 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
243 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
245 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
246 #define PTBL_BUFS (128 * 16)
249 TAILQ_ENTRY(ptbl_buf) link; /* list link */
250 vm_offset_t kva; /* va of mapping */
253 /* ptbl free list and a lock used for access synchronization. */
254 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
255 static struct mtx ptbl_buf_freelist_lock;
257 /* Base address of kva space allocated fot ptbl bufs. */
258 static vm_offset_t ptbl_buf_pool_vabase;
260 /* Pointer to ptbl_buf structures. */
261 static struct ptbl_buf *ptbl_bufs;
263 void pmap_bootstrap_ap(volatile uint32_t *);
266 * Kernel MMU interface
268 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
269 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
270 static void mmu_booke_clear_reference(mmu_t, vm_page_t);
271 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
272 vm_size_t, vm_offset_t);
273 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
274 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
275 vm_prot_t, boolean_t);
276 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
277 vm_page_t, vm_prot_t);
278 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
280 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
281 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
283 static void mmu_booke_init(mmu_t);
284 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
285 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
286 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
287 static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t);
288 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t,
290 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
292 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
293 vm_object_t, vm_pindex_t, vm_size_t);
294 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
295 static void mmu_booke_page_init(mmu_t, vm_page_t);
296 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
297 static void mmu_booke_pinit(mmu_t, pmap_t);
298 static void mmu_booke_pinit0(mmu_t, pmap_t);
299 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
301 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
302 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
303 static void mmu_booke_release(mmu_t, pmap_t);
304 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
305 static void mmu_booke_remove_all(mmu_t, vm_page_t);
306 static void mmu_booke_remove_write(mmu_t, vm_page_t);
307 static void mmu_booke_zero_page(mmu_t, vm_page_t);
308 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
309 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
310 static void mmu_booke_activate(mmu_t, struct thread *);
311 static void mmu_booke_deactivate(mmu_t, struct thread *);
312 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
313 static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t);
314 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
315 static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t);
316 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t);
317 static void mmu_booke_kremove(mmu_t, vm_offset_t);
318 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
319 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
321 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
322 vm_size_t, vm_size_t *);
323 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
324 vm_size_t, vm_offset_t);
325 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
327 static mmu_method_t mmu_booke_methods[] = {
328 /* pmap dispatcher interface */
329 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
330 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
331 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference),
332 MMUMETHOD(mmu_copy, mmu_booke_copy),
333 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
334 MMUMETHOD(mmu_enter, mmu_booke_enter),
335 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
336 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
337 MMUMETHOD(mmu_extract, mmu_booke_extract),
338 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
339 MMUMETHOD(mmu_init, mmu_booke_init),
340 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
341 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
342 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
343 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
344 MMUMETHOD(mmu_map, mmu_booke_map),
345 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
346 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
347 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
348 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
349 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
350 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
351 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
352 MMUMETHOD(mmu_protect, mmu_booke_protect),
353 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
354 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
355 MMUMETHOD(mmu_release, mmu_booke_release),
356 MMUMETHOD(mmu_remove, mmu_booke_remove),
357 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
358 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
359 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
360 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
361 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
362 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
363 MMUMETHOD(mmu_activate, mmu_booke_activate),
364 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
366 /* Internal interfaces */
367 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
368 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
369 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
370 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
371 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
372 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
373 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
375 /* dumpsys() support */
376 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
377 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
378 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
383 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
394 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
397 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
398 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
400 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
401 ("tlb_miss_lock: tried to lock self"));
403 tlb_lock(pc->pc_booke_tlb_lock);
405 CTR1(KTR_PMAP, "%s: locked", __func__);
412 tlb_miss_unlock(void)
420 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
422 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
423 __func__, pc->pc_cpuid);
425 tlb_unlock(pc->pc_booke_tlb_lock);
427 CTR1(KTR_PMAP, "%s: unlocked", __func__);
433 /* Return number of entries in TLB0. */
435 tlb0_get_tlbconf(void)
439 tlb0_cfg = mfspr(SPR_TLB0CFG);
440 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
441 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
442 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
445 /* Initialize pool of kva ptbl buffers. */
451 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
452 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
453 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
454 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
456 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
457 TAILQ_INIT(&ptbl_buf_freelist);
459 for (i = 0; i < PTBL_BUFS; i++) {
460 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
461 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
465 /* Get a ptbl_buf from the freelist. */
466 static struct ptbl_buf *
469 struct ptbl_buf *buf;
471 mtx_lock(&ptbl_buf_freelist_lock);
472 buf = TAILQ_FIRST(&ptbl_buf_freelist);
474 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
475 mtx_unlock(&ptbl_buf_freelist_lock);
477 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
482 /* Return ptbl buff to free pool. */
484 ptbl_buf_free(struct ptbl_buf *buf)
487 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
489 mtx_lock(&ptbl_buf_freelist_lock);
490 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
491 mtx_unlock(&ptbl_buf_freelist_lock);
495 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
498 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
500 struct ptbl_buf *pbuf;
502 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
504 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
506 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
507 if (pbuf->kva == (vm_offset_t)ptbl) {
508 /* Remove from pmap ptbl buf list. */
509 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
511 /* Free corresponding ptbl buf. */
517 /* Allocate page table. */
519 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
521 vm_page_t mtbl[PTBL_PAGES];
523 struct ptbl_buf *pbuf;
528 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
529 (pmap == kernel_pmap), pdir_idx);
531 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
532 ("ptbl_alloc: invalid pdir_idx"));
533 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
534 ("pte_alloc: valid ptbl entry exists!"));
536 pbuf = ptbl_buf_alloc();
538 panic("pte_alloc: couldn't alloc kernel virtual memory");
540 ptbl = (pte_t *)pbuf->kva;
542 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
544 /* Allocate ptbl pages, this will sleep! */
545 for (i = 0; i < PTBL_PAGES; i++) {
546 pidx = (PTBL_PAGES * pdir_idx) + i;
547 while ((m = vm_page_alloc(NULL, pidx,
548 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
551 vm_page_unlock_queues();
553 vm_page_lock_queues();
559 /* Map allocated pages into kernel_pmap. */
560 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
562 /* Zero whole ptbl. */
563 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
565 /* Add pbuf to the pmap ptbl bufs list. */
566 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
571 /* Free ptbl pages and invalidate pdir entry. */
573 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
581 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
582 (pmap == kernel_pmap), pdir_idx);
584 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
585 ("ptbl_free: invalid pdir_idx"));
587 ptbl = pmap->pm_pdir[pdir_idx];
589 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
591 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
594 * Invalidate the pdir entry as soon as possible, so that other CPUs
595 * don't attempt to look up the page tables we are releasing.
597 mtx_lock_spin(&tlbivax_mutex);
600 pmap->pm_pdir[pdir_idx] = NULL;
603 mtx_unlock_spin(&tlbivax_mutex);
605 for (i = 0; i < PTBL_PAGES; i++) {
606 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
607 pa = pte_vatopa(mmu, kernel_pmap, va);
608 m = PHYS_TO_VM_PAGE(pa);
609 vm_page_free_zero(m);
610 atomic_subtract_int(&cnt.v_wire_count, 1);
611 mmu_booke_kremove(mmu, va);
614 ptbl_free_pmap_ptbl(pmap, ptbl);
618 * Decrement ptbl pages hold count and attempt to free ptbl pages.
619 * Called when removing pte entry from ptbl.
621 * Return 1 if ptbl pages were freed.
624 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
631 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
632 (pmap == kernel_pmap), pdir_idx);
634 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
635 ("ptbl_unhold: invalid pdir_idx"));
636 KASSERT((pmap != kernel_pmap),
637 ("ptbl_unhold: unholding kernel ptbl!"));
639 ptbl = pmap->pm_pdir[pdir_idx];
641 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
642 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
643 ("ptbl_unhold: non kva ptbl"));
645 /* decrement hold count */
646 for (i = 0; i < PTBL_PAGES; i++) {
647 pa = pte_vatopa(mmu, kernel_pmap,
648 (vm_offset_t)ptbl + (i * PAGE_SIZE));
649 m = PHYS_TO_VM_PAGE(pa);
654 * Free ptbl pages if there are no pte etries in this ptbl.
655 * wire_count has the same value for all ptbl pages, so check the last
658 if (m->wire_count == 0) {
659 ptbl_free(mmu, pmap, pdir_idx);
661 //debugf("ptbl_unhold: e (freed ptbl)\n");
669 * Increment hold count for ptbl pages. This routine is used when a new pte
670 * entry is being inserted into the ptbl.
673 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
680 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
683 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
684 ("ptbl_hold: invalid pdir_idx"));
685 KASSERT((pmap != kernel_pmap),
686 ("ptbl_hold: holding kernel ptbl!"));
688 ptbl = pmap->pm_pdir[pdir_idx];
690 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
692 for (i = 0; i < PTBL_PAGES; i++) {
693 pa = pte_vatopa(mmu, kernel_pmap,
694 (vm_offset_t)ptbl + (i * PAGE_SIZE));
695 m = PHYS_TO_VM_PAGE(pa);
700 /* Allocate pv_entry structure. */
707 if (pv_entry_count > pv_entry_high_water)
709 pv = uma_zalloc(pvzone, M_NOWAIT);
714 /* Free pv_entry structure. */
716 pv_free(pv_entry_t pve)
720 uma_zfree(pvzone, pve);
724 /* Allocate and initialize pv_entry structure. */
726 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
730 //int su = (pmap == kernel_pmap);
731 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
732 // (u_int32_t)pmap, va, (u_int32_t)m);
736 panic("pv_insert: no pv entries!");
742 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
743 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
745 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
747 //debugf("pv_insert: e\n");
750 /* Destroy pv entry. */
752 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
756 //int su = (pmap == kernel_pmap);
757 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
759 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
760 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
763 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
764 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
765 /* remove from pv_list */
766 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
767 if (TAILQ_EMPTY(&m->md.pv_list))
768 vm_page_flag_clear(m, PG_WRITEABLE);
770 /* free pv entry struct */
776 //debugf("pv_remove: e\n");
780 * Clean pte entry, try to free page table page if requested.
782 * Return 1 if ptbl pages were freed, otherwise return 0.
785 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
787 unsigned int pdir_idx = PDIR_IDX(va);
788 unsigned int ptbl_idx = PTBL_IDX(va);
793 //int su = (pmap == kernel_pmap);
794 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
795 // su, (u_int32_t)pmap, va, flags);
797 ptbl = pmap->pm_pdir[pdir_idx];
798 KASSERT(ptbl, ("pte_remove: null ptbl"));
800 pte = &ptbl[ptbl_idx];
802 if (pte == NULL || !PTE_ISVALID(pte))
805 if (PTE_ISWIRED(pte))
806 pmap->pm_stats.wired_count--;
808 /* Handle managed entry. */
809 if (PTE_ISMANAGED(pte)) {
810 /* Get vm_page_t for mapped pte. */
811 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
813 if (PTE_ISMODIFIED(pte))
816 if (PTE_ISREFERENCED(pte))
817 vm_page_flag_set(m, PG_REFERENCED);
819 pv_remove(pmap, va, m);
822 mtx_lock_spin(&tlbivax_mutex);
825 tlb0_flush_entry(va);
830 mtx_unlock_spin(&tlbivax_mutex);
832 pmap->pm_stats.resident_count--;
834 if (flags & PTBL_UNHOLD) {
835 //debugf("pte_remove: e (unhold)\n");
836 return (ptbl_unhold(mmu, pmap, pdir_idx));
839 //debugf("pte_remove: e\n");
844 * Insert PTE for a given page and virtual address.
847 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
849 unsigned int pdir_idx = PDIR_IDX(va);
850 unsigned int ptbl_idx = PTBL_IDX(va);
853 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
854 pmap == kernel_pmap, pmap, va);
856 /* Get the page table pointer. */
857 ptbl = pmap->pm_pdir[pdir_idx];
860 /* Allocate page table pages. */
861 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
864 * Check if there is valid mapping for requested
865 * va, if there is, remove it.
867 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
868 if (PTE_ISVALID(pte)) {
869 pte_remove(mmu, pmap, va, PTBL_HOLD);
872 * pte is not used, increment hold count
875 if (pmap != kernel_pmap)
876 ptbl_hold(mmu, pmap, pdir_idx);
881 * Insert pv_entry into pv_list for mapped page if part of managed
884 if ((m->flags & PG_FICTITIOUS) == 0) {
885 if ((m->flags & PG_UNMANAGED) == 0) {
886 flags |= PTE_MANAGED;
888 /* Create and insert pv entry. */
889 pv_insert(pmap, va, m);
893 pmap->pm_stats.resident_count++;
895 mtx_lock_spin(&tlbivax_mutex);
898 tlb0_flush_entry(va);
899 if (pmap->pm_pdir[pdir_idx] == NULL) {
901 * If we just allocated a new page table, hook it in
904 pmap->pm_pdir[pdir_idx] = ptbl;
906 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
907 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
908 pte->flags |= (PTE_VALID | flags);
911 mtx_unlock_spin(&tlbivax_mutex);
914 /* Return the pa for the given pmap/va. */
916 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
921 pte = pte_find(mmu, pmap, va);
922 if ((pte != NULL) && PTE_ISVALID(pte))
923 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
927 /* Get a pointer to a PTE in a page table. */
929 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
931 unsigned int pdir_idx = PDIR_IDX(va);
932 unsigned int ptbl_idx = PTBL_IDX(va);
934 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
936 if (pmap->pm_pdir[pdir_idx])
937 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
942 /**************************************************************************/
944 /**************************************************************************/
947 * This is called during booke_init, before the system is really initialized.
950 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
952 vm_offset_t phys_kernelend;
953 struct mem_region *mp, *mp1;
956 u_int phys_avail_count;
957 vm_size_t physsz, hwphyssz, kstack0_sz;
958 vm_offset_t kernel_pdir, kstack0, va;
959 vm_paddr_t kstack0_phys;
963 debugf("mmu_booke_bootstrap: entered\n");
965 /* Initialize invalidation mutex */
966 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
968 /* Read TLB0 size and associativity. */
971 /* Align kernel start and end address (kernel image). */
972 kernstart = trunc_page(start);
973 data_start = round_page(kernelend);
974 kernsize = data_start - kernstart;
976 data_end = data_start;
978 /* Allocate space for the message buffer. */
979 msgbufp = (struct msgbuf *)data_end;
980 data_end += msgbufsize;
981 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
984 data_end = round_page(data_end);
986 /* Allocate the dynamic per-cpu area. */
987 dpcpu = (void *)data_end;
988 data_end += DPCPU_SIZE;
989 dpcpu_init(dpcpu, 0);
991 /* Allocate space for ptbl_bufs. */
992 ptbl_bufs = (struct ptbl_buf *)data_end;
993 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
994 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
997 data_end = round_page(data_end);
999 /* Allocate PTE tables for kernel KVA. */
1000 kernel_pdir = data_end;
1001 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1002 PDIR_SIZE - 1) / PDIR_SIZE;
1003 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1004 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1005 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1007 debugf(" data_end: 0x%08x\n", data_end);
1008 if (data_end - kernstart > 0x1000000) {
1009 data_end = (data_end + 0x3fffff) & ~0x3fffff;
1010 tlb1_mapin_region(kernstart + 0x1000000,
1011 kernload + 0x1000000, data_end - kernstart - 0x1000000);
1013 data_end = (data_end + 0xffffff) & ~0xffffff;
1015 debugf(" updated data_end: 0x%08x\n", data_end);
1017 kernsize += data_end - data_start;
1020 * Clear the structures - note we can only do it safely after the
1021 * possible additional TLB1 translations are in place (above) so that
1022 * all range up to the currently calculated 'data_end' is covered.
1024 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1025 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1027 /*******************************************************/
1028 /* Set the start and end of kva. */
1029 /*******************************************************/
1030 virtual_avail = round_page(data_end);
1031 virtual_end = VM_MAX_KERNEL_ADDRESS;
1033 /* Allocate KVA space for page zero/copy operations. */
1034 zero_page_va = virtual_avail;
1035 virtual_avail += PAGE_SIZE;
1036 zero_page_idle_va = virtual_avail;
1037 virtual_avail += PAGE_SIZE;
1038 copy_page_src_va = virtual_avail;
1039 virtual_avail += PAGE_SIZE;
1040 copy_page_dst_va = virtual_avail;
1041 virtual_avail += PAGE_SIZE;
1042 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1043 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1044 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1045 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1047 /* Initialize page zero/copy mutexes. */
1048 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1049 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1051 /* Allocate KVA space for ptbl bufs. */
1052 ptbl_buf_pool_vabase = virtual_avail;
1053 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1054 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1055 ptbl_buf_pool_vabase, virtual_avail);
1057 /* Calculate corresponding physical addresses for the kernel region. */
1058 phys_kernelend = kernload + kernsize;
1059 debugf("kernel image and allocated data:\n");
1060 debugf(" kernload = 0x%08x\n", kernload);
1061 debugf(" kernstart = 0x%08x\n", kernstart);
1062 debugf(" kernsize = 0x%08x\n", kernsize);
1064 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1065 panic("mmu_booke_bootstrap: phys_avail too small");
1068 * Remove kernel physical address range from avail regions list. Page
1069 * align all regions. Non-page aligned memory isn't very interesting
1070 * to us. Also, sort the entries for ascending addresses.
1073 /* Retrieve phys/avail mem regions */
1074 mem_regions(&physmem_regions, &physmem_regions_sz,
1075 &availmem_regions, &availmem_regions_sz);
1077 cnt = availmem_regions_sz;
1078 debugf("processing avail regions:\n");
1079 for (mp = availmem_regions; mp->mr_size; mp++) {
1081 e = mp->mr_start + mp->mr_size;
1082 debugf(" %08x-%08x -> ", s, e);
1083 /* Check whether this region holds all of the kernel. */
1084 if (s < kernload && e > phys_kernelend) {
1085 availmem_regions[cnt].mr_start = phys_kernelend;
1086 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1089 /* Look whether this regions starts within the kernel. */
1090 if (s >= kernload && s < phys_kernelend) {
1091 if (e <= phys_kernelend)
1095 /* Now look whether this region ends within the kernel. */
1096 if (e > kernload && e <= phys_kernelend) {
1101 /* Now page align the start and size of the region. */
1107 debugf("%08x-%08x = %x\n", s, e, sz);
1109 /* Check whether some memory is left here. */
1113 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1119 /* Do an insertion sort. */
1120 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1121 if (s < mp1->mr_start)
1124 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1132 availmem_regions_sz = cnt;
1134 /*******************************************************/
1135 /* Steal physical memory for kernel stack from the end */
1136 /* of the first avail region */
1137 /*******************************************************/
1138 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1139 kstack0_phys = availmem_regions[0].mr_start +
1140 availmem_regions[0].mr_size;
1141 kstack0_phys -= kstack0_sz;
1142 availmem_regions[0].mr_size -= kstack0_sz;
1144 /*******************************************************/
1145 /* Fill in phys_avail table, based on availmem_regions */
1146 /*******************************************************/
1147 phys_avail_count = 0;
1150 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1152 debugf("fill in phys_avail:\n");
1153 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1155 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1156 availmem_regions[i].mr_start,
1157 availmem_regions[i].mr_start +
1158 availmem_regions[i].mr_size,
1159 availmem_regions[i].mr_size);
1161 if (hwphyssz != 0 &&
1162 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1163 debugf(" hw.physmem adjust\n");
1164 if (physsz < hwphyssz) {
1165 phys_avail[j] = availmem_regions[i].mr_start;
1167 availmem_regions[i].mr_start +
1175 phys_avail[j] = availmem_regions[i].mr_start;
1176 phys_avail[j + 1] = availmem_regions[i].mr_start +
1177 availmem_regions[i].mr_size;
1179 physsz += availmem_regions[i].mr_size;
1181 physmem = btoc(physsz);
1183 /* Calculate the last available physical address. */
1184 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1186 Maxmem = powerpc_btop(phys_avail[i + 1]);
1188 debugf("Maxmem = 0x%08lx\n", Maxmem);
1189 debugf("phys_avail_count = %d\n", phys_avail_count);
1190 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1193 /*******************************************************/
1194 /* Initialize (statically allocated) kernel pmap. */
1195 /*******************************************************/
1196 PMAP_LOCK_INIT(kernel_pmap);
1197 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1199 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1200 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1201 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1202 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1204 /* Initialize kernel pdir */
1205 for (i = 0; i < kernel_ptbls; i++)
1206 kernel_pmap->pm_pdir[kptbl_min + i] =
1207 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1209 for (i = 0; i < MAXCPU; i++) {
1210 kernel_pmap->pm_tid[i] = TID_KERNEL;
1212 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1213 tidbusy[i][0] = kernel_pmap;
1217 * Fill in PTEs covering kernel code and data. They are not required
1218 * for address translation, as this area is covered by static TLB1
1219 * entries, but for pte_vatopa() to work correctly with kernel area
1222 for (va = KERNBASE; va < data_end; va += PAGE_SIZE) {
1223 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1224 pte->rpn = kernload + (va - KERNBASE);
1225 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1228 /* Mark kernel_pmap active on all CPUs */
1229 CPU_FILL(&kernel_pmap->pm_active);
1231 /*******************************************************/
1233 /*******************************************************/
1235 /* Enter kstack0 into kernel map, provide guard page */
1236 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1237 thread0.td_kstack = kstack0;
1238 thread0.td_kstack_pages = KSTACK_PAGES;
1240 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1241 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1242 kstack0_phys, kstack0_phys + kstack0_sz);
1243 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1245 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1246 for (i = 0; i < KSTACK_PAGES; i++) {
1247 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1248 kstack0 += PAGE_SIZE;
1249 kstack0_phys += PAGE_SIZE;
1252 debugf("virtual_avail = %08x\n", virtual_avail);
1253 debugf("virtual_end = %08x\n", virtual_end);
1255 debugf("mmu_booke_bootstrap: exit\n");
1259 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1264 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1265 * have the snapshot of its contents in the s/w tlb1[] table, so use
1266 * these values directly to (re)program AP's TLB1 hardware.
1268 for (i = 0; i < tlb1_idx; i ++) {
1269 /* Skip invalid entries */
1270 if (!(tlb1[i].mas1 & MAS1_VALID))
1273 tlb1_write_entry(i);
1276 set_mas4_defaults();
1280 * Get the physical page address for the given pmap/virtual address.
1283 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1288 pa = pte_vatopa(mmu, pmap, va);
1295 * Extract the physical page address associated with the given
1296 * kernel virtual address.
1299 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1302 return (pte_vatopa(mmu, kernel_pmap, va));
1306 * Initialize the pmap module.
1307 * Called by vm_init, to initialize any structures that the pmap
1308 * system needs to map virtual memory.
1311 mmu_booke_init(mmu_t mmu)
1313 int shpgperproc = PMAP_SHPGPERPROC;
1316 * Initialize the address space (zone) for the pv entries. Set a
1317 * high water mark so that the system can recover from excessive
1318 * numbers of pv entries.
1320 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1321 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1323 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1324 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1326 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1327 pv_entry_high_water = 9 * (pv_entry_max / 10);
1329 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max);
1331 /* Pre-fill pvzone with initial number of pv entries. */
1332 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1334 /* Initialize ptbl allocation. */
1339 * Map a list of wired pages into kernel virtual address space. This is
1340 * intended for temporary mappings which do not need page modification or
1341 * references recorded. Existing mappings in the region are overwritten.
1344 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1349 while (count-- > 0) {
1350 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1357 * Remove page mappings from kernel virtual address space. Intended for
1358 * temporary mappings entered by mmu_booke_qenter.
1361 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1366 while (count-- > 0) {
1367 mmu_booke_kremove(mmu, va);
1373 * Map a wired page into kernel virtual address space.
1376 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1378 unsigned int pdir_idx = PDIR_IDX(va);
1379 unsigned int ptbl_idx = PTBL_IDX(va);
1383 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1384 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1387 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID);
1390 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1392 mtx_lock_spin(&tlbivax_mutex);
1395 if (PTE_ISVALID(pte)) {
1397 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1399 /* Flush entry from TLB0 */
1400 tlb0_flush_entry(va);
1403 pte->rpn = pa & ~PTE_PA_MASK;
1406 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1407 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1408 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1410 /* Flush the real memory from the instruction cache. */
1411 if ((flags & (PTE_I | PTE_G)) == 0) {
1412 __syncicache((void *)va, PAGE_SIZE);
1416 mtx_unlock_spin(&tlbivax_mutex);
1420 * Remove a page from kernel page table.
1423 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1425 unsigned int pdir_idx = PDIR_IDX(va);
1426 unsigned int ptbl_idx = PTBL_IDX(va);
1429 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1431 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1432 (va <= VM_MAX_KERNEL_ADDRESS)),
1433 ("mmu_booke_kremove: invalid va"));
1435 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1437 if (!PTE_ISVALID(pte)) {
1439 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1444 mtx_lock_spin(&tlbivax_mutex);
1447 /* Invalidate entry in TLB0, update PTE. */
1448 tlb0_flush_entry(va);
1453 mtx_unlock_spin(&tlbivax_mutex);
1457 * Initialize pmap associated with process 0.
1460 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1463 mmu_booke_pinit(mmu, pmap);
1464 PCPU_SET(curpmap, pmap);
1468 * Initialize a preallocated and zeroed pmap structure,
1469 * such as one in a vmspace structure.
1472 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1476 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1477 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1479 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1481 PMAP_LOCK_INIT(pmap);
1482 for (i = 0; i < MAXCPU; i++)
1483 pmap->pm_tid[i] = TID_NONE;
1484 CPU_ZERO(&kernel_pmap->pm_active);
1485 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1486 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1487 TAILQ_INIT(&pmap->pm_ptbl_list);
1491 * Release any resources held by the given physical map.
1492 * Called when a pmap initialized by mmu_booke_pinit is being released.
1493 * Should only be called if the map contains no valid mappings.
1496 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1499 KASSERT(pmap->pm_stats.resident_count == 0,
1500 ("pmap_release: pmap resident count %ld != 0",
1501 pmap->pm_stats.resident_count));
1503 PMAP_LOCK_DESTROY(pmap);
1507 * Insert the given physical page at the specified virtual address in the
1508 * target physical map with the protection requested. If specified the page
1509 * will be wired down.
1512 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1513 vm_prot_t prot, boolean_t wired)
1516 vm_page_lock_queues();
1518 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1519 vm_page_unlock_queues();
1524 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1525 vm_prot_t prot, boolean_t wired)
1532 pa = VM_PAGE_TO_PHYS(m);
1533 su = (pmap == kernel_pmap);
1536 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1537 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1538 // (u_int32_t)pmap, su, pmap->pm_tid,
1539 // (u_int32_t)m, va, pa, prot, wired);
1542 KASSERT(((va >= virtual_avail) &&
1543 (va <= VM_MAX_KERNEL_ADDRESS)),
1544 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1546 KASSERT((va <= VM_MAXUSER_ADDRESS),
1547 ("mmu_booke_enter_locked: user pmap, non user va"));
1549 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1550 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object),
1551 ("mmu_booke_enter_locked: page %p is not busy", m));
1553 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1556 * If there is an existing mapping, and the physical address has not
1557 * changed, must be protection or wiring change.
1559 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1560 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1563 * Before actually updating pte->flags we calculate and
1564 * prepare its new value in a helper var.
1567 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1569 /* Wiring change, just update stats. */
1571 if (!PTE_ISWIRED(pte)) {
1573 pmap->pm_stats.wired_count++;
1576 if (PTE_ISWIRED(pte)) {
1577 flags &= ~PTE_WIRED;
1578 pmap->pm_stats.wired_count--;
1582 if (prot & VM_PROT_WRITE) {
1583 /* Add write permissions. */
1588 if ((flags & PTE_MANAGED) != 0)
1589 vm_page_flag_set(m, PG_WRITEABLE);
1591 /* Handle modified pages, sense modify status. */
1594 * The PTE_MODIFIED flag could be set by underlying
1595 * TLB misses since we last read it (above), possibly
1596 * other CPUs could update it so we check in the PTE
1597 * directly rather than rely on that saved local flags
1600 if (PTE_ISMODIFIED(pte))
1604 if (prot & VM_PROT_EXECUTE) {
1610 * Check existing flags for execute permissions: if we
1611 * are turning execute permissions on, icache should
1614 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1618 flags &= ~PTE_REFERENCED;
1621 * The new flags value is all calculated -- only now actually
1624 mtx_lock_spin(&tlbivax_mutex);
1627 tlb0_flush_entry(va);
1631 mtx_unlock_spin(&tlbivax_mutex);
1635 * If there is an existing mapping, but it's for a different
1636 * physical address, pte_enter() will delete the old mapping.
1638 //if ((pte != NULL) && PTE_ISVALID(pte))
1639 // debugf("mmu_booke_enter_locked: replace\n");
1641 // debugf("mmu_booke_enter_locked: new\n");
1643 /* Now set up the flags and install the new mapping. */
1644 flags = (PTE_SR | PTE_VALID);
1650 if (prot & VM_PROT_WRITE) {
1655 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0)
1656 vm_page_flag_set(m, PG_WRITEABLE);
1659 if (prot & VM_PROT_EXECUTE) {
1665 /* If its wired update stats. */
1667 pmap->pm_stats.wired_count++;
1671 pte_enter(mmu, pmap, m, va, flags);
1673 /* Flush the real memory from the instruction cache. */
1674 if (prot & VM_PROT_EXECUTE)
1678 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1679 __syncicache((void *)va, PAGE_SIZE);
1685 * Maps a sequence of resident pages belonging to the same object.
1686 * The sequence begins with the given page m_start. This page is
1687 * mapped at the given virtual address start. Each subsequent page is
1688 * mapped at a virtual address that is offset from start by the same
1689 * amount as the page is offset from m_start within the object. The
1690 * last page in the sequence is the page with the largest offset from
1691 * m_start that can be mapped at a virtual address less than the given
1692 * virtual address end. Not every virtual page between start and end
1693 * is mapped; only those for which a resident page exists with the
1694 * corresponding offset from m_start are mapped.
1697 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1698 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1701 vm_pindex_t diff, psize;
1703 psize = atop(end - start);
1705 vm_page_lock_queues();
1707 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1708 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1709 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1710 m = TAILQ_NEXT(m, listq);
1712 vm_page_unlock_queues();
1717 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1721 vm_page_lock_queues();
1723 mmu_booke_enter_locked(mmu, pmap, va, m,
1724 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1725 vm_page_unlock_queues();
1730 * Remove the given range of addresses from the specified map.
1732 * It is assumed that the start and end are properly rounded to the page size.
1735 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1740 int su = (pmap == kernel_pmap);
1742 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1743 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1746 KASSERT(((va >= virtual_avail) &&
1747 (va <= VM_MAX_KERNEL_ADDRESS)),
1748 ("mmu_booke_remove: kernel pmap, non kernel va"));
1750 KASSERT((va <= VM_MAXUSER_ADDRESS),
1751 ("mmu_booke_remove: user pmap, non user va"));
1754 if (PMAP_REMOVE_DONE(pmap)) {
1755 //debugf("mmu_booke_remove: e (empty)\n");
1759 hold_flag = PTBL_HOLD_FLAG(pmap);
1760 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1762 vm_page_lock_queues();
1764 for (; va < endva; va += PAGE_SIZE) {
1765 pte = pte_find(mmu, pmap, va);
1766 if ((pte != NULL) && PTE_ISVALID(pte))
1767 pte_remove(mmu, pmap, va, hold_flag);
1770 vm_page_unlock_queues();
1772 //debugf("mmu_booke_remove: e\n");
1776 * Remove physical page from all pmaps in which it resides.
1779 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1784 vm_page_lock_queues();
1785 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1786 pvn = TAILQ_NEXT(pv, pv_link);
1788 PMAP_LOCK(pv->pv_pmap);
1789 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1790 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1791 PMAP_UNLOCK(pv->pv_pmap);
1793 vm_page_flag_clear(m, PG_WRITEABLE);
1794 vm_page_unlock_queues();
1798 * Map a range of physical addresses into kernel virtual address space.
1801 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1802 vm_offset_t pa_end, int prot)
1804 vm_offset_t sva = *virt;
1805 vm_offset_t va = sva;
1807 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1808 // sva, pa_start, pa_end);
1810 while (pa_start < pa_end) {
1811 mmu_booke_kenter(mmu, va, pa_start);
1813 pa_start += PAGE_SIZE;
1817 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1822 * The pmap must be activated before it's address space can be accessed in any
1826 mmu_booke_activate(mmu_t mmu, struct thread *td)
1831 pmap = &td->td_proc->p_vmspace->vm_pmap;
1833 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1834 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1836 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1838 mtx_lock_spin(&sched_lock);
1840 cpuid = PCPU_GET(cpuid);
1841 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1842 PCPU_SET(curpmap, pmap);
1844 if (pmap->pm_tid[cpuid] == TID_NONE)
1847 /* Load PID0 register with pmap tid value. */
1848 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1849 __asm __volatile("isync");
1851 mtx_unlock_spin(&sched_lock);
1853 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1854 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1858 * Deactivate the specified process's address space.
1861 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1865 pmap = &td->td_proc->p_vmspace->vm_pmap;
1867 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1868 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1870 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1871 PCPU_SET(curpmap, NULL);
1875 * Copy the range specified by src_addr/len
1876 * from the source map to the range dst_addr/len
1877 * in the destination map.
1879 * This routine is only advisory and need not do anything.
1882 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1883 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1889 * Set the physical protection on the specified range of this map as requested.
1892 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1899 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1900 mmu_booke_remove(mmu, pmap, sva, eva);
1904 if (prot & VM_PROT_WRITE)
1907 vm_page_lock_queues();
1909 for (va = sva; va < eva; va += PAGE_SIZE) {
1910 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1911 if (PTE_ISVALID(pte)) {
1912 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1914 mtx_lock_spin(&tlbivax_mutex);
1917 /* Handle modified pages. */
1918 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1921 tlb0_flush_entry(va);
1922 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1925 mtx_unlock_spin(&tlbivax_mutex);
1930 vm_page_unlock_queues();
1934 * Clear the write and modified bits in each of the given page's mappings.
1937 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
1942 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
1943 ("mmu_booke_remove_write: page %p is not managed", m));
1946 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by
1947 * another thread while the object is locked. Thus, if PG_WRITEABLE
1948 * is clear, no page table entries need updating.
1950 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1951 if ((m->oflags & VPO_BUSY) == 0 &&
1952 (m->flags & PG_WRITEABLE) == 0)
1954 vm_page_lock_queues();
1955 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1956 PMAP_LOCK(pv->pv_pmap);
1957 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
1958 if (PTE_ISVALID(pte)) {
1959 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1961 mtx_lock_spin(&tlbivax_mutex);
1964 /* Handle modified pages. */
1965 if (PTE_ISMODIFIED(pte))
1968 /* Flush mapping from TLB0. */
1969 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1972 mtx_unlock_spin(&tlbivax_mutex);
1975 PMAP_UNLOCK(pv->pv_pmap);
1977 vm_page_flag_clear(m, PG_WRITEABLE);
1978 vm_page_unlock_queues();
1982 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
1991 va = trunc_page(va);
1992 sz = round_page(sz);
1994 vm_page_lock_queues();
1995 pmap = PCPU_GET(curpmap);
1996 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
1999 pte = pte_find(mmu, pm, va);
2000 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2006 /* Create a mapping in the active pmap. */
2008 m = PHYS_TO_VM_PAGE(pa);
2010 pte_enter(mmu, pmap, m, addr,
2011 PTE_SR | PTE_VALID | PTE_UR);
2012 __syncicache((void *)addr, PAGE_SIZE);
2013 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2016 __syncicache((void *)va, PAGE_SIZE);
2021 vm_page_unlock_queues();
2025 * Atomically extract and hold the physical page with the given
2026 * pmap and virtual address pair if that mapping permits the given
2030 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2042 pte = pte_find(mmu, pmap, va);
2043 if ((pte != NULL) && PTE_ISVALID(pte)) {
2044 if (pmap == kernel_pmap)
2049 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2050 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2052 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2063 * Initialize a vm_page's machine-dependent fields.
2066 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2069 TAILQ_INIT(&m->md.pv_list);
2073 * mmu_booke_zero_page_area zeros the specified hardware page by
2074 * mapping it into virtual memory and using bzero to clear
2077 * off and size must reside within a single page.
2080 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2084 /* XXX KASSERT off and size are within a single page? */
2086 mtx_lock(&zero_page_mutex);
2089 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2090 bzero((caddr_t)va + off, size);
2091 mmu_booke_kremove(mmu, va);
2093 mtx_unlock(&zero_page_mutex);
2097 * mmu_booke_zero_page zeros the specified hardware page.
2100 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2103 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2107 * mmu_booke_copy_page copies the specified (machine independent) page by
2108 * mapping the page into virtual memory and using memcopy to copy the page,
2109 * one machine dependent page at a time.
2112 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2114 vm_offset_t sva, dva;
2116 sva = copy_page_src_va;
2117 dva = copy_page_dst_va;
2119 mtx_lock(©_page_mutex);
2120 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2121 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2122 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2123 mmu_booke_kremove(mmu, dva);
2124 mmu_booke_kremove(mmu, sva);
2125 mtx_unlock(©_page_mutex);
2129 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2130 * into virtual memory and using bzero to clear its contents. This is intended
2131 * to be called from the vm_pagezero process only and outside of Giant. No
2135 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2139 va = zero_page_idle_va;
2140 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2141 bzero((caddr_t)va, PAGE_SIZE);
2142 mmu_booke_kremove(mmu, va);
2146 * Return whether or not the specified physical page was modified
2147 * in any of physical maps.
2150 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2156 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2157 ("mmu_booke_is_modified: page %p is not managed", m));
2161 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be
2162 * concurrently set while the object is locked. Thus, if PG_WRITEABLE
2163 * is clear, no PTEs can be modified.
2165 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2166 if ((m->oflags & VPO_BUSY) == 0 &&
2167 (m->flags & PG_WRITEABLE) == 0)
2169 vm_page_lock_queues();
2170 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2171 PMAP_LOCK(pv->pv_pmap);
2172 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2174 if (PTE_ISMODIFIED(pte))
2177 PMAP_UNLOCK(pv->pv_pmap);
2181 vm_page_unlock_queues();
2186 * Return whether or not the specified virtual address is eligible
2190 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2197 * Return whether or not the specified physical page was referenced
2198 * in any physical maps.
2201 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2207 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2208 ("mmu_booke_is_referenced: page %p is not managed", m));
2210 vm_page_lock_queues();
2211 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2212 PMAP_LOCK(pv->pv_pmap);
2213 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2215 if (PTE_ISREFERENCED(pte))
2218 PMAP_UNLOCK(pv->pv_pmap);
2222 vm_page_unlock_queues();
2227 * Clear the modify bits on the specified physical page.
2230 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2235 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2236 ("mmu_booke_clear_modify: page %p is not managed", m));
2237 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
2238 KASSERT((m->oflags & VPO_BUSY) == 0,
2239 ("mmu_booke_clear_modify: page %p is busy", m));
2242 * If the page is not PG_WRITEABLE, then no PTEs can be modified.
2243 * If the object containing the page is locked and the page is not
2244 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set.
2246 if ((m->flags & PG_WRITEABLE) == 0)
2248 vm_page_lock_queues();
2249 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2250 PMAP_LOCK(pv->pv_pmap);
2251 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2253 mtx_lock_spin(&tlbivax_mutex);
2256 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2257 tlb0_flush_entry(pv->pv_va);
2258 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2263 mtx_unlock_spin(&tlbivax_mutex);
2265 PMAP_UNLOCK(pv->pv_pmap);
2267 vm_page_unlock_queues();
2271 * Return a count of reference bits for a page, clearing those bits.
2272 * It is not necessary for every reference bit to be cleared, but it
2273 * is necessary that 0 only be returned when there are truly no
2274 * reference bits set.
2276 * XXX: The exact number of bits to check and clear is a matter that
2277 * should be tested and standardized at some point in the future for
2278 * optimal aging of shared pages.
2281 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2287 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2288 ("mmu_booke_ts_referenced: page %p is not managed", m));
2290 vm_page_lock_queues();
2291 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2292 PMAP_LOCK(pv->pv_pmap);
2293 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2295 if (PTE_ISREFERENCED(pte)) {
2296 mtx_lock_spin(&tlbivax_mutex);
2299 tlb0_flush_entry(pv->pv_va);
2300 pte->flags &= ~PTE_REFERENCED;
2303 mtx_unlock_spin(&tlbivax_mutex);
2306 PMAP_UNLOCK(pv->pv_pmap);
2311 PMAP_UNLOCK(pv->pv_pmap);
2313 vm_page_unlock_queues();
2318 * Clear the reference bit on the specified physical page.
2321 mmu_booke_clear_reference(mmu_t mmu, vm_page_t m)
2326 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2327 ("mmu_booke_clear_reference: page %p is not managed", m));
2328 vm_page_lock_queues();
2329 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2330 PMAP_LOCK(pv->pv_pmap);
2331 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2333 if (PTE_ISREFERENCED(pte)) {
2334 mtx_lock_spin(&tlbivax_mutex);
2337 tlb0_flush_entry(pv->pv_va);
2338 pte->flags &= ~PTE_REFERENCED;
2341 mtx_unlock_spin(&tlbivax_mutex);
2344 PMAP_UNLOCK(pv->pv_pmap);
2346 vm_page_unlock_queues();
2350 * Change wiring attribute for a map/virtual-address pair.
2353 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2358 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2360 if (!PTE_ISWIRED(pte)) {
2361 pte->flags |= PTE_WIRED;
2362 pmap->pm_stats.wired_count++;
2365 if (PTE_ISWIRED(pte)) {
2366 pte->flags &= ~PTE_WIRED;
2367 pmap->pm_stats.wired_count--;
2375 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2376 * page. This count may be changed upwards or downwards in the future; it is
2377 * only necessary that true be returned for a small subset of pmaps for proper
2381 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2387 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2388 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2391 vm_page_lock_queues();
2392 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2393 if (pv->pv_pmap == pmap) {
2400 vm_page_unlock_queues();
2405 * Return the number of managed mappings to the given physical page that are
2409 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2415 if ((m->flags & PG_FICTITIOUS) != 0)
2417 vm_page_lock_queues();
2418 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2419 PMAP_LOCK(pv->pv_pmap);
2420 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2421 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2423 PMAP_UNLOCK(pv->pv_pmap);
2425 vm_page_unlock_queues();
2430 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2436 * This currently does not work for entries that
2437 * overlap TLB1 entries.
2439 for (i = 0; i < tlb1_idx; i ++) {
2440 if (tlb1_iomapped(i, pa, size, &va) == 0)
2448 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2455 /* Raw physical memory dumps don't have a virtual address. */
2456 if (md->md_vaddr == ~0UL) {
2457 /* We always map a 256MB page at 256M. */
2458 gran = 256 * 1024 * 1024;
2459 pa = md->md_paddr + ofs;
2460 ppa = pa & ~(gran - 1);
2463 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2464 if (*sz > (gran - ofs))
2469 /* Minidumps are based on virtual memory addresses. */
2470 va = md->md_vaddr + ofs;
2471 if (va >= kernstart + kernsize) {
2472 gran = PAGE_SIZE - (va & PAGE_MASK);
2480 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2484 /* Raw physical memory dumps don't have a virtual address. */
2485 if (md->md_vaddr == ~0UL) {
2487 tlb1[tlb1_idx].mas1 = 0;
2488 tlb1[tlb1_idx].mas2 = 0;
2489 tlb1[tlb1_idx].mas3 = 0;
2490 tlb1_write_entry(tlb1_idx);
2494 /* Minidumps are based on virtual memory addresses. */
2495 /* Nothing to do... */
2499 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2501 static struct pmap_md md;
2505 if (dumpsys_minidump) {
2506 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2508 /* 1st: kernel .data and .bss. */
2510 md.md_vaddr = trunc_page((uintptr_t)_etext);
2511 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2514 switch (prev->md_index) {
2516 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2518 md.md_vaddr = data_start;
2519 md.md_size = data_end - data_start;
2522 /* 3rd: kernel VM. */
2523 va = prev->md_vaddr + prev->md_size;
2524 /* Find start of next chunk (from va). */
2525 while (va < virtual_end) {
2526 /* Don't dump the buffer cache. */
2527 if (va >= kmi.buffer_sva &&
2528 va < kmi.buffer_eva) {
2529 va = kmi.buffer_eva;
2532 pte = pte_find(mmu, kernel_pmap, va);
2533 if (pte != NULL && PTE_ISVALID(pte))
2537 if (va < virtual_end) {
2540 /* Find last page in chunk. */
2541 while (va < virtual_end) {
2542 /* Don't run into the buffer cache. */
2543 if (va == kmi.buffer_sva)
2545 pte = pte_find(mmu, kernel_pmap, va);
2546 if (pte == NULL || !PTE_ISVALID(pte))
2550 md.md_size = va - md.md_vaddr;
2558 } else { /* minidumps */
2559 mem_regions(&physmem_regions, &physmem_regions_sz,
2560 &availmem_regions, &availmem_regions_sz);
2563 /* first physical chunk. */
2564 md.md_paddr = physmem_regions[0].mr_start;
2565 md.md_size = physmem_regions[0].mr_size;
2568 } else if (md.md_index < physmem_regions_sz) {
2569 md.md_paddr = physmem_regions[md.md_index].mr_start;
2570 md.md_size = physmem_regions[md.md_index].mr_size;
2574 /* There's no next physical chunk. */
2583 * Map a set of physical memory pages into the kernel virtual address space.
2584 * Return a pointer to where it is mapped. This routine is intended to be used
2585 * for mapping device memory, NOT real memory.
2588 mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2594 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa);
2598 sz = 1 << (ilog2(size) & ~1);
2600 printf("Wiring VA=%x to PA=%x (size=%x), "
2601 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2602 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO);
2612 * 'Unmap' a range mapped by mmu_booke_mapdev().
2615 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2617 vm_offset_t base, offset;
2620 * Unmap only if this is inside kernel virtual space.
2622 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2623 base = trunc_page(va);
2624 offset = va & PAGE_MASK;
2625 size = roundup(offset + size, PAGE_SIZE);
2626 kmem_free(kernel_map, base, size);
2631 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2632 * specified pmap. This eliminates the blast of soft faults on process startup
2633 * and immediately after an mmap.
2636 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2637 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2640 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
2641 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2642 ("mmu_booke_object_init_pt: non-device object"));
2646 * Perform the pmap work for mincore.
2649 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2650 vm_paddr_t *locked_pa)
2657 /**************************************************************************/
2659 /**************************************************************************/
2662 * Allocate a TID. If necessary, steal one from someone else.
2663 * The new TID is flushed from the TLB before returning.
2666 tid_alloc(pmap_t pmap)
2671 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2673 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2675 thiscpu = PCPU_GET(cpuid);
2677 tid = PCPU_GET(tid_next);
2680 PCPU_SET(tid_next, tid + 1);
2682 /* If we are stealing TID then clear the relevant pmap's field */
2683 if (tidbusy[thiscpu][tid] != NULL) {
2685 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2687 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2689 /* Flush all entries from TLB0 matching this TID. */
2693 tidbusy[thiscpu][tid] = pmap;
2694 pmap->pm_tid[thiscpu] = tid;
2695 __asm __volatile("msync; isync");
2697 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2698 PCPU_GET(tid_next));
2703 /**************************************************************************/
2705 /**************************************************************************/
2708 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2718 if (mas1 & MAS1_VALID)
2723 if (mas1 & MAS1_IPROT)
2728 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2729 tid = MAS1_GETTID(mas1);
2731 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2734 size = tsize2size(tsize);
2736 debugf("%3d: (%s) [AS=%d] "
2737 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2738 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2739 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2742 /* Convert TLB0 va and way number to tlb0[] table index. */
2743 static inline unsigned int
2744 tlb0_tableidx(vm_offset_t va, unsigned int way)
2748 idx = (way * TLB0_ENTRIES_PER_WAY);
2749 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2754 * Invalidate TLB0 entry.
2757 tlb0_flush_entry(vm_offset_t va)
2760 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2762 mtx_assert(&tlbivax_mutex, MA_OWNED);
2764 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2765 __asm __volatile("isync; msync");
2766 __asm __volatile("tlbsync; msync");
2768 CTR1(KTR_PMAP, "%s: e", __func__);
2771 /* Print out contents of the MAS registers for each TLB0 entry */
2773 tlb0_print_tlbentries(void)
2775 uint32_t mas0, mas1, mas2, mas3, mas7;
2776 int entryidx, way, idx;
2778 debugf("TLB0 entries:\n");
2779 for (way = 0; way < TLB0_WAYS; way ++)
2780 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2782 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2783 mtspr(SPR_MAS0, mas0);
2784 __asm __volatile("isync");
2786 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2787 mtspr(SPR_MAS2, mas2);
2789 __asm __volatile("isync; tlbre");
2791 mas1 = mfspr(SPR_MAS1);
2792 mas2 = mfspr(SPR_MAS2);
2793 mas3 = mfspr(SPR_MAS3);
2794 mas7 = mfspr(SPR_MAS7);
2796 idx = tlb0_tableidx(mas2, way);
2797 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2801 /**************************************************************************/
2803 /**************************************************************************/
2806 * TLB1 mapping notes:
2809 * TLB1[1] Kernel text and data.
2810 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI
2811 * windows, other devices mappings.
2815 * Write given entry to TLB1 hardware.
2816 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2819 tlb1_write_entry(unsigned int idx)
2821 uint32_t mas0, mas7;
2823 //debugf("tlb1_write_entry: s\n");
2825 /* Clear high order RPN bits */
2829 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2830 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2832 mtspr(SPR_MAS0, mas0);
2833 __asm __volatile("isync");
2834 mtspr(SPR_MAS1, tlb1[idx].mas1);
2835 __asm __volatile("isync");
2836 mtspr(SPR_MAS2, tlb1[idx].mas2);
2837 __asm __volatile("isync");
2838 mtspr(SPR_MAS3, tlb1[idx].mas3);
2839 __asm __volatile("isync");
2840 mtspr(SPR_MAS7, mas7);
2841 __asm __volatile("isync; tlbwe; isync; msync");
2843 //debugf("tlb1_write_entry: e\n");
2847 * Return the largest uint value log such that 2^log <= num.
2850 ilog2(unsigned int num)
2854 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2859 * Convert TLB TSIZE value to mapped region size.
2862 tsize2size(unsigned int tsize)
2867 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2870 return ((1 << (2 * tsize)) * 1024);
2874 * Convert region size (must be power of 4) to TLB TSIZE value.
2877 size2tsize(vm_size_t size)
2880 return (ilog2(size) / 2 - 5);
2884 * Register permanent kernel mapping in TLB1.
2886 * Entries are created starting from index 0 (current free entry is
2887 * kept in tlb1_idx) and are not supposed to be invalidated.
2890 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2896 if (tlb1_idx >= TLB1_ENTRIES) {
2897 printf("tlb1_set_entry: TLB1 full!\n");
2901 /* Convert size to TSIZE */
2902 tsize = size2tsize(size);
2904 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2905 /* XXX TS is hard coded to 0 for now as we only use single address space */
2906 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2908 /* XXX LOCK tlb1[] */
2910 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2911 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2912 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags;
2914 /* Set supervisor RWX permission bits */
2915 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2917 tlb1_write_entry(tlb1_idx++);
2919 /* XXX UNLOCK tlb1[] */
2922 * XXX in general TLB1 updates should be propagated between CPUs,
2923 * since current design assumes to have the same TLB1 set-up on all
2930 tlb1_entry_size_cmp(const void *a, const void *b)
2932 const vm_size_t *sza;
2933 const vm_size_t *szb;
2939 else if (*sza < *szb)
2946 * Map in contiguous RAM region into the TLB1 using maximum of
2947 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
2949 * If necessary round up last entry size and return total size
2950 * used by all allocated entries.
2953 tlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size)
2955 vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES];
2956 vm_size_t mapped_size, sz, esz;
2960 CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x",
2961 __func__, size, va, pa);
2965 memset(entry_size, 0, sizeof(entry_size));
2967 /* Calculate entry sizes. */
2968 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) {
2970 /* Largest region that is power of 4 and fits within size */
2971 log = ilog2(sz) / 2;
2972 esz = 1 << (2 * log);
2974 /* If this is last entry cover remaining size. */
2975 if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) {
2980 entry_size[i] = esz;
2988 /* Sort entry sizes, required to get proper entry address alignment. */
2989 qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES,
2990 sizeof(vm_size_t), tlb1_entry_size_cmp);
2992 /* Load TLB1 entries. */
2993 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) {
2994 esz = entry_size[i];
2998 CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x "
2999 "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa);
3001 tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM);
3007 CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)",
3008 __func__, mapped_size, mapped_size - size);
3010 return (mapped_size);
3014 * TLB1 initialization routine, to be called after the very first
3015 * assembler level setup done in locore.S.
3018 tlb1_init(vm_offset_t ccsrbar)
3022 /* TLB1[0] is used to map the kernel. Save that entry. */
3023 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
3024 mtspr(SPR_MAS0, mas0);
3025 __asm __volatile("isync; tlbre");
3027 tlb1[0].mas1 = mfspr(SPR_MAS1);
3028 tlb1[0].mas2 = mfspr(SPR_MAS2);
3029 tlb1[0].mas3 = mfspr(SPR_MAS3);
3031 /* Map in CCSRBAR in TLB1[1] */
3033 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
3035 /* Setup TLB miss defaults */
3036 set_mas4_defaults();
3040 * Setup MAS4 defaults.
3041 * These values are loaded to MAS0-2 on a TLB miss.
3044 set_mas4_defaults(void)
3048 /* Defaults: TLB0, PID0, TSIZED=4K */
3049 mas4 = MAS4_TLBSELD0;
3050 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3054 mtspr(SPR_MAS4, mas4);
3055 __asm __volatile("isync");
3059 * Print out contents of the MAS registers for each TLB1 entry
3062 tlb1_print_tlbentries(void)
3064 uint32_t mas0, mas1, mas2, mas3, mas7;
3067 debugf("TLB1 entries:\n");
3068 for (i = 0; i < TLB1_ENTRIES; i++) {
3070 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3071 mtspr(SPR_MAS0, mas0);
3073 __asm __volatile("isync; tlbre");
3075 mas1 = mfspr(SPR_MAS1);
3076 mas2 = mfspr(SPR_MAS2);
3077 mas3 = mfspr(SPR_MAS3);
3078 mas7 = mfspr(SPR_MAS7);
3080 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3085 * Print out contents of the in-ram tlb1 table.
3088 tlb1_print_entries(void)
3092 debugf("tlb1[] table entries:\n");
3093 for (i = 0; i < TLB1_ENTRIES; i++)
3094 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3098 * Return 0 if the physical IO range is encompassed by one of the
3099 * the TLB1 entries, otherwise return related error code.
3102 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3105 vm_paddr_t pa_start;
3107 unsigned int entry_tsize;
3108 vm_size_t entry_size;
3110 *va = (vm_offset_t)NULL;
3112 /* Skip invalid entries */
3113 if (!(tlb1[i].mas1 & MAS1_VALID))
3117 * The entry must be cache-inhibited, guarded, and r/w
3118 * so it can function as an i/o page
3120 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3121 if (prot != (MAS2_I | MAS2_G))
3124 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3125 if (prot != (MAS3_SR | MAS3_SW))
3128 /* The address should be within the entry range. */
3129 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3130 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3132 entry_size = tsize2size(entry_tsize);
3133 pa_start = tlb1[i].mas3 & MAS3_RPN;
3134 pa_end = pa_start + entry_size - 1;
3136 if ((pa < pa_start) || ((pa + size) > pa_end))
3139 /* Return virtual address of this mapping. */
3140 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);