2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_param.h>
103 #include <vm/vm_page.h>
104 #include <vm/vm_kern.h>
105 #include <vm/vm_pageout.h>
106 #include <vm/vm_extern.h>
107 #include <vm/vm_object.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
112 #include <vm/vm_dumpset.h>
115 #include <machine/_inttypes.h>
116 #include <machine/cpu.h>
117 #include <machine/pcb.h>
118 #include <machine/platform.h>
120 #include <machine/tlb.h>
121 #include <machine/spr.h>
122 #include <machine/md_var.h>
123 #include <machine/mmuvar.h>
124 #include <machine/pmap.h>
125 #include <machine/pte.h>
129 #define SPARSE_MAPDEV
131 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
132 #define POW2_MAPPINGS
135 #define debugf(fmt, args...) printf(fmt, ##args)
137 #define debugf(fmt, args...)
141 #define PRI0ptrX "016lx"
143 #define PRI0ptrX "08x"
146 #define TODO panic("%s: not implemented", __func__);
148 extern unsigned char _etext[];
149 extern unsigned char _end[];
151 extern uint32_t *bootinfo;
154 vm_offset_t kernstart;
157 /* Message buffer and tables. */
158 static vm_offset_t data_start;
159 static vm_size_t data_end;
161 /* Phys/avail memory regions. */
162 static struct mem_region *availmem_regions;
163 static int availmem_regions_sz;
164 static struct mem_region *physmem_regions;
165 static int physmem_regions_sz;
167 #ifndef __powerpc64__
168 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
169 static vm_offset_t zero_page_va;
170 static struct mtx zero_page_mutex;
172 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
173 static vm_offset_t copy_page_src_va;
174 static vm_offset_t copy_page_dst_va;
175 static struct mtx copy_page_mutex;
178 static struct mtx tlbivax_mutex;
180 /**************************************************************************/
182 /**************************************************************************/
184 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
185 vm_prot_t, u_int flags, int8_t psind);
187 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
188 static uma_zone_t ptbl_root_zone;
191 * If user pmap is processed with mmu_booke_remove and the resident count
192 * drops to 0, there are no more pages to remove, so we need not continue.
194 #define PMAP_REMOVE_DONE(pmap) \
195 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
197 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
198 extern int elf32_nxstack;
201 /**************************************************************************/
202 /* TLB and TID handling */
203 /**************************************************************************/
205 /* Translation ID busy table */
206 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
209 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
210 * core revisions and should be read from h/w registers during early config.
212 uint32_t tlb0_entries;
214 uint32_t tlb0_entries_per_way;
215 uint32_t tlb1_entries;
217 #define TLB0_ENTRIES (tlb0_entries)
218 #define TLB0_WAYS (tlb0_ways)
219 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
221 #define TLB1_ENTRIES (tlb1_entries)
223 static tlbtid_t tid_alloc(struct pmap *);
227 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
229 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
233 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
234 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
235 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
236 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
238 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
240 static vm_size_t tsize2size(unsigned int);
241 static unsigned int size2tsize(vm_size_t);
242 static unsigned long ilog2(unsigned long);
244 static void set_mas4_defaults(void);
246 static inline void tlb0_flush_entry(vm_offset_t);
247 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
249 /**************************************************************************/
250 /* Page table management */
251 /**************************************************************************/
253 static struct rwlock_padalign pvh_global_lock;
255 /* Data for the pv entry allocation mechanism */
256 static uma_zone_t pvzone;
257 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
259 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
261 #ifndef PMAP_SHPGPERPROC
262 #define PMAP_SHPGPERPROC 200
265 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
266 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
267 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
268 static pte_t *pte_find(pmap_t, vm_offset_t);
269 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
271 static pv_entry_t pv_alloc(void);
272 static void pv_free(pv_entry_t);
273 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
274 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
276 static void booke_pmap_init_qpages(void);
278 static inline void tlb_miss_lock(void);
279 static inline void tlb_miss_unlock(void);
282 extern tlb_entry_t __boot_tlb1[];
283 void pmap_bootstrap_ap(volatile uint32_t *);
287 * Kernel MMU interface
289 static void mmu_booke_clear_modify(vm_page_t);
290 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
291 vm_size_t, vm_offset_t);
292 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
293 static void mmu_booke_copy_pages(vm_page_t *,
294 vm_offset_t, vm_page_t *, vm_offset_t, int);
295 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
296 vm_prot_t, u_int flags, int8_t psind);
297 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
298 vm_page_t, vm_prot_t);
299 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
301 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
302 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
304 static void mmu_booke_init(void);
305 static boolean_t mmu_booke_is_modified(vm_page_t);
306 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
307 static boolean_t mmu_booke_is_referenced(vm_page_t);
308 static int mmu_booke_ts_referenced(vm_page_t);
309 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
311 static int mmu_booke_mincore(pmap_t, vm_offset_t,
313 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
314 vm_object_t, vm_pindex_t, vm_size_t);
315 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t);
316 static void mmu_booke_page_init(vm_page_t);
317 static int mmu_booke_page_wired_mappings(vm_page_t);
318 static int mmu_booke_pinit(pmap_t);
319 static void mmu_booke_pinit0(pmap_t);
320 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
322 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int);
323 static void mmu_booke_qremove(vm_offset_t, int);
324 static void mmu_booke_release(pmap_t);
325 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
326 static void mmu_booke_remove_all(vm_page_t);
327 static void mmu_booke_remove_write(vm_page_t);
328 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
329 static void mmu_booke_zero_page(vm_page_t);
330 static void mmu_booke_zero_page_area(vm_page_t, int, int);
331 static void mmu_booke_activate(struct thread *);
332 static void mmu_booke_deactivate(struct thread *);
333 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
334 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
335 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
336 static void mmu_booke_unmapdev(vm_offset_t, vm_size_t);
337 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
338 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
339 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
340 static void mmu_booke_kremove(vm_offset_t);
341 static boolean_t mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
342 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
344 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
346 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
348 static void mmu_booke_scan_init(void);
349 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m);
350 static void mmu_booke_quick_remove_page(vm_offset_t addr);
351 static int mmu_booke_change_attr(vm_offset_t addr,
352 vm_size_t sz, vm_memattr_t mode);
353 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
354 int *is_user, vm_offset_t *decoded_addr);
355 static void mmu_booke_page_array_startup(long);
356 static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
358 static struct pmap_funcs mmu_booke_methods = {
359 /* pmap dispatcher interface */
360 .clear_modify = mmu_booke_clear_modify,
361 .copy = mmu_booke_copy,
362 .copy_page = mmu_booke_copy_page,
363 .copy_pages = mmu_booke_copy_pages,
364 .enter = mmu_booke_enter,
365 .enter_object = mmu_booke_enter_object,
366 .enter_quick = mmu_booke_enter_quick,
367 .extract = mmu_booke_extract,
368 .extract_and_hold = mmu_booke_extract_and_hold,
369 .init = mmu_booke_init,
370 .is_modified = mmu_booke_is_modified,
371 .is_prefaultable = mmu_booke_is_prefaultable,
372 .is_referenced = mmu_booke_is_referenced,
373 .ts_referenced = mmu_booke_ts_referenced,
374 .map = mmu_booke_map,
375 .mincore = mmu_booke_mincore,
376 .object_init_pt = mmu_booke_object_init_pt,
377 .page_exists_quick = mmu_booke_page_exists_quick,
378 .page_init = mmu_booke_page_init,
379 .page_wired_mappings = mmu_booke_page_wired_mappings,
380 .pinit = mmu_booke_pinit,
381 .pinit0 = mmu_booke_pinit0,
382 .protect = mmu_booke_protect,
383 .qenter = mmu_booke_qenter,
384 .qremove = mmu_booke_qremove,
385 .release = mmu_booke_release,
386 .remove = mmu_booke_remove,
387 .remove_all = mmu_booke_remove_all,
388 .remove_write = mmu_booke_remove_write,
389 .sync_icache = mmu_booke_sync_icache,
390 .unwire = mmu_booke_unwire,
391 .zero_page = mmu_booke_zero_page,
392 .zero_page_area = mmu_booke_zero_page_area,
393 .activate = mmu_booke_activate,
394 .deactivate = mmu_booke_deactivate,
395 .quick_enter_page = mmu_booke_quick_enter_page,
396 .quick_remove_page = mmu_booke_quick_remove_page,
397 .page_array_startup = mmu_booke_page_array_startup,
398 .page_is_mapped = mmu_booke_page_is_mapped,
400 /* Internal interfaces */
401 .bootstrap = mmu_booke_bootstrap,
402 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
403 .mapdev = mmu_booke_mapdev,
404 .mapdev_attr = mmu_booke_mapdev_attr,
405 .kenter = mmu_booke_kenter,
406 .kenter_attr = mmu_booke_kenter_attr,
407 .kextract = mmu_booke_kextract,
408 .kremove = mmu_booke_kremove,
409 .unmapdev = mmu_booke_unmapdev,
410 .change_attr = mmu_booke_change_attr,
411 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
413 /* dumpsys() support */
414 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
415 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
416 .dumpsys_pa_init = mmu_booke_scan_init,
419 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
427 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
429 static __inline uint32_t
430 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
435 if (ma != VM_MEMATTR_DEFAULT) {
437 case VM_MEMATTR_UNCACHEABLE:
438 return (MAS2_I | MAS2_G);
439 case VM_MEMATTR_WRITE_COMBINING:
440 case VM_MEMATTR_WRITE_BACK:
441 case VM_MEMATTR_PREFETCHABLE:
443 case VM_MEMATTR_WRITE_THROUGH:
444 return (MAS2_W | MAS2_M);
445 case VM_MEMATTR_CACHEABLE:
451 * Assume the page is cache inhibited and access is guarded unless
452 * it's in our available memory array.
454 attrib = _TLB_ENTRY_IO;
455 for (i = 0; i < physmem_regions_sz; i++) {
456 if ((pa >= physmem_regions[i].mr_start) &&
457 (pa < (physmem_regions[i].mr_start +
458 physmem_regions[i].mr_size))) {
459 attrib = _TLB_ENTRY_MEM;
476 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
478 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
479 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
481 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
482 ("tlb_miss_lock: tried to lock self"));
484 tlb_lock(pc->pc_booke.tlb_lock);
486 CTR1(KTR_PMAP, "%s: locked", __func__);
493 tlb_miss_unlock(void)
501 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
503 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
504 __func__, pc->pc_cpuid);
506 tlb_unlock(pc->pc_booke.tlb_lock);
508 CTR1(KTR_PMAP, "%s: unlocked", __func__);
514 /* Return number of entries in TLB0. */
516 tlb0_get_tlbconf(void)
520 tlb0_cfg = mfspr(SPR_TLB0CFG);
521 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
522 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
523 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
526 /* Return number of entries in TLB1. */
528 tlb1_get_tlbconf(void)
532 tlb1_cfg = mfspr(SPR_TLB1CFG);
533 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
536 /**************************************************************************/
537 /* Page table related */
538 /**************************************************************************/
540 /* Allocate pv_entry structure. */
547 if (pv_entry_count > pv_entry_high_water)
548 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
549 pv = uma_zalloc(pvzone, M_NOWAIT);
554 /* Free pv_entry structure. */
556 pv_free(pv_entry_t pve)
560 uma_zfree(pvzone, pve);
563 /* Allocate and initialize pv_entry structure. */
565 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
569 //int su = (pmap == kernel_pmap);
570 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
571 // (u_int32_t)pmap, va, (u_int32_t)m);
575 panic("pv_insert: no pv entries!");
581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
582 rw_assert(&pvh_global_lock, RA_WLOCKED);
584 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
586 //debugf("pv_insert: e\n");
589 /* Destroy pv entry. */
591 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
595 //int su = (pmap == kernel_pmap);
596 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
598 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
599 rw_assert(&pvh_global_lock, RA_WLOCKED);
602 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
603 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
604 /* remove from pv_list */
605 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
606 if (TAILQ_EMPTY(&m->md.pv_list))
607 vm_page_aflag_clear(m, PGA_WRITEABLE);
609 /* free pv entry struct */
615 //debugf("pv_remove: e\n");
618 /**************************************************************************/
620 /**************************************************************************/
623 * This is called during booke_init, before the system is really initialized.
626 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
628 vm_paddr_t phys_kernelend;
629 struct mem_region *mp, *mp1;
632 vm_paddr_t physsz, hwphyssz;
633 u_int phys_avail_count;
634 vm_size_t kstack0_sz;
635 vm_paddr_t kstack0_phys;
639 debugf("mmu_booke_bootstrap: entered\n");
641 /* Set interesting system properties */
647 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
651 /* Initialize invalidation mutex */
652 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
654 /* Read TLB0 size and associativity. */
658 * Align kernel start and end address (kernel image).
659 * Note that kernel end does not necessarily relate to kernsize.
660 * kernsize is the size of the kernel that is actually mapped.
662 data_start = round_page(kernelend);
663 data_end = data_start;
665 /* Allocate the dynamic per-cpu area. */
666 dpcpu = (void *)data_end;
667 data_end += DPCPU_SIZE;
669 /* Allocate space for the message buffer. */
670 msgbufp = (struct msgbuf *)data_end;
671 data_end += msgbufsize;
672 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
673 (uintptr_t)msgbufp, data_end);
675 data_end = round_page(data_end);
676 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
678 /* Retrieve phys/avail mem regions */
679 mem_regions(&physmem_regions, &physmem_regions_sz,
680 &availmem_regions, &availmem_regions_sz);
682 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
683 panic("mmu_booke_bootstrap: phys_avail too small");
685 data_end = round_page(data_end);
686 vm_page_array = (vm_page_t)data_end;
688 * Get a rough idea (upper bound) on the size of the page array. The
689 * vm_page_array will not handle any more pages than we have in the
690 * avail_regions array, and most likely much less.
693 for (mp = availmem_regions; mp->mr_size; mp++) {
696 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
697 data_end += round_page(sz * sizeof(struct vm_page));
699 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
700 data_end = roundup2(data_end, 1 << 20);
702 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
703 debugf(" kernstart: %#zx\n", kernstart);
704 debugf(" kernsize: %#zx\n", kernsize);
706 if (data_end - kernstart > kernsize) {
707 kernsize += tlb1_mapin_region(kernstart + kernsize,
708 kernload + kernsize, (data_end - kernstart) - kernsize,
711 data_end = kernstart + kernsize;
712 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
715 * Clear the structures - note we can only do it safely after the
716 * possible additional TLB1 translations are in place (above) so that
717 * all range up to the currently calculated 'data_end' is covered.
719 bzero((void *)data_start, data_end - data_start);
720 dpcpu_init(dpcpu, 0);
722 /*******************************************************/
723 /* Set the start and end of kva. */
724 /*******************************************************/
725 virtual_avail = round_page(data_end);
726 virtual_end = VM_MAX_KERNEL_ADDRESS;
728 #ifndef __powerpc64__
729 /* Allocate KVA space for page zero/copy operations. */
730 zero_page_va = virtual_avail;
731 virtual_avail += PAGE_SIZE;
732 copy_page_src_va = virtual_avail;
733 virtual_avail += PAGE_SIZE;
734 copy_page_dst_va = virtual_avail;
735 virtual_avail += PAGE_SIZE;
736 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
737 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
738 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
740 /* Initialize page zero/copy mutexes. */
741 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
742 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
744 /* Allocate KVA space for ptbl bufs. */
745 ptbl_buf_pool_vabase = virtual_avail;
746 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
747 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
748 ptbl_buf_pool_vabase, virtual_avail);
751 /* Calculate corresponding physical addresses for the kernel region. */
752 phys_kernelend = kernload + kernsize;
753 debugf("kernel image and allocated data:\n");
754 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
755 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
756 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
759 * Remove kernel physical address range from avail regions list. Page
760 * align all regions. Non-page aligned memory isn't very interesting
761 * to us. Also, sort the entries for ascending addresses.
765 cnt = availmem_regions_sz;
766 debugf("processing avail regions:\n");
767 for (mp = availmem_regions; mp->mr_size; mp++) {
769 e = mp->mr_start + mp->mr_size;
770 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
771 /* Check whether this region holds all of the kernel. */
772 if (s < kernload && e > phys_kernelend) {
773 availmem_regions[cnt].mr_start = phys_kernelend;
774 availmem_regions[cnt++].mr_size = e - phys_kernelend;
777 /* Look whether this regions starts within the kernel. */
778 if (s >= kernload && s < phys_kernelend) {
779 if (e <= phys_kernelend)
783 /* Now look whether this region ends within the kernel. */
784 if (e > kernload && e <= phys_kernelend) {
789 /* Now page align the start and size of the region. */
795 debugf("%09jx-%09jx = %jx\n",
796 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
798 /* Check whether some memory is left here. */
802 (cnt - (mp - availmem_regions)) * sizeof(*mp));
808 /* Do an insertion sort. */
809 for (mp1 = availmem_regions; mp1 < mp; mp1++)
810 if (s < mp1->mr_start)
813 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
821 availmem_regions_sz = cnt;
823 /*******************************************************/
824 /* Steal physical memory for kernel stack from the end */
825 /* of the first avail region */
826 /*******************************************************/
827 kstack0_sz = kstack_pages * PAGE_SIZE;
828 kstack0_phys = availmem_regions[0].mr_start +
829 availmem_regions[0].mr_size;
830 kstack0_phys -= kstack0_sz;
831 availmem_regions[0].mr_size -= kstack0_sz;
833 /*******************************************************/
834 /* Fill in phys_avail table, based on availmem_regions */
835 /*******************************************************/
836 phys_avail_count = 0;
839 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
841 debugf("fill in phys_avail:\n");
842 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
843 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
844 (uintmax_t)availmem_regions[i].mr_start,
845 (uintmax_t)availmem_regions[i].mr_start +
846 availmem_regions[i].mr_size,
847 (uintmax_t)availmem_regions[i].mr_size);
850 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
851 debugf(" hw.physmem adjust\n");
852 if (physsz < hwphyssz) {
853 phys_avail[j] = availmem_regions[i].mr_start;
855 availmem_regions[i].mr_start +
859 dump_avail[j] = phys_avail[j];
860 dump_avail[j + 1] = phys_avail[j + 1];
865 phys_avail[j] = availmem_regions[i].mr_start;
866 phys_avail[j + 1] = availmem_regions[i].mr_start +
867 availmem_regions[i].mr_size;
869 physsz += availmem_regions[i].mr_size;
870 dump_avail[j] = phys_avail[j];
871 dump_avail[j + 1] = phys_avail[j + 1];
873 physmem = btoc(physsz);
875 /* Calculate the last available physical address. */
876 for (i = 0; phys_avail[i + 2] != 0; i += 2)
878 Maxmem = powerpc_btop(phys_avail[i + 1]);
880 debugf("Maxmem = 0x%08lx\n", Maxmem);
881 debugf("phys_avail_count = %d\n", phys_avail_count);
882 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
883 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
887 * Map the physical memory contiguously in TLB1.
888 * Round so it fits into a single mapping.
890 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
891 phys_avail[i + 1], _TLB_ENTRY_MEM);
894 /*******************************************************/
895 /* Initialize (statically allocated) kernel pmap. */
896 /*******************************************************/
897 PMAP_LOCK_INIT(kernel_pmap);
899 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
900 kernel_pte_alloc(virtual_avail, kernstart);
901 for (i = 0; i < MAXCPU; i++) {
902 kernel_pmap->pm_tid[i] = TID_KERNEL;
904 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
905 tidbusy[i][TID_KERNEL] = kernel_pmap;
908 /* Mark kernel_pmap active on all CPUs */
909 CPU_FILL(&kernel_pmap->pm_active);
912 * Initialize the global pv list lock.
914 rw_init(&pvh_global_lock, "pmap pv global");
916 /*******************************************************/
918 /*******************************************************/
920 /* Enter kstack0 into kernel map, provide guard page */
921 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
922 thread0.td_kstack = kstack0;
923 thread0.td_kstack_pages = kstack_pages;
925 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
926 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
927 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
928 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
929 kstack0, kstack0 + kstack0_sz);
931 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
932 for (i = 0; i < kstack_pages; i++) {
933 mmu_booke_kenter(kstack0, kstack0_phys);
934 kstack0 += PAGE_SIZE;
935 kstack0_phys += PAGE_SIZE;
938 pmap_bootstrapped = 1;
940 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
941 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
943 debugf("mmu_booke_bootstrap: exit\n");
953 /* Prepare TLB1 image for AP processors */
955 for (i = 0; i < TLB1_ENTRIES; i++) {
956 tlb1_read_entry(&tmp, i);
958 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
959 memcpy(e++, &tmp, sizeof(tmp));
964 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
969 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
970 * have the snapshot of its contents in the s/w __boot_tlb1[] table
971 * created by tlb1_ap_prep(), so use these values directly to
972 * (re)program AP's TLB1 hardware.
974 * Start at index 1 because index 0 has the kernel map.
976 for (i = 1; i < TLB1_ENTRIES; i++) {
977 if (__boot_tlb1[i].mas1 & MAS1_VALID)
978 tlb1_write_entry(&__boot_tlb1[i], i);
986 booke_pmap_init_qpages(void)
993 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
994 if (pc->pc_qmap_addr == 0)
995 panic("pmap_init_qpages: unable to allocate KVA");
999 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1002 * Get the physical page address for the given pmap/virtual address.
1005 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1010 pa = pte_vatopa(pmap, va);
1017 * Extract the physical page address associated with the given
1018 * kernel virtual address.
1021 mmu_booke_kextract(vm_offset_t va)
1027 #ifdef __powerpc64__
1028 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1029 return (DMAP_TO_PHYS(va));
1032 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1033 p = pte_vatopa(kernel_pmap, va);
1036 /* Check TLB1 mappings */
1037 for (i = 0; i < TLB1_ENTRIES; i++) {
1038 tlb1_read_entry(&e, i);
1039 if (!(e.mas1 & MAS1_VALID))
1041 if (va >= e.virt && va < e.virt + e.size)
1042 return (e.phys + (va - e.virt));
1050 * Initialize the pmap module.
1051 * Called by vm_init, to initialize any structures that the pmap
1052 * system needs to map virtual memory.
1057 int shpgperproc = PMAP_SHPGPERPROC;
1060 * Initialize the address space (zone) for the pv entries. Set a
1061 * high water mark so that the system can recover from excessive
1062 * numbers of pv entries.
1064 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1065 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1067 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1068 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1070 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1071 pv_entry_high_water = 9 * (pv_entry_max / 10);
1073 uma_zone_reserve_kva(pvzone, pv_entry_max);
1075 /* Pre-fill pvzone with initial number of pv entries. */
1076 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1078 /* Create a UMA zone for page table roots. */
1079 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1080 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1082 /* Initialize ptbl allocation. */
1087 * Map a list of wired pages into kernel virtual address space. This is
1088 * intended for temporary mappings which do not need page modification or
1089 * references recorded. Existing mappings in the region are overwritten.
1092 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count)
1097 while (count-- > 0) {
1098 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1105 * Remove page mappings from kernel virtual address space. Intended for
1106 * temporary mappings entered by mmu_booke_qenter.
1109 mmu_booke_qremove(vm_offset_t sva, int count)
1114 while (count-- > 0) {
1115 mmu_booke_kremove(va);
1121 * Map a wired page into kernel virtual address space.
1124 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1127 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1131 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1136 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1137 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1139 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1140 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1141 flags |= PTE_PS_4KB;
1143 pte = pte_find(kernel_pmap, va);
1144 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1146 mtx_lock_spin(&tlbivax_mutex);
1149 if (PTE_ISVALID(pte)) {
1150 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1152 /* Flush entry from TLB0 */
1153 tlb0_flush_entry(va);
1156 *pte = PTE_RPN_FROM_PA(pa) | flags;
1158 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1159 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1160 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1162 /* Flush the real memory from the instruction cache. */
1163 if ((flags & (PTE_I | PTE_G)) == 0)
1164 __syncicache((void *)va, PAGE_SIZE);
1167 mtx_unlock_spin(&tlbivax_mutex);
1171 * Remove a page from kernel page table.
1174 mmu_booke_kremove(vm_offset_t va)
1178 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1180 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1181 (va <= VM_MAX_KERNEL_ADDRESS)),
1182 ("mmu_booke_kremove: invalid va"));
1184 pte = pte_find(kernel_pmap, va);
1186 if (!PTE_ISVALID(pte)) {
1187 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1192 mtx_lock_spin(&tlbivax_mutex);
1195 /* Invalidate entry in TLB0, update PTE. */
1196 tlb0_flush_entry(va);
1200 mtx_unlock_spin(&tlbivax_mutex);
1204 * Figure out where a given kernel pointer (usually in a fault) points
1205 * to from the VM's perspective, potentially remapping into userland's
1209 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1210 vm_offset_t *decoded_addr)
1213 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1218 *decoded_addr = addr;
1223 mmu_booke_page_is_mapped(vm_page_t m)
1226 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1230 * Initialize pmap associated with process 0.
1233 mmu_booke_pinit0(pmap_t pmap)
1236 PMAP_LOCK_INIT(pmap);
1237 mmu_booke_pinit(pmap);
1238 PCPU_SET(curpmap, pmap);
1242 * Insert the given physical page at the specified virtual address in the
1243 * target physical map with the protection requested. If specified the page
1244 * will be wired down.
1247 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1248 vm_prot_t prot, u_int flags, int8_t psind)
1252 rw_wlock(&pvh_global_lock);
1254 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1256 rw_wunlock(&pvh_global_lock);
1261 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1262 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1267 int error, su, sync;
1269 pa = VM_PAGE_TO_PHYS(m);
1270 su = (pmap == kernel_pmap);
1273 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1274 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1275 // (u_int32_t)pmap, su, pmap->pm_tid,
1276 // (u_int32_t)m, va, pa, prot, flags);
1279 KASSERT(((va >= virtual_avail) &&
1280 (va <= VM_MAX_KERNEL_ADDRESS)),
1281 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1283 KASSERT((va <= VM_MAXUSER_ADDRESS),
1284 ("mmu_booke_enter_locked: user pmap, non user va"));
1286 if ((m->oflags & VPO_UNMANAGED) == 0) {
1287 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1288 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1290 VM_OBJECT_ASSERT_LOCKED(m->object);
1293 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1296 * If there is an existing mapping, and the physical address has not
1297 * changed, must be protection or wiring change.
1299 if (((pte = pte_find(pmap, va)) != NULL) &&
1300 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1303 * Before actually updating pte->flags we calculate and
1304 * prepare its new value in a helper var.
1307 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1309 /* Wiring change, just update stats. */
1310 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1311 if (!PTE_ISWIRED(pte)) {
1313 pmap->pm_stats.wired_count++;
1316 if (PTE_ISWIRED(pte)) {
1317 flags &= ~PTE_WIRED;
1318 pmap->pm_stats.wired_count--;
1322 if (prot & VM_PROT_WRITE) {
1323 /* Add write permissions. */
1328 if ((flags & PTE_MANAGED) != 0)
1329 vm_page_aflag_set(m, PGA_WRITEABLE);
1331 /* Handle modified pages, sense modify status. */
1334 * The PTE_MODIFIED flag could be set by underlying
1335 * TLB misses since we last read it (above), possibly
1336 * other CPUs could update it so we check in the PTE
1337 * directly rather than rely on that saved local flags
1340 if (PTE_ISMODIFIED(pte))
1344 if (prot & VM_PROT_EXECUTE) {
1350 * Check existing flags for execute permissions: if we
1351 * are turning execute permissions on, icache should
1354 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1358 flags &= ~PTE_REFERENCED;
1361 * The new flags value is all calculated -- only now actually
1364 mtx_lock_spin(&tlbivax_mutex);
1367 tlb0_flush_entry(va);
1368 *pte &= ~PTE_FLAGS_MASK;
1372 mtx_unlock_spin(&tlbivax_mutex);
1376 * If there is an existing mapping, but it's for a different
1377 * physical address, pte_enter() will delete the old mapping.
1379 //if ((pte != NULL) && PTE_ISVALID(pte))
1380 // debugf("mmu_booke_enter_locked: replace\n");
1382 // debugf("mmu_booke_enter_locked: new\n");
1384 /* Now set up the flags and install the new mapping. */
1385 flags = (PTE_SR | PTE_VALID);
1391 if (prot & VM_PROT_WRITE) {
1396 if ((m->oflags & VPO_UNMANAGED) == 0)
1397 vm_page_aflag_set(m, PGA_WRITEABLE);
1400 if (prot & VM_PROT_EXECUTE) {
1406 /* If its wired update stats. */
1407 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1410 error = pte_enter(pmap, m, va, flags,
1411 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1413 return (KERN_RESOURCE_SHORTAGE);
1415 if ((flags & PMAP_ENTER_WIRED) != 0)
1416 pmap->pm_stats.wired_count++;
1418 /* Flush the real memory from the instruction cache. */
1419 if (prot & VM_PROT_EXECUTE)
1423 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1424 __syncicache((void *)va, PAGE_SIZE);
1428 return (KERN_SUCCESS);
1432 * Maps a sequence of resident pages belonging to the same object.
1433 * The sequence begins with the given page m_start. This page is
1434 * mapped at the given virtual address start. Each subsequent page is
1435 * mapped at a virtual address that is offset from start by the same
1436 * amount as the page is offset from m_start within the object. The
1437 * last page in the sequence is the page with the largest offset from
1438 * m_start that can be mapped at a virtual address less than the given
1439 * virtual address end. Not every virtual page between start and end
1440 * is mapped; only those for which a resident page exists with the
1441 * corresponding offset from m_start are mapped.
1444 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1445 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1448 vm_pindex_t diff, psize;
1450 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1452 psize = atop(end - start);
1454 rw_wlock(&pvh_global_lock);
1456 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1457 mmu_booke_enter_locked(pmap, start + ptoa(diff), m,
1458 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1459 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1460 m = TAILQ_NEXT(m, listq);
1463 rw_wunlock(&pvh_global_lock);
1467 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1471 rw_wlock(&pvh_global_lock);
1473 mmu_booke_enter_locked(pmap, va, m,
1474 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1475 PMAP_ENTER_QUICK_LOCKED, 0);
1477 rw_wunlock(&pvh_global_lock);
1481 * Remove the given range of addresses from the specified map.
1483 * It is assumed that the start and end are properly rounded to the page size.
1486 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1491 int su = (pmap == kernel_pmap);
1493 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1494 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1497 KASSERT(((va >= virtual_avail) &&
1498 (va <= VM_MAX_KERNEL_ADDRESS)),
1499 ("mmu_booke_remove: kernel pmap, non kernel va"));
1501 KASSERT((va <= VM_MAXUSER_ADDRESS),
1502 ("mmu_booke_remove: user pmap, non user va"));
1505 if (PMAP_REMOVE_DONE(pmap)) {
1506 //debugf("mmu_booke_remove: e (empty)\n");
1510 hold_flag = PTBL_HOLD_FLAG(pmap);
1511 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1513 rw_wlock(&pvh_global_lock);
1515 for (; va < endva; va += PAGE_SIZE) {
1516 pte = pte_find_next(pmap, &va);
1517 if ((pte == NULL) || !PTE_ISVALID(pte))
1521 pte_remove(pmap, va, hold_flag);
1524 rw_wunlock(&pvh_global_lock);
1526 //debugf("mmu_booke_remove: e\n");
1530 * Remove physical page from all pmaps in which it resides.
1533 mmu_booke_remove_all(vm_page_t m)
1538 rw_wlock(&pvh_global_lock);
1539 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1540 PMAP_LOCK(pv->pv_pmap);
1541 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1542 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1543 PMAP_UNLOCK(pv->pv_pmap);
1545 vm_page_aflag_clear(m, PGA_WRITEABLE);
1546 rw_wunlock(&pvh_global_lock);
1550 * Map a range of physical addresses into kernel virtual address space.
1553 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1554 vm_paddr_t pa_end, int prot)
1556 vm_offset_t sva = *virt;
1557 vm_offset_t va = sva;
1559 #ifdef __powerpc64__
1560 /* XXX: Handle memory not starting at 0x0. */
1561 if (pa_end < ctob(Maxmem))
1562 return (PHYS_TO_DMAP(pa_start));
1565 while (pa_start < pa_end) {
1566 mmu_booke_kenter(va, pa_start);
1568 pa_start += PAGE_SIZE;
1576 * The pmap must be activated before it's address space can be accessed in any
1580 mmu_booke_activate(struct thread *td)
1585 pmap = &td->td_proc->p_vmspace->vm_pmap;
1587 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1588 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1590 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1594 cpuid = PCPU_GET(cpuid);
1595 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1596 PCPU_SET(curpmap, pmap);
1598 if (pmap->pm_tid[cpuid] == TID_NONE)
1601 /* Load PID0 register with pmap tid value. */
1602 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1603 __asm __volatile("isync");
1605 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1609 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1610 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1614 * Deactivate the specified process's address space.
1617 mmu_booke_deactivate(struct thread *td)
1621 pmap = &td->td_proc->p_vmspace->vm_pmap;
1623 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1624 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1626 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1628 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1629 PCPU_SET(curpmap, NULL);
1633 * Copy the range specified by src_addr/len
1634 * from the source map to the range dst_addr/len
1635 * in the destination map.
1637 * This routine is only advisory and need not do anything.
1640 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1641 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1647 * Set the physical protection on the specified range of this map as requested.
1650 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1657 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1658 mmu_booke_remove(pmap, sva, eva);
1662 if (prot & VM_PROT_WRITE)
1666 for (va = sva; va < eva; va += PAGE_SIZE) {
1667 if ((pte = pte_find(pmap, va)) != NULL) {
1668 if (PTE_ISVALID(pte)) {
1669 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1671 mtx_lock_spin(&tlbivax_mutex);
1674 /* Handle modified pages. */
1675 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1678 tlb0_flush_entry(va);
1679 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1682 mtx_unlock_spin(&tlbivax_mutex);
1690 * Clear the write and modified bits in each of the given page's mappings.
1693 mmu_booke_remove_write(vm_page_t m)
1698 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1699 ("mmu_booke_remove_write: page %p is not managed", m));
1700 vm_page_assert_busied(m);
1702 if (!pmap_page_is_write_mapped(m))
1704 rw_wlock(&pvh_global_lock);
1705 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1706 PMAP_LOCK(pv->pv_pmap);
1707 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1708 if (PTE_ISVALID(pte)) {
1709 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1711 mtx_lock_spin(&tlbivax_mutex);
1714 /* Handle modified pages. */
1715 if (PTE_ISMODIFIED(pte))
1718 /* Flush mapping from TLB0. */
1719 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1722 mtx_unlock_spin(&tlbivax_mutex);
1725 PMAP_UNLOCK(pv->pv_pmap);
1727 vm_page_aflag_clear(m, PGA_WRITEABLE);
1728 rw_wunlock(&pvh_global_lock);
1732 * Atomically extract and hold the physical page with the given
1733 * pmap and virtual address pair if that mapping permits the given
1737 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1746 pte = pte_find(pmap, va);
1747 if ((pte != NULL) && PTE_ISVALID(pte)) {
1748 if (pmap == kernel_pmap)
1753 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1754 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1755 if (!vm_page_wire_mapped(m))
1764 * Initialize a vm_page's machine-dependent fields.
1767 mmu_booke_page_init(vm_page_t m)
1770 m->md.pv_tracked = 0;
1771 TAILQ_INIT(&m->md.pv_list);
1775 * Return whether or not the specified physical page was modified
1776 * in any of physical maps.
1779 mmu_booke_is_modified(vm_page_t m)
1785 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1786 ("mmu_booke_is_modified: page %p is not managed", m));
1790 * If the page is not busied then this check is racy.
1792 if (!pmap_page_is_write_mapped(m))
1795 rw_wlock(&pvh_global_lock);
1796 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1797 PMAP_LOCK(pv->pv_pmap);
1798 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1800 if (PTE_ISMODIFIED(pte))
1803 PMAP_UNLOCK(pv->pv_pmap);
1807 rw_wunlock(&pvh_global_lock);
1812 * Return whether or not the specified virtual address is eligible
1816 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1823 * Return whether or not the specified physical page was referenced
1824 * in any physical maps.
1827 mmu_booke_is_referenced(vm_page_t m)
1833 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1834 ("mmu_booke_is_referenced: page %p is not managed", m));
1836 rw_wlock(&pvh_global_lock);
1837 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1838 PMAP_LOCK(pv->pv_pmap);
1839 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1841 if (PTE_ISREFERENCED(pte))
1844 PMAP_UNLOCK(pv->pv_pmap);
1848 rw_wunlock(&pvh_global_lock);
1853 * Clear the modify bits on the specified physical page.
1856 mmu_booke_clear_modify(vm_page_t m)
1861 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1862 ("mmu_booke_clear_modify: page %p is not managed", m));
1863 vm_page_assert_busied(m);
1865 if (!pmap_page_is_write_mapped(m))
1868 rw_wlock(&pvh_global_lock);
1869 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1870 PMAP_LOCK(pv->pv_pmap);
1871 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1873 mtx_lock_spin(&tlbivax_mutex);
1876 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1877 tlb0_flush_entry(pv->pv_va);
1878 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1883 mtx_unlock_spin(&tlbivax_mutex);
1885 PMAP_UNLOCK(pv->pv_pmap);
1887 rw_wunlock(&pvh_global_lock);
1891 * Return a count of reference bits for a page, clearing those bits.
1892 * It is not necessary for every reference bit to be cleared, but it
1893 * is necessary that 0 only be returned when there are truly no
1894 * reference bits set.
1896 * As an optimization, update the page's dirty field if a modified bit is
1897 * found while counting reference bits. This opportunistic update can be
1898 * performed at low cost and can eliminate the need for some future calls
1899 * to pmap_is_modified(). However, since this function stops after
1900 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1901 * dirty pages. Those dirty pages will only be detected by a future call
1902 * to pmap_is_modified().
1905 mmu_booke_ts_referenced(vm_page_t m)
1911 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1912 ("mmu_booke_ts_referenced: page %p is not managed", m));
1914 rw_wlock(&pvh_global_lock);
1915 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1916 PMAP_LOCK(pv->pv_pmap);
1917 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1919 if (PTE_ISMODIFIED(pte))
1921 if (PTE_ISREFERENCED(pte)) {
1922 mtx_lock_spin(&tlbivax_mutex);
1925 tlb0_flush_entry(pv->pv_va);
1926 *pte &= ~PTE_REFERENCED;
1929 mtx_unlock_spin(&tlbivax_mutex);
1931 if (++count >= PMAP_TS_REFERENCED_MAX) {
1932 PMAP_UNLOCK(pv->pv_pmap);
1937 PMAP_UNLOCK(pv->pv_pmap);
1939 rw_wunlock(&pvh_global_lock);
1944 * Clear the wired attribute from the mappings for the specified range of
1945 * addresses in the given pmap. Every valid mapping within that range must
1946 * have the wired attribute set. In contrast, invalid mappings cannot have
1947 * the wired attribute set, so they are ignored.
1949 * The wired attribute of the page table entry is not a hardware feature, so
1950 * there is no need to invalidate any TLB entries.
1953 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1959 for (va = sva; va < eva; va += PAGE_SIZE) {
1960 if ((pte = pte_find(pmap, va)) != NULL &&
1962 if (!PTE_ISWIRED(pte))
1963 panic("mmu_booke_unwire: pte %p isn't wired",
1966 pmap->pm_stats.wired_count--;
1974 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
1975 * page. This count may be changed upwards or downwards in the future; it is
1976 * only necessary that true be returned for a small subset of pmaps for proper
1980 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
1986 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1987 ("mmu_booke_page_exists_quick: page %p is not managed", m));
1990 rw_wlock(&pvh_global_lock);
1991 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1992 if (pv->pv_pmap == pmap) {
1999 rw_wunlock(&pvh_global_lock);
2004 * Return the number of managed mappings to the given physical page that are
2008 mmu_booke_page_wired_mappings(vm_page_t m)
2014 if ((m->oflags & VPO_UNMANAGED) != 0)
2016 rw_wlock(&pvh_global_lock);
2017 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2018 PMAP_LOCK(pv->pv_pmap);
2019 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2020 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2022 PMAP_UNLOCK(pv->pv_pmap);
2024 rw_wunlock(&pvh_global_lock);
2029 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2035 * This currently does not work for entries that
2036 * overlap TLB1 entries.
2038 for (i = 0; i < TLB1_ENTRIES; i ++) {
2039 if (tlb1_iomapped(i, pa, size, &va) == 0)
2047 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2053 /* Minidumps are based on virtual memory addresses. */
2055 *va = (void *)(vm_offset_t)pa;
2059 /* Raw physical memory dumps don't have a virtual address. */
2060 /* We always map a 256MB page at 256M. */
2061 gran = 256 * 1024 * 1024;
2062 ppa = rounddown2(pa, gran);
2065 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2067 if (sz > (gran - ofs))
2068 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2073 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2081 /* Minidumps are based on virtual memory addresses. */
2082 /* Nothing to do... */
2086 for (i = 0; i < TLB1_ENTRIES; i++) {
2087 tlb1_read_entry(&e, i);
2088 if (!(e.mas1 & MAS1_VALID))
2092 /* Raw physical memory dumps don't have a virtual address. */
2097 tlb1_write_entry(&e, i);
2099 gran = 256 * 1024 * 1024;
2100 ppa = rounddown2(pa, gran);
2102 if (sz > (gran - ofs)) {
2107 tlb1_write_entry(&e, i);
2111 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2114 mmu_booke_scan_init()
2121 /* Initialize phys. segments for dumpsys(). */
2122 memset(&dump_map, 0, sizeof(dump_map));
2123 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2124 &availmem_regions_sz);
2125 for (i = 0; i < physmem_regions_sz; i++) {
2126 dump_map[i].pa_start = physmem_regions[i].mr_start;
2127 dump_map[i].pa_size = physmem_regions[i].mr_size;
2132 /* Virtual segments for minidumps: */
2133 memset(&dump_map, 0, sizeof(dump_map));
2135 /* 1st: kernel .data and .bss. */
2136 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2137 dump_map[0].pa_size =
2138 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2140 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2141 dump_map[1].pa_start = data_start;
2142 dump_map[1].pa_size = data_end - data_start;
2144 /* 3rd: kernel VM. */
2145 va = dump_map[1].pa_start + dump_map[1].pa_size;
2146 /* Find start of next chunk (from va). */
2147 while (va < virtual_end) {
2148 /* Don't dump the buffer cache. */
2149 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2150 va = kmi.buffer_eva;
2153 pte = pte_find(kernel_pmap, va);
2154 if (pte != NULL && PTE_ISVALID(pte))
2158 if (va < virtual_end) {
2159 dump_map[2].pa_start = va;
2161 /* Find last page in chunk. */
2162 while (va < virtual_end) {
2163 /* Don't run into the buffer cache. */
2164 if (va == kmi.buffer_sva)
2166 pte = pte_find(kernel_pmap, va);
2167 if (pte == NULL || !PTE_ISVALID(pte))
2171 dump_map[2].pa_size = va - dump_map[2].pa_start;
2176 * Map a set of physical memory pages into the kernel virtual address space.
2177 * Return a pointer to where it is mapped. This routine is intended to be used
2178 * for mapping device memory, NOT real memory.
2181 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2184 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2188 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2192 for (i = 0; i < TLB1_ENTRIES; i++) {
2193 tlb1_read_entry(e, i);
2194 if ((e->mas1 & MAS1_VALID) == 0)
2203 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2207 #ifndef __powerpc64__
2210 uintptr_t va, retva;
2216 * Check if this is premapped in TLB1.
2221 wimge = tlb_calc_wimg(pa, ma);
2222 for (i = 0; i < TLB1_ENTRIES; i++) {
2223 tlb1_read_entry(&e, i);
2224 if (!(e.mas1 & MAS1_VALID))
2226 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2228 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2229 va = e.virt + (pa - e.phys);
2230 tmppa = e.phys + e.size;
2231 sz -= MIN(sz, e.size - (pa - e.phys));
2232 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2233 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2235 sz -= MIN(sz, e.size);
2236 tmppa = e.phys + e.size;
2240 return ((void *)va);
2244 size = roundup(size, PAGE_SIZE);
2246 #ifdef __powerpc64__
2247 KASSERT(pa < VM_MAPDEV_PA_MAX,
2248 ("Unsupported physical address! %lx", pa));
2249 va = VM_MAPDEV_BASE + pa;
2251 #ifdef POW2_MAPPINGS
2253 * Align the mapping to a power of 2 size, taking into account that we
2254 * may need to increase the size multiple times to satisfy the size and
2255 * alignment requirements.
2257 * This works in the general case because it's very rare (near never?)
2258 * to have different access properties (WIMG) within a single
2259 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2260 * can be undefined, and exact mappings will be used instead.
2263 size = roundup2(size, 1 << ilog2(size));
2264 while (rounddown2(va, size) + size < va + sz)
2266 va = rounddown2(va, size);
2267 pa = rounddown2(pa, size);
2271 * The device mapping area is between VM_MAXUSER_ADDRESS and
2272 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2274 #ifdef SPARSE_MAPDEV
2276 * With a sparse mapdev, align to the largest starting region. This
2277 * could feasibly be optimized for a 'best-fit' alignment, but that
2278 * calculation could be very costly.
2279 * Align to the smaller of:
2280 * - first set bit in overlap of (pa & size mask)
2281 * - largest size envelope
2283 * It's possible the device mapping may start at a PA that's not larger
2284 * than the size mask, so we need to offset in to maximize the TLB entry
2285 * range and minimize the number of used TLB entries.
2288 tmpva = tlb1_map_base;
2289 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2290 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2291 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2292 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2294 va = atomic_fetchadd_int(&tlb1_map_base, size);
2298 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2301 return ((void *)retva);
2305 * 'Unmap' a range mapped by mmu_booke_mapdev().
2308 mmu_booke_unmapdev(vm_offset_t va, vm_size_t size)
2310 #ifdef SUPPORTS_SHRINKING_TLB1
2311 vm_offset_t base, offset;
2314 * Unmap only if this is inside kernel virtual space.
2316 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2317 base = trunc_page(va);
2318 offset = va & PAGE_MASK;
2319 size = roundup(offset + size, PAGE_SIZE);
2320 mmu_booke_qremove(base, atop(size));
2321 kva_free(base, size);
2327 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2328 * specified pmap. This eliminates the blast of soft faults on process startup
2329 * and immediately after an mmap.
2332 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2333 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2336 VM_OBJECT_ASSERT_WLOCKED(object);
2337 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2338 ("mmu_booke_object_init_pt: non-device object"));
2342 * Perform the pmap work for mincore.
2345 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2348 /* XXX: this should be implemented at some point */
2353 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode)
2360 addr = trunc_page(addr);
2362 /* Only allow changes to mapped kernel addresses. This includes:
2364 * - DMAP (powerpc64)
2367 if (addr <= VM_MAXUSER_ADDRESS ||
2368 #ifdef __powerpc64__
2369 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2370 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2372 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2374 (addr > VM_MAX_KERNEL_ADDRESS))
2377 /* Check TLB1 mappings */
2378 for (i = 0; i < TLB1_ENTRIES; i++) {
2379 tlb1_read_entry(&e, i);
2380 if (!(e.mas1 & MAS1_VALID))
2382 if (addr >= e.virt && addr < e.virt + e.size)
2385 if (i < TLB1_ENTRIES) {
2386 /* Only allow full mappings to be modified for now. */
2387 /* Validate the range. */
2388 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2389 tlb1_read_entry(&e, j);
2390 if (va != e.virt || (sz - (va - addr) < e.size))
2393 for (va = addr; va < addr + sz; va += e.size, i++) {
2394 tlb1_read_entry(&e, i);
2395 e.mas2 &= ~MAS2_WIMGE_MASK;
2396 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2399 * Write it out to the TLB. Should really re-sync with other
2402 tlb1_write_entry(&e, i);
2407 /* Not in TLB1, try through pmap */
2408 /* First validate the range. */
2409 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2410 pte = pte_find(kernel_pmap, va);
2411 if (pte == NULL || !PTE_ISVALID(pte))
2415 mtx_lock_spin(&tlbivax_mutex);
2417 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2418 pte = pte_find(kernel_pmap, va);
2419 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2420 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2421 tlb0_flush_entry(va);
2424 mtx_unlock_spin(&tlbivax_mutex);
2430 mmu_booke_page_array_startup(long pages)
2432 vm_page_array_size = pages;
2435 /**************************************************************************/
2437 /**************************************************************************/
2440 * Allocate a TID. If necessary, steal one from someone else.
2441 * The new TID is flushed from the TLB before returning.
2444 tid_alloc(pmap_t pmap)
2449 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2451 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2453 thiscpu = PCPU_GET(cpuid);
2455 tid = PCPU_GET(booke.tid_next);
2458 PCPU_SET(booke.tid_next, tid + 1);
2460 /* If we are stealing TID then clear the relevant pmap's field */
2461 if (tidbusy[thiscpu][tid] != NULL) {
2462 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2464 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2466 /* Flush all entries from TLB0 matching this TID. */
2470 tidbusy[thiscpu][tid] = pmap;
2471 pmap->pm_tid[thiscpu] = tid;
2472 __asm __volatile("msync; isync");
2474 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2475 PCPU_GET(booke.tid_next));
2480 /**************************************************************************/
2482 /**************************************************************************/
2484 /* Convert TLB0 va and way number to tlb0[] table index. */
2485 static inline unsigned int
2486 tlb0_tableidx(vm_offset_t va, unsigned int way)
2490 idx = (way * TLB0_ENTRIES_PER_WAY);
2491 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2496 * Invalidate TLB0 entry.
2499 tlb0_flush_entry(vm_offset_t va)
2502 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2504 mtx_assert(&tlbivax_mutex, MA_OWNED);
2506 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2507 __asm __volatile("isync; msync");
2508 __asm __volatile("tlbsync; msync");
2510 CTR1(KTR_PMAP, "%s: e", __func__);
2513 /**************************************************************************/
2515 /**************************************************************************/
2518 * TLB1 mapping notes:
2520 * TLB1[0] Kernel text and data.
2521 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2522 * windows, other devices mappings.
2526 * Read an entry from given TLB1 slot.
2529 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2534 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2537 __asm __volatile("wrteei 0");
2539 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2540 mtspr(SPR_MAS0, mas0);
2541 __asm __volatile("isync; tlbre");
2543 entry->mas1 = mfspr(SPR_MAS1);
2544 entry->mas2 = mfspr(SPR_MAS2);
2545 entry->mas3 = mfspr(SPR_MAS3);
2547 switch ((mfpvr() >> 16) & 0xFFFF) {
2552 entry->mas7 = mfspr(SPR_MAS7);
2558 __asm __volatile("wrtee %0" :: "r"(msr));
2560 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2561 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2562 (entry->mas3 & MAS3_RPN);
2564 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2567 struct tlbwrite_args {
2573 tlb1_find_free(void)
2578 for (i = 0; i < TLB1_ENTRIES; i++) {
2579 tlb1_read_entry(&e, i);
2580 if ((e.mas1 & MAS1_VALID) == 0)
2587 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2592 for (i = 0; i < TLB1_ENTRIES; i++) {
2593 tlb1_read_entry(&e, i);
2594 if ((e.mas1 & MAS1_VALID) == 0)
2596 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2597 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2598 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2599 __asm __volatile("isync; tlbwe; isync; msync");
2605 tlb1_write_entry_int(void *arg)
2607 struct tlbwrite_args *args = arg;
2612 tlb1_purge_va_range(args->e->virt, args->e->size);
2613 idx = tlb1_find_free();
2615 panic("No free TLB1 entries!\n");
2618 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2620 mtspr(SPR_MAS0, mas0);
2621 mtspr(SPR_MAS1, args->e->mas1);
2622 mtspr(SPR_MAS2, args->e->mas2);
2623 mtspr(SPR_MAS3, args->e->mas3);
2624 switch ((mfpvr() >> 16) & 0xFFFF) {
2631 mtspr(SPR_MAS7, args->e->mas7);
2637 __asm __volatile("isync; tlbwe; isync; msync");
2642 tlb1_write_entry_sync(void *arg)
2644 /* Empty synchronization point for smp_rendezvous(). */
2648 * Write given entry to TLB1 hardware.
2651 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2653 struct tlbwrite_args args;
2659 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2661 smp_rendezvous(tlb1_write_entry_sync,
2662 tlb1_write_entry_int,
2663 tlb1_write_entry_sync, &args);
2670 __asm __volatile("wrteei 0");
2671 tlb1_write_entry_int(&args);
2672 __asm __volatile("wrtee %0" :: "r"(msr));
2677 * Convert TLB TSIZE value to mapped region size.
2680 tsize2size(unsigned int tsize)
2685 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2688 return ((1 << (2 * tsize)) * 1024);
2692 * Convert region size (must be power of 4) to TLB TSIZE value.
2695 size2tsize(vm_size_t size)
2698 return (ilog2(size) / 2 - 5);
2702 * Register permanent kernel mapping in TLB1.
2704 * Entries are created starting from index 0 (current free entry is
2705 * kept in tlb1_idx) and are not supposed to be invalidated.
2708 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2715 /* First try to update an existing entry. */
2716 for (index = 0; index < TLB1_ENTRIES; index++) {
2717 tlb1_read_entry(&e, index);
2718 /* Check if we're just updating the flags, and update them. */
2719 if (e.phys == pa && e.virt == va && e.size == size) {
2720 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2721 tlb1_write_entry(&e, index);
2726 /* Convert size to TSIZE */
2727 tsize = size2tsize(size);
2729 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2730 /* XXX TS is hard coded to 0 for now as we only use single address space */
2731 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2736 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2737 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2738 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2740 /* Set supervisor RWX permission bits */
2741 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2742 e.mas7 = (pa >> 32) & MAS7_RPN;
2744 tlb1_write_entry(&e, -1);
2750 * Map in contiguous RAM region into the TLB1.
2753 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2756 vm_size_t mapped, sz, ssize;
2763 sz = 1UL << (ilog2(size) & ~1);
2764 /* Align size to PA */
2768 } while (pa % sz != 0);
2770 /* Now align from there to VA */
2774 } while (va % sz != 0);
2776 #ifdef __powerpc64__
2778 * Clamp TLB1 entries to 4G.
2780 * While the e6500 supports up to 1TB mappings, the e5500
2781 * only supports up to 4G mappings. (0b1011)
2783 * If any e6500 machines capable of supporting a very
2784 * large amount of memory appear in the future, we can
2787 * For now, though, since we have plenty of space in TLB1,
2788 * always avoid creating entries larger than 4GB.
2790 sz = MIN(sz, 1UL << 32);
2793 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2794 (void *)va, (uintmax_t)pa, (long)sz);
2795 if (tlb1_set_entry(va, pa, sz,
2796 _TLB_ENTRY_SHARED | wimge) < 0)
2803 mapped = (va - base);
2805 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2806 mapped, mapped - ssize);
2812 * TLB1 initialization routine, to be called after the very first
2813 * assembler level setup done in locore.S.
2819 uint32_t mas0, mas1, mas3, mas7;
2824 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2825 mtspr(SPR_MAS0, mas0);
2826 __asm __volatile("isync; tlbre");
2828 mas1 = mfspr(SPR_MAS1);
2829 mas2 = mfspr(SPR_MAS2);
2830 mas3 = mfspr(SPR_MAS3);
2831 mas7 = mfspr(SPR_MAS7);
2833 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2836 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2837 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2838 kernstart = trunc_page(mas2);
2840 /* Setup TLB miss defaults */
2841 set_mas4_defaults();
2845 * pmap_early_io_unmap() should be used in short conjunction with
2846 * pmap_early_io_map(), as in the following snippet:
2848 * x = pmap_early_io_map(...);
2849 * <do something with x>
2850 * pmap_early_io_unmap(x, size);
2852 * And avoiding more allocations between.
2855 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2861 size = roundup(size, PAGE_SIZE);
2863 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2864 tlb1_read_entry(&e, i);
2865 if (!(e.mas1 & MAS1_VALID))
2867 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2869 e.mas1 &= ~MAS1_VALID;
2870 tlb1_write_entry(&e, i);
2873 if (tlb1_map_base == va + isize)
2874 tlb1_map_base -= isize;
2878 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2885 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2887 for (i = 0; i < TLB1_ENTRIES; i++) {
2888 tlb1_read_entry(&e, i);
2889 if (!(e.mas1 & MAS1_VALID))
2891 if (pa >= e.phys && (pa + size) <=
2893 return (e.virt + (pa - e.phys));
2896 pa_base = rounddown(pa, PAGE_SIZE);
2897 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2898 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2899 va = tlb1_map_base + (pa - pa_base);
2902 sz = 1 << (ilog2(size) & ~1);
2903 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2904 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2907 tlb1_map_base += sz;
2914 pmap_track_page(pmap_t pmap, vm_offset_t va)
2918 struct pv_entry *pve;
2920 va = trunc_page(va);
2921 pa = pmap_kextract(va);
2922 page = PHYS_TO_VM_PAGE(pa);
2924 rw_wlock(&pvh_global_lock);
2927 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
2928 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
2932 page->md.pv_tracked = true;
2933 pv_insert(pmap, va, page);
2936 rw_wunlock(&pvh_global_lock);
2940 * Setup MAS4 defaults.
2941 * These values are loaded to MAS0-2 on a TLB miss.
2944 set_mas4_defaults(void)
2948 /* Defaults: TLB0, PID0, TSIZED=4K */
2949 mas4 = MAS4_TLBSELD0;
2950 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
2954 mtspr(SPR_MAS4, mas4);
2955 __asm __volatile("isync");
2959 * Return 0 if the physical IO range is encompassed by one of the
2960 * the TLB1 entries, otherwise return related error code.
2963 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
2966 vm_paddr_t pa_start;
2968 unsigned int entry_tsize;
2969 vm_size_t entry_size;
2972 *va = (vm_offset_t)NULL;
2974 tlb1_read_entry(&e, i);
2975 /* Skip invalid entries */
2976 if (!(e.mas1 & MAS1_VALID))
2980 * The entry must be cache-inhibited, guarded, and r/w
2981 * so it can function as an i/o page
2983 prot = e.mas2 & (MAS2_I | MAS2_G);
2984 if (prot != (MAS2_I | MAS2_G))
2987 prot = e.mas3 & (MAS3_SR | MAS3_SW);
2988 if (prot != (MAS3_SR | MAS3_SW))
2991 /* The address should be within the entry range. */
2992 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2993 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
2995 entry_size = tsize2size(entry_tsize);
2996 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
2997 (e.mas3 & MAS3_RPN);
2998 pa_end = pa_start + entry_size;
3000 if ((pa < pa_start) || ((pa + size) > pa_end))
3003 /* Return virtual address of this mapping. */
3004 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3009 /* Print out contents of the MAS registers for each TLB0 entry */
3011 #ifdef __powerpc64__
3012 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3014 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3025 if (mas1 & MAS1_VALID)
3030 if (mas1 & MAS1_IPROT)
3035 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3036 tid = MAS1_GETTID(mas1);
3038 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3041 size = tsize2size(tsize);
3043 printf("%3d: (%s) [AS=%d] "
3044 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3045 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3046 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3049 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3051 uint32_t mas0, mas1, mas3, mas7;
3052 #ifdef __powerpc64__
3057 int entryidx, way, idx;
3059 printf("TLB0 entries:\n");
3060 for (way = 0; way < TLB0_WAYS; way ++)
3061 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3062 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3063 mtspr(SPR_MAS0, mas0);
3065 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3066 mtspr(SPR_MAS2, mas2);
3068 __asm __volatile("isync; tlbre");
3070 mas1 = mfspr(SPR_MAS1);
3071 mas2 = mfspr(SPR_MAS2);
3072 mas3 = mfspr(SPR_MAS3);
3073 mas7 = mfspr(SPR_MAS7);
3075 idx = tlb0_tableidx(mas2, way);
3076 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3081 * Print out contents of the MAS registers for each TLB1 entry
3083 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3085 uint32_t mas0, mas1, mas3, mas7;
3086 #ifdef __powerpc64__
3093 printf("TLB1 entries:\n");
3094 for (i = 0; i < TLB1_ENTRIES; i++) {
3095 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3096 mtspr(SPR_MAS0, mas0);
3098 __asm __volatile("isync; tlbre");
3100 mas1 = mfspr(SPR_MAS1);
3101 mas2 = mfspr(SPR_MAS2);
3102 mas3 = mfspr(SPR_MAS3);
3103 mas7 = mfspr(SPR_MAS7);
3105 tlb_print_entry(i, mas1, mas2, mas3, mas7);