2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
36 * Kernel and user threads run within one common virtual address space
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
76 #include <sys/cdefs.h>
77 __FBSDID("$FreeBSD$");
80 #include "opt_kstack_pages.h"
82 #include <sys/param.h>
84 #include <sys/malloc.h>
88 #include <sys/queue.h>
89 #include <sys/systm.h>
90 #include <sys/kernel.h>
91 #include <sys/kerneldump.h>
92 #include <sys/linker.h>
93 #include <sys/msgbuf.h>
95 #include <sys/mutex.h>
96 #include <sys/rwlock.h>
97 #include <sys/sched.h>
99 #include <sys/vmmeter.h>
102 #include <vm/vm_param.h>
103 #include <vm/vm_page.h>
104 #include <vm/vm_kern.h>
105 #include <vm/vm_pageout.h>
106 #include <vm/vm_extern.h>
107 #include <vm/vm_object.h>
108 #include <vm/vm_map.h>
109 #include <vm/vm_pager.h>
110 #include <vm/vm_phys.h>
111 #include <vm/vm_pagequeue.h>
112 #include <vm/vm_dumpset.h>
115 #include <machine/_inttypes.h>
116 #include <machine/cpu.h>
117 #include <machine/pcb.h>
118 #include <machine/platform.h>
120 #include <machine/tlb.h>
121 #include <machine/spr.h>
122 #include <machine/md_var.h>
123 #include <machine/mmuvar.h>
124 #include <machine/pmap.h>
125 #include <machine/pte.h>
129 #define SPARSE_MAPDEV
131 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
132 #define POW2_MAPPINGS
135 #define debugf(fmt, args...) printf(fmt, ##args)
138 #define debugf(fmt, args...)
139 #define __debug_used __unused
143 #define PRI0ptrX "016lx"
145 #define PRI0ptrX "08x"
148 #define TODO panic("%s: not implemented", __func__);
150 extern unsigned char _etext[];
151 extern unsigned char _end[];
153 extern uint32_t *bootinfo;
156 vm_offset_t kernstart;
159 /* Message buffer and tables. */
160 static vm_offset_t data_start;
161 static vm_size_t data_end;
163 /* Phys/avail memory regions. */
164 static struct mem_region *availmem_regions;
165 static int availmem_regions_sz;
166 static struct mem_region *physmem_regions;
167 static int physmem_regions_sz;
169 #ifndef __powerpc64__
170 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
171 static vm_offset_t zero_page_va;
172 static struct mtx zero_page_mutex;
174 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
175 static vm_offset_t copy_page_src_va;
176 static vm_offset_t copy_page_dst_va;
177 static struct mtx copy_page_mutex;
180 static struct mtx tlbivax_mutex;
182 /**************************************************************************/
184 /**************************************************************************/
186 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
187 vm_prot_t, u_int flags, int8_t psind);
189 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
190 static uma_zone_t ptbl_root_zone;
193 * If user pmap is processed with mmu_booke_remove and the resident count
194 * drops to 0, there are no more pages to remove, so we need not continue.
196 #define PMAP_REMOVE_DONE(pmap) \
197 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
199 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
200 extern int elf32_nxstack;
203 /**************************************************************************/
204 /* TLB and TID handling */
205 /**************************************************************************/
207 /* Translation ID busy table */
208 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
211 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
212 * core revisions and should be read from h/w registers during early config.
214 uint32_t tlb0_entries;
216 uint32_t tlb0_entries_per_way;
217 uint32_t tlb1_entries;
219 #define TLB0_ENTRIES (tlb0_entries)
220 #define TLB0_WAYS (tlb0_ways)
221 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
223 #define TLB1_ENTRIES (tlb1_entries)
225 static tlbtid_t tid_alloc(struct pmap *);
229 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
231 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
235 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
236 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
237 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
238 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
240 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
242 static vm_size_t tsize2size(unsigned int);
243 static unsigned int size2tsize(vm_size_t);
244 static unsigned long ilog2(unsigned long);
246 static void set_mas4_defaults(void);
248 static inline void tlb0_flush_entry(vm_offset_t);
249 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
251 /**************************************************************************/
252 /* Page table management */
253 /**************************************************************************/
255 static struct rwlock_padalign pvh_global_lock;
257 /* Data for the pv entry allocation mechanism */
258 static uma_zone_t pvzone;
259 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
261 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
263 #ifndef PMAP_SHPGPERPROC
264 #define PMAP_SHPGPERPROC 200
267 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
268 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
269 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
270 static pte_t *pte_find(pmap_t, vm_offset_t);
271 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
273 static pv_entry_t pv_alloc(void);
274 static void pv_free(pv_entry_t);
275 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
276 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
278 static void booke_pmap_init_qpages(void);
280 static inline void tlb_miss_lock(void);
281 static inline void tlb_miss_unlock(void);
284 extern tlb_entry_t __boot_tlb1[];
285 void pmap_bootstrap_ap(volatile uint32_t *);
289 * Kernel MMU interface
291 static void mmu_booke_clear_modify(vm_page_t);
292 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
293 vm_size_t, vm_offset_t);
294 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
295 static void mmu_booke_copy_pages(vm_page_t *,
296 vm_offset_t, vm_page_t *, vm_offset_t, int);
297 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
298 vm_prot_t, u_int flags, int8_t psind);
299 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
300 vm_page_t, vm_prot_t);
301 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
303 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
304 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
306 static void mmu_booke_init(void);
307 static boolean_t mmu_booke_is_modified(vm_page_t);
308 static boolean_t mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
309 static boolean_t mmu_booke_is_referenced(vm_page_t);
310 static int mmu_booke_ts_referenced(vm_page_t);
311 static vm_offset_t mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
313 static int mmu_booke_mincore(pmap_t, vm_offset_t,
315 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
316 vm_object_t, vm_pindex_t, vm_size_t);
317 static boolean_t mmu_booke_page_exists_quick(pmap_t, vm_page_t);
318 static void mmu_booke_page_init(vm_page_t);
319 static int mmu_booke_page_wired_mappings(vm_page_t);
320 static int mmu_booke_pinit(pmap_t);
321 static void mmu_booke_pinit0(pmap_t);
322 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
324 static void mmu_booke_qenter(vm_offset_t, vm_page_t *, int);
325 static void mmu_booke_qremove(vm_offset_t, int);
326 static void mmu_booke_release(pmap_t);
327 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
328 static void mmu_booke_remove_all(vm_page_t);
329 static void mmu_booke_remove_write(vm_page_t);
330 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
331 static void mmu_booke_zero_page(vm_page_t);
332 static void mmu_booke_zero_page_area(vm_page_t, int, int);
333 static void mmu_booke_activate(struct thread *);
334 static void mmu_booke_deactivate(struct thread *);
335 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
336 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
337 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
338 static void mmu_booke_unmapdev(void *, vm_size_t);
339 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
340 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
341 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
342 static void mmu_booke_kremove(vm_offset_t);
343 static int mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
344 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
346 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
348 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
350 static void mmu_booke_scan_init(void);
351 static vm_offset_t mmu_booke_quick_enter_page(vm_page_t m);
352 static void mmu_booke_quick_remove_page(vm_offset_t addr);
353 static int mmu_booke_change_attr(vm_offset_t addr,
354 vm_size_t sz, vm_memattr_t mode);
355 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
356 int *is_user, vm_offset_t *decoded_addr);
357 static void mmu_booke_page_array_startup(long);
358 static boolean_t mmu_booke_page_is_mapped(vm_page_t m);
359 static bool mmu_booke_ps_enabled(pmap_t pmap);
361 static struct pmap_funcs mmu_booke_methods = {
362 /* pmap dispatcher interface */
363 .clear_modify = mmu_booke_clear_modify,
364 .copy = mmu_booke_copy,
365 .copy_page = mmu_booke_copy_page,
366 .copy_pages = mmu_booke_copy_pages,
367 .enter = mmu_booke_enter,
368 .enter_object = mmu_booke_enter_object,
369 .enter_quick = mmu_booke_enter_quick,
370 .extract = mmu_booke_extract,
371 .extract_and_hold = mmu_booke_extract_and_hold,
372 .init = mmu_booke_init,
373 .is_modified = mmu_booke_is_modified,
374 .is_prefaultable = mmu_booke_is_prefaultable,
375 .is_referenced = mmu_booke_is_referenced,
376 .ts_referenced = mmu_booke_ts_referenced,
377 .map = mmu_booke_map,
378 .mincore = mmu_booke_mincore,
379 .object_init_pt = mmu_booke_object_init_pt,
380 .page_exists_quick = mmu_booke_page_exists_quick,
381 .page_init = mmu_booke_page_init,
382 .page_wired_mappings = mmu_booke_page_wired_mappings,
383 .pinit = mmu_booke_pinit,
384 .pinit0 = mmu_booke_pinit0,
385 .protect = mmu_booke_protect,
386 .qenter = mmu_booke_qenter,
387 .qremove = mmu_booke_qremove,
388 .release = mmu_booke_release,
389 .remove = mmu_booke_remove,
390 .remove_all = mmu_booke_remove_all,
391 .remove_write = mmu_booke_remove_write,
392 .sync_icache = mmu_booke_sync_icache,
393 .unwire = mmu_booke_unwire,
394 .zero_page = mmu_booke_zero_page,
395 .zero_page_area = mmu_booke_zero_page_area,
396 .activate = mmu_booke_activate,
397 .deactivate = mmu_booke_deactivate,
398 .quick_enter_page = mmu_booke_quick_enter_page,
399 .quick_remove_page = mmu_booke_quick_remove_page,
400 .page_array_startup = mmu_booke_page_array_startup,
401 .page_is_mapped = mmu_booke_page_is_mapped,
402 .ps_enabled = mmu_booke_ps_enabled,
404 /* Internal interfaces */
405 .bootstrap = mmu_booke_bootstrap,
406 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
407 .mapdev = mmu_booke_mapdev,
408 .mapdev_attr = mmu_booke_mapdev_attr,
409 .kenter = mmu_booke_kenter,
410 .kenter_attr = mmu_booke_kenter_attr,
411 .kextract = mmu_booke_kextract,
412 .kremove = mmu_booke_kremove,
413 .unmapdev = mmu_booke_unmapdev,
414 .change_attr = mmu_booke_change_attr,
415 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
417 /* dumpsys() support */
418 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
419 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
420 .dumpsys_pa_init = mmu_booke_scan_init,
423 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
431 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
433 static __inline uint32_t
434 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
439 if (ma != VM_MEMATTR_DEFAULT) {
441 case VM_MEMATTR_UNCACHEABLE:
442 return (MAS2_I | MAS2_G);
443 case VM_MEMATTR_WRITE_COMBINING:
444 case VM_MEMATTR_WRITE_BACK:
445 case VM_MEMATTR_PREFETCHABLE:
447 case VM_MEMATTR_WRITE_THROUGH:
448 return (MAS2_W | MAS2_M);
449 case VM_MEMATTR_CACHEABLE:
455 * Assume the page is cache inhibited and access is guarded unless
456 * it's in our available memory array.
458 attrib = _TLB_ENTRY_IO;
459 for (i = 0; i < physmem_regions_sz; i++) {
460 if ((pa >= physmem_regions[i].mr_start) &&
461 (pa < (physmem_regions[i].mr_start +
462 physmem_regions[i].mr_size))) {
463 attrib = _TLB_ENTRY_MEM;
480 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
482 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
483 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
485 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
486 ("tlb_miss_lock: tried to lock self"));
488 tlb_lock(pc->pc_booke.tlb_lock);
490 CTR1(KTR_PMAP, "%s: locked", __func__);
497 tlb_miss_unlock(void)
505 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
507 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
508 __func__, pc->pc_cpuid);
510 tlb_unlock(pc->pc_booke.tlb_lock);
512 CTR1(KTR_PMAP, "%s: unlocked", __func__);
518 /* Return number of entries in TLB0. */
520 tlb0_get_tlbconf(void)
524 tlb0_cfg = mfspr(SPR_TLB0CFG);
525 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
526 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
527 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
530 /* Return number of entries in TLB1. */
532 tlb1_get_tlbconf(void)
536 tlb1_cfg = mfspr(SPR_TLB1CFG);
537 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
540 /**************************************************************************/
541 /* Page table related */
542 /**************************************************************************/
544 /* Allocate pv_entry structure. */
551 if (pv_entry_count > pv_entry_high_water)
552 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
553 pv = uma_zalloc(pvzone, M_NOWAIT);
558 /* Free pv_entry structure. */
560 pv_free(pv_entry_t pve)
564 uma_zfree(pvzone, pve);
567 /* Allocate and initialize pv_entry structure. */
569 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
573 //int su = (pmap == kernel_pmap);
574 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
575 // (u_int32_t)pmap, va, (u_int32_t)m);
579 panic("pv_insert: no pv entries!");
585 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
586 rw_assert(&pvh_global_lock, RA_WLOCKED);
588 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
590 //debugf("pv_insert: e\n");
593 /* Destroy pv entry. */
595 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
599 //int su = (pmap == kernel_pmap);
600 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
602 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
603 rw_assert(&pvh_global_lock, RA_WLOCKED);
606 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
607 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
608 /* remove from pv_list */
609 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
610 if (TAILQ_EMPTY(&m->md.pv_list))
611 vm_page_aflag_clear(m, PGA_WRITEABLE);
613 /* free pv entry struct */
619 //debugf("pv_remove: e\n");
622 /**************************************************************************/
624 /**************************************************************************/
627 * This is called during booke_init, before the system is really initialized.
630 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
632 vm_paddr_t phys_kernelend;
633 struct mem_region *mp, *mp1;
636 vm_paddr_t physsz, hwphyssz;
637 u_int phys_avail_count __debug_used;
638 vm_size_t kstack0_sz;
639 vm_paddr_t kstack0_phys;
643 debugf("mmu_booke_bootstrap: entered\n");
645 /* Set interesting system properties */
651 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
655 /* Initialize invalidation mutex */
656 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
658 /* Read TLB0 size and associativity. */
662 * Align kernel start and end address (kernel image).
663 * Note that kernel end does not necessarily relate to kernsize.
664 * kernsize is the size of the kernel that is actually mapped.
666 data_start = round_page(kernelend);
667 data_end = data_start;
669 /* Allocate the dynamic per-cpu area. */
670 dpcpu = (void *)data_end;
671 data_end += DPCPU_SIZE;
673 /* Allocate space for the message buffer. */
674 msgbufp = (struct msgbuf *)data_end;
675 data_end += msgbufsize;
676 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
677 (uintptr_t)msgbufp, data_end);
679 data_end = round_page(data_end);
680 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
682 /* Retrieve phys/avail mem regions */
683 mem_regions(&physmem_regions, &physmem_regions_sz,
684 &availmem_regions, &availmem_regions_sz);
686 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
687 panic("mmu_booke_bootstrap: phys_avail too small");
689 data_end = round_page(data_end);
690 vm_page_array = (vm_page_t)data_end;
692 * Get a rough idea (upper bound) on the size of the page array. The
693 * vm_page_array will not handle any more pages than we have in the
694 * avail_regions array, and most likely much less.
697 for (mp = availmem_regions; mp->mr_size; mp++) {
700 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
701 data_end += round_page(sz * sizeof(struct vm_page));
703 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
704 data_end = roundup2(data_end, 1 << 20);
706 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
707 debugf(" kernstart: %#zx\n", kernstart);
708 debugf(" kernsize: %#zx\n", kernsize);
710 if (data_end - kernstart > kernsize) {
711 kernsize += tlb1_mapin_region(kernstart + kernsize,
712 kernload + kernsize, (data_end - kernstart) - kernsize,
715 data_end = kernstart + kernsize;
716 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
719 * Clear the structures - note we can only do it safely after the
720 * possible additional TLB1 translations are in place (above) so that
721 * all range up to the currently calculated 'data_end' is covered.
723 bzero((void *)data_start, data_end - data_start);
724 dpcpu_init(dpcpu, 0);
726 /*******************************************************/
727 /* Set the start and end of kva. */
728 /*******************************************************/
729 virtual_avail = round_page(data_end);
730 virtual_end = VM_MAX_KERNEL_ADDRESS;
732 #ifndef __powerpc64__
733 /* Allocate KVA space for page zero/copy operations. */
734 zero_page_va = virtual_avail;
735 virtual_avail += PAGE_SIZE;
736 copy_page_src_va = virtual_avail;
737 virtual_avail += PAGE_SIZE;
738 copy_page_dst_va = virtual_avail;
739 virtual_avail += PAGE_SIZE;
740 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
741 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
742 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
744 /* Initialize page zero/copy mutexes. */
745 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
746 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
748 /* Allocate KVA space for ptbl bufs. */
749 ptbl_buf_pool_vabase = virtual_avail;
750 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
751 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
752 ptbl_buf_pool_vabase, virtual_avail);
755 /* Calculate corresponding physical addresses for the kernel region. */
756 phys_kernelend = kernload + kernsize;
757 debugf("kernel image and allocated data:\n");
758 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
759 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
760 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
763 * Remove kernel physical address range from avail regions list. Page
764 * align all regions. Non-page aligned memory isn't very interesting
765 * to us. Also, sort the entries for ascending addresses.
769 cnt = availmem_regions_sz;
770 debugf("processing avail regions:\n");
771 for (mp = availmem_regions; mp->mr_size; mp++) {
773 e = mp->mr_start + mp->mr_size;
774 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
775 /* Check whether this region holds all of the kernel. */
776 if (s < kernload && e > phys_kernelend) {
777 availmem_regions[cnt].mr_start = phys_kernelend;
778 availmem_regions[cnt++].mr_size = e - phys_kernelend;
781 /* Look whether this regions starts within the kernel. */
782 if (s >= kernload && s < phys_kernelend) {
783 if (e <= phys_kernelend)
787 /* Now look whether this region ends within the kernel. */
788 if (e > kernload && e <= phys_kernelend) {
793 /* Now page align the start and size of the region. */
799 debugf("%09jx-%09jx = %jx\n",
800 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
802 /* Check whether some memory is left here. */
806 (cnt - (mp - availmem_regions)) * sizeof(*mp));
812 /* Do an insertion sort. */
813 for (mp1 = availmem_regions; mp1 < mp; mp1++)
814 if (s < mp1->mr_start)
817 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
825 availmem_regions_sz = cnt;
827 /*******************************************************/
828 /* Steal physical memory for kernel stack from the end */
829 /* of the first avail region */
830 /*******************************************************/
831 kstack0_sz = kstack_pages * PAGE_SIZE;
832 kstack0_phys = availmem_regions[0].mr_start +
833 availmem_regions[0].mr_size;
834 kstack0_phys -= kstack0_sz;
835 availmem_regions[0].mr_size -= kstack0_sz;
837 /*******************************************************/
838 /* Fill in phys_avail table, based on availmem_regions */
839 /*******************************************************/
840 phys_avail_count = 0;
843 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
845 debugf("fill in phys_avail:\n");
846 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
847 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
848 (uintmax_t)availmem_regions[i].mr_start,
849 (uintmax_t)availmem_regions[i].mr_start +
850 availmem_regions[i].mr_size,
851 (uintmax_t)availmem_regions[i].mr_size);
854 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
855 debugf(" hw.physmem adjust\n");
856 if (physsz < hwphyssz) {
857 phys_avail[j] = availmem_regions[i].mr_start;
859 availmem_regions[i].mr_start +
863 dump_avail[j] = phys_avail[j];
864 dump_avail[j + 1] = phys_avail[j + 1];
869 phys_avail[j] = availmem_regions[i].mr_start;
870 phys_avail[j + 1] = availmem_regions[i].mr_start +
871 availmem_regions[i].mr_size;
873 physsz += availmem_regions[i].mr_size;
874 dump_avail[j] = phys_avail[j];
875 dump_avail[j + 1] = phys_avail[j + 1];
877 physmem = btoc(physsz);
879 /* Calculate the last available physical address. */
880 for (i = 0; phys_avail[i + 2] != 0; i += 2)
882 Maxmem = powerpc_btop(phys_avail[i + 1]);
884 debugf("Maxmem = 0x%08lx\n", Maxmem);
885 debugf("phys_avail_count = %d\n", phys_avail_count);
886 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
887 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
891 * Map the physical memory contiguously in TLB1.
892 * Round so it fits into a single mapping.
894 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
895 phys_avail[i + 1], _TLB_ENTRY_MEM);
898 /*******************************************************/
899 /* Initialize (statically allocated) kernel pmap. */
900 /*******************************************************/
901 PMAP_LOCK_INIT(kernel_pmap);
903 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
904 kernel_pte_alloc(virtual_avail, kernstart);
905 for (i = 0; i < MAXCPU; i++) {
906 kernel_pmap->pm_tid[i] = TID_KERNEL;
908 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
909 tidbusy[i][TID_KERNEL] = kernel_pmap;
912 /* Mark kernel_pmap active on all CPUs */
913 CPU_FILL(&kernel_pmap->pm_active);
916 * Initialize the global pv list lock.
918 rw_init(&pvh_global_lock, "pmap pv global");
920 /*******************************************************/
922 /*******************************************************/
924 /* Enter kstack0 into kernel map, provide guard page */
925 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
926 thread0.td_kstack = kstack0;
927 thread0.td_kstack_pages = kstack_pages;
929 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
930 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
931 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
932 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
933 kstack0, kstack0 + kstack0_sz);
935 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
936 for (i = 0; i < kstack_pages; i++) {
937 mmu_booke_kenter(kstack0, kstack0_phys);
938 kstack0 += PAGE_SIZE;
939 kstack0_phys += PAGE_SIZE;
942 pmap_bootstrapped = 1;
944 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
945 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
947 debugf("mmu_booke_bootstrap: exit\n");
957 /* Prepare TLB1 image for AP processors */
959 for (i = 0; i < TLB1_ENTRIES; i++) {
960 tlb1_read_entry(&tmp, i);
962 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
963 memcpy(e++, &tmp, sizeof(tmp));
968 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
973 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
974 * have the snapshot of its contents in the s/w __boot_tlb1[] table
975 * created by tlb1_ap_prep(), so use these values directly to
976 * (re)program AP's TLB1 hardware.
978 * Start at index 1 because index 0 has the kernel map.
980 for (i = 1; i < TLB1_ENTRIES; i++) {
981 if (__boot_tlb1[i].mas1 & MAS1_VALID)
982 tlb1_write_entry(&__boot_tlb1[i], i);
990 booke_pmap_init_qpages(void)
997 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
998 if (pc->pc_qmap_addr == 0)
999 panic("pmap_init_qpages: unable to allocate KVA");
1003 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1006 * Get the physical page address for the given pmap/virtual address.
1009 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1014 pa = pte_vatopa(pmap, va);
1021 * Extract the physical page address associated with the given
1022 * kernel virtual address.
1025 mmu_booke_kextract(vm_offset_t va)
1031 #ifdef __powerpc64__
1032 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1033 return (DMAP_TO_PHYS(va));
1036 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1037 p = pte_vatopa(kernel_pmap, va);
1040 /* Check TLB1 mappings */
1041 for (i = 0; i < TLB1_ENTRIES; i++) {
1042 tlb1_read_entry(&e, i);
1043 if (!(e.mas1 & MAS1_VALID))
1045 if (va >= e.virt && va < e.virt + e.size)
1046 return (e.phys + (va - e.virt));
1054 * Initialize the pmap module.
1055 * Called by vm_init, to initialize any structures that the pmap
1056 * system needs to map virtual memory.
1059 mmu_booke_init(void)
1061 int shpgperproc = PMAP_SHPGPERPROC;
1064 * Initialize the address space (zone) for the pv entries. Set a
1065 * high water mark so that the system can recover from excessive
1066 * numbers of pv entries.
1068 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1069 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1071 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1072 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1074 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1075 pv_entry_high_water = 9 * (pv_entry_max / 10);
1077 uma_zone_reserve_kva(pvzone, pv_entry_max);
1079 /* Pre-fill pvzone with initial number of pv entries. */
1080 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1082 /* Create a UMA zone for page table roots. */
1083 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1084 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1086 /* Initialize ptbl allocation. */
1091 * Map a list of wired pages into kernel virtual address space. This is
1092 * intended for temporary mappings which do not need page modification or
1093 * references recorded. Existing mappings in the region are overwritten.
1096 mmu_booke_qenter(vm_offset_t sva, vm_page_t *m, int count)
1101 while (count-- > 0) {
1102 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1109 * Remove page mappings from kernel virtual address space. Intended for
1110 * temporary mappings entered by mmu_booke_qenter.
1113 mmu_booke_qremove(vm_offset_t sva, int count)
1118 while (count-- > 0) {
1119 mmu_booke_kremove(va);
1125 * Map a wired page into kernel virtual address space.
1128 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1131 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1135 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1140 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1141 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1143 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1144 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1145 flags |= PTE_PS_4KB;
1147 pte = pte_find(kernel_pmap, va);
1148 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1150 mtx_lock_spin(&tlbivax_mutex);
1153 if (PTE_ISVALID(pte)) {
1154 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1156 /* Flush entry from TLB0 */
1157 tlb0_flush_entry(va);
1160 *pte = PTE_RPN_FROM_PA(pa) | flags;
1162 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1163 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1164 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1166 /* Flush the real memory from the instruction cache. */
1167 if ((flags & (PTE_I | PTE_G)) == 0)
1168 __syncicache((void *)va, PAGE_SIZE);
1171 mtx_unlock_spin(&tlbivax_mutex);
1175 * Remove a page from kernel page table.
1178 mmu_booke_kremove(vm_offset_t va)
1182 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1184 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1185 (va <= VM_MAX_KERNEL_ADDRESS)),
1186 ("mmu_booke_kremove: invalid va"));
1188 pte = pte_find(kernel_pmap, va);
1190 if (!PTE_ISVALID(pte)) {
1191 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1196 mtx_lock_spin(&tlbivax_mutex);
1199 /* Invalidate entry in TLB0, update PTE. */
1200 tlb0_flush_entry(va);
1204 mtx_unlock_spin(&tlbivax_mutex);
1208 * Figure out where a given kernel pointer (usually in a fault) points
1209 * to from the VM's perspective, potentially remapping into userland's
1213 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1214 vm_offset_t *decoded_addr)
1217 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1222 *decoded_addr = addr;
1227 mmu_booke_page_is_mapped(vm_page_t m)
1230 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1234 mmu_booke_ps_enabled(pmap_t pmap __unused)
1240 * Initialize pmap associated with process 0.
1243 mmu_booke_pinit0(pmap_t pmap)
1246 PMAP_LOCK_INIT(pmap);
1247 mmu_booke_pinit(pmap);
1248 PCPU_SET(curpmap, pmap);
1252 * Insert the given physical page at the specified virtual address in the
1253 * target physical map with the protection requested. If specified the page
1254 * will be wired down.
1257 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1258 vm_prot_t prot, u_int flags, int8_t psind)
1262 rw_wlock(&pvh_global_lock);
1264 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1266 rw_wunlock(&pvh_global_lock);
1271 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1272 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1277 int error, su, sync;
1279 pa = VM_PAGE_TO_PHYS(m);
1280 su = (pmap == kernel_pmap);
1283 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1284 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1285 // (u_int32_t)pmap, su, pmap->pm_tid,
1286 // (u_int32_t)m, va, pa, prot, flags);
1289 KASSERT(((va >= virtual_avail) &&
1290 (va <= VM_MAX_KERNEL_ADDRESS)),
1291 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1293 KASSERT((va <= VM_MAXUSER_ADDRESS),
1294 ("mmu_booke_enter_locked: user pmap, non user va"));
1296 if ((m->oflags & VPO_UNMANAGED) == 0) {
1297 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1298 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1300 VM_OBJECT_ASSERT_LOCKED(m->object);
1303 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1306 * If there is an existing mapping, and the physical address has not
1307 * changed, must be protection or wiring change.
1309 if (((pte = pte_find(pmap, va)) != NULL) &&
1310 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1313 * Before actually updating pte->flags we calculate and
1314 * prepare its new value in a helper var.
1317 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1319 /* Wiring change, just update stats. */
1320 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1321 if (!PTE_ISWIRED(pte)) {
1323 pmap->pm_stats.wired_count++;
1326 if (PTE_ISWIRED(pte)) {
1327 flags &= ~PTE_WIRED;
1328 pmap->pm_stats.wired_count--;
1332 if (prot & VM_PROT_WRITE) {
1333 /* Add write permissions. */
1338 if ((flags & PTE_MANAGED) != 0)
1339 vm_page_aflag_set(m, PGA_WRITEABLE);
1341 /* Handle modified pages, sense modify status. */
1344 * The PTE_MODIFIED flag could be set by underlying
1345 * TLB misses since we last read it (above), possibly
1346 * other CPUs could update it so we check in the PTE
1347 * directly rather than rely on that saved local flags
1350 if (PTE_ISMODIFIED(pte))
1354 if (prot & VM_PROT_EXECUTE) {
1360 * Check existing flags for execute permissions: if we
1361 * are turning execute permissions on, icache should
1364 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1368 flags &= ~PTE_REFERENCED;
1371 * The new flags value is all calculated -- only now actually
1374 mtx_lock_spin(&tlbivax_mutex);
1377 tlb0_flush_entry(va);
1378 *pte &= ~PTE_FLAGS_MASK;
1382 mtx_unlock_spin(&tlbivax_mutex);
1386 * If there is an existing mapping, but it's for a different
1387 * physical address, pte_enter() will delete the old mapping.
1389 //if ((pte != NULL) && PTE_ISVALID(pte))
1390 // debugf("mmu_booke_enter_locked: replace\n");
1392 // debugf("mmu_booke_enter_locked: new\n");
1394 /* Now set up the flags and install the new mapping. */
1395 flags = (PTE_SR | PTE_VALID);
1401 if (prot & VM_PROT_WRITE) {
1406 if ((m->oflags & VPO_UNMANAGED) == 0)
1407 vm_page_aflag_set(m, PGA_WRITEABLE);
1410 if (prot & VM_PROT_EXECUTE) {
1416 /* If its wired update stats. */
1417 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1420 error = pte_enter(pmap, m, va, flags,
1421 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1423 return (KERN_RESOURCE_SHORTAGE);
1425 if ((flags & PMAP_ENTER_WIRED) != 0)
1426 pmap->pm_stats.wired_count++;
1428 /* Flush the real memory from the instruction cache. */
1429 if (prot & VM_PROT_EXECUTE)
1433 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1434 __syncicache((void *)va, PAGE_SIZE);
1438 return (KERN_SUCCESS);
1442 * Maps a sequence of resident pages belonging to the same object.
1443 * The sequence begins with the given page m_start. This page is
1444 * mapped at the given virtual address start. Each subsequent page is
1445 * mapped at a virtual address that is offset from start by the same
1446 * amount as the page is offset from m_start within the object. The
1447 * last page in the sequence is the page with the largest offset from
1448 * m_start that can be mapped at a virtual address less than the given
1449 * virtual address end. Not every virtual page between start and end
1450 * is mapped; only those for which a resident page exists with the
1451 * corresponding offset from m_start are mapped.
1454 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1455 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1458 vm_pindex_t diff, psize;
1460 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1462 psize = atop(end - start);
1464 rw_wlock(&pvh_global_lock);
1466 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1467 mmu_booke_enter_locked(pmap, start + ptoa(diff), m,
1468 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1469 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1470 m = TAILQ_NEXT(m, listq);
1473 rw_wunlock(&pvh_global_lock);
1477 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1481 rw_wlock(&pvh_global_lock);
1483 mmu_booke_enter_locked(pmap, va, m,
1484 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1485 PMAP_ENTER_QUICK_LOCKED, 0);
1487 rw_wunlock(&pvh_global_lock);
1491 * Remove the given range of addresses from the specified map.
1493 * It is assumed that the start and end are properly rounded to the page size.
1496 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1501 int su = (pmap == kernel_pmap);
1503 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1504 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1507 KASSERT(((va >= virtual_avail) &&
1508 (va <= VM_MAX_KERNEL_ADDRESS)),
1509 ("mmu_booke_remove: kernel pmap, non kernel va"));
1511 KASSERT((va <= VM_MAXUSER_ADDRESS),
1512 ("mmu_booke_remove: user pmap, non user va"));
1515 if (PMAP_REMOVE_DONE(pmap)) {
1516 //debugf("mmu_booke_remove: e (empty)\n");
1520 hold_flag = PTBL_HOLD_FLAG(pmap);
1521 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1523 rw_wlock(&pvh_global_lock);
1525 for (; va < endva; va += PAGE_SIZE) {
1526 pte = pte_find_next(pmap, &va);
1527 if ((pte == NULL) || !PTE_ISVALID(pte))
1531 pte_remove(pmap, va, hold_flag);
1534 rw_wunlock(&pvh_global_lock);
1536 //debugf("mmu_booke_remove: e\n");
1540 * Remove physical page from all pmaps in which it resides.
1543 mmu_booke_remove_all(vm_page_t m)
1548 rw_wlock(&pvh_global_lock);
1549 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1550 PMAP_LOCK(pv->pv_pmap);
1551 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1552 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1553 PMAP_UNLOCK(pv->pv_pmap);
1555 vm_page_aflag_clear(m, PGA_WRITEABLE);
1556 rw_wunlock(&pvh_global_lock);
1560 * Map a range of physical addresses into kernel virtual address space.
1563 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1564 vm_paddr_t pa_end, int prot)
1566 vm_offset_t sva = *virt;
1567 vm_offset_t va = sva;
1569 #ifdef __powerpc64__
1570 /* XXX: Handle memory not starting at 0x0. */
1571 if (pa_end < ctob(Maxmem))
1572 return (PHYS_TO_DMAP(pa_start));
1575 while (pa_start < pa_end) {
1576 mmu_booke_kenter(va, pa_start);
1578 pa_start += PAGE_SIZE;
1586 * The pmap must be activated before it's address space can be accessed in any
1590 mmu_booke_activate(struct thread *td)
1595 pmap = &td->td_proc->p_vmspace->vm_pmap;
1597 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1598 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1600 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1604 cpuid = PCPU_GET(cpuid);
1605 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1606 PCPU_SET(curpmap, pmap);
1608 if (pmap->pm_tid[cpuid] == TID_NONE)
1611 /* Load PID0 register with pmap tid value. */
1612 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1613 __asm __volatile("isync");
1615 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1619 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1620 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1624 * Deactivate the specified process's address space.
1627 mmu_booke_deactivate(struct thread *td)
1631 pmap = &td->td_proc->p_vmspace->vm_pmap;
1633 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1634 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1636 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1638 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1639 PCPU_SET(curpmap, NULL);
1643 * Copy the range specified by src_addr/len
1644 * from the source map to the range dst_addr/len
1645 * in the destination map.
1647 * This routine is only advisory and need not do anything.
1650 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1651 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1657 * Set the physical protection on the specified range of this map as requested.
1660 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1667 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1668 mmu_booke_remove(pmap, sva, eva);
1672 if (prot & VM_PROT_WRITE)
1676 for (va = sva; va < eva; va += PAGE_SIZE) {
1677 if ((pte = pte_find(pmap, va)) != NULL) {
1678 if (PTE_ISVALID(pte)) {
1679 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1681 mtx_lock_spin(&tlbivax_mutex);
1684 /* Handle modified pages. */
1685 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1688 tlb0_flush_entry(va);
1689 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1692 mtx_unlock_spin(&tlbivax_mutex);
1700 * Clear the write and modified bits in each of the given page's mappings.
1703 mmu_booke_remove_write(vm_page_t m)
1708 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1709 ("mmu_booke_remove_write: page %p is not managed", m));
1710 vm_page_assert_busied(m);
1712 if (!pmap_page_is_write_mapped(m))
1714 rw_wlock(&pvh_global_lock);
1715 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1716 PMAP_LOCK(pv->pv_pmap);
1717 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1718 if (PTE_ISVALID(pte)) {
1719 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1721 mtx_lock_spin(&tlbivax_mutex);
1724 /* Handle modified pages. */
1725 if (PTE_ISMODIFIED(pte))
1728 /* Flush mapping from TLB0. */
1729 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1732 mtx_unlock_spin(&tlbivax_mutex);
1735 PMAP_UNLOCK(pv->pv_pmap);
1737 vm_page_aflag_clear(m, PGA_WRITEABLE);
1738 rw_wunlock(&pvh_global_lock);
1742 * Atomically extract and hold the physical page with the given
1743 * pmap and virtual address pair if that mapping permits the given
1747 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1756 pte = pte_find(pmap, va);
1757 if ((pte != NULL) && PTE_ISVALID(pte)) {
1758 if (pmap == kernel_pmap)
1763 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1764 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1765 if (!vm_page_wire_mapped(m))
1774 * Initialize a vm_page's machine-dependent fields.
1777 mmu_booke_page_init(vm_page_t m)
1780 m->md.pv_tracked = 0;
1781 TAILQ_INIT(&m->md.pv_list);
1785 * Return whether or not the specified physical page was modified
1786 * in any of physical maps.
1789 mmu_booke_is_modified(vm_page_t m)
1795 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1796 ("mmu_booke_is_modified: page %p is not managed", m));
1800 * If the page is not busied then this check is racy.
1802 if (!pmap_page_is_write_mapped(m))
1805 rw_wlock(&pvh_global_lock);
1806 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1807 PMAP_LOCK(pv->pv_pmap);
1808 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1810 if (PTE_ISMODIFIED(pte))
1813 PMAP_UNLOCK(pv->pv_pmap);
1817 rw_wunlock(&pvh_global_lock);
1822 * Return whether or not the specified virtual address is eligible
1826 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1833 * Return whether or not the specified physical page was referenced
1834 * in any physical maps.
1837 mmu_booke_is_referenced(vm_page_t m)
1843 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1844 ("mmu_booke_is_referenced: page %p is not managed", m));
1846 rw_wlock(&pvh_global_lock);
1847 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1848 PMAP_LOCK(pv->pv_pmap);
1849 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1851 if (PTE_ISREFERENCED(pte))
1854 PMAP_UNLOCK(pv->pv_pmap);
1858 rw_wunlock(&pvh_global_lock);
1863 * Clear the modify bits on the specified physical page.
1866 mmu_booke_clear_modify(vm_page_t m)
1871 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1872 ("mmu_booke_clear_modify: page %p is not managed", m));
1873 vm_page_assert_busied(m);
1875 if (!pmap_page_is_write_mapped(m))
1878 rw_wlock(&pvh_global_lock);
1879 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1880 PMAP_LOCK(pv->pv_pmap);
1881 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1883 mtx_lock_spin(&tlbivax_mutex);
1886 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1887 tlb0_flush_entry(pv->pv_va);
1888 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1893 mtx_unlock_spin(&tlbivax_mutex);
1895 PMAP_UNLOCK(pv->pv_pmap);
1897 rw_wunlock(&pvh_global_lock);
1901 * Return a count of reference bits for a page, clearing those bits.
1902 * It is not necessary for every reference bit to be cleared, but it
1903 * is necessary that 0 only be returned when there are truly no
1904 * reference bits set.
1906 * As an optimization, update the page's dirty field if a modified bit is
1907 * found while counting reference bits. This opportunistic update can be
1908 * performed at low cost and can eliminate the need for some future calls
1909 * to pmap_is_modified(). However, since this function stops after
1910 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1911 * dirty pages. Those dirty pages will only be detected by a future call
1912 * to pmap_is_modified().
1915 mmu_booke_ts_referenced(vm_page_t m)
1921 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1922 ("mmu_booke_ts_referenced: page %p is not managed", m));
1924 rw_wlock(&pvh_global_lock);
1925 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1926 PMAP_LOCK(pv->pv_pmap);
1927 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1929 if (PTE_ISMODIFIED(pte))
1931 if (PTE_ISREFERENCED(pte)) {
1932 mtx_lock_spin(&tlbivax_mutex);
1935 tlb0_flush_entry(pv->pv_va);
1936 *pte &= ~PTE_REFERENCED;
1939 mtx_unlock_spin(&tlbivax_mutex);
1941 if (++count >= PMAP_TS_REFERENCED_MAX) {
1942 PMAP_UNLOCK(pv->pv_pmap);
1947 PMAP_UNLOCK(pv->pv_pmap);
1949 rw_wunlock(&pvh_global_lock);
1954 * Clear the wired attribute from the mappings for the specified range of
1955 * addresses in the given pmap. Every valid mapping within that range must
1956 * have the wired attribute set. In contrast, invalid mappings cannot have
1957 * the wired attribute set, so they are ignored.
1959 * The wired attribute of the page table entry is not a hardware feature, so
1960 * there is no need to invalidate any TLB entries.
1963 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1969 for (va = sva; va < eva; va += PAGE_SIZE) {
1970 if ((pte = pte_find(pmap, va)) != NULL &&
1972 if (!PTE_ISWIRED(pte))
1973 panic("mmu_booke_unwire: pte %p isn't wired",
1976 pmap->pm_stats.wired_count--;
1984 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
1985 * page. This count may be changed upwards or downwards in the future; it is
1986 * only necessary that true be returned for a small subset of pmaps for proper
1990 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
1996 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1997 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2000 rw_wlock(&pvh_global_lock);
2001 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2002 if (pv->pv_pmap == pmap) {
2009 rw_wunlock(&pvh_global_lock);
2014 * Return the number of managed mappings to the given physical page that are
2018 mmu_booke_page_wired_mappings(vm_page_t m)
2024 if ((m->oflags & VPO_UNMANAGED) != 0)
2026 rw_wlock(&pvh_global_lock);
2027 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2028 PMAP_LOCK(pv->pv_pmap);
2029 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2030 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2032 PMAP_UNLOCK(pv->pv_pmap);
2034 rw_wunlock(&pvh_global_lock);
2039 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2045 * This currently does not work for entries that
2046 * overlap TLB1 entries.
2048 for (i = 0; i < TLB1_ENTRIES; i ++) {
2049 if (tlb1_iomapped(i, pa, size, &va) == 0)
2057 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2063 /* Minidumps are based on virtual memory addresses. */
2065 *va = (void *)(vm_offset_t)pa;
2069 /* Raw physical memory dumps don't have a virtual address. */
2070 /* We always map a 256MB page at 256M. */
2071 gran = 256 * 1024 * 1024;
2072 ppa = rounddown2(pa, gran);
2075 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2077 if (sz > (gran - ofs))
2078 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2083 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2091 /* Minidumps are based on virtual memory addresses. */
2092 /* Nothing to do... */
2096 for (i = 0; i < TLB1_ENTRIES; i++) {
2097 tlb1_read_entry(&e, i);
2098 if (!(e.mas1 & MAS1_VALID))
2102 /* Raw physical memory dumps don't have a virtual address. */
2107 tlb1_write_entry(&e, i);
2109 gran = 256 * 1024 * 1024;
2110 ppa = rounddown2(pa, gran);
2112 if (sz > (gran - ofs)) {
2117 tlb1_write_entry(&e, i);
2121 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2124 mmu_booke_scan_init(void)
2131 /* Initialize phys. segments for dumpsys(). */
2132 memset(&dump_map, 0, sizeof(dump_map));
2133 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2134 &availmem_regions_sz);
2135 for (i = 0; i < physmem_regions_sz; i++) {
2136 dump_map[i].pa_start = physmem_regions[i].mr_start;
2137 dump_map[i].pa_size = physmem_regions[i].mr_size;
2142 /* Virtual segments for minidumps: */
2143 memset(&dump_map, 0, sizeof(dump_map));
2145 /* 1st: kernel .data and .bss. */
2146 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2147 dump_map[0].pa_size =
2148 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2150 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2151 dump_map[1].pa_start = data_start;
2152 dump_map[1].pa_size = data_end - data_start;
2154 /* 3rd: kernel VM. */
2155 va = dump_map[1].pa_start + dump_map[1].pa_size;
2156 /* Find start of next chunk (from va). */
2157 while (va < virtual_end) {
2158 /* Don't dump the buffer cache. */
2159 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2160 va = kmi.buffer_eva;
2163 pte = pte_find(kernel_pmap, va);
2164 if (pte != NULL && PTE_ISVALID(pte))
2168 if (va < virtual_end) {
2169 dump_map[2].pa_start = va;
2171 /* Find last page in chunk. */
2172 while (va < virtual_end) {
2173 /* Don't run into the buffer cache. */
2174 if (va == kmi.buffer_sva)
2176 pte = pte_find(kernel_pmap, va);
2177 if (pte == NULL || !PTE_ISVALID(pte))
2181 dump_map[2].pa_size = va - dump_map[2].pa_start;
2186 * Map a set of physical memory pages into the kernel virtual address space.
2187 * Return a pointer to where it is mapped. This routine is intended to be used
2188 * for mapping device memory, NOT real memory.
2191 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2194 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2198 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2202 for (i = 0; i < TLB1_ENTRIES; i++) {
2203 tlb1_read_entry(e, i);
2204 if ((e->mas1 & MAS1_VALID) == 0)
2213 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2217 #ifndef __powerpc64__
2220 uintptr_t va, retva;
2226 * Check if this is premapped in TLB1.
2231 wimge = tlb_calc_wimg(pa, ma);
2232 for (i = 0; i < TLB1_ENTRIES; i++) {
2233 tlb1_read_entry(&e, i);
2234 if (!(e.mas1 & MAS1_VALID))
2236 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2238 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2239 va = e.virt + (pa - e.phys);
2240 tmppa = e.phys + e.size;
2241 sz -= MIN(sz, e.size - (pa - e.phys));
2242 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2243 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2245 sz -= MIN(sz, e.size);
2246 tmppa = e.phys + e.size;
2250 return ((void *)va);
2254 size = roundup(size, PAGE_SIZE);
2256 #ifdef __powerpc64__
2257 KASSERT(pa < VM_MAPDEV_PA_MAX,
2258 ("Unsupported physical address! %lx", pa));
2259 va = VM_MAPDEV_BASE + pa;
2261 #ifdef POW2_MAPPINGS
2263 * Align the mapping to a power of 2 size, taking into account that we
2264 * may need to increase the size multiple times to satisfy the size and
2265 * alignment requirements.
2267 * This works in the general case because it's very rare (near never?)
2268 * to have different access properties (WIMG) within a single
2269 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2270 * can be undefined, and exact mappings will be used instead.
2273 size = roundup2(size, 1 << ilog2(size));
2274 while (rounddown2(va, size) + size < va + sz)
2276 va = rounddown2(va, size);
2277 pa = rounddown2(pa, size);
2281 * The device mapping area is between VM_MAXUSER_ADDRESS and
2282 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2284 #ifdef SPARSE_MAPDEV
2286 * With a sparse mapdev, align to the largest starting region. This
2287 * could feasibly be optimized for a 'best-fit' alignment, but that
2288 * calculation could be very costly.
2289 * Align to the smaller of:
2290 * - first set bit in overlap of (pa & size mask)
2291 * - largest size envelope
2293 * It's possible the device mapping may start at a PA that's not larger
2294 * than the size mask, so we need to offset in to maximize the TLB entry
2295 * range and minimize the number of used TLB entries.
2298 tmpva = tlb1_map_base;
2299 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2300 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2301 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2302 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2304 va = atomic_fetchadd_int(&tlb1_map_base, size);
2308 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2311 return ((void *)retva);
2315 * 'Unmap' a range mapped by mmu_booke_mapdev().
2318 mmu_booke_unmapdev(void *p, vm_size_t size)
2320 #ifdef SUPPORTS_SHRINKING_TLB1
2321 vm_offset_t base, offset, va;
2324 * Unmap only if this is inside kernel virtual space.
2326 va = (vm_offset_t)p;
2327 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2328 base = trunc_page(va);
2329 offset = va & PAGE_MASK;
2330 size = roundup(offset + size, PAGE_SIZE);
2331 mmu_booke_qremove(base, atop(size));
2332 kva_free(base, size);
2338 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2339 * specified pmap. This eliminates the blast of soft faults on process startup
2340 * and immediately after an mmap.
2343 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2344 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2347 VM_OBJECT_ASSERT_WLOCKED(object);
2348 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2349 ("mmu_booke_object_init_pt: non-device object"));
2353 * Perform the pmap work for mincore.
2356 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2359 /* XXX: this should be implemented at some point */
2364 mmu_booke_change_attr(vm_offset_t addr, vm_size_t sz, vm_memattr_t mode)
2371 addr = trunc_page(addr);
2373 /* Only allow changes to mapped kernel addresses. This includes:
2375 * - DMAP (powerpc64)
2378 if (addr <= VM_MAXUSER_ADDRESS ||
2379 #ifdef __powerpc64__
2380 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2381 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2383 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2385 (addr > VM_MAX_KERNEL_ADDRESS))
2388 /* Check TLB1 mappings */
2389 for (i = 0; i < TLB1_ENTRIES; i++) {
2390 tlb1_read_entry(&e, i);
2391 if (!(e.mas1 & MAS1_VALID))
2393 if (addr >= e.virt && addr < e.virt + e.size)
2396 if (i < TLB1_ENTRIES) {
2397 /* Only allow full mappings to be modified for now. */
2398 /* Validate the range. */
2399 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2400 tlb1_read_entry(&e, j);
2401 if (va != e.virt || (sz - (va - addr) < e.size))
2404 for (va = addr; va < addr + sz; va += e.size, i++) {
2405 tlb1_read_entry(&e, i);
2406 e.mas2 &= ~MAS2_WIMGE_MASK;
2407 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2410 * Write it out to the TLB. Should really re-sync with other
2413 tlb1_write_entry(&e, i);
2418 /* Not in TLB1, try through pmap */
2419 /* First validate the range. */
2420 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2421 pte = pte_find(kernel_pmap, va);
2422 if (pte == NULL || !PTE_ISVALID(pte))
2426 mtx_lock_spin(&tlbivax_mutex);
2428 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2429 pte = pte_find(kernel_pmap, va);
2430 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2431 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2432 tlb0_flush_entry(va);
2435 mtx_unlock_spin(&tlbivax_mutex);
2441 mmu_booke_page_array_startup(long pages)
2443 vm_page_array_size = pages;
2446 /**************************************************************************/
2448 /**************************************************************************/
2451 * Allocate a TID. If necessary, steal one from someone else.
2452 * The new TID is flushed from the TLB before returning.
2455 tid_alloc(pmap_t pmap)
2460 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2462 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2464 thiscpu = PCPU_GET(cpuid);
2466 tid = PCPU_GET(booke.tid_next);
2469 PCPU_SET(booke.tid_next, tid + 1);
2471 /* If we are stealing TID then clear the relevant pmap's field */
2472 if (tidbusy[thiscpu][tid] != NULL) {
2473 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2475 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2477 /* Flush all entries from TLB0 matching this TID. */
2481 tidbusy[thiscpu][tid] = pmap;
2482 pmap->pm_tid[thiscpu] = tid;
2483 __asm __volatile("msync; isync");
2485 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2486 PCPU_GET(booke.tid_next));
2491 /**************************************************************************/
2493 /**************************************************************************/
2495 /* Convert TLB0 va and way number to tlb0[] table index. */
2496 static inline unsigned int
2497 tlb0_tableidx(vm_offset_t va, unsigned int way)
2501 idx = (way * TLB0_ENTRIES_PER_WAY);
2502 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2507 * Invalidate TLB0 entry.
2510 tlb0_flush_entry(vm_offset_t va)
2513 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2515 mtx_assert(&tlbivax_mutex, MA_OWNED);
2517 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2518 __asm __volatile("isync; msync");
2519 __asm __volatile("tlbsync; msync");
2521 CTR1(KTR_PMAP, "%s: e", __func__);
2524 /**************************************************************************/
2526 /**************************************************************************/
2529 * TLB1 mapping notes:
2531 * TLB1[0] Kernel text and data.
2532 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2533 * windows, other devices mappings.
2537 * Read an entry from given TLB1 slot.
2540 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2545 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2548 __asm __volatile("wrteei 0");
2550 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2551 mtspr(SPR_MAS0, mas0);
2552 __asm __volatile("isync; tlbre");
2554 entry->mas1 = mfspr(SPR_MAS1);
2555 entry->mas2 = mfspr(SPR_MAS2);
2556 entry->mas3 = mfspr(SPR_MAS3);
2558 switch ((mfpvr() >> 16) & 0xFFFF) {
2563 entry->mas7 = mfspr(SPR_MAS7);
2569 __asm __volatile("wrtee %0" :: "r"(msr));
2571 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2572 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2573 (entry->mas3 & MAS3_RPN);
2575 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2578 struct tlbwrite_args {
2584 tlb1_find_free(void)
2589 for (i = 0; i < TLB1_ENTRIES; i++) {
2590 tlb1_read_entry(&e, i);
2591 if ((e.mas1 & MAS1_VALID) == 0)
2598 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2603 for (i = 0; i < TLB1_ENTRIES; i++) {
2604 tlb1_read_entry(&e, i);
2605 if ((e.mas1 & MAS1_VALID) == 0)
2607 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2608 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2609 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2610 __asm __volatile("isync; tlbwe; isync; msync");
2616 tlb1_write_entry_int(void *arg)
2618 struct tlbwrite_args *args = arg;
2623 tlb1_purge_va_range(args->e->virt, args->e->size);
2624 idx = tlb1_find_free();
2626 panic("No free TLB1 entries!\n");
2629 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2631 mtspr(SPR_MAS0, mas0);
2632 mtspr(SPR_MAS1, args->e->mas1);
2633 mtspr(SPR_MAS2, args->e->mas2);
2634 mtspr(SPR_MAS3, args->e->mas3);
2635 switch ((mfpvr() >> 16) & 0xFFFF) {
2642 mtspr(SPR_MAS7, args->e->mas7);
2648 __asm __volatile("isync; tlbwe; isync; msync");
2653 tlb1_write_entry_sync(void *arg)
2655 /* Empty synchronization point for smp_rendezvous(). */
2659 * Write given entry to TLB1 hardware.
2662 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2664 struct tlbwrite_args args;
2670 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2672 smp_rendezvous(tlb1_write_entry_sync,
2673 tlb1_write_entry_int,
2674 tlb1_write_entry_sync, &args);
2681 __asm __volatile("wrteei 0");
2682 tlb1_write_entry_int(&args);
2683 __asm __volatile("wrtee %0" :: "r"(msr));
2688 * Convert TLB TSIZE value to mapped region size.
2691 tsize2size(unsigned int tsize)
2696 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2699 return ((1 << (2 * tsize)) * 1024);
2703 * Convert region size (must be power of 4) to TLB TSIZE value.
2706 size2tsize(vm_size_t size)
2709 return (ilog2(size) / 2 - 5);
2713 * Register permanent kernel mapping in TLB1.
2715 * Entries are created starting from index 0 (current free entry is
2716 * kept in tlb1_idx) and are not supposed to be invalidated.
2719 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2726 /* First try to update an existing entry. */
2727 for (index = 0; index < TLB1_ENTRIES; index++) {
2728 tlb1_read_entry(&e, index);
2729 /* Check if we're just updating the flags, and update them. */
2730 if (e.phys == pa && e.virt == va && e.size == size) {
2731 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2732 tlb1_write_entry(&e, index);
2737 /* Convert size to TSIZE */
2738 tsize = size2tsize(size);
2740 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2741 /* XXX TS is hard coded to 0 for now as we only use single address space */
2742 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2747 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2748 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2749 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2751 /* Set supervisor RWX permission bits */
2752 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2753 e.mas7 = (pa >> 32) & MAS7_RPN;
2755 tlb1_write_entry(&e, -1);
2761 * Map in contiguous RAM region into the TLB1.
2764 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2767 vm_size_t mapped, sz, ssize;
2774 sz = 1UL << (ilog2(size) & ~1);
2775 /* Align size to PA */
2779 } while (pa % sz != 0);
2781 /* Now align from there to VA */
2785 } while (va % sz != 0);
2787 #ifdef __powerpc64__
2789 * Clamp TLB1 entries to 4G.
2791 * While the e6500 supports up to 1TB mappings, the e5500
2792 * only supports up to 4G mappings. (0b1011)
2794 * If any e6500 machines capable of supporting a very
2795 * large amount of memory appear in the future, we can
2798 * For now, though, since we have plenty of space in TLB1,
2799 * always avoid creating entries larger than 4GB.
2801 sz = MIN(sz, 1UL << 32);
2804 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2805 (void *)va, (uintmax_t)pa, (long)sz);
2806 if (tlb1_set_entry(va, pa, sz,
2807 _TLB_ENTRY_SHARED | wimge) < 0)
2814 mapped = (va - base);
2816 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2817 mapped, mapped - ssize);
2823 * TLB1 initialization routine, to be called after the very first
2824 * assembler level setup done in locore.S.
2830 uint32_t mas0, mas1, mas3, mas7;
2835 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2836 mtspr(SPR_MAS0, mas0);
2837 __asm __volatile("isync; tlbre");
2839 mas1 = mfspr(SPR_MAS1);
2840 mas2 = mfspr(SPR_MAS2);
2841 mas3 = mfspr(SPR_MAS3);
2842 mas7 = mfspr(SPR_MAS7);
2844 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2847 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2848 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2849 kernstart = trunc_page(mas2);
2851 /* Setup TLB miss defaults */
2852 set_mas4_defaults();
2856 * pmap_early_io_unmap() should be used in short conjunction with
2857 * pmap_early_io_map(), as in the following snippet:
2859 * x = pmap_early_io_map(...);
2860 * <do something with x>
2861 * pmap_early_io_unmap(x, size);
2863 * And avoiding more allocations between.
2866 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2872 size = roundup(size, PAGE_SIZE);
2874 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2875 tlb1_read_entry(&e, i);
2876 if (!(e.mas1 & MAS1_VALID))
2878 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2880 e.mas1 &= ~MAS1_VALID;
2881 tlb1_write_entry(&e, i);
2884 if (tlb1_map_base == va + isize)
2885 tlb1_map_base -= isize;
2889 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2896 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2898 for (i = 0; i < TLB1_ENTRIES; i++) {
2899 tlb1_read_entry(&e, i);
2900 if (!(e.mas1 & MAS1_VALID))
2902 if (pa >= e.phys && (pa + size) <=
2904 return (e.virt + (pa - e.phys));
2907 pa_base = rounddown(pa, PAGE_SIZE);
2908 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2909 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2910 va = tlb1_map_base + (pa - pa_base);
2913 sz = 1 << (ilog2(size) & ~1);
2914 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2915 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2918 tlb1_map_base += sz;
2925 pmap_track_page(pmap_t pmap, vm_offset_t va)
2929 struct pv_entry *pve;
2931 va = trunc_page(va);
2932 pa = pmap_kextract(va);
2933 page = PHYS_TO_VM_PAGE(pa);
2935 rw_wlock(&pvh_global_lock);
2938 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
2939 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
2943 page->md.pv_tracked = true;
2944 pv_insert(pmap, va, page);
2947 rw_wunlock(&pvh_global_lock);
2951 * Setup MAS4 defaults.
2952 * These values are loaded to MAS0-2 on a TLB miss.
2955 set_mas4_defaults(void)
2959 /* Defaults: TLB0, PID0, TSIZED=4K */
2960 mas4 = MAS4_TLBSELD0;
2961 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
2965 mtspr(SPR_MAS4, mas4);
2966 __asm __volatile("isync");
2970 * Return 0 if the physical IO range is encompassed by one of the
2971 * the TLB1 entries, otherwise return related error code.
2974 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
2977 vm_paddr_t pa_start;
2979 unsigned int entry_tsize;
2980 vm_size_t entry_size;
2983 *va = (vm_offset_t)NULL;
2985 tlb1_read_entry(&e, i);
2986 /* Skip invalid entries */
2987 if (!(e.mas1 & MAS1_VALID))
2991 * The entry must be cache-inhibited, guarded, and r/w
2992 * so it can function as an i/o page
2994 prot = e.mas2 & (MAS2_I | MAS2_G);
2995 if (prot != (MAS2_I | MAS2_G))
2998 prot = e.mas3 & (MAS3_SR | MAS3_SW);
2999 if (prot != (MAS3_SR | MAS3_SW))
3002 /* The address should be within the entry range. */
3003 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3004 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3006 entry_size = tsize2size(entry_tsize);
3007 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
3008 (e.mas3 & MAS3_RPN);
3009 pa_end = pa_start + entry_size;
3011 if ((pa < pa_start) || ((pa + size) > pa_end))
3014 /* Return virtual address of this mapping. */
3015 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3020 /* Print out contents of the MAS registers for each TLB0 entry */
3022 #ifdef __powerpc64__
3023 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3025 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3036 if (mas1 & MAS1_VALID)
3041 if (mas1 & MAS1_IPROT)
3046 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3047 tid = MAS1_GETTID(mas1);
3049 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3052 size = tsize2size(tsize);
3054 printf("%3d: (%s) [AS=%d] "
3055 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3056 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3057 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3060 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3062 uint32_t mas0, mas1, mas3, mas7;
3063 #ifdef __powerpc64__
3068 int entryidx, way, idx;
3070 printf("TLB0 entries:\n");
3071 for (way = 0; way < TLB0_WAYS; way ++)
3072 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3073 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3074 mtspr(SPR_MAS0, mas0);
3076 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3077 mtspr(SPR_MAS2, mas2);
3079 __asm __volatile("isync; tlbre");
3081 mas1 = mfspr(SPR_MAS1);
3082 mas2 = mfspr(SPR_MAS2);
3083 mas3 = mfspr(SPR_MAS3);
3084 mas7 = mfspr(SPR_MAS7);
3086 idx = tlb0_tableidx(mas2, way);
3087 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3092 * Print out contents of the MAS registers for each TLB1 entry
3094 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3096 uint32_t mas0, mas1, mas3, mas7;
3097 #ifdef __powerpc64__
3104 printf("TLB1 entries:\n");
3105 for (i = 0; i < TLB1_ENTRIES; i++) {
3106 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3107 mtspr(SPR_MAS0, mas0);
3109 __asm __volatile("isync; tlbre");
3111 mas1 = mfspr(SPR_MAS1);
3112 mas2 = mfspr(SPR_MAS2);
3113 mas3 = mfspr(SPR_MAS3);
3114 mas7 = mfspr(SPR_MAS7);
3116 tlb_print_entry(i, mas1, mas2, mas3, mas7);