2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/param.h>
55 #include <sys/malloc.h>
59 #include <sys/queue.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/linker.h>
63 #include <sys/msgbuf.h>
65 #include <sys/mutex.h>
66 #include <sys/rwlock.h>
67 #include <sys/sched.h>
69 #include <sys/vmmeter.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
82 #include <machine/cpu.h>
83 #include <machine/pcb.h>
84 #include <machine/platform.h>
86 #include <machine/tlb.h>
87 #include <machine/spr.h>
88 #include <machine/md_var.h>
89 #include <machine/mmuvar.h>
90 #include <machine/pmap.h>
91 #include <machine/pte.h>
96 #define debugf(fmt, args...) printf(fmt, ##args)
98 #define debugf(fmt, args...)
101 #define TODO panic("%s: not implemented", __func__);
103 extern struct mtx sched_lock;
105 extern int dumpsys_minidump;
107 extern unsigned char _etext[];
108 extern unsigned char _end[];
110 extern uint32_t *bootinfo;
113 extern uint32_t bp_ntlb1s;
116 vm_paddr_t ccsrbar_pa;
118 vm_offset_t kernstart;
121 /* Message buffer and tables. */
122 static vm_offset_t data_start;
123 static vm_size_t data_end;
125 /* Phys/avail memory regions. */
126 static struct mem_region *availmem_regions;
127 static int availmem_regions_sz;
128 static struct mem_region *physmem_regions;
129 static int physmem_regions_sz;
131 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
132 static vm_offset_t zero_page_va;
133 static struct mtx zero_page_mutex;
135 static struct mtx tlbivax_mutex;
138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
139 * by idle thred only, no lock required.
141 static vm_offset_t zero_page_idle_va;
143 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
144 static vm_offset_t copy_page_src_va;
145 static vm_offset_t copy_page_dst_va;
146 static struct mtx copy_page_mutex;
148 /**************************************************************************/
150 /**************************************************************************/
152 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
153 vm_prot_t, boolean_t);
155 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
156 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
159 * If user pmap is processed with mmu_booke_remove and the resident count
160 * drops to 0, there are no more pages to remove, so we need not continue.
162 #define PMAP_REMOVE_DONE(pmap) \
163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
165 extern void tid_flush(tlbtid_t);
167 /**************************************************************************/
168 /* TLB and TID handling */
169 /**************************************************************************/
171 /* Translation ID busy table */
172 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
176 * core revisions and should be read from h/w registers during early config.
178 uint32_t tlb0_entries;
180 uint32_t tlb0_entries_per_way;
182 #define TLB0_ENTRIES (tlb0_entries)
183 #define TLB0_WAYS (tlb0_ways)
184 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
186 #define TLB1_ENTRIES 16
188 /* In-ram copy of the TLB1 */
189 static tlb_entry_t tlb1[TLB1_ENTRIES];
191 /* Next free entry in the TLB1 */
192 static unsigned int tlb1_idx;
194 static tlbtid_t tid_alloc(struct pmap *);
196 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
198 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
199 static void tlb1_write_entry(unsigned int);
200 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
201 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
203 static vm_size_t tsize2size(unsigned int);
204 static unsigned int size2tsize(vm_size_t);
205 static unsigned int ilog2(unsigned int);
207 static void set_mas4_defaults(void);
209 static inline void tlb0_flush_entry(vm_offset_t);
210 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
212 /**************************************************************************/
213 /* Page table management */
214 /**************************************************************************/
216 static struct rwlock_padalign pvh_global_lock;
218 /* Data for the pv entry allocation mechanism */
219 static uma_zone_t pvzone;
220 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
222 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
224 #ifndef PMAP_SHPGPERPROC
225 #define PMAP_SHPGPERPROC 200
228 static void ptbl_init(void);
229 static struct ptbl_buf *ptbl_buf_alloc(void);
230 static void ptbl_buf_free(struct ptbl_buf *);
231 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
233 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
234 static void ptbl_free(mmu_t, pmap_t, unsigned int);
235 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
236 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
238 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
239 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
240 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
241 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
243 static pv_entry_t pv_alloc(void);
244 static void pv_free(pv_entry_t);
245 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
246 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
248 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
249 #define PTBL_BUFS (128 * 16)
252 TAILQ_ENTRY(ptbl_buf) link; /* list link */
253 vm_offset_t kva; /* va of mapping */
256 /* ptbl free list and a lock used for access synchronization. */
257 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
258 static struct mtx ptbl_buf_freelist_lock;
260 /* Base address of kva space allocated fot ptbl bufs. */
261 static vm_offset_t ptbl_buf_pool_vabase;
263 /* Pointer to ptbl_buf structures. */
264 static struct ptbl_buf *ptbl_bufs;
266 void pmap_bootstrap_ap(volatile uint32_t *);
269 * Kernel MMU interface
271 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
272 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
273 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
274 vm_size_t, vm_offset_t);
275 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
276 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
277 vm_offset_t, vm_page_t *, vm_offset_t, int);
278 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
279 vm_prot_t, boolean_t);
280 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
281 vm_page_t, vm_prot_t);
282 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
284 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
285 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
287 static void mmu_booke_init(mmu_t);
288 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
289 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
290 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
291 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
292 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
294 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
296 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
297 vm_object_t, vm_pindex_t, vm_size_t);
298 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
299 static void mmu_booke_page_init(mmu_t, vm_page_t);
300 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
301 static void mmu_booke_pinit(mmu_t, pmap_t);
302 static void mmu_booke_pinit0(mmu_t, pmap_t);
303 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
305 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
306 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
307 static void mmu_booke_release(mmu_t, pmap_t);
308 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
309 static void mmu_booke_remove_all(mmu_t, vm_page_t);
310 static void mmu_booke_remove_write(mmu_t, vm_page_t);
311 static void mmu_booke_zero_page(mmu_t, vm_page_t);
312 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
313 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
314 static void mmu_booke_activate(mmu_t, struct thread *);
315 static void mmu_booke_deactivate(mmu_t, struct thread *);
316 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
317 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
318 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
319 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
320 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
321 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
322 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
323 static void mmu_booke_kremove(mmu_t, vm_offset_t);
324 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
325 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
327 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
328 vm_size_t, vm_size_t *);
329 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
330 vm_size_t, vm_offset_t);
331 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
333 static mmu_method_t mmu_booke_methods[] = {
334 /* pmap dispatcher interface */
335 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
336 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
337 MMUMETHOD(mmu_copy, mmu_booke_copy),
338 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
339 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
340 MMUMETHOD(mmu_enter, mmu_booke_enter),
341 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
342 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
343 MMUMETHOD(mmu_extract, mmu_booke_extract),
344 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
345 MMUMETHOD(mmu_init, mmu_booke_init),
346 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
347 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
348 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
349 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
350 MMUMETHOD(mmu_map, mmu_booke_map),
351 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
352 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
353 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
354 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
355 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
356 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
357 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
358 MMUMETHOD(mmu_protect, mmu_booke_protect),
359 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
360 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
361 MMUMETHOD(mmu_release, mmu_booke_release),
362 MMUMETHOD(mmu_remove, mmu_booke_remove),
363 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
364 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
365 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
366 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
367 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
368 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
369 MMUMETHOD(mmu_activate, mmu_booke_activate),
370 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
372 /* Internal interfaces */
373 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
374 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
375 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
376 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
377 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
378 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
379 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
380 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
381 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
383 /* dumpsys() support */
384 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
385 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
386 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
391 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
393 static __inline uint32_t
394 tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
399 if (ma != VM_MEMATTR_DEFAULT) {
401 case VM_MEMATTR_UNCACHEABLE:
402 return (PTE_I | PTE_G);
403 case VM_MEMATTR_WRITE_COMBINING:
404 case VM_MEMATTR_WRITE_BACK:
405 case VM_MEMATTR_PREFETCHABLE:
407 case VM_MEMATTR_WRITE_THROUGH:
408 return (PTE_W | PTE_M);
413 * Assume the page is cache inhibited and access is guarded unless
414 * it's in our available memory array.
416 attrib = _TLB_ENTRY_IO;
417 for (i = 0; i < physmem_regions_sz; i++) {
418 if ((pa >= physmem_regions[i].mr_start) &&
419 (pa < (physmem_regions[i].mr_start +
420 physmem_regions[i].mr_size))) {
421 attrib = _TLB_ENTRY_MEM;
438 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
441 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
442 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
444 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
445 ("tlb_miss_lock: tried to lock self"));
447 tlb_lock(pc->pc_booke_tlb_lock);
449 CTR1(KTR_PMAP, "%s: locked", __func__);
456 tlb_miss_unlock(void)
464 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
466 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
467 __func__, pc->pc_cpuid);
469 tlb_unlock(pc->pc_booke_tlb_lock);
471 CTR1(KTR_PMAP, "%s: unlocked", __func__);
477 /* Return number of entries in TLB0. */
479 tlb0_get_tlbconf(void)
483 tlb0_cfg = mfspr(SPR_TLB0CFG);
484 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
485 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
486 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
489 /* Initialize pool of kva ptbl buffers. */
495 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
496 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
497 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
498 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
500 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
501 TAILQ_INIT(&ptbl_buf_freelist);
503 for (i = 0; i < PTBL_BUFS; i++) {
504 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
505 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
509 /* Get a ptbl_buf from the freelist. */
510 static struct ptbl_buf *
513 struct ptbl_buf *buf;
515 mtx_lock(&ptbl_buf_freelist_lock);
516 buf = TAILQ_FIRST(&ptbl_buf_freelist);
518 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
519 mtx_unlock(&ptbl_buf_freelist_lock);
521 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
526 /* Return ptbl buff to free pool. */
528 ptbl_buf_free(struct ptbl_buf *buf)
531 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
533 mtx_lock(&ptbl_buf_freelist_lock);
534 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
535 mtx_unlock(&ptbl_buf_freelist_lock);
539 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
542 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
544 struct ptbl_buf *pbuf;
546 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
548 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
550 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
551 if (pbuf->kva == (vm_offset_t)ptbl) {
552 /* Remove from pmap ptbl buf list. */
553 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
555 /* Free corresponding ptbl buf. */
561 /* Allocate page table. */
563 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
565 vm_page_t mtbl[PTBL_PAGES];
567 struct ptbl_buf *pbuf;
572 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
573 (pmap == kernel_pmap), pdir_idx);
575 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
576 ("ptbl_alloc: invalid pdir_idx"));
577 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
578 ("pte_alloc: valid ptbl entry exists!"));
580 pbuf = ptbl_buf_alloc();
582 panic("pte_alloc: couldn't alloc kernel virtual memory");
584 ptbl = (pte_t *)pbuf->kva;
586 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
588 /* Allocate ptbl pages, this will sleep! */
589 for (i = 0; i < PTBL_PAGES; i++) {
590 pidx = (PTBL_PAGES * pdir_idx) + i;
591 while ((m = vm_page_alloc(NULL, pidx,
592 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
595 rw_wunlock(&pvh_global_lock);
597 rw_wlock(&pvh_global_lock);
603 /* Map allocated pages into kernel_pmap. */
604 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
606 /* Zero whole ptbl. */
607 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
609 /* Add pbuf to the pmap ptbl bufs list. */
610 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
615 /* Free ptbl pages and invalidate pdir entry. */
617 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
625 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
626 (pmap == kernel_pmap), pdir_idx);
628 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
629 ("ptbl_free: invalid pdir_idx"));
631 ptbl = pmap->pm_pdir[pdir_idx];
633 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
635 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
638 * Invalidate the pdir entry as soon as possible, so that other CPUs
639 * don't attempt to look up the page tables we are releasing.
641 mtx_lock_spin(&tlbivax_mutex);
644 pmap->pm_pdir[pdir_idx] = NULL;
647 mtx_unlock_spin(&tlbivax_mutex);
649 for (i = 0; i < PTBL_PAGES; i++) {
650 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
651 pa = pte_vatopa(mmu, kernel_pmap, va);
652 m = PHYS_TO_VM_PAGE(pa);
653 vm_page_free_zero(m);
654 atomic_subtract_int(&cnt.v_wire_count, 1);
655 mmu_booke_kremove(mmu, va);
658 ptbl_free_pmap_ptbl(pmap, ptbl);
662 * Decrement ptbl pages hold count and attempt to free ptbl pages.
663 * Called when removing pte entry from ptbl.
665 * Return 1 if ptbl pages were freed.
668 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
675 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
676 (pmap == kernel_pmap), pdir_idx);
678 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
679 ("ptbl_unhold: invalid pdir_idx"));
680 KASSERT((pmap != kernel_pmap),
681 ("ptbl_unhold: unholding kernel ptbl!"));
683 ptbl = pmap->pm_pdir[pdir_idx];
685 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
686 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
687 ("ptbl_unhold: non kva ptbl"));
689 /* decrement hold count */
690 for (i = 0; i < PTBL_PAGES; i++) {
691 pa = pte_vatopa(mmu, kernel_pmap,
692 (vm_offset_t)ptbl + (i * PAGE_SIZE));
693 m = PHYS_TO_VM_PAGE(pa);
698 * Free ptbl pages if there are no pte etries in this ptbl.
699 * wire_count has the same value for all ptbl pages, so check the last
702 if (m->wire_count == 0) {
703 ptbl_free(mmu, pmap, pdir_idx);
705 //debugf("ptbl_unhold: e (freed ptbl)\n");
713 * Increment hold count for ptbl pages. This routine is used when a new pte
714 * entry is being inserted into the ptbl.
717 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
724 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
727 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
728 ("ptbl_hold: invalid pdir_idx"));
729 KASSERT((pmap != kernel_pmap),
730 ("ptbl_hold: holding kernel ptbl!"));
732 ptbl = pmap->pm_pdir[pdir_idx];
734 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
736 for (i = 0; i < PTBL_PAGES; i++) {
737 pa = pte_vatopa(mmu, kernel_pmap,
738 (vm_offset_t)ptbl + (i * PAGE_SIZE));
739 m = PHYS_TO_VM_PAGE(pa);
744 /* Allocate pv_entry structure. */
751 if (pv_entry_count > pv_entry_high_water)
753 pv = uma_zalloc(pvzone, M_NOWAIT);
758 /* Free pv_entry structure. */
760 pv_free(pv_entry_t pve)
764 uma_zfree(pvzone, pve);
768 /* Allocate and initialize pv_entry structure. */
770 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
774 //int su = (pmap == kernel_pmap);
775 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
776 // (u_int32_t)pmap, va, (u_int32_t)m);
780 panic("pv_insert: no pv entries!");
786 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
787 rw_assert(&pvh_global_lock, RA_WLOCKED);
789 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
791 //debugf("pv_insert: e\n");
794 /* Destroy pv entry. */
796 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
800 //int su = (pmap == kernel_pmap);
801 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
803 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
804 rw_assert(&pvh_global_lock, RA_WLOCKED);
807 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
808 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
809 /* remove from pv_list */
810 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
811 if (TAILQ_EMPTY(&m->md.pv_list))
812 vm_page_aflag_clear(m, PGA_WRITEABLE);
814 /* free pv entry struct */
820 //debugf("pv_remove: e\n");
824 * Clean pte entry, try to free page table page if requested.
826 * Return 1 if ptbl pages were freed, otherwise return 0.
829 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
831 unsigned int pdir_idx = PDIR_IDX(va);
832 unsigned int ptbl_idx = PTBL_IDX(va);
837 //int su = (pmap == kernel_pmap);
838 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
839 // su, (u_int32_t)pmap, va, flags);
841 ptbl = pmap->pm_pdir[pdir_idx];
842 KASSERT(ptbl, ("pte_remove: null ptbl"));
844 pte = &ptbl[ptbl_idx];
846 if (pte == NULL || !PTE_ISVALID(pte))
849 if (PTE_ISWIRED(pte))
850 pmap->pm_stats.wired_count--;
852 /* Handle managed entry. */
853 if (PTE_ISMANAGED(pte)) {
854 /* Get vm_page_t for mapped pte. */
855 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
857 if (PTE_ISMODIFIED(pte))
860 if (PTE_ISREFERENCED(pte))
861 vm_page_aflag_set(m, PGA_REFERENCED);
863 pv_remove(pmap, va, m);
866 mtx_lock_spin(&tlbivax_mutex);
869 tlb0_flush_entry(va);
874 mtx_unlock_spin(&tlbivax_mutex);
876 pmap->pm_stats.resident_count--;
878 if (flags & PTBL_UNHOLD) {
879 //debugf("pte_remove: e (unhold)\n");
880 return (ptbl_unhold(mmu, pmap, pdir_idx));
883 //debugf("pte_remove: e\n");
888 * Insert PTE for a given page and virtual address.
891 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
893 unsigned int pdir_idx = PDIR_IDX(va);
894 unsigned int ptbl_idx = PTBL_IDX(va);
897 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
898 pmap == kernel_pmap, pmap, va);
900 /* Get the page table pointer. */
901 ptbl = pmap->pm_pdir[pdir_idx];
904 /* Allocate page table pages. */
905 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
908 * Check if there is valid mapping for requested
909 * va, if there is, remove it.
911 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
912 if (PTE_ISVALID(pte)) {
913 pte_remove(mmu, pmap, va, PTBL_HOLD);
916 * pte is not used, increment hold count
919 if (pmap != kernel_pmap)
920 ptbl_hold(mmu, pmap, pdir_idx);
925 * Insert pv_entry into pv_list for mapped page if part of managed
928 if ((m->oflags & VPO_UNMANAGED) == 0) {
929 flags |= PTE_MANAGED;
931 /* Create and insert pv entry. */
932 pv_insert(pmap, va, m);
935 pmap->pm_stats.resident_count++;
937 mtx_lock_spin(&tlbivax_mutex);
940 tlb0_flush_entry(va);
941 if (pmap->pm_pdir[pdir_idx] == NULL) {
943 * If we just allocated a new page table, hook it in
946 pmap->pm_pdir[pdir_idx] = ptbl;
948 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
949 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
950 pte->flags |= (PTE_VALID | flags);
953 mtx_unlock_spin(&tlbivax_mutex);
956 /* Return the pa for the given pmap/va. */
958 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
963 pte = pte_find(mmu, pmap, va);
964 if ((pte != NULL) && PTE_ISVALID(pte))
965 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
969 /* Get a pointer to a PTE in a page table. */
971 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
973 unsigned int pdir_idx = PDIR_IDX(va);
974 unsigned int ptbl_idx = PTBL_IDX(va);
976 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
978 if (pmap->pm_pdir[pdir_idx])
979 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
984 /**************************************************************************/
986 /**************************************************************************/
989 * This is called during booke_init, before the system is really initialized.
992 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
994 vm_offset_t phys_kernelend;
995 struct mem_region *mp, *mp1;
998 u_int phys_avail_count;
999 vm_size_t physsz, hwphyssz, kstack0_sz;
1000 vm_offset_t kernel_pdir, kstack0, va;
1001 vm_paddr_t kstack0_phys;
1005 debugf("mmu_booke_bootstrap: entered\n");
1007 /* Initialize invalidation mutex */
1008 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1010 /* Read TLB0 size and associativity. */
1014 * Align kernel start and end address (kernel image).
1015 * Note that kernel end does not necessarily relate to kernsize.
1016 * kernsize is the size of the kernel that is actually mapped.
1017 * Also note that "start - 1" is deliberate. With SMP, the
1018 * entry point is exactly a page from the actual load address.
1019 * As such, trunc_page() has no effect and we're off by a page.
1020 * Since we always have the ELF header between the load address
1021 * and the entry point, we can safely subtract 1 to compensate.
1023 kernstart = trunc_page(start - 1);
1024 data_start = round_page(kernelend);
1025 data_end = data_start;
1028 * Addresses of preloaded modules (like file systems) use
1029 * physical addresses. Make sure we relocate those into
1030 * virtual addresses.
1032 preload_addr_relocate = kernstart - kernload;
1034 /* Allocate the dynamic per-cpu area. */
1035 dpcpu = (void *)data_end;
1036 data_end += DPCPU_SIZE;
1038 /* Allocate space for the message buffer. */
1039 msgbufp = (struct msgbuf *)data_end;
1040 data_end += msgbufsize;
1041 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1044 data_end = round_page(data_end);
1046 /* Allocate space for ptbl_bufs. */
1047 ptbl_bufs = (struct ptbl_buf *)data_end;
1048 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1049 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1052 data_end = round_page(data_end);
1054 /* Allocate PTE tables for kernel KVA. */
1055 kernel_pdir = data_end;
1056 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1057 PDIR_SIZE - 1) / PDIR_SIZE;
1058 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1059 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1060 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1062 debugf(" data_end: 0x%08x\n", data_end);
1063 if (data_end - kernstart > kernsize) {
1064 kernsize += tlb1_mapin_region(kernstart + kernsize,
1065 kernload + kernsize, (data_end - kernstart) - kernsize);
1067 data_end = kernstart + kernsize;
1068 debugf(" updated data_end: 0x%08x\n", data_end);
1071 * Clear the structures - note we can only do it safely after the
1072 * possible additional TLB1 translations are in place (above) so that
1073 * all range up to the currently calculated 'data_end' is covered.
1075 dpcpu_init(dpcpu, 0);
1076 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1077 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1079 /*******************************************************/
1080 /* Set the start and end of kva. */
1081 /*******************************************************/
1082 virtual_avail = round_page(data_end);
1083 virtual_end = VM_MAX_KERNEL_ADDRESS;
1085 /* Allocate KVA space for page zero/copy operations. */
1086 zero_page_va = virtual_avail;
1087 virtual_avail += PAGE_SIZE;
1088 zero_page_idle_va = virtual_avail;
1089 virtual_avail += PAGE_SIZE;
1090 copy_page_src_va = virtual_avail;
1091 virtual_avail += PAGE_SIZE;
1092 copy_page_dst_va = virtual_avail;
1093 virtual_avail += PAGE_SIZE;
1094 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1095 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1096 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1097 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1099 /* Initialize page zero/copy mutexes. */
1100 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1101 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1103 /* Allocate KVA space for ptbl bufs. */
1104 ptbl_buf_pool_vabase = virtual_avail;
1105 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1106 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1107 ptbl_buf_pool_vabase, virtual_avail);
1109 /* Calculate corresponding physical addresses for the kernel region. */
1110 phys_kernelend = kernload + kernsize;
1111 debugf("kernel image and allocated data:\n");
1112 debugf(" kernload = 0x%08x\n", kernload);
1113 debugf(" kernstart = 0x%08x\n", kernstart);
1114 debugf(" kernsize = 0x%08x\n", kernsize);
1116 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1117 panic("mmu_booke_bootstrap: phys_avail too small");
1120 * Remove kernel physical address range from avail regions list. Page
1121 * align all regions. Non-page aligned memory isn't very interesting
1122 * to us. Also, sort the entries for ascending addresses.
1125 /* Retrieve phys/avail mem regions */
1126 mem_regions(&physmem_regions, &physmem_regions_sz,
1127 &availmem_regions, &availmem_regions_sz);
1129 cnt = availmem_regions_sz;
1130 debugf("processing avail regions:\n");
1131 for (mp = availmem_regions; mp->mr_size; mp++) {
1133 e = mp->mr_start + mp->mr_size;
1134 debugf(" %08x-%08x -> ", s, e);
1135 /* Check whether this region holds all of the kernel. */
1136 if (s < kernload && e > phys_kernelend) {
1137 availmem_regions[cnt].mr_start = phys_kernelend;
1138 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1141 /* Look whether this regions starts within the kernel. */
1142 if (s >= kernload && s < phys_kernelend) {
1143 if (e <= phys_kernelend)
1147 /* Now look whether this region ends within the kernel. */
1148 if (e > kernload && e <= phys_kernelend) {
1153 /* Now page align the start and size of the region. */
1159 debugf("%08x-%08x = %x\n", s, e, sz);
1161 /* Check whether some memory is left here. */
1165 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1171 /* Do an insertion sort. */
1172 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1173 if (s < mp1->mr_start)
1176 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1184 availmem_regions_sz = cnt;
1186 /*******************************************************/
1187 /* Steal physical memory for kernel stack from the end */
1188 /* of the first avail region */
1189 /*******************************************************/
1190 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1191 kstack0_phys = availmem_regions[0].mr_start +
1192 availmem_regions[0].mr_size;
1193 kstack0_phys -= kstack0_sz;
1194 availmem_regions[0].mr_size -= kstack0_sz;
1196 /*******************************************************/
1197 /* Fill in phys_avail table, based on availmem_regions */
1198 /*******************************************************/
1199 phys_avail_count = 0;
1202 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1204 debugf("fill in phys_avail:\n");
1205 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1207 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1208 availmem_regions[i].mr_start,
1209 availmem_regions[i].mr_start +
1210 availmem_regions[i].mr_size,
1211 availmem_regions[i].mr_size);
1213 if (hwphyssz != 0 &&
1214 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1215 debugf(" hw.physmem adjust\n");
1216 if (physsz < hwphyssz) {
1217 phys_avail[j] = availmem_regions[i].mr_start;
1219 availmem_regions[i].mr_start +
1227 phys_avail[j] = availmem_regions[i].mr_start;
1228 phys_avail[j + 1] = availmem_regions[i].mr_start +
1229 availmem_regions[i].mr_size;
1231 physsz += availmem_regions[i].mr_size;
1233 physmem = btoc(physsz);
1235 /* Calculate the last available physical address. */
1236 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1238 Maxmem = powerpc_btop(phys_avail[i + 1]);
1240 debugf("Maxmem = 0x%08lx\n", Maxmem);
1241 debugf("phys_avail_count = %d\n", phys_avail_count);
1242 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1245 /*******************************************************/
1246 /* Initialize (statically allocated) kernel pmap. */
1247 /*******************************************************/
1248 PMAP_LOCK_INIT(kernel_pmap);
1249 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1251 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1252 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1253 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1254 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1256 /* Initialize kernel pdir */
1257 for (i = 0; i < kernel_ptbls; i++)
1258 kernel_pmap->pm_pdir[kptbl_min + i] =
1259 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1261 for (i = 0; i < MAXCPU; i++) {
1262 kernel_pmap->pm_tid[i] = TID_KERNEL;
1264 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1265 tidbusy[i][0] = kernel_pmap;
1269 * Fill in PTEs covering kernel code and data. They are not required
1270 * for address translation, as this area is covered by static TLB1
1271 * entries, but for pte_vatopa() to work correctly with kernel area
1274 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1275 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1276 pte->rpn = kernload + (va - kernstart);
1277 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1280 /* Mark kernel_pmap active on all CPUs */
1281 CPU_FILL(&kernel_pmap->pm_active);
1284 * Initialize the global pv list lock.
1286 rw_init(&pvh_global_lock, "pmap pv global");
1288 /*******************************************************/
1290 /*******************************************************/
1292 /* Enter kstack0 into kernel map, provide guard page */
1293 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1294 thread0.td_kstack = kstack0;
1295 thread0.td_kstack_pages = KSTACK_PAGES;
1297 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1298 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1299 kstack0_phys, kstack0_phys + kstack0_sz);
1300 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1302 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1303 for (i = 0; i < KSTACK_PAGES; i++) {
1304 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1305 kstack0 += PAGE_SIZE;
1306 kstack0_phys += PAGE_SIZE;
1309 debugf("virtual_avail = %08x\n", virtual_avail);
1310 debugf("virtual_end = %08x\n", virtual_end);
1312 debugf("mmu_booke_bootstrap: exit\n");
1316 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1321 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1322 * have the snapshot of its contents in the s/w tlb1[] table, so use
1323 * these values directly to (re)program AP's TLB1 hardware.
1325 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1326 /* Skip invalid entries */
1327 if (!(tlb1[i].mas1 & MAS1_VALID))
1330 tlb1_write_entry(i);
1333 set_mas4_defaults();
1337 * Get the physical page address for the given pmap/virtual address.
1340 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1345 pa = pte_vatopa(mmu, pmap, va);
1352 * Extract the physical page address associated with the given
1353 * kernel virtual address.
1356 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1360 /* Check TLB1 mappings */
1361 for (i = 0; i < tlb1_idx; i++) {
1362 if (!(tlb1[i].mas1 & MAS1_VALID))
1364 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size)
1365 return (tlb1[i].phys + (va - tlb1[i].virt));
1368 return (pte_vatopa(mmu, kernel_pmap, va));
1372 * Initialize the pmap module.
1373 * Called by vm_init, to initialize any structures that the pmap
1374 * system needs to map virtual memory.
1377 mmu_booke_init(mmu_t mmu)
1379 int shpgperproc = PMAP_SHPGPERPROC;
1382 * Initialize the address space (zone) for the pv entries. Set a
1383 * high water mark so that the system can recover from excessive
1384 * numbers of pv entries.
1386 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1387 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1389 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1390 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1392 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1393 pv_entry_high_water = 9 * (pv_entry_max / 10);
1395 uma_zone_reserve_kva(pvzone, pv_entry_max);
1397 /* Pre-fill pvzone with initial number of pv entries. */
1398 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1400 /* Initialize ptbl allocation. */
1405 * Map a list of wired pages into kernel virtual address space. This is
1406 * intended for temporary mappings which do not need page modification or
1407 * references recorded. Existing mappings in the region are overwritten.
1410 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1415 while (count-- > 0) {
1416 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1423 * Remove page mappings from kernel virtual address space. Intended for
1424 * temporary mappings entered by mmu_booke_qenter.
1427 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1432 while (count-- > 0) {
1433 mmu_booke_kremove(mmu, va);
1439 * Map a wired page into kernel virtual address space.
1442 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1445 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1449 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1451 unsigned int pdir_idx = PDIR_IDX(va);
1452 unsigned int ptbl_idx = PTBL_IDX(va);
1456 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1457 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1459 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1460 flags |= tlb_calc_wimg(pa, ma);
1462 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1464 mtx_lock_spin(&tlbivax_mutex);
1467 if (PTE_ISVALID(pte)) {
1469 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1471 /* Flush entry from TLB0 */
1472 tlb0_flush_entry(va);
1475 pte->rpn = pa & ~PTE_PA_MASK;
1478 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1479 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1480 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1482 /* Flush the real memory from the instruction cache. */
1483 if ((flags & (PTE_I | PTE_G)) == 0) {
1484 __syncicache((void *)va, PAGE_SIZE);
1488 mtx_unlock_spin(&tlbivax_mutex);
1492 * Remove a page from kernel page table.
1495 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1497 unsigned int pdir_idx = PDIR_IDX(va);
1498 unsigned int ptbl_idx = PTBL_IDX(va);
1501 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1503 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1504 (va <= VM_MAX_KERNEL_ADDRESS)),
1505 ("mmu_booke_kremove: invalid va"));
1507 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1509 if (!PTE_ISVALID(pte)) {
1511 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1516 mtx_lock_spin(&tlbivax_mutex);
1519 /* Invalidate entry in TLB0, update PTE. */
1520 tlb0_flush_entry(va);
1525 mtx_unlock_spin(&tlbivax_mutex);
1529 * Initialize pmap associated with process 0.
1532 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1535 PMAP_LOCK_INIT(pmap);
1536 mmu_booke_pinit(mmu, pmap);
1537 PCPU_SET(curpmap, pmap);
1541 * Initialize a preallocated and zeroed pmap structure,
1542 * such as one in a vmspace structure.
1545 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1549 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1550 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1552 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1554 for (i = 0; i < MAXCPU; i++)
1555 pmap->pm_tid[i] = TID_NONE;
1556 CPU_ZERO(&kernel_pmap->pm_active);
1557 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1558 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1559 TAILQ_INIT(&pmap->pm_ptbl_list);
1563 * Release any resources held by the given physical map.
1564 * Called when a pmap initialized by mmu_booke_pinit is being released.
1565 * Should only be called if the map contains no valid mappings.
1568 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1571 KASSERT(pmap->pm_stats.resident_count == 0,
1572 ("pmap_release: pmap resident count %ld != 0",
1573 pmap->pm_stats.resident_count));
1577 * Insert the given physical page at the specified virtual address in the
1578 * target physical map with the protection requested. If specified the page
1579 * will be wired down.
1582 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1583 vm_prot_t prot, boolean_t wired)
1586 rw_wlock(&pvh_global_lock);
1588 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1589 rw_wunlock(&pvh_global_lock);
1594 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1595 vm_prot_t prot, boolean_t wired)
1602 pa = VM_PAGE_TO_PHYS(m);
1603 su = (pmap == kernel_pmap);
1606 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1607 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1608 // (u_int32_t)pmap, su, pmap->pm_tid,
1609 // (u_int32_t)m, va, pa, prot, wired);
1612 KASSERT(((va >= virtual_avail) &&
1613 (va <= VM_MAX_KERNEL_ADDRESS)),
1614 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1616 KASSERT((va <= VM_MAXUSER_ADDRESS),
1617 ("mmu_booke_enter_locked: user pmap, non user va"));
1619 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1620 VM_OBJECT_ASSERT_LOCKED(m->object);
1622 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1625 * If there is an existing mapping, and the physical address has not
1626 * changed, must be protection or wiring change.
1628 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1629 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1632 * Before actually updating pte->flags we calculate and
1633 * prepare its new value in a helper var.
1636 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1638 /* Wiring change, just update stats. */
1640 if (!PTE_ISWIRED(pte)) {
1642 pmap->pm_stats.wired_count++;
1645 if (PTE_ISWIRED(pte)) {
1646 flags &= ~PTE_WIRED;
1647 pmap->pm_stats.wired_count--;
1651 if (prot & VM_PROT_WRITE) {
1652 /* Add write permissions. */
1657 if ((flags & PTE_MANAGED) != 0)
1658 vm_page_aflag_set(m, PGA_WRITEABLE);
1660 /* Handle modified pages, sense modify status. */
1663 * The PTE_MODIFIED flag could be set by underlying
1664 * TLB misses since we last read it (above), possibly
1665 * other CPUs could update it so we check in the PTE
1666 * directly rather than rely on that saved local flags
1669 if (PTE_ISMODIFIED(pte))
1673 if (prot & VM_PROT_EXECUTE) {
1679 * Check existing flags for execute permissions: if we
1680 * are turning execute permissions on, icache should
1683 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1687 flags &= ~PTE_REFERENCED;
1690 * The new flags value is all calculated -- only now actually
1693 mtx_lock_spin(&tlbivax_mutex);
1696 tlb0_flush_entry(va);
1700 mtx_unlock_spin(&tlbivax_mutex);
1704 * If there is an existing mapping, but it's for a different
1705 * physical address, pte_enter() will delete the old mapping.
1707 //if ((pte != NULL) && PTE_ISVALID(pte))
1708 // debugf("mmu_booke_enter_locked: replace\n");
1710 // debugf("mmu_booke_enter_locked: new\n");
1712 /* Now set up the flags and install the new mapping. */
1713 flags = (PTE_SR | PTE_VALID);
1719 if (prot & VM_PROT_WRITE) {
1724 if ((m->oflags & VPO_UNMANAGED) == 0)
1725 vm_page_aflag_set(m, PGA_WRITEABLE);
1728 if (prot & VM_PROT_EXECUTE) {
1734 /* If its wired update stats. */
1736 pmap->pm_stats.wired_count++;
1740 pte_enter(mmu, pmap, m, va, flags);
1742 /* Flush the real memory from the instruction cache. */
1743 if (prot & VM_PROT_EXECUTE)
1747 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1748 __syncicache((void *)va, PAGE_SIZE);
1754 * Maps a sequence of resident pages belonging to the same object.
1755 * The sequence begins with the given page m_start. This page is
1756 * mapped at the given virtual address start. Each subsequent page is
1757 * mapped at a virtual address that is offset from start by the same
1758 * amount as the page is offset from m_start within the object. The
1759 * last page in the sequence is the page with the largest offset from
1760 * m_start that can be mapped at a virtual address less than the given
1761 * virtual address end. Not every virtual page between start and end
1762 * is mapped; only those for which a resident page exists with the
1763 * corresponding offset from m_start are mapped.
1766 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1767 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1770 vm_pindex_t diff, psize;
1772 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1774 psize = atop(end - start);
1776 rw_wlock(&pvh_global_lock);
1778 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1779 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1780 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1781 m = TAILQ_NEXT(m, listq);
1783 rw_wunlock(&pvh_global_lock);
1788 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1792 rw_wlock(&pvh_global_lock);
1794 mmu_booke_enter_locked(mmu, pmap, va, m,
1795 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1796 rw_wunlock(&pvh_global_lock);
1801 * Remove the given range of addresses from the specified map.
1803 * It is assumed that the start and end are properly rounded to the page size.
1806 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1811 int su = (pmap == kernel_pmap);
1813 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1814 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1817 KASSERT(((va >= virtual_avail) &&
1818 (va <= VM_MAX_KERNEL_ADDRESS)),
1819 ("mmu_booke_remove: kernel pmap, non kernel va"));
1821 KASSERT((va <= VM_MAXUSER_ADDRESS),
1822 ("mmu_booke_remove: user pmap, non user va"));
1825 if (PMAP_REMOVE_DONE(pmap)) {
1826 //debugf("mmu_booke_remove: e (empty)\n");
1830 hold_flag = PTBL_HOLD_FLAG(pmap);
1831 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1833 rw_wlock(&pvh_global_lock);
1835 for (; va < endva; va += PAGE_SIZE) {
1836 pte = pte_find(mmu, pmap, va);
1837 if ((pte != NULL) && PTE_ISVALID(pte))
1838 pte_remove(mmu, pmap, va, hold_flag);
1841 rw_wunlock(&pvh_global_lock);
1843 //debugf("mmu_booke_remove: e\n");
1847 * Remove physical page from all pmaps in which it resides.
1850 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1855 rw_wlock(&pvh_global_lock);
1856 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1857 pvn = TAILQ_NEXT(pv, pv_link);
1859 PMAP_LOCK(pv->pv_pmap);
1860 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1861 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1862 PMAP_UNLOCK(pv->pv_pmap);
1864 vm_page_aflag_clear(m, PGA_WRITEABLE);
1865 rw_wunlock(&pvh_global_lock);
1869 * Map a range of physical addresses into kernel virtual address space.
1872 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1873 vm_paddr_t pa_end, int prot)
1875 vm_offset_t sva = *virt;
1876 vm_offset_t va = sva;
1878 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1879 // sva, pa_start, pa_end);
1881 while (pa_start < pa_end) {
1882 mmu_booke_kenter(mmu, va, pa_start);
1884 pa_start += PAGE_SIZE;
1888 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1893 * The pmap must be activated before it's address space can be accessed in any
1897 mmu_booke_activate(mmu_t mmu, struct thread *td)
1902 pmap = &td->td_proc->p_vmspace->vm_pmap;
1904 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1905 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1907 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1909 mtx_lock_spin(&sched_lock);
1911 cpuid = PCPU_GET(cpuid);
1912 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1913 PCPU_SET(curpmap, pmap);
1915 if (pmap->pm_tid[cpuid] == TID_NONE)
1918 /* Load PID0 register with pmap tid value. */
1919 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1920 __asm __volatile("isync");
1922 mtx_unlock_spin(&sched_lock);
1924 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1925 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1929 * Deactivate the specified process's address space.
1932 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1936 pmap = &td->td_proc->p_vmspace->vm_pmap;
1938 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1939 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1941 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1942 PCPU_SET(curpmap, NULL);
1946 * Copy the range specified by src_addr/len
1947 * from the source map to the range dst_addr/len
1948 * in the destination map.
1950 * This routine is only advisory and need not do anything.
1953 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1954 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1960 * Set the physical protection on the specified range of this map as requested.
1963 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1970 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1971 mmu_booke_remove(mmu, pmap, sva, eva);
1975 if (prot & VM_PROT_WRITE)
1979 for (va = sva; va < eva; va += PAGE_SIZE) {
1980 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1981 if (PTE_ISVALID(pte)) {
1982 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1984 mtx_lock_spin(&tlbivax_mutex);
1987 /* Handle modified pages. */
1988 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1991 tlb0_flush_entry(va);
1992 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1995 mtx_unlock_spin(&tlbivax_mutex);
2003 * Clear the write and modified bits in each of the given page's mappings.
2006 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2011 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2012 ("mmu_booke_remove_write: page %p is not managed", m));
2015 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2016 * set by another thread while the object is locked. Thus,
2017 * if PGA_WRITEABLE is clear, no page table entries need updating.
2019 VM_OBJECT_ASSERT_WLOCKED(m->object);
2020 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2022 rw_wlock(&pvh_global_lock);
2023 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2024 PMAP_LOCK(pv->pv_pmap);
2025 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2026 if (PTE_ISVALID(pte)) {
2027 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2029 mtx_lock_spin(&tlbivax_mutex);
2032 /* Handle modified pages. */
2033 if (PTE_ISMODIFIED(pte))
2036 /* Flush mapping from TLB0. */
2037 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2040 mtx_unlock_spin(&tlbivax_mutex);
2043 PMAP_UNLOCK(pv->pv_pmap);
2045 vm_page_aflag_clear(m, PGA_WRITEABLE);
2046 rw_wunlock(&pvh_global_lock);
2050 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2059 va = trunc_page(va);
2060 sz = round_page(sz);
2062 rw_wlock(&pvh_global_lock);
2063 pmap = PCPU_GET(curpmap);
2064 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2067 pte = pte_find(mmu, pm, va);
2068 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2074 /* Create a mapping in the active pmap. */
2076 m = PHYS_TO_VM_PAGE(pa);
2078 pte_enter(mmu, pmap, m, addr,
2079 PTE_SR | PTE_VALID | PTE_UR);
2080 __syncicache((void *)addr, PAGE_SIZE);
2081 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2084 __syncicache((void *)va, PAGE_SIZE);
2089 rw_wunlock(&pvh_global_lock);
2093 * Atomically extract and hold the physical page with the given
2094 * pmap and virtual address pair if that mapping permits the given
2098 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2110 pte = pte_find(mmu, pmap, va);
2111 if ((pte != NULL) && PTE_ISVALID(pte)) {
2112 if (pmap == kernel_pmap)
2117 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2118 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2120 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2131 * Initialize a vm_page's machine-dependent fields.
2134 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2137 TAILQ_INIT(&m->md.pv_list);
2141 * mmu_booke_zero_page_area zeros the specified hardware page by
2142 * mapping it into virtual memory and using bzero to clear
2145 * off and size must reside within a single page.
2148 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2152 /* XXX KASSERT off and size are within a single page? */
2154 mtx_lock(&zero_page_mutex);
2157 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2158 bzero((caddr_t)va + off, size);
2159 mmu_booke_kremove(mmu, va);
2161 mtx_unlock(&zero_page_mutex);
2165 * mmu_booke_zero_page zeros the specified hardware page.
2168 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2171 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2175 * mmu_booke_copy_page copies the specified (machine independent) page by
2176 * mapping the page into virtual memory and using memcopy to copy the page,
2177 * one machine dependent page at a time.
2180 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2182 vm_offset_t sva, dva;
2184 sva = copy_page_src_va;
2185 dva = copy_page_dst_va;
2187 mtx_lock(©_page_mutex);
2188 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2189 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2190 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2191 mmu_booke_kremove(mmu, dva);
2192 mmu_booke_kremove(mmu, sva);
2193 mtx_unlock(©_page_mutex);
2197 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2198 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2201 vm_offset_t a_pg_offset, b_pg_offset;
2204 mtx_lock(©_page_mutex);
2205 while (xfersize > 0) {
2206 a_pg_offset = a_offset & PAGE_MASK;
2207 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2208 mmu_booke_kenter(mmu, copy_page_src_va,
2209 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2210 a_cp = (char *)copy_page_src_va + a_pg_offset;
2211 b_pg_offset = b_offset & PAGE_MASK;
2212 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2213 mmu_booke_kenter(mmu, copy_page_dst_va,
2214 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2215 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2216 bcopy(a_cp, b_cp, cnt);
2217 mmu_booke_kremove(mmu, copy_page_dst_va);
2218 mmu_booke_kremove(mmu, copy_page_src_va);
2223 mtx_unlock(©_page_mutex);
2227 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2228 * into virtual memory and using bzero to clear its contents. This is intended
2229 * to be called from the vm_pagezero process only and outside of Giant. No
2233 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2237 va = zero_page_idle_va;
2238 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2239 bzero((caddr_t)va, PAGE_SIZE);
2240 mmu_booke_kremove(mmu, va);
2244 * Return whether or not the specified physical page was modified
2245 * in any of physical maps.
2248 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2254 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2255 ("mmu_booke_is_modified: page %p is not managed", m));
2259 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2260 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2261 * is clear, no PTEs can be modified.
2263 VM_OBJECT_ASSERT_WLOCKED(m->object);
2264 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2266 rw_wlock(&pvh_global_lock);
2267 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2268 PMAP_LOCK(pv->pv_pmap);
2269 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2271 if (PTE_ISMODIFIED(pte))
2274 PMAP_UNLOCK(pv->pv_pmap);
2278 rw_wunlock(&pvh_global_lock);
2283 * Return whether or not the specified virtual address is eligible
2287 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2294 * Return whether or not the specified physical page was referenced
2295 * in any physical maps.
2298 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2304 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2305 ("mmu_booke_is_referenced: page %p is not managed", m));
2307 rw_wlock(&pvh_global_lock);
2308 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2309 PMAP_LOCK(pv->pv_pmap);
2310 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2312 if (PTE_ISREFERENCED(pte))
2315 PMAP_UNLOCK(pv->pv_pmap);
2319 rw_wunlock(&pvh_global_lock);
2324 * Clear the modify bits on the specified physical page.
2327 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2332 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2333 ("mmu_booke_clear_modify: page %p is not managed", m));
2334 VM_OBJECT_ASSERT_WLOCKED(m->object);
2335 KASSERT(!vm_page_xbusied(m),
2336 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2339 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2340 * If the object containing the page is locked and the page is not
2341 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2343 if ((m->aflags & PGA_WRITEABLE) == 0)
2345 rw_wlock(&pvh_global_lock);
2346 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2347 PMAP_LOCK(pv->pv_pmap);
2348 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2350 mtx_lock_spin(&tlbivax_mutex);
2353 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2354 tlb0_flush_entry(pv->pv_va);
2355 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2360 mtx_unlock_spin(&tlbivax_mutex);
2362 PMAP_UNLOCK(pv->pv_pmap);
2364 rw_wunlock(&pvh_global_lock);
2368 * Return a count of reference bits for a page, clearing those bits.
2369 * It is not necessary for every reference bit to be cleared, but it
2370 * is necessary that 0 only be returned when there are truly no
2371 * reference bits set.
2373 * XXX: The exact number of bits to check and clear is a matter that
2374 * should be tested and standardized at some point in the future for
2375 * optimal aging of shared pages.
2378 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2384 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2385 ("mmu_booke_ts_referenced: page %p is not managed", m));
2387 rw_wlock(&pvh_global_lock);
2388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2389 PMAP_LOCK(pv->pv_pmap);
2390 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2392 if (PTE_ISREFERENCED(pte)) {
2393 mtx_lock_spin(&tlbivax_mutex);
2396 tlb0_flush_entry(pv->pv_va);
2397 pte->flags &= ~PTE_REFERENCED;
2400 mtx_unlock_spin(&tlbivax_mutex);
2403 PMAP_UNLOCK(pv->pv_pmap);
2408 PMAP_UNLOCK(pv->pv_pmap);
2410 rw_wunlock(&pvh_global_lock);
2415 * Change wiring attribute for a map/virtual-address pair.
2418 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2423 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2425 if (!PTE_ISWIRED(pte)) {
2426 pte->flags |= PTE_WIRED;
2427 pmap->pm_stats.wired_count++;
2430 if (PTE_ISWIRED(pte)) {
2431 pte->flags &= ~PTE_WIRED;
2432 pmap->pm_stats.wired_count--;
2440 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2441 * page. This count may be changed upwards or downwards in the future; it is
2442 * only necessary that true be returned for a small subset of pmaps for proper
2446 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2452 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2453 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2456 rw_wlock(&pvh_global_lock);
2457 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2458 if (pv->pv_pmap == pmap) {
2465 rw_wunlock(&pvh_global_lock);
2470 * Return the number of managed mappings to the given physical page that are
2474 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2480 if ((m->oflags & VPO_UNMANAGED) != 0)
2482 rw_wlock(&pvh_global_lock);
2483 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2484 PMAP_LOCK(pv->pv_pmap);
2485 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2486 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2488 PMAP_UNLOCK(pv->pv_pmap);
2490 rw_wunlock(&pvh_global_lock);
2495 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2501 * This currently does not work for entries that
2502 * overlap TLB1 entries.
2504 for (i = 0; i < tlb1_idx; i ++) {
2505 if (tlb1_iomapped(i, pa, size, &va) == 0)
2513 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2520 /* Raw physical memory dumps don't have a virtual address. */
2521 if (md->md_vaddr == ~0UL) {
2522 /* We always map a 256MB page at 256M. */
2523 gran = 256 * 1024 * 1024;
2524 pa = md->md_paddr + ofs;
2525 ppa = pa & ~(gran - 1);
2528 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2529 if (*sz > (gran - ofs))
2534 /* Minidumps are based on virtual memory addresses. */
2535 va = md->md_vaddr + ofs;
2536 if (va >= kernstart + kernsize) {
2537 gran = PAGE_SIZE - (va & PAGE_MASK);
2545 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2549 /* Raw physical memory dumps don't have a virtual address. */
2550 if (md->md_vaddr == ~0UL) {
2552 tlb1[tlb1_idx].mas1 = 0;
2553 tlb1[tlb1_idx].mas2 = 0;
2554 tlb1[tlb1_idx].mas3 = 0;
2555 tlb1_write_entry(tlb1_idx);
2559 /* Minidumps are based on virtual memory addresses. */
2560 /* Nothing to do... */
2564 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2566 static struct pmap_md md;
2570 if (dumpsys_minidump) {
2571 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2573 /* 1st: kernel .data and .bss. */
2575 md.md_vaddr = trunc_page((uintptr_t)_etext);
2576 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2579 switch (prev->md_index) {
2581 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2583 md.md_vaddr = data_start;
2584 md.md_size = data_end - data_start;
2587 /* 3rd: kernel VM. */
2588 va = prev->md_vaddr + prev->md_size;
2589 /* Find start of next chunk (from va). */
2590 while (va < virtual_end) {
2591 /* Don't dump the buffer cache. */
2592 if (va >= kmi.buffer_sva &&
2593 va < kmi.buffer_eva) {
2594 va = kmi.buffer_eva;
2597 pte = pte_find(mmu, kernel_pmap, va);
2598 if (pte != NULL && PTE_ISVALID(pte))
2602 if (va < virtual_end) {
2605 /* Find last page in chunk. */
2606 while (va < virtual_end) {
2607 /* Don't run into the buffer cache. */
2608 if (va == kmi.buffer_sva)
2610 pte = pte_find(mmu, kernel_pmap, va);
2611 if (pte == NULL || !PTE_ISVALID(pte))
2615 md.md_size = va - md.md_vaddr;
2623 } else { /* minidumps */
2624 mem_regions(&physmem_regions, &physmem_regions_sz,
2625 &availmem_regions, &availmem_regions_sz);
2628 /* first physical chunk. */
2629 md.md_paddr = physmem_regions[0].mr_start;
2630 md.md_size = physmem_regions[0].mr_size;
2633 } else if (md.md_index < physmem_regions_sz) {
2634 md.md_paddr = physmem_regions[md.md_index].mr_start;
2635 md.md_size = physmem_regions[md.md_index].mr_size;
2639 /* There's no next physical chunk. */
2648 * Map a set of physical memory pages into the kernel virtual address space.
2649 * Return a pointer to where it is mapped. This routine is intended to be used
2650 * for mapping device memory, NOT real memory.
2653 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2656 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2660 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2667 * CCSR is premapped. Note that (pa + size - 1) is there to make sure
2668 * we don't wrap around. Devices on the local bus typically extend all
2669 * the way up to and including 0xffffffff. In that case (pa + size)
2670 * would be 0. This creates a false positive (i.e. we think it's
2671 * within the CCSR) and not create a mapping.
2673 if (ma == VM_MEMATTR_DEFAULT && pa >= ccsrbar_pa &&
2674 (pa + size - 1) < (ccsrbar_pa + CCSRBAR_SIZE)) {
2675 va = CCSRBAR_VA + (pa - ccsrbar_pa);
2676 return ((void *)va);
2679 if (size < PAGE_SIZE)
2682 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) &&
2683 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS)
2686 va = kva_alloc(size);
2690 sz = 1 << (ilog2(size) & ~1);
2692 printf("Wiring VA=%x to PA=%x (size=%x), "
2693 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2694 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma));
2704 * 'Unmap' a range mapped by mmu_booke_mapdev().
2707 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2709 #ifdef SUPPORTS_SHRINKING_TLB1
2710 vm_offset_t base, offset;
2713 * Unmap only if this is inside kernel virtual space.
2715 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2716 base = trunc_page(va);
2717 offset = va & PAGE_MASK;
2718 size = roundup(offset + size, PAGE_SIZE);
2719 kva_free(base, size);
2725 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2726 * specified pmap. This eliminates the blast of soft faults on process startup
2727 * and immediately after an mmap.
2730 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2731 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2734 VM_OBJECT_ASSERT_WLOCKED(object);
2735 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2736 ("mmu_booke_object_init_pt: non-device object"));
2740 * Perform the pmap work for mincore.
2743 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2744 vm_paddr_t *locked_pa)
2751 /**************************************************************************/
2753 /**************************************************************************/
2756 * Allocate a TID. If necessary, steal one from someone else.
2757 * The new TID is flushed from the TLB before returning.
2760 tid_alloc(pmap_t pmap)
2765 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2767 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2769 thiscpu = PCPU_GET(cpuid);
2771 tid = PCPU_GET(tid_next);
2774 PCPU_SET(tid_next, tid + 1);
2776 /* If we are stealing TID then clear the relevant pmap's field */
2777 if (tidbusy[thiscpu][tid] != NULL) {
2779 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2781 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2783 /* Flush all entries from TLB0 matching this TID. */
2787 tidbusy[thiscpu][tid] = pmap;
2788 pmap->pm_tid[thiscpu] = tid;
2789 __asm __volatile("msync; isync");
2791 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2792 PCPU_GET(tid_next));
2797 /**************************************************************************/
2799 /**************************************************************************/
2802 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2812 if (mas1 & MAS1_VALID)
2817 if (mas1 & MAS1_IPROT)
2822 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2823 tid = MAS1_GETTID(mas1);
2825 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2828 size = tsize2size(tsize);
2830 debugf("%3d: (%s) [AS=%d] "
2831 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2832 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2833 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2836 /* Convert TLB0 va and way number to tlb0[] table index. */
2837 static inline unsigned int
2838 tlb0_tableidx(vm_offset_t va, unsigned int way)
2842 idx = (way * TLB0_ENTRIES_PER_WAY);
2843 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2848 * Invalidate TLB0 entry.
2851 tlb0_flush_entry(vm_offset_t va)
2854 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2856 mtx_assert(&tlbivax_mutex, MA_OWNED);
2858 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2859 __asm __volatile("isync; msync");
2860 __asm __volatile("tlbsync; msync");
2862 CTR1(KTR_PMAP, "%s: e", __func__);
2865 /* Print out contents of the MAS registers for each TLB0 entry */
2867 tlb0_print_tlbentries(void)
2869 uint32_t mas0, mas1, mas2, mas3, mas7;
2870 int entryidx, way, idx;
2872 debugf("TLB0 entries:\n");
2873 for (way = 0; way < TLB0_WAYS; way ++)
2874 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2876 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2877 mtspr(SPR_MAS0, mas0);
2878 __asm __volatile("isync");
2880 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2881 mtspr(SPR_MAS2, mas2);
2883 __asm __volatile("isync; tlbre");
2885 mas1 = mfspr(SPR_MAS1);
2886 mas2 = mfspr(SPR_MAS2);
2887 mas3 = mfspr(SPR_MAS3);
2888 mas7 = mfspr(SPR_MAS7);
2890 idx = tlb0_tableidx(mas2, way);
2891 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2895 /**************************************************************************/
2897 /**************************************************************************/
2900 * TLB1 mapping notes:
2903 * TLB1[1] Kernel text and data.
2904 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI
2905 * windows, other devices mappings.
2909 * Write given entry to TLB1 hardware.
2910 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2913 tlb1_write_entry(unsigned int idx)
2915 uint32_t mas0, mas7;
2917 //debugf("tlb1_write_entry: s\n");
2919 /* Clear high order RPN bits */
2923 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2924 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2926 mtspr(SPR_MAS0, mas0);
2927 __asm __volatile("isync");
2928 mtspr(SPR_MAS1, tlb1[idx].mas1);
2929 __asm __volatile("isync");
2930 mtspr(SPR_MAS2, tlb1[idx].mas2);
2931 __asm __volatile("isync");
2932 mtspr(SPR_MAS3, tlb1[idx].mas3);
2933 __asm __volatile("isync");
2934 mtspr(SPR_MAS7, mas7);
2935 __asm __volatile("isync; tlbwe; isync; msync");
2937 //debugf("tlb1_write_entry: e\n");
2941 * Return the largest uint value log such that 2^log <= num.
2944 ilog2(unsigned int num)
2948 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2953 * Convert TLB TSIZE value to mapped region size.
2956 tsize2size(unsigned int tsize)
2961 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2964 return ((1 << (2 * tsize)) * 1024);
2968 * Convert region size (must be power of 4) to TLB TSIZE value.
2971 size2tsize(vm_size_t size)
2974 return (ilog2(size) / 2 - 5);
2978 * Register permanent kernel mapping in TLB1.
2980 * Entries are created starting from index 0 (current free entry is
2981 * kept in tlb1_idx) and are not supposed to be invalidated.
2984 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2990 index = atomic_fetchadd_int(&tlb1_idx, 1);
2991 if (index >= TLB1_ENTRIES) {
2992 printf("tlb1_set_entry: TLB1 full!\n");
2996 /* Convert size to TSIZE */
2997 tsize = size2tsize(size);
2999 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3000 /* XXX TS is hard coded to 0 for now as we only use single address space */
3001 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3004 * Atomicity is preserved by the atomic increment above since nothing
3005 * is ever removed from tlb1.
3008 tlb1[index].phys = pa;
3009 tlb1[index].virt = va;
3010 tlb1[index].size = size;
3011 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3012 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3013 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags;
3015 /* Set supervisor RWX permission bits */
3016 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3018 tlb1_write_entry(index);
3021 * XXX in general TLB1 updates should be propagated between CPUs,
3022 * since current design assumes to have the same TLB1 set-up on all
3029 * Map in contiguous RAM region into the TLB1 using maximum of
3030 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3032 * If necessary round up last entry size and return total size
3033 * used by all allocated entries.
3036 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3038 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3039 vm_size_t mapped, pgsz, base, mask;
3042 /* Round up to the next 1M */
3043 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
3048 pgsz = 64*1024*1024;
3049 while (mapped < size) {
3050 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3051 while (pgsz > (size - mapped))
3057 /* We under-map. Correct for this. */
3058 if (mapped < size) {
3059 while (pgs[idx - 1] == pgsz) {
3063 /* XXX We may increase beyond out starting point. */
3072 /* Align address to the boundary */
3074 va = (va + mask) & ~mask;
3075 pa = (pa + mask) & ~mask;
3078 for (idx = 0; idx < nents; idx++) {
3080 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3081 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3086 mapped = (va - base);
3087 debugf("mapped size 0x%08x (wasted space 0x%08x)\n",
3088 mapped, mapped - size);
3093 * TLB1 initialization routine, to be called after the very first
3094 * assembler level setup done in locore.S.
3097 tlb1_init(vm_offset_t ccsrbar)
3099 uint32_t mas0, mas1, mas3;
3103 ccsrbar_pa = ccsrbar;
3105 if (bootinfo != NULL && bootinfo[0] != 1) {
3106 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3110 /* The first entry/entries are used to map the kernel. */
3111 for (i = 0; i < tlb1_idx; i++) {
3112 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3113 mtspr(SPR_MAS0, mas0);
3114 __asm __volatile("isync; tlbre");
3116 mas1 = mfspr(SPR_MAS1);
3117 if ((mas1 & MAS1_VALID) == 0)
3120 mas3 = mfspr(SPR_MAS3);
3122 tlb1[i].mas1 = mas1;
3123 tlb1[i].mas2 = mfspr(SPR_MAS2);
3124 tlb1[i].mas3 = mas3;
3127 kernload = mas3 & MAS3_RPN;
3129 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3130 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
3133 /* Map in CCSRBAR. */
3134 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO);
3137 bp_ntlb1s = tlb1_idx;
3140 /* Purge the remaining entries */
3141 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3142 tlb1_write_entry(i);
3144 /* Setup TLB miss defaults */
3145 set_mas4_defaults();
3149 * Setup MAS4 defaults.
3150 * These values are loaded to MAS0-2 on a TLB miss.
3153 set_mas4_defaults(void)
3157 /* Defaults: TLB0, PID0, TSIZED=4K */
3158 mas4 = MAS4_TLBSELD0;
3159 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3163 mtspr(SPR_MAS4, mas4);
3164 __asm __volatile("isync");
3168 * Print out contents of the MAS registers for each TLB1 entry
3171 tlb1_print_tlbentries(void)
3173 uint32_t mas0, mas1, mas2, mas3, mas7;
3176 debugf("TLB1 entries:\n");
3177 for (i = 0; i < TLB1_ENTRIES; i++) {
3179 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3180 mtspr(SPR_MAS0, mas0);
3182 __asm __volatile("isync; tlbre");
3184 mas1 = mfspr(SPR_MAS1);
3185 mas2 = mfspr(SPR_MAS2);
3186 mas3 = mfspr(SPR_MAS3);
3187 mas7 = mfspr(SPR_MAS7);
3189 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3194 * Print out contents of the in-ram tlb1 table.
3197 tlb1_print_entries(void)
3201 debugf("tlb1[] table entries:\n");
3202 for (i = 0; i < TLB1_ENTRIES; i++)
3203 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3207 * Return 0 if the physical IO range is encompassed by one of the
3208 * the TLB1 entries, otherwise return related error code.
3211 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3214 vm_paddr_t pa_start;
3216 unsigned int entry_tsize;
3217 vm_size_t entry_size;
3219 *va = (vm_offset_t)NULL;
3221 /* Skip invalid entries */
3222 if (!(tlb1[i].mas1 & MAS1_VALID))
3226 * The entry must be cache-inhibited, guarded, and r/w
3227 * so it can function as an i/o page
3229 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3230 if (prot != (MAS2_I | MAS2_G))
3233 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3234 if (prot != (MAS3_SR | MAS3_SW))
3237 /* The address should be within the entry range. */
3238 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3239 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3241 entry_size = tsize2size(entry_tsize);
3242 pa_start = tlb1[i].mas3 & MAS3_RPN;
3243 pa_end = pa_start + entry_size - 1;
3245 if ((pa < pa_start) || ((pa + size) > pa_end))
3248 /* Return virtual address of this mapping. */
3249 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);