2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2020 Justin Hibbits
5 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
6 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Some hw specific parts of this pmap were derived or influenced
30 * by NetBSD's ibm4xx pmap module. More generic code is shared with
31 * a few other pmap modules from the FreeBSD tree.
37 * Kernel and user threads run within one common virtual address space
41 * Virtual address space layout:
42 * -----------------------------
43 * 0x0000_0000 - 0x7fff_ffff : user process
44 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
45 * 0xc000_0000 - 0xffff_efff : KVA
48 #include <sys/cdefs.h>
49 __FBSDID("$FreeBSD$");
52 #include "opt_kstack_pages.h"
54 #include <sys/param.h>
56 #include <sys/malloc.h>
60 #include <sys/queue.h>
61 #include <sys/systm.h>
62 #include <sys/kernel.h>
63 #include <sys/kerneldump.h>
64 #include <sys/linker.h>
65 #include <sys/msgbuf.h>
67 #include <sys/mutex.h>
68 #include <sys/rwlock.h>
69 #include <sys/sched.h>
71 #include <sys/vmmeter.h>
74 #include <vm/vm_page.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_pageout.h>
77 #include <vm/vm_extern.h>
78 #include <vm/vm_object.h>
79 #include <vm/vm_param.h>
80 #include <vm/vm_map.h>
81 #include <vm/vm_pager.h>
82 #include <vm/vm_phys.h>
83 #include <vm/vm_pagequeue.h>
86 #include <machine/_inttypes.h>
87 #include <machine/cpu.h>
88 #include <machine/pcb.h>
89 #include <machine/platform.h>
91 #include <machine/tlb.h>
92 #include <machine/spr.h>
93 #include <machine/md_var.h>
94 #include <machine/mmuvar.h>
95 #include <machine/pmap.h>
96 #include <machine/pte.h>
100 #define PRI0ptrX "08x"
102 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
103 static vm_offset_t zero_page_va;
104 static struct mtx zero_page_mutex;
106 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
107 static vm_offset_t copy_page_src_va;
108 static vm_offset_t copy_page_dst_va;
109 static struct mtx copy_page_mutex;
111 static vm_offset_t kernel_ptbl_root;
112 static unsigned int kernel_ptbls; /* Number of KVA ptbls. */
114 /**************************************************************************/
116 /**************************************************************************/
118 #define VM_MAPDEV_BASE ((vm_offset_t)VM_MAXUSER_ADDRESS + PAGE_SIZE)
120 static void tid_flush(tlbtid_t tid);
121 static unsigned long ilog2(unsigned long);
123 /**************************************************************************/
124 /* Page table management */
125 /**************************************************************************/
127 #define PMAP_ROOT_SIZE (sizeof(pte_t**) * PDIR_NENTRIES)
128 static void ptbl_init(void);
129 static struct ptbl_buf *ptbl_buf_alloc(void);
130 static void ptbl_buf_free(struct ptbl_buf *);
131 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
133 static pte_t *ptbl_alloc(pmap_t, unsigned int, boolean_t);
134 static void ptbl_free(pmap_t, unsigned int);
135 static void ptbl_hold(pmap_t, unsigned int);
136 static int ptbl_unhold(pmap_t, unsigned int);
138 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
139 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, boolean_t);
140 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
141 static pte_t *pte_find(pmap_t, vm_offset_t);
144 TAILQ_ENTRY(ptbl_buf) link; /* list link */
145 vm_offset_t kva; /* va of mapping */
148 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
149 #define PTBL_BUFS (128 * 16)
151 /* ptbl free list and a lock used for access synchronization. */
152 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
153 static struct mtx ptbl_buf_freelist_lock;
155 /* Base address of kva space allocated fot ptbl bufs. */
156 static vm_offset_t ptbl_buf_pool_vabase;
158 /* Pointer to ptbl_buf structures. */
159 static struct ptbl_buf *ptbl_bufs;
161 /**************************************************************************/
162 /* Page table related */
163 /**************************************************************************/
166 /* Initialize pool of kva ptbl buffers. */
172 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
173 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
174 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
175 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
177 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
178 TAILQ_INIT(&ptbl_buf_freelist);
180 for (i = 0; i < PTBL_BUFS; i++) {
182 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
183 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
187 /* Get a ptbl_buf from the freelist. */
188 static struct ptbl_buf *
191 struct ptbl_buf *buf;
193 mtx_lock(&ptbl_buf_freelist_lock);
194 buf = TAILQ_FIRST(&ptbl_buf_freelist);
196 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
197 mtx_unlock(&ptbl_buf_freelist_lock);
199 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
204 /* Return ptbl buff to free pool. */
206 ptbl_buf_free(struct ptbl_buf *buf)
209 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
211 mtx_lock(&ptbl_buf_freelist_lock);
212 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
213 mtx_unlock(&ptbl_buf_freelist_lock);
217 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
220 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
222 struct ptbl_buf *pbuf;
224 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
226 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
228 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
229 if (pbuf->kva == (vm_offset_t)ptbl) {
230 /* Remove from pmap ptbl buf list. */
231 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
233 /* Free corresponding ptbl buf. */
239 /* Allocate page table. */
241 ptbl_alloc(pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
243 vm_page_t mtbl[PTBL_PAGES];
245 struct ptbl_buf *pbuf;
250 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
251 (pmap == kernel_pmap), pdir_idx);
253 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
254 ("ptbl_alloc: invalid pdir_idx"));
255 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
256 ("pte_alloc: valid ptbl entry exists!"));
258 pbuf = ptbl_buf_alloc();
260 panic("pte_alloc: couldn't alloc kernel virtual memory");
262 ptbl = (pte_t *)pbuf->kva;
264 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
266 for (i = 0; i < PTBL_PAGES; i++) {
267 pidx = (PTBL_PAGES * pdir_idx) + i;
268 while ((m = vm_page_alloc(NULL, pidx,
269 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
271 ptbl_free_pmap_ptbl(pmap, ptbl);
272 for (j = 0; j < i; j++)
273 vm_page_free(mtbl[j]);
278 rw_wunlock(&pvh_global_lock);
280 rw_wlock(&pvh_global_lock);
286 /* Map allocated pages into kernel_pmap. */
287 mmu_booke_qenter((vm_offset_t)ptbl, mtbl, PTBL_PAGES);
289 /* Zero whole ptbl. */
290 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
292 /* Add pbuf to the pmap ptbl bufs list. */
293 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
298 /* Free ptbl pages and invalidate pdir entry. */
300 ptbl_free(pmap_t pmap, unsigned int pdir_idx)
308 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
309 (pmap == kernel_pmap), pdir_idx);
311 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
312 ("ptbl_free: invalid pdir_idx"));
314 ptbl = pmap->pm_pdir[pdir_idx];
316 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
318 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
321 * Invalidate the pdir entry as soon as possible, so that other CPUs
322 * don't attempt to look up the page tables we are releasing.
324 mtx_lock_spin(&tlbivax_mutex);
327 pmap->pm_pdir[pdir_idx] = NULL;
330 mtx_unlock_spin(&tlbivax_mutex);
332 for (i = 0; i < PTBL_PAGES; i++) {
333 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
334 pa = pte_vatopa(kernel_pmap, va);
335 m = PHYS_TO_VM_PAGE(pa);
336 vm_page_free_zero(m);
338 mmu_booke_kremove(va);
341 ptbl_free_pmap_ptbl(pmap, ptbl);
345 * Decrement ptbl pages hold count and attempt to free ptbl pages.
346 * Called when removing pte entry from ptbl.
348 * Return 1 if ptbl pages were freed.
351 ptbl_unhold(pmap_t pmap, unsigned int pdir_idx)
358 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
359 (pmap == kernel_pmap), pdir_idx);
361 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
362 ("ptbl_unhold: invalid pdir_idx"));
363 KASSERT((pmap != kernel_pmap),
364 ("ptbl_unhold: unholding kernel ptbl!"));
366 ptbl = pmap->pm_pdir[pdir_idx];
368 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
369 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
370 ("ptbl_unhold: non kva ptbl"));
372 /* decrement hold count */
373 for (i = 0; i < PTBL_PAGES; i++) {
374 pa = pte_vatopa(kernel_pmap,
375 (vm_offset_t)ptbl + (i * PAGE_SIZE));
376 m = PHYS_TO_VM_PAGE(pa);
381 * Free ptbl pages if there are no pte etries in this ptbl.
382 * ref_count has the same value for all ptbl pages, so check the last
385 if (m->ref_count == 0) {
386 ptbl_free(pmap, pdir_idx);
388 //debugf("ptbl_unhold: e (freed ptbl)\n");
396 * Increment hold count for ptbl pages. This routine is used when a new pte
397 * entry is being inserted into the ptbl.
400 ptbl_hold(pmap_t pmap, unsigned int pdir_idx)
407 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
410 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
411 ("ptbl_hold: invalid pdir_idx"));
412 KASSERT((pmap != kernel_pmap),
413 ("ptbl_hold: holding kernel ptbl!"));
415 ptbl = pmap->pm_pdir[pdir_idx];
417 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
419 for (i = 0; i < PTBL_PAGES; i++) {
420 pa = pte_vatopa(kernel_pmap,
421 (vm_offset_t)ptbl + (i * PAGE_SIZE));
422 m = PHYS_TO_VM_PAGE(pa);
428 * Clean pte entry, try to free page table page if requested.
430 * Return 1 if ptbl pages were freed, otherwise return 0.
433 pte_remove(pmap_t pmap, vm_offset_t va, uint8_t flags)
435 unsigned int pdir_idx = PDIR_IDX(va);
436 unsigned int ptbl_idx = PTBL_IDX(va);
441 //int su = (pmap == kernel_pmap);
442 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
443 // su, (u_int32_t)pmap, va, flags);
445 ptbl = pmap->pm_pdir[pdir_idx];
446 KASSERT(ptbl, ("pte_remove: null ptbl"));
448 pte = &ptbl[ptbl_idx];
450 if (pte == NULL || !PTE_ISVALID(pte))
453 if (PTE_ISWIRED(pte))
454 pmap->pm_stats.wired_count--;
456 /* Get vm_page_t for mapped pte. */
457 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
459 /* Handle managed entry. */
460 if (PTE_ISMANAGED(pte)) {
462 if (PTE_ISMODIFIED(pte))
465 if (PTE_ISREFERENCED(pte))
466 vm_page_aflag_set(m, PGA_REFERENCED);
468 pv_remove(pmap, va, m);
469 } else if (pmap == kernel_pmap && m && m->md.pv_tracked) {
471 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is
472 * used. This is needed by the NCSW support code for fast
473 * VA<->PA translation.
475 pv_remove(pmap, va, m);
476 if (TAILQ_EMPTY(&m->md.pv_list))
477 m->md.pv_tracked = false;
480 mtx_lock_spin(&tlbivax_mutex);
483 tlb0_flush_entry(va);
487 mtx_unlock_spin(&tlbivax_mutex);
489 pmap->pm_stats.resident_count--;
491 if (flags & PTBL_UNHOLD) {
492 //debugf("pte_remove: e (unhold)\n");
493 return (ptbl_unhold(pmap, pdir_idx));
496 //debugf("pte_remove: e\n");
501 * Insert PTE for a given page and virtual address.
504 pte_enter(pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
507 unsigned int pdir_idx = PDIR_IDX(va);
508 unsigned int ptbl_idx = PTBL_IDX(va);
509 pte_t *ptbl, *pte, pte_tmp;
511 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
512 pmap == kernel_pmap, pmap, va);
514 /* Get the page table pointer. */
515 ptbl = pmap->pm_pdir[pdir_idx];
518 /* Allocate page table pages. */
519 ptbl = ptbl_alloc(pmap, pdir_idx, nosleep);
521 KASSERT(nosleep, ("nosleep and NULL ptbl"));
524 pmap->pm_pdir[pdir_idx] = ptbl;
525 pte = &ptbl[ptbl_idx];
528 * Check if there is valid mapping for requested
529 * va, if there is, remove it.
531 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
532 if (PTE_ISVALID(pte)) {
533 pte_remove(pmap, va, PTBL_HOLD);
536 * pte is not used, increment hold count
539 if (pmap != kernel_pmap)
540 ptbl_hold(pmap, pdir_idx);
545 * Insert pv_entry into pv_list for mapped page if part of managed
548 if ((m->oflags & VPO_UNMANAGED) == 0) {
549 flags |= PTE_MANAGED;
551 /* Create and insert pv entry. */
552 pv_insert(pmap, va, m);
555 pmap->pm_stats.resident_count++;
557 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
558 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
560 mtx_lock_spin(&tlbivax_mutex);
563 tlb0_flush_entry(va);
567 mtx_unlock_spin(&tlbivax_mutex);
571 /* Return the pa for the given pmap/va. */
573 pte_vatopa(pmap_t pmap, vm_offset_t va)
578 pte = pte_find(pmap, va);
579 if ((pte != NULL) && PTE_ISVALID(pte))
580 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
584 /* Get a pointer to a PTE in a page table. */
586 pte_find(pmap_t pmap, vm_offset_t va)
588 unsigned int pdir_idx = PDIR_IDX(va);
589 unsigned int ptbl_idx = PTBL_IDX(va);
591 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
593 if (pmap->pm_pdir[pdir_idx])
594 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
599 /* Get a pointer to a PTE in a page table, or the next closest (greater) one. */
600 static __inline pte_t *
601 pte_find_next(pmap_t pmap, vm_offset_t *pva)
608 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
613 pdir = pmap->pm_pdir;
614 for (; i < PDIR_NENTRIES; i++, j = 0) {
617 for (; j < PTBL_NENTRIES; j++) {
619 if (!PTE_ISVALID(pte))
621 *pva = PDIR_SIZE * i + PAGE_SIZE * j;
628 /* Set up kernel page tables. */
630 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr)
634 vm_offset_t pdir_start;
637 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
638 kernel_pmap->pm_pdir = (pte_t **)kernel_ptbl_root;
640 pdir_start = kernel_ptbl_root + PDIR_NENTRIES * sizeof(pte_t);
642 /* Initialize kernel pdir */
643 for (i = 0; i < kernel_ptbls; i++) {
644 kernel_pmap->pm_pdir[kptbl_min + i] =
645 (pte_t *)(pdir_start + (i * PAGE_SIZE * PTBL_PAGES));
649 * Fill in PTEs covering kernel code and data. They are not required
650 * for address translation, as this area is covered by static TLB1
651 * entries, but for pte_vatopa() to work correctly with kernel area
654 for (va = addr; va < data_end; va += PAGE_SIZE) {
655 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
657 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
658 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
659 PTE_VALID | PTE_PS_4KB;
664 mmu_booke_alloc_kernel_pgtables(vm_offset_t data_end)
666 /* Allocate space for ptbl_bufs. */
667 ptbl_bufs = (struct ptbl_buf *)data_end;
668 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
669 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
670 (uintptr_t)ptbl_bufs, data_end);
672 data_end = round_page(data_end);
674 kernel_ptbl_root = data_end;
675 data_end += PDIR_NENTRIES * sizeof(pte_t*);
677 /* Allocate PTE tables for kernel KVA. */
678 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS,
680 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
681 debugf(" kernel ptbls: %d\n", kernel_ptbls);
682 debugf(" kernel pdir at %#jx end = %#jx\n",
683 (uintmax_t)kernel_ptbl_root, (uintmax_t)data_end);
689 * Initialize a preallocated and zeroed pmap structure,
690 * such as one in a vmspace structure.
693 mmu_booke_pinit(pmap_t pmap)
697 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
698 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
700 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
702 for (i = 0; i < MAXCPU; i++)
703 pmap->pm_tid[i] = TID_NONE;
704 CPU_ZERO(&kernel_pmap->pm_active);
705 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
706 pmap->pm_pdir = uma_zalloc(ptbl_root_zone, M_WAITOK);
707 bzero(pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
708 TAILQ_INIT(&pmap->pm_ptbl_list);
714 * Release any resources held by the given physical map.
715 * Called when a pmap initialized by mmu_booke_pinit is being released.
716 * Should only be called if the map contains no valid mappings.
719 mmu_booke_release(pmap_t pmap)
722 KASSERT(pmap->pm_stats.resident_count == 0,
723 ("pmap_release: pmap resident count %ld != 0",
724 pmap->pm_stats.resident_count));
725 uma_zfree(ptbl_root_zone, pmap->pm_pdir);
729 mmu_booke_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
739 rw_wlock(&pvh_global_lock);
740 pmap = PCPU_GET(curpmap);
741 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
744 pte = pte_find(pm, va);
745 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
749 sync_sz = PAGE_SIZE - (va & PAGE_MASK);
750 sync_sz = min(sync_sz, sz);
753 /* Create a mapping in the active pmap. */
755 m = PHYS_TO_VM_PAGE(pa);
757 pte_enter(pmap, m, addr,
758 PTE_SR | PTE_VALID, FALSE);
759 addr += (va & PAGE_MASK);
760 __syncicache((void *)addr, sync_sz);
761 pte_remove(pmap, addr, PTBL_UNHOLD);
764 __syncicache((void *)va, sync_sz);
769 rw_wunlock(&pvh_global_lock);
773 * mmu_booke_zero_page_area zeros the specified hardware page by
774 * mapping it into virtual memory and using bzero to clear
777 * off and size must reside within a single page.
780 mmu_booke_zero_page_area(vm_page_t m, int off, int size)
784 /* XXX KASSERT off and size are within a single page? */
786 mtx_lock(&zero_page_mutex);
789 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(m));
790 bzero((caddr_t)va + off, size);
791 mmu_booke_kremove(va);
793 mtx_unlock(&zero_page_mutex);
797 * mmu_booke_zero_page zeros the specified hardware page.
800 mmu_booke_zero_page(vm_page_t m)
805 mtx_lock(&zero_page_mutex);
807 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(m));
809 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
810 __asm __volatile("dcbz 0,%0" :: "r"(va + off));
812 mmu_booke_kremove(va);
814 mtx_unlock(&zero_page_mutex);
818 * mmu_booke_copy_page copies the specified (machine independent) page by
819 * mapping the page into virtual memory and using memcopy to copy the page,
820 * one machine dependent page at a time.
823 mmu_booke_copy_page(vm_page_t sm, vm_page_t dm)
825 vm_offset_t sva, dva;
827 sva = copy_page_src_va;
828 dva = copy_page_dst_va;
830 mtx_lock(©_page_mutex);
831 mmu_booke_kenter(sva, VM_PAGE_TO_PHYS(sm));
832 mmu_booke_kenter(dva, VM_PAGE_TO_PHYS(dm));
834 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
836 mmu_booke_kremove(dva);
837 mmu_booke_kremove(sva);
838 mtx_unlock(©_page_mutex);
842 mmu_booke_copy_pages(vm_page_t *ma, vm_offset_t a_offset,
843 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
846 vm_offset_t a_pg_offset, b_pg_offset;
849 mtx_lock(©_page_mutex);
850 while (xfersize > 0) {
851 a_pg_offset = a_offset & PAGE_MASK;
852 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
853 mmu_booke_kenter(copy_page_src_va,
854 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
855 a_cp = (char *)copy_page_src_va + a_pg_offset;
856 b_pg_offset = b_offset & PAGE_MASK;
857 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
858 mmu_booke_kenter(copy_page_dst_va,
859 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
860 b_cp = (char *)copy_page_dst_va + b_pg_offset;
861 bcopy(a_cp, b_cp, cnt);
862 mmu_booke_kremove(copy_page_dst_va);
863 mmu_booke_kremove(copy_page_src_va);
868 mtx_unlock(©_page_mutex);
872 mmu_booke_quick_enter_page(vm_page_t m)
879 paddr = VM_PAGE_TO_PHYS(m);
881 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
882 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
886 qaddr = PCPU_GET(qmap_addr);
888 pte = pte_find(kernel_pmap, qaddr);
890 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy"));
893 * XXX: tlbivax is broadcast to other cores, but qaddr should
894 * not be present in other TLBs. Is there a better instruction
895 * sequence to use? Or just forget it & use mmu_booke_kenter()...
897 __asm __volatile("tlbivax 0, %0" :: "r"(qaddr & MAS2_EPN_MASK));
898 __asm __volatile("isync; msync");
900 *pte = PTE_RPN_FROM_PA(paddr) | flags;
902 /* Flush the real memory from the instruction cache. */
903 if ((flags & (PTE_I | PTE_G)) == 0)
904 __syncicache((void *)qaddr, PAGE_SIZE);
910 mmu_booke_quick_remove_page(vm_offset_t addr)
914 pte = pte_find(kernel_pmap, addr);
916 KASSERT(PCPU_GET(qmap_addr) == addr,
917 ("mmu_booke_quick_remove_page: invalid address"));
919 ("mmu_booke_quick_remove_page: PTE not in use"));
925 /**************************************************************************/
927 /**************************************************************************/
930 * Return the largest uint value log such that 2^log <= num.
933 ilog2(unsigned long num)
937 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
942 * Invalidate all TLB0 entries which match the given TID. Note this is
943 * dedicated for cases when invalidations should NOT be propagated to other
947 tid_flush(tlbtid_t tid)
950 uint32_t mas0, mas1, mas2;
954 /* Don't evict kernel translations */
955 if (tid == TID_KERNEL)
959 __asm __volatile("wrteei 0");
962 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use
963 * it for PID invalidation.
965 switch ((mfpvr() >> 16) & 0xffff) {
969 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
971 __asm __volatile("isync; .long 0x7c200024; isync; msync");
972 __asm __volatile("wrtee %0" :: "r"(msr));
976 for (way = 0; way < TLB0_WAYS; way++)
977 for (entry = 0; entry < TLB0_ENTRIES_PER_WAY; entry++) {
979 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
980 mtspr(SPR_MAS0, mas0);
982 mas2 = entry << MAS2_TLB0_ENTRY_IDX_SHIFT;
983 mtspr(SPR_MAS2, mas2);
985 __asm __volatile("isync; tlbre");
987 mas1 = mfspr(SPR_MAS1);
989 if (!(mas1 & MAS1_VALID))
991 if (((mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT) != tid)
994 mtspr(SPR_MAS1, mas1);
995 __asm __volatile("isync; tlbwe; isync; msync");
997 __asm __volatile("wrtee %0" :: "r"(msr));