2 * Copyright (C) 1996 Wolfgang Solfrank.
3 * Copyright (C) 1996 TooLs GmbH.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $NetBSD: fpu.c,v 1.5 2001/07/22 11:29:46 wiz Exp $
34 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/limits.h>
39 #include <machine/altivec.h>
40 #include <machine/fpu.h>
41 #include <machine/ieeefp.h>
42 #include <machine/pcb.h>
43 #include <machine/psl.h>
45 #include <powerpc/fpu/fpu_arith.h>
46 #include <powerpc/fpu/fpu_emu.h>
47 #include <powerpc/fpu/fpu_extern.h>
49 void spe_handle_fpdata(struct trapframe *);
50 void spe_handle_fpround(struct trapframe *);
51 static int spe_emu_instr(uint32_t, struct fpemu *, struct fpn **, uint32_t *);
54 save_vec_int(struct thread *td)
62 * Temporarily re-enable the vector unit during the save
68 * Save the vector registers and SPEFSCR to the PCB
70 #define EVSTDW(n) __asm ("evstdw %1,0(%0)" \
71 :: "b"(pcb->pcb_vec.vr[n]), "n"(n));
72 EVSTDW(0); EVSTDW(1); EVSTDW(2); EVSTDW(3);
73 EVSTDW(4); EVSTDW(5); EVSTDW(6); EVSTDW(7);
74 EVSTDW(8); EVSTDW(9); EVSTDW(10); EVSTDW(11);
75 EVSTDW(12); EVSTDW(13); EVSTDW(14); EVSTDW(15);
76 EVSTDW(16); EVSTDW(17); EVSTDW(18); EVSTDW(19);
77 EVSTDW(20); EVSTDW(21); EVSTDW(22); EVSTDW(23);
78 EVSTDW(24); EVSTDW(25); EVSTDW(26); EVSTDW(27);
79 EVSTDW(28); EVSTDW(29); EVSTDW(30); EVSTDW(31);
82 __asm ( "evxor 0,0,0\n"
84 "evstdd 0,0(%0)" :: "b"(&pcb->pcb_vec.spare[0]));
85 pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR);
88 * Disable vector unit again
96 enable_vec(struct thread *td)
100 struct trapframe *tf;
106 * Save the thread's SPE CPU number, and set the CPU's current
109 td->td_pcb->pcb_veccpu = PCPU_GET(cpuid);
110 PCPU_SET(vecthread, td);
113 * Enable the vector unit for when the thread returns from the
114 * exception. If this is the first time the unit has been used by
115 * the thread, initialise the vector registers and VSCR to 0, and
116 * set the flag to indicate that the vector unit is in use.
119 if (!(pcb->pcb_flags & PCB_VEC)) {
120 memset(&pcb->pcb_vec, 0, sizeof pcb->pcb_vec);
121 pcb->pcb_flags |= PCB_VEC;
122 pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR);
126 * Temporarily enable the vector unit so the registers
130 mtmsr(msr | PSL_VEC);
132 /* Restore SPEFSCR and ACC. Use %r0 as the scratch for ACC. */
133 mtspr(SPR_SPEFSCR, pcb->pcb_vec.vscr);
134 __asm __volatile("isync;evldd 0, 0(%0); evmra 0,0\n"
135 :: "b"(&pcb->pcb_vec.spare[0]));
138 * The lower half of each register will be restored on trap return. Use
139 * %r0 as a scratch register, and restore it last.
141 #define EVLDW(n) __asm __volatile("evldw 0, 0(%0); evmergehilo "#n",0,"#n \
142 :: "b"(&pcb->pcb_vec.vr[n]));
143 EVLDW(1); EVLDW(2); EVLDW(3); EVLDW(4);
144 EVLDW(5); EVLDW(6); EVLDW(7); EVLDW(8);
145 EVLDW(9); EVLDW(10); EVLDW(11); EVLDW(12);
146 EVLDW(13); EVLDW(14); EVLDW(15); EVLDW(16);
147 EVLDW(17); EVLDW(18); EVLDW(19); EVLDW(20);
148 EVLDW(21); EVLDW(22); EVLDW(23); EVLDW(24);
149 EVLDW(25); EVLDW(26); EVLDW(27); EVLDW(28);
150 EVLDW(29); EVLDW(30); EVLDW(31); EVLDW(0);
158 save_vec(struct thread *td)
167 * Clear the current vec thread and pcb's CPU id
168 * XXX should this be left clear to allow lazy save/restore ?
170 pcb->pcb_veccpu = INT_MAX;
171 PCPU_SET(vecthread, NULL);
175 * Save SPE state without dropping ownership. This will only save state if
176 * the current vector-thread is `td'. This is used for taking core dumps, so
177 * don't leak kernel information; overwrite the low words of each vector with
178 * their real value, taken from the thread's trap frame, unconditionally.
181 save_vec_nodrop(struct thread *td)
186 if (td == PCPU_GET(vecthread))
191 for (i = 0; i < 32; i++) {
192 pcb->pcb_vec.vr[i][1] =
193 td->td_frame ? td->td_frame->fixreg[i] : 0;
197 #define SPE_INST_MASK 0x31f
224 #define EVFSADD 0x280
225 #define EVFSSUB 0x281
226 #define EVFSABS 0x284
227 #define EVFSNABS 0x285
228 #define EVFSNEG 0x286
229 #define EVFSMUL 0x288
230 #define EVFSDIV 0x289
231 #define EVFSCMPGT 0x28c
232 #define EVFSCMPLT 0x28d
233 #define EVFSCMPEQ 0x28e
234 #define EVFSCFUI 0x290
235 #define EVFSCFSI 0x291
236 #define EVFSCTUI 0x294
237 #define EVFSCTSI 0x295
238 #define EVFSCTUF 0x296
239 #define EVFSCTSF 0x297
240 #define EVFSCTUIZ 0x298
241 #define EVFSCTSIZ 0x29a
246 #define EFSNABS 0x2c5
250 #define EFSCMPGT 0x2cc
251 #define EFSCMPLT 0x2cd
252 #define EFSCMPEQ 0x2ce
254 #define EFSCFUI 0x2d0
255 #define EFSCFSI 0x2d1
256 #define EFSCTUI 0x2d4
257 #define EFSCTSI 0x2d5
258 #define EFSCTUF 0x2d6
259 #define EFSCTSF 0x2d7
260 #define EFSCTUIZ 0x2d8
261 #define EFSCTSIZ 0x2da
266 #define EFDNABS 0x2e5
270 #define EFDCMPGT 0x2ec
271 #define EFDCMPLT 0x2ed
272 #define EFDCMPEQ 0x2ee
274 #define EFDCFUI 0x2f0
275 #define EFDCFSI 0x2f1
276 #define EFDCTUI 0x2f4
277 #define EFDCTSI 0x2f5
278 #define EFDCTUF 0x2f6
279 #define EFDCTSF 0x2f7
280 #define EFDCTUIZ 0x2f8
281 #define EFDCTSIZ 0x2fa
290 static uint32_t fpscr_to_spefscr(uint32_t fpscr)
296 if (fpscr & FPSCR_VX)
297 spefscr |= SPEFSCR_FINV;
298 if (fpscr & FPSCR_OX)
299 spefscr |= SPEFSCR_FOVF;
300 if (fpscr & FPSCR_UX)
301 spefscr |= SPEFSCR_FUNF;
302 if (fpscr & FPSCR_ZX)
303 spefscr |= SPEFSCR_FDBZ;
304 if (fpscr & FPSCR_XX)
305 spefscr |= SPEFSCR_FX;
310 /* Sign is 0 for unsigned, 1 for signed. */
312 spe_to_int(struct fpemu *fpemu, struct fpn *fpn, uint32_t *val, int sign)
316 res[0] = fpu_ftox(fpemu, fpn, res);
317 if (res[0] != UINT_MAX && res[0] != 0)
318 fpemu->fe_cx |= FPSCR_OX;
319 else if (sign == 0 && res[0] != 0)
320 fpemu->fe_cx |= FPSCR_UX;
327 /* Masked instruction */
329 * For compare instructions, returns 1 if success, 0 if not. For all others,
330 * returns -1, or -2 if no result needs recorded.
333 spe_emu_instr(uint32_t instr, struct fpemu *fpemu,
334 struct fpn **result, uint32_t *iresult)
336 switch (instr & SPE_INST_MASK) {
340 /* Taken care of elsewhere. */
343 fpemu->fe_cx &= ~FPSCR_RN;
344 fpemu->fe_cx |= FP_RZ;
346 spe_to_int(fpemu, &fpemu->fe_f2, iresult, 0);
349 fpemu->fe_cx &= ~FPSCR_RN;
350 fpemu->fe_cx |= FP_RZ;
352 spe_to_int(fpemu, &fpemu->fe_f2, iresult, 1);
355 *result = fpu_add(fpemu);
358 *result = fpu_sub(fpemu);
361 *result = fpu_mul(fpemu);
364 *result = fpu_div(fpemu);
367 fpu_compare(fpemu, 0);
368 if (fpemu->fe_cx & FPSCR_FG)
372 fpu_compare(fpemu, 0);
373 if (fpemu->fe_cx & FPSCR_FL)
377 fpu_compare(fpemu, 0);
378 if (fpemu->fe_cx & FPSCR_FE)
382 printf("Unknown instruction %x\n", instr);
389 spe_explode(struct fpemu *fe, struct fpn *fp, uint32_t type,
390 uint32_t hi, uint32_t lo)
394 fp->fp_sign = hi >> 31;
398 s = fpu_stof(fp, hi);
402 s = fpu_dtof(fp, hi, lo);
406 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
408 * Input is a signalling NaN. All operations that return
409 * an input NaN operand put it through a ``NaN conversion'',
410 * which basically just means ``turn on the quiet bit''.
411 * We do this here so that all NaNs internally look quiet
412 * (we can tell signalling ones by their class).
414 fp->fp_mant[0] |= FP_QUIETBIT;
415 fe->fe_cx = FPSCR_VXSNAN; /* assert invalid operand */
424 * Save the high word of a 64-bit GPR for manipulation in the exception handler.
427 spe_save_reg_high(int reg)
430 #define EVSTDW(n) case n: __asm __volatile ("evstdw %1,0(%0)" \
431 :: "b"(vec), "n"(n) : "memory"); break;
433 EVSTDW(0); EVSTDW(1); EVSTDW(2); EVSTDW(3);
434 EVSTDW(4); EVSTDW(5); EVSTDW(6); EVSTDW(7);
435 EVSTDW(8); EVSTDW(9); EVSTDW(10); EVSTDW(11);
436 EVSTDW(12); EVSTDW(13); EVSTDW(14); EVSTDW(15);
437 EVSTDW(16); EVSTDW(17); EVSTDW(18); EVSTDW(19);
438 EVSTDW(20); EVSTDW(21); EVSTDW(22); EVSTDW(23);
439 EVSTDW(24); EVSTDW(25); EVSTDW(26); EVSTDW(27);
440 EVSTDW(28); EVSTDW(29); EVSTDW(30); EVSTDW(31);
448 * Load the given value into the high word of the requested register.
451 spe_load_reg_high(int reg, uint32_t val)
453 #define EVLDW(n) case n: __asm __volatile("evmergelo "#n",%0,"#n \
456 EVLDW(1); EVLDW(2); EVLDW(3); EVLDW(4);
457 EVLDW(5); EVLDW(6); EVLDW(7); EVLDW(8);
458 EVLDW(9); EVLDW(10); EVLDW(11); EVLDW(12);
459 EVLDW(13); EVLDW(14); EVLDW(15); EVLDW(16);
460 EVLDW(17); EVLDW(18); EVLDW(19); EVLDW(20);
461 EVLDW(21); EVLDW(22); EVLDW(23); EVLDW(24);
462 EVLDW(25); EVLDW(26); EVLDW(27); EVLDW(28);
463 EVLDW(29); EVLDW(30); EVLDW(31); EVLDW(0);
470 spe_handle_fpdata(struct trapframe *frame)
474 uint32_t instr, instr_sec_op;
475 uint32_t cr_shift, ra, rb, rd, src;
476 uint32_t high, low, res, tmp; /* For vector operations. */
477 uint32_t spefscr = 0;
478 uint32_t ftod_res[2];
479 int width; /* Single, Double, Vector, Integer */
483 err = fueword32((void *)frame->srr0, &instr);
489 if ((instr >> OPC_SHIFT) != SPE_OPC)
494 * 'cr' field is the upper 3 bits of rd. Magically, since a) rd is 5
495 * bits, b) each 'cr' field is 4 bits, and c) Only the 'GT' bit is
496 * modified for most compare operations, the full value of rd can be
497 * used as a shift value.
499 rd = (instr >> 21) & 0x1f;
500 ra = (instr >> 16) & 0x1f;
501 rb = (instr >> 11) & 0x1f;
502 src = (instr >> 5) & 0x7;
503 cr_shift = 28 - (rd & 0x1f);
505 instr_sec_op = (instr & 0x7ff);
507 memset(&fpemu, 0, sizeof(fpemu));
512 mtmsr(msr | PSL_VEC);
513 switch (instr_sec_op) {
515 high = spe_save_reg_high(ra) & ~(1U << 31);
516 frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
517 spe_load_reg_high(rd, high);
520 high = spe_save_reg_high(ra) | (1U << 31);
521 frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
522 spe_load_reg_high(rd, high);
525 high = spe_save_reg_high(ra) ^ (1U << 31);
526 frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
527 spe_load_reg_high(rd, high);
531 spe_explode(&fpemu, &fpemu.fe_f1, SINGLE,
532 spe_save_reg_high(ra), 0);
533 spe_explode(&fpemu, &fpemu.fe_f2, SINGLE,
534 spe_save_reg_high(rb), 0);
535 high = spe_emu_instr(instr_sec_op, &fpemu, &result,
539 spe_load_reg_high(rd, tmp);
541 spefscr = fpscr_to_spefscr(fpemu.fe_cx) << 16;
542 /* Clear the fpemu to start over on the lower bits. */
543 memset(&fpemu, 0, sizeof(fpemu));
546 spe_explode(&fpemu, &fpemu.fe_f1, SINGLE,
547 frame->fixreg[ra], 0);
548 spe_explode(&fpemu, &fpemu.fe_f2, SINGLE,
549 frame->fixreg[rb], 0);
550 spefscr |= fpscr_to_spefscr(fpemu.fe_cx);
551 low = spe_emu_instr(instr_sec_op, &fpemu, &result,
553 if (instr_sec_op == EVFSCMPEQ ||
554 instr_sec_op == EVFSCMPGT ||
555 instr_sec_op == EVFSCMPLT) {
556 res = (high << 3) | (low << 2) |
557 ((high | low) << 1) | (high & low);
566 switch (instr_sec_op) {
568 frame->fixreg[rd] = frame->fixreg[ra] & ~(1U << 31);
571 frame->fixreg[rd] = frame->fixreg[ra] | (1U << 31);
574 frame->fixreg[rd] = frame->fixreg[ra] ^ (1U << 31);
577 mtmsr(msr | PSL_VEC);
578 spe_explode(&fpemu, &fpemu.fe_f3, DOUBLE,
579 spe_save_reg_high(rb), frame->fixreg[rb]);
580 result = &fpemu.fe_f3;
584 spe_explode(&fpemu, &fpemu.fe_f1, SINGLE,
585 frame->fixreg[ra], 0);
586 spe_explode(&fpemu, &fpemu.fe_f2, SINGLE,
587 frame->fixreg[rb], 0);
592 mtmsr(msr | PSL_VEC);
593 switch (instr_sec_op) {
595 high = spe_save_reg_high(ra) & ~(1U << 31);
596 frame->fixreg[rd] = frame->fixreg[ra];
597 spe_load_reg_high(rd, high);
600 high = spe_save_reg_high(ra) | (1U << 31);
601 frame->fixreg[rd] = frame->fixreg[ra];
602 spe_load_reg_high(rd, high);
605 high = spe_save_reg_high(ra) ^ (1U << 31);
606 frame->fixreg[rd] = frame->fixreg[ra];
607 spe_load_reg_high(rd, high);
610 spe_explode(&fpemu, &fpemu.fe_f3, SINGLE,
611 frame->fixreg[rb], 0);
612 result = &fpemu.fe_f3;
616 spe_explode(&fpemu, &fpemu.fe_f1, DOUBLE,
617 spe_save_reg_high(ra), frame->fixreg[ra]);
618 spe_explode(&fpemu, &fpemu.fe_f2, DOUBLE,
619 spe_save_reg_high(rb), frame->fixreg[rb]);
624 switch (instr_sec_op) {
627 /* Already handled. */
630 res = spe_emu_instr(instr_sec_op, &fpemu, &result,
637 switch (instr_sec_op & SPE_INST_MASK) {
641 frame->cr &= ~(0xf << cr_shift);
642 frame->cr |= (res << cr_shift);
655 frame->fixreg[rd] = fpu_ftos(&fpemu, result);
658 spe_load_reg_high(rd, fpu_ftod(&fpemu, result, ftod_res));
659 frame->fixreg[rd] = ftod_res[1];
662 panic("Unknown storage width %d", width);
668 spefscr |= (mfspr(SPR_SPEFSCR) & ~SPEFSCR_FINVS);
669 mtspr(SPR_SPEFSCR, spefscr);
677 spe_handle_fpround(struct trapframe *frame)
681 * Punt fpround exceptions for now. This leaves the truncated result in
682 * the register. We'll deal with overflow/underflow later.