2 * Copyright (c) 2017 Justin Hibbits
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
41 #include <machine/cpu.h>
43 #include <powerpc/mpc85xx/mpc85xx.h>
45 #include "cpufreq_if.h"
47 /* No worries about uint32_t math overflow in here, because the highest
48 * multiplier supported is 4, and the highest speed part is still well below
52 #define GUTS_PORPLLSR (CCSRBAR_VA + 0xe0000)
53 #define GUTS_PMJCR (CCSRBAR_VA + 0xe007c)
54 #define PMJCR_RATIO_M 0x3f
55 #define PMJCR_CORE_MULT(x,y) ((x) << (16 + ((y) * 8)))
56 #define PMJCR_GET_CORE_MULT(x,y) (((x) >> (16 + ((y) * 8))) & 0x3f)
57 #define GUTS_POWMGTCSR (CCSRBAR_VA + 0xe0080)
58 #define POWMGTCSR_JOG 0x00200000
59 #define POWMGTCSR_INT_MASK 0x00000f00
63 struct mpc85xx_jog_softc {
71 static struct ofw_compat_data *mpc85xx_jog_devcompat(void);
72 static void mpc85xx_jog_identify(driver_t *driver, device_t parent);
73 static int mpc85xx_jog_probe(device_t dev);
74 static int mpc85xx_jog_attach(device_t dev);
75 static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count);
76 static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set);
77 static int mpc85xx_jog_get(device_t dev, struct cf_setting *set);
78 static int mpc85xx_jog_type(device_t dev, int *type);
80 static device_method_t mpc85xx_jog_methods[] = {
81 /* Device interface */
82 DEVMETHOD(device_identify, mpc85xx_jog_identify),
83 DEVMETHOD(device_probe, mpc85xx_jog_probe),
84 DEVMETHOD(device_attach, mpc85xx_jog_attach),
86 /* cpufreq interface */
87 DEVMETHOD(cpufreq_drv_set, mpc85xx_jog_set),
88 DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get),
89 DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type),
90 DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings),
94 static driver_t mpc85xx_jog_driver = {
97 sizeof(struct mpc85xx_jog_softc)
100 DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, 0, 0);
102 struct mpc85xx_constraints {
103 int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */
104 int min_mult; /* Minimum PLL multiplier. */
107 static struct mpc85xx_constraints mpc8536_constraints = {
112 static struct mpc85xx_constraints p1022_constraints = {
117 static struct ofw_compat_data jog_compat[] = {
118 {"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints},
119 {"fsl,p1022-guts", (uintptr_t)&p1022_constraints},
123 static struct ofw_compat_data *
124 mpc85xx_jog_devcompat()
129 node = OF_finddevice("/soc");
133 for (i = 0; jog_compat[i].ocd_str != NULL; i++)
134 if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0)
137 if (jog_compat[i].ocd_str == NULL)
140 return (&jog_compat[i]);
144 mpc85xx_jog_identify(driver_t *driver, device_t parent)
146 struct ofw_compat_data *compat;
148 /* Make sure we're not being doubly invoked. */
149 if (device_find_child(parent, "mpc85xx_jog", -1) != NULL)
152 compat = mpc85xx_jog_devcompat();
157 * We attach a child for every CPU since settings need to
158 * be performed on every CPU in the SMP case.
160 if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL)
161 device_printf(parent, "add jog child failed\n");
165 mpc85xx_jog_probe(device_t dev)
167 struct ofw_compat_data *compat;
169 compat = mpc85xx_jog_devcompat();
170 if (compat == NULL || compat->ocd_str == NULL)
173 device_set_desc(dev, "Freescale CPU Jogger");
178 mpc85xx_jog_attach(device_t dev)
180 struct ofw_compat_data *compat;
181 struct mpc85xx_jog_softc *sc;
182 struct mpc85xx_constraints *constraints;
186 sc = device_get_softc(dev);
189 compat = mpc85xx_jog_devcompat();
190 constraints = (struct mpc85xx_constraints *)compat->ocd_data;
191 cpu = ofw_bus_get_node(device_get_parent(dev));
194 device_printf(dev,"No CPU device tree node!\n");
198 OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu));
200 reg = ccsr_read4(GUTS_PORPLLSR);
203 * Assume power-on PLL is the highest PLL config supported on the
206 sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu);
207 sc->min_freq = constraints->threshold;
208 sc->low = constraints->min_mult;
210 cpufreq_register(dev);
215 mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count)
217 struct mpc85xx_jog_softc *sc;
221 sc = device_get_softc(dev);
222 if (sets == NULL || count == NULL)
224 if (*count < sc->high - 1)
227 sysclk = mpc85xx_get_system_clock();
228 /* Return a list of valid settings for this driver. */
229 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high);
231 for (i = sc->high; i >= sc->low; --i) {
232 sets[sc->high - i].freq = sysclk * i / MHZ;
233 sets[sc->high - i].dev = dev;
234 sets[sc->high - i].spec[0] = i;
236 *count = sc->high - sc->low + 1;
245 volatile int inprogress;
249 mpc85xx_jog_set_int(void *arg)
251 struct jog_rv_args *args = arg;
254 if (PCPU_GET(cpuid) == args->cpu) {
255 reg = ccsr_read4(GUTS_PMJCR);
256 reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu);
257 reg |= PMJCR_CORE_MULT(args->mult, args->cpu);
259 reg &= ~(1 << (12 + args->cpu));
261 reg |= (1 << (12 + args->cpu));
263 ccsr_write4(GUTS_PMJCR, reg);
265 reg = ccsr_read4(GUTS_POWMGTCSR);
266 reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK;
267 ccsr_write4(GUTS_POWMGTCSR, reg);
269 /* Wait for completion */
272 reg = ccsr_read4(GUTS_POWMGTCSR);
273 } while (reg & POWMGTCSR_JOG);
275 reg = ccsr_read4(GUTS_POWMGTCSR);
276 ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK);
277 ccsr_read4(GUTS_POWMGTCSR);
279 args->inprogress = 0;
281 while (args->inprogress)
287 mpc85xx_jog_set(device_t dev, const struct cf_setting *set)
289 struct mpc85xx_jog_softc *sc;
290 struct jog_rv_args args;
295 sc = device_get_softc(dev);
297 args.slow = (set->freq <= sc->min_freq);
298 args.mult = set->spec[0];
299 args.cpu = PCPU_GET(cpuid);
301 smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int,
302 smp_no_rendezvous_barrier, &args);
308 mpc85xx_jog_get(device_t dev, struct cf_setting *set)
310 struct mpc85xx_jog_softc *sc;
317 sc = device_get_softc(dev);
318 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
320 pmjcr = ccsr_read4(GUTS_PORPLLSR);
321 freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu);
322 freq *= mpc85xx_get_system_clock();
332 mpc85xx_jog_type(device_t dev, int *type)
338 *type = CPUFREQ_TYPE_ABSOLUTE;