1 /* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
11 * contributed to Berkeley.
13 * All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Lawrence Berkeley Laboratory.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 * @(#)fpu_div.c 8.1 (Berkeley) 6/11/93
46 * Perform an FPU divide (return x / y).
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
52 #include <sys/types.h>
53 #include <sys/systm.h>
55 #include <machine/fpu.h>
57 #include <powerpc/fpu/fpu_arith.h>
58 #include <powerpc/fpu/fpu_emu.h>
61 * Division of normal numbers is done as follows:
63 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e.
64 * If X and Y are the mantissas (1.bbbb's), the quotient is then:
66 * q = (X / Y) * 2^((x exponent) - (y exponent))
68 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y)
69 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only
70 * if X < Y. In that case, it will have to be shifted left one bit to
71 * become a normal number, and the exponent decremented. Thus, the
72 * desired exponent is:
74 * left_shift = x->fp_mant < y->fp_mant;
75 * result_exp = x->fp_exp - y->fp_exp - left_shift;
77 * The quotient mantissa X/Y can then be computed one bit at a time
78 * using the following algorithm:
80 * Q = 0; -- Initial quotient.
81 * R = X; -- Initial remainder,
82 * if (left_shift) -- but fixed up in advance.
84 * for (bit = FP_NMANT; --bit >= 0; R *= 2) {
91 * The subtraction R -= Y always removes the uppermost bit from R (and
92 * can sometimes remove additional lower-order 1 bits); this proof is
95 * This loop correctly calculates the guard and round bits since they are
96 * included in the expanded internal representation. The sticky bit
97 * is to be set if and only if any other bits beyond guard and round
98 * would be set. From the above it is obvious that this is true if and
99 * only if the remainder R is nonzero when the loop terminates.
101 * Examining the loop above, we can see that the quotient Q is built
102 * one bit at a time ``from the top down''. This means that we can
103 * dispense with the multi-word arithmetic and just build it one word
104 * at a time, writing each result word when it is done.
106 * Furthermore, since X and Y are both in [1.0,2.0), we know that,
107 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and
108 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1
109 * set, and R can be set initially to either X - Y (when X >= Y) or
110 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult,
111 * so we will simply calculate R - Y and see if that underflows.
112 * This leads to the following revised version of the algorithm:
118 * result_exp = x->fp_exp - y->fp_exp;
123 * result_exp = x->fp_exp - y->fp_exp - 1;
134 * } while ((bit >>= 1) != 0);
136 * for (i = 1; i < 4; i++) {
137 * q = 0, bit = 1 << 31;
145 * } while ((bit >>= 1) != 0);
149 * This can be refined just a bit further by moving the `R <<= 1'
150 * calculations to the front of the do-loops and eliding the first one.
151 * The process can be terminated immediately whenever R becomes 0, but
152 * this is relatively rare, and we do not bother.
156 fpu_div(struct fpemu *fe)
158 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
160 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
164 * Since divide is not commutative, we cannot just use ORDER.
165 * Check either operand for NaN first; if there is at least one,
166 * order the signalling one (if only one) onto the right, then
167 * return it. Otherwise we have the following cases:
169 * Inf / Inf = NaN, plus NV exception
170 * Inf / num = Inf [i.e., return x]
171 * Inf / 0 = Inf [i.e., return x]
172 * 0 / Inf = 0 [i.e., return x]
173 * 0 / num = 0 [i.e., return x]
174 * 0 / 0 = NaN, plus NV exception
176 * num / num = num (do the divide)
177 * num / 0 = Inf, plus DZ exception
179 DPRINTF(FPE_REG, ("fpu_div:\n"));
182 DPRINTF(FPE_REG, ("=>\n"));
183 if (ISNAN(x) || ISNAN(y)) {
185 fe->fe_cx |= FPSCR_VXSNAN;
190 * Need to split the following out cause they generate different
194 if (x->fp_class == y->fp_class) {
195 fe->fe_cx |= FPSCR_VXIDI;
196 return (fpu_newnan(fe));
202 fe->fe_cx |= FPSCR_ZX;
203 if (x->fp_class == y->fp_class) {
204 fe->fe_cx |= FPSCR_VXZDZ;
205 return (fpu_newnan(fe));
211 /* all results at this point use XOR of operand signs */
212 x->fp_sign ^= y->fp_sign;
214 x->fp_class = FPC_ZERO;
219 fe->fe_cx = FPSCR_ZX;
220 x->fp_class = FPC_INF;
226 * Macros for the divide. See comments at top for algorithm.
227 * Note that we expand R, D, and Y here.
230 #define SUBTRACT /* D = R - Y */ \
231 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
232 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0)
234 #define NONNEGATIVE /* D >= 0 */ \
237 #ifdef FPU_SHL1_BY_ADD
238 #define SHL1 /* R <<= 1 */ \
239 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
240 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0)
243 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \
244 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
247 #define LOOP /* do ... while (bit >>= 1) */ \
253 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
255 } while ((bit >>= 1) != 0)
257 #define WORD(r, i) /* calculate r->fp_mant[i] */ \
263 /* Setup. Note that we put our result in x. */
276 x->fp_exp -= y->fp_exp;
277 r0 = d0, r1 = d1, r2 = d2, r3 = d3;
281 x->fp_exp -= y->fp_exp + 1;
289 x->fp_sticky = r0 | r1 | r2 | r3;