1 /* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
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9 * This software was developed by the Computer Systems Engineering group
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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42 * @(#)fpu_div.c 8.1 (Berkeley) 6/11/93
46 * Perform an FPU divide (return x / y).
49 #include <sys/cdefs.h>
50 __FBSDID("$FreeBSD$");
52 #include <sys/types.h>
53 #include <sys/systm.h>
55 #include <machine/fpu.h>
56 #include <machine/reg.h>
58 #include <powerpc/fpu/fpu_arith.h>
59 #include <powerpc/fpu/fpu_emu.h>
62 * Division of normal numbers is done as follows:
64 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e.
65 * If X and Y are the mantissas (1.bbbb's), the quotient is then:
67 * q = (X / Y) * 2^((x exponent) - (y exponent))
69 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y)
70 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only
71 * if X < Y. In that case, it will have to be shifted left one bit to
72 * become a normal number, and the exponent decremented. Thus, the
73 * desired exponent is:
75 * left_shift = x->fp_mant < y->fp_mant;
76 * result_exp = x->fp_exp - y->fp_exp - left_shift;
78 * The quotient mantissa X/Y can then be computed one bit at a time
79 * using the following algorithm:
81 * Q = 0; -- Initial quotient.
82 * R = X; -- Initial remainder,
83 * if (left_shift) -- but fixed up in advance.
85 * for (bit = FP_NMANT; --bit >= 0; R *= 2) {
92 * The subtraction R -= Y always removes the uppermost bit from R (and
93 * can sometimes remove additional lower-order 1 bits); this proof is
96 * This loop correctly calculates the guard and round bits since they are
97 * included in the expanded internal representation. The sticky bit
98 * is to be set if and only if any other bits beyond guard and round
99 * would be set. From the above it is obvious that this is true if and
100 * only if the remainder R is nonzero when the loop terminates.
102 * Examining the loop above, we can see that the quotient Q is built
103 * one bit at a time ``from the top down''. This means that we can
104 * dispense with the multi-word arithmetic and just build it one word
105 * at a time, writing each result word when it is done.
107 * Furthermore, since X and Y are both in [1.0,2.0), we know that,
108 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and
109 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1
110 * set, and R can be set initially to either X - Y (when X >= Y) or
111 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult,
112 * so we will simply calculate R - Y and see if that underflows.
113 * This leads to the following revised version of the algorithm:
119 * result_exp = x->fp_exp - y->fp_exp;
124 * result_exp = x->fp_exp - y->fp_exp - 1;
135 * } while ((bit >>= 1) != 0);
137 * for (i = 1; i < 4; i++) {
138 * q = 0, bit = 1 << 31;
146 * } while ((bit >>= 1) != 0);
150 * This can be refined just a bit further by moving the `R <<= 1'
151 * calculations to the front of the do-loops and eliding the first one.
152 * The process can be terminated immediately whenever R becomes 0, but
153 * this is relatively rare, and we do not bother.
157 fpu_div(struct fpemu *fe)
159 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
161 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
165 * Since divide is not commutative, we cannot just use ORDER.
166 * Check either operand for NaN first; if there is at least one,
167 * order the signalling one (if only one) onto the right, then
168 * return it. Otherwise we have the following cases:
170 * Inf / Inf = NaN, plus NV exception
171 * Inf / num = Inf [i.e., return x]
172 * Inf / 0 = Inf [i.e., return x]
173 * 0 / Inf = 0 [i.e., return x]
174 * 0 / num = 0 [i.e., return x]
175 * 0 / 0 = NaN, plus NV exception
177 * num / num = num (do the divide)
178 * num / 0 = Inf, plus DZ exception
180 DPRINTF(FPE_REG, ("fpu_div:\n"));
183 DPRINTF(FPE_REG, ("=>\n"));
184 if (ISNAN(x) || ISNAN(y)) {
186 fe->fe_cx |= FPSCR_VXSNAN;
191 * Need to split the following out cause they generate different
195 if (x->fp_class == y->fp_class) {
196 fe->fe_cx |= FPSCR_VXIDI;
197 return (fpu_newnan(fe));
203 fe->fe_cx |= FPSCR_ZX;
204 if (x->fp_class == y->fp_class) {
205 fe->fe_cx |= FPSCR_VXZDZ;
206 return (fpu_newnan(fe));
212 /* all results at this point use XOR of operand signs */
213 x->fp_sign ^= y->fp_sign;
215 x->fp_class = FPC_ZERO;
220 fe->fe_cx = FPSCR_ZX;
221 x->fp_class = FPC_INF;
227 * Macros for the divide. See comments at top for algorithm.
228 * Note that we expand R, D, and Y here.
231 #define SUBTRACT /* D = R - Y */ \
232 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
233 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0)
235 #define NONNEGATIVE /* D >= 0 */ \
238 #ifdef FPU_SHL1_BY_ADD
239 #define SHL1 /* R <<= 1 */ \
240 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
241 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0)
244 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \
245 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
248 #define LOOP /* do ... while (bit >>= 1) */ \
254 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
256 } while ((bit >>= 1) != 0)
258 #define WORD(r, i) /* calculate r->fp_mant[i] */ \
264 /* Setup. Note that we put our result in x. */
277 x->fp_exp -= y->fp_exp;
278 r0 = d0, r1 = d1, r2 = d2, r3 = d3;
282 x->fp_exp -= y->fp_exp + 1;
290 x->fp_sticky = r0 | r1 | r2 | r3;