sys/powerpc/fpu/fpu_emu.c

   1 /*      $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */
   2
   3 /*-
   4  * SPDX-License-Identifier: BSD-4-Clause
   5  *
   6  * Copyright 2001 Wasabi Systems, Inc.
   7  * All rights reserved.
   8  *
   9  * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed for the NetBSD Project by
  22  *      Wasabi Systems, Inc.
  23  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  24  *    or promote products derived from this software without specific prior
  25  *    written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * Copyright (c) 1992, 1993
  42  *      The Regents of the University of California.  All rights reserved.
  43  *
  44  * This software was developed by the Computer Systems Engineering group
  45  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  46  * contributed to Berkeley.
  47  *
  48  * All advertising materials mentioning features or use of this software
  49  * must display the following acknowledgement:
  50  *      This product includes software developed by the University of
  51  *      California, Lawrence Berkeley Laboratory.
  52  *
  53  * Redistribution and use in source and binary forms, with or without
  54  * modification, are permitted provided that the following conditions
  55  * are met:
  56  * 1. Redistributions of source code must retain the above copyright
  57  *    notice, this list of conditions and the following disclaimer.
  58  * 2. Redistributions in binary form must reproduce the above copyright
  59  *    notice, this list of conditions and the following disclaimer in the
  60  *    documentation and/or other materials provided with the distribution.
  61  * 3. Neither the name of the University nor the names of its contributors
  62  *    may be used to endorse or promote products derived from this software
  63  *    without specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  66  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  69  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  70  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  71  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  72  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  73  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  74  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  75  * SUCH DAMAGE.
  76  *
  77  *      @(#)fpu.c       8.1 (Berkeley) 6/11/93
  78  */
  79
  80 #include <sys/cdefs.h>
  81 __FBSDID("$FreeBSD$");
  82
  83 #include "opt_ddb.h"
  84
  85 #include <sys/param.h>
  86 #include <sys/systm.h>
  87 #include <sys/kdb.h>
  88 #include <sys/kernel.h>
  89 #include <sys/proc.h>
  90 #include <sys/sysctl.h>
  91 #include <sys/signal.h>
  92 #include <sys/syslog.h>
  93 #include <sys/signalvar.h>
  94
  95 #include <machine/fpu.h>
  96 #include <machine/reg.h>
  97
  98 #include <powerpc/fpu/fpu_emu.h>
  99 #include <powerpc/fpu/fpu_extern.h>
 100 #include <powerpc/fpu/fpu_instr.h>
 101
 102 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW, 0, "FPU emulator");
 103
 104 #define FPU_EMU_EVCNT_DECL(name)                                        \
 105 static u_int fpu_emu_evcnt_##name;                                      \
 106 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD,             \
 107     &fpu_emu_evcnt_##name, 0, "")
 108
 109 #define FPU_EMU_EVCNT_INCR(name)        fpu_emu_evcnt_##name++
 110
 111 FPU_EMU_EVCNT_DECL(stfiwx);
 112 FPU_EMU_EVCNT_DECL(fpstore);
 113 FPU_EMU_EVCNT_DECL(fpload);
 114 FPU_EMU_EVCNT_DECL(fcmpu);
 115 FPU_EMU_EVCNT_DECL(frsp);
 116 FPU_EMU_EVCNT_DECL(fctiw);
 117 FPU_EMU_EVCNT_DECL(fcmpo);
 118 FPU_EMU_EVCNT_DECL(mtfsb1);
 119 FPU_EMU_EVCNT_DECL(fnegabs);
 120 FPU_EMU_EVCNT_DECL(mcrfs);
 121 FPU_EMU_EVCNT_DECL(mtfsb0);
 122 FPU_EMU_EVCNT_DECL(fmr);
 123 FPU_EMU_EVCNT_DECL(mtfsfi);
 124 FPU_EMU_EVCNT_DECL(fnabs);
 125 FPU_EMU_EVCNT_DECL(fabs);
 126 FPU_EMU_EVCNT_DECL(mffs);
 127 FPU_EMU_EVCNT_DECL(mtfsf);
 128 FPU_EMU_EVCNT_DECL(fctid);
 129 FPU_EMU_EVCNT_DECL(fcfid);
 130 FPU_EMU_EVCNT_DECL(fdiv);
 131 FPU_EMU_EVCNT_DECL(fsub);
 132 FPU_EMU_EVCNT_DECL(fadd);
 133 FPU_EMU_EVCNT_DECL(fsqrt);
 134 FPU_EMU_EVCNT_DECL(fsel);
 135 FPU_EMU_EVCNT_DECL(fpres);
 136 FPU_EMU_EVCNT_DECL(fmul);
 137 FPU_EMU_EVCNT_DECL(frsqrte);
 138 FPU_EMU_EVCNT_DECL(fmulsub);
 139 FPU_EMU_EVCNT_DECL(fmuladd);
 140 FPU_EMU_EVCNT_DECL(fnmsub);
 141 FPU_EMU_EVCNT_DECL(fnmadd);
 142
 143 /* FPSR exception masks */
 144 #define FPSR_EX_MSK     (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX|           \
 145                         FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI|  \
 146                         FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\
 147                         FPSCR_VXSQRT|FPSCR_VXCVI)
 148 #define FPSR_EX         (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE)
 149 #define FPSR_EXOP       (FPSR_EX_MSK&(~FPSR_EX))
 150
 151 int fpe_debug = 0;
 152
 153 #ifdef DEBUG
 154 vm_offset_t opc_disasm(vm_offset_t, int);
 155
 156 /*
 157  * Dump a `fpn' structure.
 158  */
 159 void
 160 fpu_dumpfpn(struct fpn *fp)
 161 {
 162         static const char *class[] = {
 163                 "SNAN", "QNAN", "ZERO", "NUM", "INF"
 164         };
 165
 166         printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2],
 167                 fp->fp_sign ? '-' : ' ',
 168                 fp->fp_mant[0], fp->fp_mant[1],
 169                 fp->fp_mant[2], fp->fp_mant[3],
 170                 fp->fp_exp);
 171 }
 172 #endif
 173
 174 /*
 175  * fpu_execute returns the following error numbers (0 = no error):
 176  */
 177 #define FPE             1       /* take a floating point exception */
 178 #define NOTFPU          2       /* not an FPU instruction */
 179 #define FAULT           3
 180
 181
 182 /*
 183  * Emulate a floating-point instruction.
 184  * Return zero for success, else signal number.
 185  * (Typically: zero, SIGFPE, SIGILL, SIGSEGV)
 186  */
 187 int
 188 fpu_emulate(struct trapframe *frame, struct fpu *fpf)
 189 {
 190         union instr insn;
 191         struct fpemu fe;
 192         int sig;
 193
 194         /* initialize insn.is_datasize to tell it is *not* initialized */
 195         fe.fe_fpstate = fpf;
 196         fe.fe_cx = 0;
 197
 198         /* always set this (to avoid a warning) */
 199
 200         if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) {
 201 #ifdef DEBUG
 202                 printf("fpu_emulate: fault reading opcode\n");
 203 #endif
 204                 return SIGSEGV;
 205         }
 206
 207         DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n",
 208             insn.i_int, (void *)frame->srr0));
 209
 210
 211         if ((insn.i_any.i_opcd == OPC_TWI) ||
 212             ((insn.i_any.i_opcd == OPC_integer_31) &&
 213             (insn.i_x.i_xo == OPC31_TW))) {
 214                 /* Check for the two trap insns. */
 215                 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n"));
 216                 return (SIGTRAP);
 217         }
 218         sig = 0;
 219         switch (fpu_execute(frame, &fe, &insn)) {
 220         case 0:
 221                 DPRINTF(FPE_EX, ("fpu_emulate: success\n"));
 222                 frame->srr0 += 4;
 223                 break;
 224
 225         case FPE:
 226                 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n"));
 227                 sig = SIGFPE;
 228                 break;
 229
 230         case FAULT:
 231                 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n"));
 232                 sig = SIGSEGV;
 233                 break;
 234
 235         case NOTFPU:
 236         default:
 237                 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n"));
 238 #ifdef DEBUG
 239                 if (fpe_debug & FPE_EX) {
 240                         printf("fpu_emulate:  illegal insn %x at %p:",
 241                         insn.i_int, (void *) (frame->srr0));
 242                         opc_disasm(frame->srr0, insn.i_int);
 243                 }
 244 #endif
 245                 sig = SIGILL;
 246 #ifdef DEBUG
 247                 if (fpe_debug & FPE_EX)
 248                         kdb_enter(KDB_WHY_UNSET, "illegal instruction");
 249 #endif
 250                 break;
 251         }
 252
 253         return (sig);
 254 }
 255
 256 /*
 257  * Execute an FPU instruction (one that runs entirely in the FPU; not
 258  * FBfcc or STF, for instance).  On return, fe->fe_fs->fs_fsr will be
 259  * modified to reflect the setting the hardware would have left.
 260  *
 261  * Note that we do not catch all illegal opcodes, so you can, for instance,
 262  * multiply two integers this way.
 263  */
 264 int
 265 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn)
 266 {
 267         struct fpn *fp;
 268         union instr instr = *insn;
 269         int *a;
 270         vm_offset_t addr;
 271         int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr;
 272         unsigned int cond;
 273         struct fpu *fs;
 274
 275         /* Setup work. */
 276         fp = NULL;
 277         fs = fe->fe_fpstate;
 278         fe->fe_fpscr = ((int *)&fs->fpscr)[1];
 279
 280         /*
 281          * On PowerPC all floating point values are stored in registers
 282          * as doubles, even when used for single precision operations.
 283          */
 284         type = FTYPE_DBL;
 285         cond = instr.i_any.i_rc;
 286         setcr = 0;
 287         bf = 0; /* XXX gcc */
 288
 289 #if defined(DDB) && defined(DEBUG)
 290         if (fpe_debug & FPE_EX) {
 291                 vm_offset_t loc = tf->srr0;
 292
 293                 printf("Trying to emulate: %p ", (void *)loc);
 294                 opc_disasm(loc, instr.i_int);
 295         }
 296 #endif
 297
 298         /*
 299          * `Decode' and execute instruction.
 300          */
 301
 302         if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) ||
 303             instr.i_any.i_opcd == OPC_integer_31) {
 304                 /*
 305                  * Handle load/store insns:
 306                  *
 307                  * Convert to/from single if needed, calculate addr,
 308                  * and update index reg if needed.
 309                  */
 310                 double buf;
 311                 size_t size = sizeof(float);
 312                 int store, update;
 313
 314                 cond = 0; /* ld/st never set condition codes */
 315
 316
 317                 if (instr.i_any.i_opcd == OPC_integer_31) {
 318                         if (instr.i_x.i_xo == OPC31_STFIWX) {
 319                                 FPU_EMU_EVCNT_INCR(stfiwx);
 320
 321                                 /* Store as integer */
 322                                 ra = instr.i_x.i_ra;
 323                                 rb = instr.i_x.i_rb;
 324                                 DPRINTF(FPE_INSN,
 325                                         ("reg %d has %jx reg %d has %jx\n",
 326                                         ra, (uintmax_t)tf->fixreg[ra], rb,
 327                                         (uintmax_t)tf->fixreg[rb]));
 328
 329                                 addr = tf->fixreg[rb];
 330                                 if (ra != 0)
 331                                         addr += tf->fixreg[ra];
 332                                 rt = instr.i_x.i_rt;
 333                                 a = (int *)&fs->fpr[rt].fpr;
 334                                 DPRINTF(FPE_INSN,
 335                                         ("fpu_execute: Store INT %x at %p\n",
 336                                                 a[1], (void *)addr));
 337                                 if (copyout(&a[1], (void *)addr, sizeof(int)))
 338                                         return (FAULT);
 339                                 return (0);
 340                         }
 341
 342                         if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP)
 343                                 /* Not an indexed FP load/store op */
 344                                 return (NOTFPU);
 345
 346                         store = (instr.i_x.i_xo & 0x80);
 347                         if (instr.i_x.i_xo & 0x40)
 348                                 size = sizeof(double);
 349                         else
 350                                 type = FTYPE_SNG;
 351                         update = (instr.i_x.i_xo & 0x20);
 352
 353                         /* calculate EA of load/store */
 354                         ra = instr.i_x.i_ra;
 355                         rb = instr.i_x.i_rb;
 356                         DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n",
 357                                 ra, (uintmax_t)tf->fixreg[ra], rb,
 358                                 (uintmax_t)tf->fixreg[rb]));
 359                         addr = tf->fixreg[rb];
 360                         if (ra != 0)
 361                                 addr += tf->fixreg[ra];
 362                         rt = instr.i_x.i_rt;
 363                 } else {
 364                         store = instr.i_d.i_opcd & 0x4;
 365                         if (instr.i_d.i_opcd & 0x2)
 366                                 size = sizeof(double);
 367                         else
 368                                 type = FTYPE_SNG;
 369                         update = instr.i_d.i_opcd & 0x1;
 370
 371                         /* calculate EA of load/store */
 372                         ra = instr.i_d.i_ra;
 373                         addr = instr.i_d.i_d;
 374                         DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n",
 375                                 ra, (uintmax_t)tf->fixreg[ra],
 376                                 (uintmax_t)addr));
 377                         if (ra != 0)
 378                                 addr += tf->fixreg[ra];
 379                         rt = instr.i_d.i_rt;
 380                 }
 381
 382                 if (update && ra == 0)
 383                         return (NOTFPU);
 384
 385                 if (store) {
 386                         /* Store */
 387                         FPU_EMU_EVCNT_INCR(fpstore);
 388                         if (type != FTYPE_DBL) {
 389                                 DPRINTF(FPE_INSN,
 390                                         ("fpu_execute: Store SNG at %p\n",
 391                                                 (void *)addr));
 392                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt);
 393                                 fpu_implode(fe, fp, type, (void *)&buf);
 394                                 if (copyout(&buf, (void *)addr, size))
 395                                         return (FAULT);
 396                         } else {
 397                                 DPRINTF(FPE_INSN,
 398                                         ("fpu_execute: Store DBL at %p\n",
 399                                                 (void *)addr));
 400                                 if (copyout(&fs->fpr[rt].fpr, (void *)addr,
 401                                     size))
 402                                         return (FAULT);
 403                         }
 404                 } else {
 405                         /* Load */
 406                         FPU_EMU_EVCNT_INCR(fpload);
 407                         DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n",
 408                                 (void *)addr));
 409                         if (copyin((const void *)addr, &fs->fpr[rt].fpr,
 410                             size))
 411                                 return (FAULT);
 412                         if (type != FTYPE_DBL) {
 413                                 fpu_explode(fe, fp = &fe->fe_f1, type, rt);
 414                                 fpu_implode(fe, fp, FTYPE_DBL,
 415                                         (u_int *)&fs->fpr[rt].fpr);
 416                         }
 417                 }
 418                 if (update)
 419                         tf->fixreg[ra] = addr;
 420                 /* Complete. */
 421                 return (0);
 422 #ifdef notyet
 423         } else if (instr.i_any.i_opcd == OPC_load_st_62) {
 424                 /* These are 64-bit extensions */
 425                 return (NOTFPU);
 426 #endif
 427         } else if (instr.i_any.i_opcd == OPC_sp_fp_59 ||
 428                 instr.i_any.i_opcd == OPC_dp_fp_63) {
 429
 430
 431                 if (instr.i_any.i_opcd == OPC_dp_fp_63 &&
 432                     !(instr.i_a.i_xo & OPC63M_MASK)) {
 433                         /* Format X */
 434                         rt = instr.i_x.i_rt;
 435                         ra = instr.i_x.i_ra;
 436                         rb = instr.i_x.i_rb;
 437
 438
 439                         /* One of the special opcodes.... */
 440                         switch (instr.i_x.i_xo) {
 441                         case    OPC63_FCMPU:
 442                                 FPU_EMU_EVCNT_INCR(fcmpu);
 443                                 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n"));
 444                                 rt >>= 2;
 445                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 446                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 447                                 fpu_compare(fe, 0);
 448                                 /* Make sure we do the condition regs. */
 449                                 cond = 0;
 450                                 /* N.B.: i_rs is already left shifted by two. */
 451                                 bf = instr.i_x.i_rs & 0xfc;
 452                                 setcr = 1;
 453                                 break;
 454
 455                         case    OPC63_FRSP:
 456                                 /*
 457                                  * Convert to single:
 458                                  *
 459                                  * PowerPC uses this to round a double
 460                                  * precision value to single precision,
 461                                  * but values in registers are always
 462                                  * stored in double precision format.
 463                                  */
 464                                 FPU_EMU_EVCNT_INCR(frsp);
 465                                 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n"));
 466                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb);
 467                                 fpu_implode(fe, fp, FTYPE_SNG,
 468                                         (u_int *)&fs->fpr[rt].fpr);
 469                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
 470                                 type = FTYPE_DBL;
 471                                 break;
 472                         case    OPC63_FCTIW:
 473                         case    OPC63_FCTIWZ:
 474                                 FPU_EMU_EVCNT_INCR(fctiw);
 475                                 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n"));
 476                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 477                                 type = FTYPE_INT;
 478                                 break;
 479                         case    OPC63_FCMPO:
 480                                 FPU_EMU_EVCNT_INCR(fcmpo);
 481                                 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n"));
 482                                 rt >>= 2;
 483                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 484                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 485                                 fpu_compare(fe, 1);
 486                                 /* Make sure we do the condition regs. */
 487                                 cond = 0;
 488                                 /* N.B.: i_rs is already left shifted by two. */
 489                                 bf = instr.i_x.i_rs & 0xfc;
 490                                 setcr = 1;
 491                                 break;
 492                         case    OPC63_MTFSB1:
 493                                 FPU_EMU_EVCNT_INCR(mtfsb1);
 494                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n"));
 495                                 fe->fe_fpscr |=
 496                                         (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt)));
 497                                 break;
 498                         case    OPC63_FNEG:
 499                                 FPU_EMU_EVCNT_INCR(fnegabs);
 500                                 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n"));
 501                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 502                                         sizeof(double));
 503                                 a = (int *)&fs->fpr[rt].fpr;
 504                                 *a ^= (1U << 31);
 505                                 break;
 506                         case    OPC63_MCRFS:
 507                                 FPU_EMU_EVCNT_INCR(mcrfs);
 508                                 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n"));
 509                                 cond = 0;
 510                                 rt &= 0x1c;
 511                                 ra &= 0x1c;
 512                                 /* Extract the bits we want */
 513                                 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf;
 514                                 /* Clear the bits we copied. */
 515                                 fe->fe_cx =
 516                                         (FPSR_EX_MSK | (0xf << (28 - ra)));
 517                                 fe->fe_fpscr &= fe->fe_cx;
 518                                 /* Now shove them in the right part of cr */
 519                                 tf->cr &= ~(0xf << (28 - rt));
 520                                 tf->cr |= (mask << (28 - rt));
 521                                 break;
 522                         case    OPC63_MTFSB0:
 523                                 FPU_EMU_EVCNT_INCR(mtfsb0);
 524                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n"));
 525                                 fe->fe_fpscr &=
 526                                         ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt)));
 527                                 break;
 528                         case    OPC63_FMR:
 529                                 FPU_EMU_EVCNT_INCR(fmr);
 530                                 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n"));
 531                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 532                                         sizeof(double));
 533                                 break;
 534                         case    OPC63_MTFSFI:
 535                                 FPU_EMU_EVCNT_INCR(mtfsfi);
 536                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n"));
 537                                 rb >>= 1;
 538                                 rt &= 0x1c; /* Already left-shifted 4 */
 539                                 fe->fe_cx = rb << (28 - rt);
 540                                 mask = 0xf<<(28 - rt);
 541                                 fe->fe_fpscr = (fe->fe_fpscr & ~mask) |
 542                                         fe->fe_cx;
 543 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */
 544                                 break;
 545                         case    OPC63_FNABS:
 546                                 FPU_EMU_EVCNT_INCR(fnabs);
 547                                 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
 548                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 549                                         sizeof(double));
 550                                 a = (int *)&fs->fpr[rt].fpr;
 551                                 *a |= (1U << 31);
 552                                 break;
 553                         case    OPC63_FABS:
 554                                 FPU_EMU_EVCNT_INCR(fabs);
 555                                 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
 556                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 557                                         sizeof(double));
 558                                 a = (int *)&fs->fpr[rt].fpr;
 559                                 *a &= ~(1U << 31);
 560                                 break;
 561                         case    OPC63_MFFS:
 562                                 FPU_EMU_EVCNT_INCR(mffs);
 563                                 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n"));
 564                                 memcpy(&fs->fpr[rt].fpr, &fs->fpscr,
 565                                         sizeof(fs->fpscr));
 566                                 break;
 567                         case    OPC63_MTFSF:
 568                                 FPU_EMU_EVCNT_INCR(mtfsf);
 569                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n"));
 570                                 if ((rt = instr.i_xfl.i_flm) == -1)
 571                                         mask = -1;
 572                                 else {
 573                                         mask = 0;
 574                                         /* Convert 1 bit -> 4 bits */
 575                                         for (ra = 0; ra < 8; ra ++)
 576                                                 if (rt & (1<<ra))
 577                                                         mask |= (0xf<<(4*ra));
 578                                 }
 579                                 a = (int *)&fs->fpr[rt].fpr;
 580                                 fe->fe_cx = mask & a[1];
 581                                 fe->fe_fpscr = (fe->fe_fpscr&~mask) |
 582                                         (fe->fe_cx);
 583 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */
 584                                 break;
 585                         case    OPC63_FCTID:
 586                         case    OPC63_FCTIDZ:
 587                                 FPU_EMU_EVCNT_INCR(fctid);
 588                                 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n"));
 589                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 590                                 type = FTYPE_LNG;
 591                                 break;
 592                         case    OPC63_FCFID:
 593                                 FPU_EMU_EVCNT_INCR(fcfid);
 594                                 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n"));
 595                                 type = FTYPE_LNG;
 596                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 597                                 type = FTYPE_DBL;
 598                                 break;
 599                         default:
 600                                 return (NOTFPU);
 601                                 break;
 602                         }
 603                 } else {
 604                         /* Format A */
 605                         rt = instr.i_a.i_frt;
 606                         ra = instr.i_a.i_fra;
 607                         rb = instr.i_a.i_frb;
 608                         rc = instr.i_a.i_frc;
 609
 610                         /*
 611                          * All arithmetic operations work on registers, which
 612                          * are stored as doubles.
 613                          */
 614                         type = FTYPE_DBL;
 615                         switch ((unsigned int)instr.i_a.i_xo) {
 616                         case    OPC59_FDIVS:
 617                                 FPU_EMU_EVCNT_INCR(fdiv);
 618                                 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n"));
 619                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 620                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 621                                 fp = fpu_div(fe);
 622                                 break;
 623                         case    OPC59_FSUBS:
 624                                 FPU_EMU_EVCNT_INCR(fsub);
 625                                 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
 626                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 627                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 628                                 fp = fpu_sub(fe);
 629                                 break;
 630                         case    OPC59_FADDS:
 631                                 FPU_EMU_EVCNT_INCR(fadd);
 632                                 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
 633                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 634                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 635                                 fp = fpu_add(fe);
 636                                 break;
 637                         case    OPC59_FSQRTS:
 638                                 FPU_EMU_EVCNT_INCR(fsqrt);
 639                                 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n"));
 640                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 641                                 fp = fpu_sqrt(fe);
 642                                 break;
 643                         case    OPC63M_FSEL:
 644                                 FPU_EMU_EVCNT_INCR(fsel);
 645                                 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n"));
 646                                 a = (int *)&fe->fe_fpstate->fpr[ra].fpr;
 647                                 if ((*a & 0x80000000) && (*a & 0x7fffffff))
 648                                         /* fra < 0 */
 649                                         rc = rb;
 650                                 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt));
 651                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr,
 652                                         sizeof(double));
 653                                 break;
 654                         case    OPC59_FRES:
 655                                 FPU_EMU_EVCNT_INCR(fpres);
 656                                 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n"));
 657                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 658                                 fp = fpu_sqrt(fe);
 659                                 /* now we've gotta overwrite the dest reg */
 660                                 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1;
 661                                 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
 662                                 fpu_div(fe);
 663                                 break;
 664                         case    OPC59_FMULS:
 665                                 FPU_EMU_EVCNT_INCR(fmul);
 666                                 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n"));
 667                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 668                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 669                                 fp = fpu_mul(fe);
 670                                 break;
 671                         case    OPC63M_FRSQRTE:
 672                                 /* Reciprocal sqrt() estimate */
 673                                 FPU_EMU_EVCNT_INCR(frsqrte);
 674                                 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n"));
 675                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 676                                 fp = fpu_sqrt(fe);
 677                                 fe->fe_f2 = *fp;
 678                                 /* now we've gotta overwrite the dest reg */
 679                                 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1;
 680                                 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
 681                                 fpu_div(fe);
 682                                 break;
 683                         case    OPC59_FMSUBS:
 684                                 FPU_EMU_EVCNT_INCR(fmulsub);
 685                                 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n"));
 686                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 687                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 688                                 fp = fpu_mul(fe);
 689                                 fe->fe_f1 = *fp;
 690                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 691                                 fp = fpu_sub(fe);
 692                                 break;
 693                         case    OPC59_FMADDS:
 694                                 FPU_EMU_EVCNT_INCR(fmuladd);
 695                                 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n"));
 696                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 697                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 698                                 fp = fpu_mul(fe);
 699                                 fe->fe_f1 = *fp;
 700                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 701                                 fp = fpu_add(fe);
 702                                 break;
 703                         case    OPC59_FNMSUBS:
 704                                 FPU_EMU_EVCNT_INCR(fnmsub);
 705                                 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n"));
 706                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 707                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 708                                 fp = fpu_mul(fe);
 709                                 fe->fe_f1 = *fp;
 710                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 711                                 fp = fpu_sub(fe);
 712                                 /* Negate */
 713                                 fp->fp_sign ^= 1;
 714                                 break;
 715                         case    OPC59_FNMADDS:
 716                                 FPU_EMU_EVCNT_INCR(fnmadd);
 717                                 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n"));
 718                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 719                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 720                                 fp = fpu_mul(fe);
 721                                 fe->fe_f1 = *fp;
 722                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 723                                 fp = fpu_add(fe);
 724                                 /* Negate */
 725                                 fp->fp_sign ^= 1;
 726                                 break;
 727                         default:
 728                                 return (NOTFPU);
 729                                 break;
 730                         }
 731
 732                         /* If the instruction was single precision, round */
 733                         if (!(instr.i_any.i_opcd & 0x4)) {
 734                                 fpu_implode(fe, fp, FTYPE_SNG,
 735                                         (u_int *)&fs->fpr[rt].fpr);
 736                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
 737                         }
 738                 }
 739         } else {
 740                 return (NOTFPU);
 741         }
 742
 743         /*
 744          * ALU operation is complete.  Collapse the result and then check
 745          * for exceptions.  If we got any, and they are enabled, do not
 746          * alter the destination register, just stop with an exception.
 747          * Otherwise set new current exceptions and accrue.
 748          */
 749         if (fp)
 750                 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr);
 751         cx = fe->fe_cx;
 752         fsr = fe->fe_fpscr;
 753         if (cx != 0) {
 754                 fsr &= ~FPSCR_FX;
 755                 if ((cx^fsr)&FPSR_EX_MSK)
 756                         fsr |= FPSCR_FX;
 757                 mask = fsr & FPSR_EX;
 758                 mask <<= (25-3);
 759                 if (cx & mask)
 760                         fsr |= FPSCR_FEX;
 761                 if (cx & FPSCR_FPRF) {
 762                         /* Need to replace CC */
 763                         fsr &= ~FPSCR_FPRF;
 764                 }
 765                 if (cx & (FPSR_EXOP))
 766                         fsr |= FPSCR_VX;
 767                 fsr |= cx;
 768                 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr));
 769         }
 770
 771         if (cond) {
 772                 cond = fsr & 0xf0000000;
 773                 /* Isolate condition codes */
 774                 cond >>= 28;
 775                 /* Move fpu condition codes to cr[1] */
 776                 tf->cr &= (0x0f000000);
 777                 tf->cr |= (cond<<24);
 778                 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond));
 779         }
 780
 781         if (setcr) {
 782                 cond = fsr & FPSCR_FPCC;
 783                 /* Isolate condition codes */
 784                 cond <<= 16;
 785                 /* Move fpu condition codes to cr[1] */
 786                 tf->cr &= ~(0xf0000000>>bf);
 787                 tf->cr |= (cond>>bf);
 788                 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n",
 789                         bf/4, (uintmax_t)tf->cr, cond));
 790         }
 791
 792         ((int *)&fs->fpscr)[1] = fsr;
 793         if (fsr & FPSCR_FEX)
 794                 return(FPE);
 795         return (0);     /* success */
 796 }