sys/powerpc/fpu/fpu_emu.c

   1 /*      $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */
   2
   3 /*-
   4  * SPDX-License-Identifier: BSD-4-Clause
   5  *
   6  * Copyright 2001 Wasabi Systems, Inc.
   7  * All rights reserved.
   8  *
   9  * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed for the NetBSD Project by
  22  *      Wasabi Systems, Inc.
  23  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  24  *    or promote products derived from this software without specific prior
  25  *    written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGE.
  38  */
  39
  40 /*
  41  * Copyright (c) 1992, 1993
  42  *      The Regents of the University of California.  All rights reserved.
  43  *
  44  * This software was developed by the Computer Systems Engineering group
  45  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  46  * contributed to Berkeley.
  47  *
  48  * All advertising materials mentioning features or use of this software
  49  * must display the following acknowledgement:
  50  *      This product includes software developed by the University of
  51  *      California, Lawrence Berkeley Laboratory.
  52  *
  53  * Redistribution and use in source and binary forms, with or without
  54  * modification, are permitted provided that the following conditions
  55  * are met:
  56  * 1. Redistributions of source code must retain the above copyright
  57  *    notice, this list of conditions and the following disclaimer.
  58  * 2. Redistributions in binary form must reproduce the above copyright
  59  *    notice, this list of conditions and the following disclaimer in the
  60  *    documentation and/or other materials provided with the distribution.
  61  * 3. Neither the name of the University nor the names of its contributors
  62  *    may be used to endorse or promote products derived from this software
  63  *    without specific prior written permission.
  64  *
  65  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  66  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  67  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  68  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  69  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  70  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  71  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  72  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  73  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  74  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  75  * SUCH DAMAGE.
  76  *
  77  *      @(#)fpu.c       8.1 (Berkeley) 6/11/93
  78  */
  79
  80 #include <sys/cdefs.h>
  81 __FBSDID("$FreeBSD$");
  82
  83 #include "opt_ddb.h"
  84
  85 #include <sys/param.h>
  86 #include <sys/systm.h>
  87 #include <sys/kdb.h>
  88 #include <sys/kernel.h>
  89 #include <sys/proc.h>
  90 #include <sys/sysctl.h>
  91 #include <sys/signal.h>
  92 #include <sys/syslog.h>
  93 #include <sys/signalvar.h>
  94
  95 #include <machine/fpu.h>
  96 #include <machine/reg.h>
  97
  98 #include <powerpc/fpu/fpu_emu.h>
  99 #include <powerpc/fpu/fpu_extern.h>
 100 #include <powerpc/fpu/fpu_instr.h>
 101
 102 static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
 103     "FPU emulator");
 104
 105 #define FPU_EMU_EVCNT_DECL(name)                                        \
 106 static u_int fpu_emu_evcnt_##name;                                      \
 107 SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD,             \
 108     &fpu_emu_evcnt_##name, 0, "")
 109
 110 #define FPU_EMU_EVCNT_INCR(name)        fpu_emu_evcnt_##name++
 111
 112 FPU_EMU_EVCNT_DECL(stfiwx);
 113 FPU_EMU_EVCNT_DECL(fpstore);
 114 FPU_EMU_EVCNT_DECL(fpload);
 115 FPU_EMU_EVCNT_DECL(fcmpu);
 116 FPU_EMU_EVCNT_DECL(frsp);
 117 FPU_EMU_EVCNT_DECL(fctiw);
 118 FPU_EMU_EVCNT_DECL(fcmpo);
 119 FPU_EMU_EVCNT_DECL(mtfsb1);
 120 FPU_EMU_EVCNT_DECL(fnegabs);
 121 FPU_EMU_EVCNT_DECL(mcrfs);
 122 FPU_EMU_EVCNT_DECL(mtfsb0);
 123 FPU_EMU_EVCNT_DECL(fmr);
 124 FPU_EMU_EVCNT_DECL(mtfsfi);
 125 FPU_EMU_EVCNT_DECL(fnabs);
 126 FPU_EMU_EVCNT_DECL(fabs);
 127 FPU_EMU_EVCNT_DECL(mffs);
 128 FPU_EMU_EVCNT_DECL(mtfsf);
 129 FPU_EMU_EVCNT_DECL(fctid);
 130 FPU_EMU_EVCNT_DECL(fcfid);
 131 FPU_EMU_EVCNT_DECL(fdiv);
 132 FPU_EMU_EVCNT_DECL(fsub);
 133 FPU_EMU_EVCNT_DECL(fadd);
 134 FPU_EMU_EVCNT_DECL(fsqrt);
 135 FPU_EMU_EVCNT_DECL(fsel);
 136 FPU_EMU_EVCNT_DECL(fpres);
 137 FPU_EMU_EVCNT_DECL(fmul);
 138 FPU_EMU_EVCNT_DECL(frsqrte);
 139 FPU_EMU_EVCNT_DECL(fmulsub);
 140 FPU_EMU_EVCNT_DECL(fmuladd);
 141 FPU_EMU_EVCNT_DECL(fnmsub);
 142 FPU_EMU_EVCNT_DECL(fnmadd);
 143
 144 /* FPSR exception masks */
 145 #define FPSR_EX_MSK     (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX|           \
 146                         FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI|  \
 147                         FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\
 148                         FPSCR_VXSQRT|FPSCR_VXCVI)
 149 #define FPSR_EX         (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE)
 150 #define FPSR_EXOP       (FPSR_EX_MSK&(~FPSR_EX))
 151
 152 int fpe_debug = 0;
 153
 154 #ifdef DEBUG
 155 vm_offset_t opc_disasm(vm_offset_t, int);
 156
 157 /*
 158  * Dump a `fpn' structure.
 159  */
 160 void
 161 fpu_dumpfpn(struct fpn *fp)
 162 {
 163         static const char *class[] = {
 164                 "SNAN", "QNAN", "ZERO", "NUM", "INF"
 165         };
 166
 167         printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2],
 168                 fp->fp_sign ? '-' : ' ',
 169                 fp->fp_mant[0], fp->fp_mant[1],
 170                 fp->fp_mant[2], fp->fp_mant[3],
 171                 fp->fp_exp);
 172 }
 173 #endif
 174
 175 /*
 176  * fpu_execute returns the following error numbers (0 = no error):
 177  */
 178 #define FPE             1       /* take a floating point exception */
 179 #define NOTFPU          2       /* not an FPU instruction */
 180 #define FAULT           3
 181
 182 /*
 183  * Emulate a floating-point instruction.
 184  * Return zero for success, else signal number.
 185  * (Typically: zero, SIGFPE, SIGILL, SIGSEGV)
 186  */
 187 int
 188 fpu_emulate(struct trapframe *frame, struct fpu *fpf)
 189 {
 190         union instr insn;
 191         struct fpemu fe;
 192         int sig;
 193
 194         /* initialize insn.is_datasize to tell it is *not* initialized */
 195         fe.fe_fpstate = fpf;
 196         fe.fe_cx = 0;
 197
 198         /* always set this (to avoid a warning) */
 199
 200         if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) {
 201 #ifdef DEBUG
 202                 printf("fpu_emulate: fault reading opcode\n");
 203 #endif
 204                 return SIGSEGV;
 205         }
 206
 207         DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n",
 208             insn.i_int, (void *)frame->srr0));
 209
 210         if ((insn.i_any.i_opcd == OPC_TWI) ||
 211             ((insn.i_any.i_opcd == OPC_integer_31) &&
 212             (insn.i_x.i_xo == OPC31_TW))) {
 213                 /* Check for the two trap insns. */
 214                 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n"));
 215                 return (SIGTRAP);
 216         }
 217         sig = 0;
 218         switch (fpu_execute(frame, &fe, &insn)) {
 219         case 0:
 220                 DPRINTF(FPE_EX, ("fpu_emulate: success\n"));
 221                 frame->srr0 += 4;
 222                 break;
 223
 224         case FPE:
 225                 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n"));
 226                 sig = SIGFPE;
 227                 break;
 228
 229         case FAULT:
 230                 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n"));
 231                 sig = SIGSEGV;
 232                 break;
 233
 234         case NOTFPU:
 235         default:
 236                 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n"));
 237 #ifdef DEBUG
 238                 if (fpe_debug & FPE_EX) {
 239                         printf("fpu_emulate:  illegal insn %x at %p:",
 240                         insn.i_int, (void *) (frame->srr0));
 241                         opc_disasm(frame->srr0, insn.i_int);
 242                 }
 243 #endif
 244                 sig = SIGILL;
 245 #ifdef DEBUG
 246                 if (fpe_debug & FPE_EX)
 247                         kdb_enter(KDB_WHY_UNSET, "illegal instruction");
 248 #endif
 249                 break;
 250         }
 251
 252         return (sig);
 253 }
 254
 255 /*
 256  * Execute an FPU instruction (one that runs entirely in the FPU; not
 257  * FBfcc or STF, for instance).  On return, fe->fe_fs->fs_fsr will be
 258  * modified to reflect the setting the hardware would have left.
 259  *
 260  * Note that we do not catch all illegal opcodes, so you can, for instance,
 261  * multiply two integers this way.
 262  */
 263 int
 264 fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn)
 265 {
 266         struct fpn *fp;
 267         union instr instr = *insn;
 268         int *a;
 269         vm_offset_t addr;
 270         int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr;
 271         unsigned int cond;
 272         struct fpu *fs;
 273
 274         /* Setup work. */
 275         fp = NULL;
 276         fs = fe->fe_fpstate;
 277         fe->fe_fpscr = ((int *)&fs->fpscr)[1];
 278
 279         /*
 280          * On PowerPC all floating point values are stored in registers
 281          * as doubles, even when used for single precision operations.
 282          */
 283         type = FTYPE_DBL;
 284         cond = instr.i_any.i_rc;
 285         setcr = 0;
 286         bf = 0; /* XXX gcc */
 287
 288 #if defined(DDB) && defined(DEBUG)
 289         if (fpe_debug & FPE_EX) {
 290                 vm_offset_t loc = tf->srr0;
 291
 292                 printf("Trying to emulate: %p ", (void *)loc);
 293                 opc_disasm(loc, instr.i_int);
 294         }
 295 #endif
 296
 297         /*
 298          * `Decode' and execute instruction.
 299          */
 300
 301         if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) ||
 302             instr.i_any.i_opcd == OPC_integer_31) {
 303                 /*
 304                  * Handle load/store insns:
 305                  *
 306                  * Convert to/from single if needed, calculate addr,
 307                  * and update index reg if needed.
 308                  */
 309                 double buf;
 310                 size_t size = sizeof(float);
 311                 int store, update;
 312
 313                 cond = 0; /* ld/st never set condition codes */
 314
 315                 if (instr.i_any.i_opcd == OPC_integer_31) {
 316                         if (instr.i_x.i_xo == OPC31_STFIWX) {
 317                                 FPU_EMU_EVCNT_INCR(stfiwx);
 318
 319                                 /* Store as integer */
 320                                 ra = instr.i_x.i_ra;
 321                                 rb = instr.i_x.i_rb;
 322                                 DPRINTF(FPE_INSN,
 323                                         ("reg %d has %jx reg %d has %jx\n",
 324                                         ra, (uintmax_t)tf->fixreg[ra], rb,
 325                                         (uintmax_t)tf->fixreg[rb]));
 326
 327                                 addr = tf->fixreg[rb];
 328                                 if (ra != 0)
 329                                         addr += tf->fixreg[ra];
 330                                 rt = instr.i_x.i_rt;
 331                                 a = (int *)&fs->fpr[rt].fpr;
 332                                 DPRINTF(FPE_INSN,
 333                                         ("fpu_execute: Store INT %x at %p\n",
 334                                                 a[1], (void *)addr));
 335                                 if (copyout(&a[1], (void *)addr, sizeof(int)))
 336                                         return (FAULT);
 337                                 return (0);
 338                         }
 339
 340                         if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP)
 341                                 /* Not an indexed FP load/store op */
 342                                 return (NOTFPU);
 343
 344                         store = (instr.i_x.i_xo & 0x80);
 345                         if (instr.i_x.i_xo & 0x40)
 346                                 size = sizeof(double);
 347                         else
 348                                 type = FTYPE_SNG;
 349                         update = (instr.i_x.i_xo & 0x20);
 350
 351                         /* calculate EA of load/store */
 352                         ra = instr.i_x.i_ra;
 353                         rb = instr.i_x.i_rb;
 354                         DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n",
 355                                 ra, (uintmax_t)tf->fixreg[ra], rb,
 356                                 (uintmax_t)tf->fixreg[rb]));
 357                         addr = tf->fixreg[rb];
 358                         if (ra != 0)
 359                                 addr += tf->fixreg[ra];
 360                         rt = instr.i_x.i_rt;
 361                 } else {
 362                         store = instr.i_d.i_opcd & 0x4;
 363                         if (instr.i_d.i_opcd & 0x2)
 364                                 size = sizeof(double);
 365                         else
 366                                 type = FTYPE_SNG;
 367                         update = instr.i_d.i_opcd & 0x1;
 368
 369                         /* calculate EA of load/store */
 370                         ra = instr.i_d.i_ra;
 371                         addr = instr.i_d.i_d;
 372                         DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n",
 373                                 ra, (uintmax_t)tf->fixreg[ra],
 374                                 (uintmax_t)addr));
 375                         if (ra != 0)
 376                                 addr += tf->fixreg[ra];
 377                         rt = instr.i_d.i_rt;
 378                 }
 379
 380                 if (update && ra == 0)
 381                         return (NOTFPU);
 382
 383                 if (store) {
 384                         /* Store */
 385                         FPU_EMU_EVCNT_INCR(fpstore);
 386                         if (type != FTYPE_DBL) {
 387                                 DPRINTF(FPE_INSN,
 388                                         ("fpu_execute: Store SNG at %p\n",
 389                                                 (void *)addr));
 390                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt);
 391                                 fpu_implode(fe, fp, type, (void *)&buf);
 392                                 if (copyout(&buf, (void *)addr, size))
 393                                         return (FAULT);
 394                         } else {
 395                                 DPRINTF(FPE_INSN,
 396                                         ("fpu_execute: Store DBL at %p\n",
 397                                                 (void *)addr));
 398                                 if (copyout(&fs->fpr[rt].fpr, (void *)addr,
 399                                     size))
 400                                         return (FAULT);
 401                         }
 402                 } else {
 403                         /* Load */
 404                         FPU_EMU_EVCNT_INCR(fpload);
 405                         DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n",
 406                                 (void *)addr));
 407                         if (copyin((const void *)addr, &fs->fpr[rt].fpr,
 408                             size))
 409                                 return (FAULT);
 410                         if (type != FTYPE_DBL) {
 411                                 fpu_explode(fe, fp = &fe->fe_f1, type, rt);
 412                                 fpu_implode(fe, fp, FTYPE_DBL,
 413                                         (u_int *)&fs->fpr[rt].fpr);
 414                         }
 415                 }
 416                 if (update)
 417                         tf->fixreg[ra] = addr;
 418                 /* Complete. */
 419                 return (0);
 420 #ifdef notyet
 421         } else if (instr.i_any.i_opcd == OPC_load_st_62) {
 422                 /* These are 64-bit extensions */
 423                 return (NOTFPU);
 424 #endif
 425         } else if (instr.i_any.i_opcd == OPC_sp_fp_59 ||
 426                 instr.i_any.i_opcd == OPC_dp_fp_63) {
 427                 if (instr.i_any.i_opcd == OPC_dp_fp_63 &&
 428                     !(instr.i_a.i_xo & OPC63M_MASK)) {
 429                         /* Format X */
 430                         rt = instr.i_x.i_rt;
 431                         ra = instr.i_x.i_ra;
 432                         rb = instr.i_x.i_rb;
 433
 434                         /* One of the special opcodes.... */
 435                         switch (instr.i_x.i_xo) {
 436                         case    OPC63_FCMPU:
 437                                 FPU_EMU_EVCNT_INCR(fcmpu);
 438                                 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n"));
 439                                 rt >>= 2;
 440                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 441                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 442                                 fpu_compare(fe, 0);
 443                                 /* Make sure we do the condition regs. */
 444                                 cond = 0;
 445                                 /* N.B.: i_rs is already left shifted by two. */
 446                                 bf = instr.i_x.i_rs & 0xfc;
 447                                 setcr = 1;
 448                                 break;
 449
 450                         case    OPC63_FRSP:
 451                                 /*
 452                                  * Convert to single:
 453                                  *
 454                                  * PowerPC uses this to round a double
 455                                  * precision value to single precision,
 456                                  * but values in registers are always
 457                                  * stored in double precision format.
 458                                  */
 459                                 FPU_EMU_EVCNT_INCR(frsp);
 460                                 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n"));
 461                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb);
 462                                 fpu_implode(fe, fp, FTYPE_SNG,
 463                                         (u_int *)&fs->fpr[rt].fpr);
 464                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
 465                                 type = FTYPE_DBL;
 466                                 break;
 467                         case    OPC63_FCTIW:
 468                         case    OPC63_FCTIWZ:
 469                                 FPU_EMU_EVCNT_INCR(fctiw);
 470                                 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n"));
 471                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 472                                 type = FTYPE_INT;
 473                                 break;
 474                         case    OPC63_FCMPO:
 475                                 FPU_EMU_EVCNT_INCR(fcmpo);
 476                                 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n"));
 477                                 rt >>= 2;
 478                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 479                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 480                                 fpu_compare(fe, 1);
 481                                 /* Make sure we do the condition regs. */
 482                                 cond = 0;
 483                                 /* N.B.: i_rs is already left shifted by two. */
 484                                 bf = instr.i_x.i_rs & 0xfc;
 485                                 setcr = 1;
 486                                 break;
 487                         case    OPC63_MTFSB1:
 488                                 FPU_EMU_EVCNT_INCR(mtfsb1);
 489                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n"));
 490                                 fe->fe_fpscr |=
 491                                         (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt)));
 492                                 break;
 493                         case    OPC63_FNEG:
 494                                 FPU_EMU_EVCNT_INCR(fnegabs);
 495                                 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n"));
 496                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 497                                         sizeof(double));
 498                                 a = (int *)&fs->fpr[rt].fpr;
 499                                 *a ^= (1U << 31);
 500                                 break;
 501                         case    OPC63_MCRFS:
 502                                 FPU_EMU_EVCNT_INCR(mcrfs);
 503                                 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n"));
 504                                 cond = 0;
 505                                 rt &= 0x1c;
 506                                 ra &= 0x1c;
 507                                 /* Extract the bits we want */
 508                                 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf;
 509                                 /* Clear the bits we copied. */
 510                                 fe->fe_cx =
 511                                         (FPSR_EX_MSK | (0xf << (28 - ra)));
 512                                 fe->fe_fpscr &= fe->fe_cx;
 513                                 /* Now shove them in the right part of cr */
 514                                 tf->cr &= ~(0xf << (28 - rt));
 515                                 tf->cr |= (mask << (28 - rt));
 516                                 break;
 517                         case    OPC63_MTFSB0:
 518                                 FPU_EMU_EVCNT_INCR(mtfsb0);
 519                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n"));
 520                                 fe->fe_fpscr &=
 521                                         ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt)));
 522                                 break;
 523                         case    OPC63_FMR:
 524                                 FPU_EMU_EVCNT_INCR(fmr);
 525                                 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n"));
 526                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 527                                         sizeof(double));
 528                                 break;
 529                         case    OPC63_MTFSFI:
 530                                 FPU_EMU_EVCNT_INCR(mtfsfi);
 531                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n"));
 532                                 rb >>= 1;
 533                                 rt &= 0x1c; /* Already left-shifted 4 */
 534                                 fe->fe_cx = rb << (28 - rt);
 535                                 mask = 0xf<<(28 - rt);
 536                                 fe->fe_fpscr = (fe->fe_fpscr & ~mask) |
 537                                         fe->fe_cx;
 538 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */
 539                                 break;
 540                         case    OPC63_FNABS:
 541                                 FPU_EMU_EVCNT_INCR(fnabs);
 542                                 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
 543                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 544                                         sizeof(double));
 545                                 a = (int *)&fs->fpr[rt].fpr;
 546                                 *a |= (1U << 31);
 547                                 break;
 548                         case    OPC63_FABS:
 549                                 FPU_EMU_EVCNT_INCR(fabs);
 550                                 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n"));
 551                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rb].fpr,
 552                                         sizeof(double));
 553                                 a = (int *)&fs->fpr[rt].fpr;
 554                                 *a &= ~(1U << 31);
 555                                 break;
 556                         case    OPC63_MFFS:
 557                                 FPU_EMU_EVCNT_INCR(mffs);
 558                                 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n"));
 559                                 memcpy(&fs->fpr[rt].fpr, &fs->fpscr,
 560                                         sizeof(fs->fpscr));
 561                                 break;
 562                         case    OPC63_MTFSF:
 563                                 FPU_EMU_EVCNT_INCR(mtfsf);
 564                                 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n"));
 565                                 if ((rt = instr.i_xfl.i_flm) == -1)
 566                                         mask = -1;
 567                                 else {
 568                                         mask = 0;
 569                                         /* Convert 1 bit -> 4 bits */
 570                                         for (ra = 0; ra < 8; ra ++)
 571                                                 if (rt & (1<<ra))
 572                                                         mask |= (0xf<<(4*ra));
 573                                 }
 574                                 a = (int *)&fs->fpr[rt].fpr;
 575                                 fe->fe_cx = mask & a[1];
 576                                 fe->fe_fpscr = (fe->fe_fpscr&~mask) |
 577                                         (fe->fe_cx);
 578 /* XXX weird stuff about OX, FX, FEX, and VX should be handled */
 579                                 break;
 580                         case    OPC63_FCTID:
 581                         case    OPC63_FCTIDZ:
 582                                 FPU_EMU_EVCNT_INCR(fctid);
 583                                 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n"));
 584                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 585                                 type = FTYPE_LNG;
 586                                 break;
 587                         case    OPC63_FCFID:
 588                                 FPU_EMU_EVCNT_INCR(fcfid);
 589                                 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n"));
 590                                 type = FTYPE_LNG;
 591                                 fpu_explode(fe, fp = &fe->fe_f1, type, rb);
 592                                 type = FTYPE_DBL;
 593                                 break;
 594                         default:
 595                                 return (NOTFPU);
 596                                 break;
 597                         }
 598                 } else {
 599                         /* Format A */
 600                         rt = instr.i_a.i_frt;
 601                         ra = instr.i_a.i_fra;
 602                         rb = instr.i_a.i_frb;
 603                         rc = instr.i_a.i_frc;
 604
 605                         /*
 606                          * All arithmetic operations work on registers, which
 607                          * are stored as doubles.
 608                          */
 609                         type = FTYPE_DBL;
 610                         switch ((unsigned int)instr.i_a.i_xo) {
 611                         case    OPC59_FDIVS:
 612                                 FPU_EMU_EVCNT_INCR(fdiv);
 613                                 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n"));
 614                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 615                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 616                                 fp = fpu_div(fe);
 617                                 break;
 618                         case    OPC59_FSUBS:
 619                                 FPU_EMU_EVCNT_INCR(fsub);
 620                                 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
 621                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 622                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 623                                 fp = fpu_sub(fe);
 624                                 break;
 625                         case    OPC59_FADDS:
 626                                 FPU_EMU_EVCNT_INCR(fadd);
 627                                 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
 628                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 629                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 630                                 fp = fpu_add(fe);
 631                                 break;
 632                         case    OPC59_FSQRTS:
 633                                 FPU_EMU_EVCNT_INCR(fsqrt);
 634                                 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n"));
 635                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 636                                 fp = fpu_sqrt(fe);
 637                                 break;
 638                         case    OPC63M_FSEL:
 639                                 FPU_EMU_EVCNT_INCR(fsel);
 640                                 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n"));
 641                                 a = (int *)&fe->fe_fpstate->fpr[ra].fpr;
 642                                 if ((*a & 0x80000000) && (*a & 0x7fffffff))
 643                                         /* fra < 0 */
 644                                         rc = rb;
 645                                 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt));
 646                                 memcpy(&fs->fpr[rt].fpr, &fs->fpr[rc].fpr,
 647                                         sizeof(double));
 648                                 break;
 649                         case    OPC59_FRES:
 650                                 FPU_EMU_EVCNT_INCR(fpres);
 651                                 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n"));
 652                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 653                                 fp = fpu_sqrt(fe);
 654                                 /* now we've gotta overwrite the dest reg */
 655                                 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1;
 656                                 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
 657                                 fpu_div(fe);
 658                                 break;
 659                         case    OPC59_FMULS:
 660                                 FPU_EMU_EVCNT_INCR(fmul);
 661                                 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n"));
 662                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 663                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 664                                 fp = fpu_mul(fe);
 665                                 break;
 666                         case    OPC63M_FRSQRTE:
 667                                 /* Reciprocal sqrt() estimate */
 668                                 FPU_EMU_EVCNT_INCR(frsqrte);
 669                                 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n"));
 670                                 fpu_explode(fe, &fe->fe_f1, type, rb);
 671                                 fp = fpu_sqrt(fe);
 672                                 fe->fe_f2 = *fp;
 673                                 /* now we've gotta overwrite the dest reg */
 674                                 *((int *)&fe->fe_fpstate->fpr[rt].fpr) = 1;
 675                                 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
 676                                 fpu_div(fe);
 677                                 break;
 678                         case    OPC59_FMSUBS:
 679                                 FPU_EMU_EVCNT_INCR(fmulsub);
 680                                 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n"));
 681                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 682                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 683                                 fp = fpu_mul(fe);
 684                                 fe->fe_f1 = *fp;
 685                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 686                                 fp = fpu_sub(fe);
 687                                 break;
 688                         case    OPC59_FMADDS:
 689                                 FPU_EMU_EVCNT_INCR(fmuladd);
 690                                 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n"));
 691                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 692                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 693                                 fp = fpu_mul(fe);
 694                                 fe->fe_f1 = *fp;
 695                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 696                                 fp = fpu_add(fe);
 697                                 break;
 698                         case    OPC59_FNMSUBS:
 699                                 FPU_EMU_EVCNT_INCR(fnmsub);
 700                                 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n"));
 701                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 702                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 703                                 fp = fpu_mul(fe);
 704                                 fe->fe_f1 = *fp;
 705                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 706                                 fp = fpu_sub(fe);
 707                                 /* Negate */
 708                                 fp->fp_sign ^= 1;
 709                                 break;
 710                         case    OPC59_FNMADDS:
 711                                 FPU_EMU_EVCNT_INCR(fnmadd);
 712                                 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n"));
 713                                 fpu_explode(fe, &fe->fe_f1, type, ra);
 714                                 fpu_explode(fe, &fe->fe_f2, type, rc);
 715                                 fp = fpu_mul(fe);
 716                                 fe->fe_f1 = *fp;
 717                                 fpu_explode(fe, &fe->fe_f2, type, rb);
 718                                 fp = fpu_add(fe);
 719                                 /* Negate */
 720                                 fp->fp_sign ^= 1;
 721                                 break;
 722                         default:
 723                                 return (NOTFPU);
 724                                 break;
 725                         }
 726
 727                         /* If the instruction was single precision, round */
 728                         if (!(instr.i_any.i_opcd & 0x4)) {
 729                                 fpu_implode(fe, fp, FTYPE_SNG,
 730                                         (u_int *)&fs->fpr[rt].fpr);
 731                                 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
 732                         }
 733                 }
 734         } else {
 735                 return (NOTFPU);
 736         }
 737
 738         /*
 739          * ALU operation is complete.  Collapse the result and then check
 740          * for exceptions.  If we got any, and they are enabled, do not
 741          * alter the destination register, just stop with an exception.
 742          * Otherwise set new current exceptions and accrue.
 743          */
 744         if (fp)
 745                 fpu_implode(fe, fp, type, (u_int *)&fs->fpr[rt].fpr);
 746         cx = fe->fe_cx;
 747         fsr = fe->fe_fpscr;
 748         if (cx != 0) {
 749                 fsr &= ~FPSCR_FX;
 750                 if ((cx^fsr)&FPSR_EX_MSK)
 751                         fsr |= FPSCR_FX;
 752                 mask = fsr & FPSR_EX;
 753                 mask <<= (25-3);
 754                 if (cx & mask)
 755                         fsr |= FPSCR_FEX;
 756                 if (cx & FPSCR_FPRF) {
 757                         /* Need to replace CC */
 758                         fsr &= ~FPSCR_FPRF;
 759                 }
 760                 if (cx & (FPSR_EXOP))
 761                         fsr |= FPSCR_VX;
 762                 fsr |= cx;
 763                 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr));
 764         }
 765
 766         if (cond) {
 767                 cond = fsr & 0xf0000000;
 768                 /* Isolate condition codes */
 769                 cond >>= 28;
 770                 /* Move fpu condition codes to cr[1] */
 771                 tf->cr &= (0x0f000000);
 772                 tf->cr |= (cond<<24);
 773                 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond));
 774         }
 775
 776         if (setcr) {
 777                 cond = fsr & FPSCR_FPCC;
 778                 /* Isolate condition codes */
 779                 cond <<= 16;
 780                 /* Move fpu condition codes to cr[1] */
 781                 tf->cr &= ~(0xf0000000>>bf);
 782                 tf->cr |= (cond>>bf);
 783                 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n",
 784                         bf/4, (uintmax_t)tf->cr, cond));
 785         }
 786
 787         ((int *)&fs->fpscr)[1] = fsr;
 788         if (fsr & FPSCR_FEX)
 789                 return(FPE);
 790         return (0);     /* success */
 791 }